1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4 #include <linux/module.h> 5 #include <linux/device.h> 6 #include <linux/pci.h> 7 #include <linux/ptp_classify.h> 8 9 #include "igb.h" 10 11 #define INCVALUE_MASK 0x7fffffff 12 #define ISGN 0x80000000 13 14 /* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 * 55 * SYSTIM is converted to real time using a timecounter. As 56 * timecounter_cyc2time() allows old timestamps, the timecounter needs 57 * to be updated at least once per half of the SYSTIM interval. 58 * Scheduling of delayed work is not very accurate, and also the NIC 59 * clock can be adjusted to run up to 6% faster and the system clock 60 * up to 10% slower, so we aim for 6 minutes to be sure the actual 61 * interval in the NIC time is shorter than 9.16 minutes. 62 */ 63 64 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6) 65 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 66 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 68 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 69 #define IGB_NBITS_82580 40 70 71 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 72 static void igb_ptp_sdp_init(struct igb_adapter *adapter); 73 74 /* SYSTIM read access for the 82576 */ 75 static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 76 { 77 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 78 struct e1000_hw *hw = &igb->hw; 79 u64 val; 80 u32 lo, hi; 81 82 lo = rd32(E1000_SYSTIML); 83 hi = rd32(E1000_SYSTIMH); 84 85 val = ((u64) hi) << 32; 86 val |= lo; 87 88 return val; 89 } 90 91 /* SYSTIM read access for the 82580 */ 92 static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 93 { 94 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 95 struct e1000_hw *hw = &igb->hw; 96 u32 lo, hi; 97 u64 val; 98 99 /* The timestamp latches on lowest register read. For the 82580 100 * the lowest register is SYSTIMR instead of SYSTIML. However we only 101 * need to provide nanosecond resolution, so we just ignore it. 102 */ 103 rd32(E1000_SYSTIMR); 104 lo = rd32(E1000_SYSTIML); 105 hi = rd32(E1000_SYSTIMH); 106 107 val = ((u64) hi) << 32; 108 val |= lo; 109 110 return val; 111 } 112 113 /* SYSTIM read access for I210/I211 */ 114 static void igb_ptp_read_i210(struct igb_adapter *adapter, 115 struct timespec64 *ts) 116 { 117 struct e1000_hw *hw = &adapter->hw; 118 u32 sec, nsec; 119 120 /* The timestamp latches on lowest register read. For I210/I211, the 121 * lowest register is SYSTIMR. Since we only need to provide nanosecond 122 * resolution, we can ignore it. 123 */ 124 rd32(E1000_SYSTIMR); 125 nsec = rd32(E1000_SYSTIML); 126 sec = rd32(E1000_SYSTIMH); 127 128 ts->tv_sec = sec; 129 ts->tv_nsec = nsec; 130 } 131 132 static void igb_ptp_write_i210(struct igb_adapter *adapter, 133 const struct timespec64 *ts) 134 { 135 struct e1000_hw *hw = &adapter->hw; 136 137 /* Writing the SYSTIMR register is not necessary as it only provides 138 * sub-nanosecond resolution. 139 */ 140 wr32(E1000_SYSTIML, ts->tv_nsec); 141 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 142 } 143 144 /** 145 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 146 * @adapter: board private structure 147 * @hwtstamps: timestamp structure to update 148 * @systim: unsigned 64bit system time value. 149 * 150 * We need to convert the system time value stored in the RX/TXSTMP registers 151 * into a hwtstamp which can be used by the upper level timestamping functions. 152 * 153 * The 'tmreg_lock' spinlock is used to protect the consistency of the 154 * system time value. This is needed because reading the 64 bit time 155 * value involves reading two (or three) 32 bit registers. The first 156 * read latches the value. Ditto for writing. 157 * 158 * In addition, here have extended the system time with an overflow 159 * counter in software. 160 **/ 161 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 162 struct skb_shared_hwtstamps *hwtstamps, 163 u64 systim) 164 { 165 unsigned long flags; 166 u64 ns; 167 168 memset(hwtstamps, 0, sizeof(*hwtstamps)); 169 170 switch (adapter->hw.mac.type) { 171 case e1000_82576: 172 case e1000_82580: 173 case e1000_i354: 174 case e1000_i350: 175 spin_lock_irqsave(&adapter->tmreg_lock, flags); 176 ns = timecounter_cyc2time(&adapter->tc, systim); 177 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 178 179 hwtstamps->hwtstamp = ns_to_ktime(ns); 180 break; 181 case e1000_i210: 182 case e1000_i211: 183 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 184 hwtstamps->hwtstamp = ktime_set(systim >> 32, 185 systim & 0xFFFFFFFF); 186 break; 187 default: 188 break; 189 } 190 } 191 192 /* PTP clock operations */ 193 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 194 { 195 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 196 ptp_caps); 197 struct e1000_hw *hw = &igb->hw; 198 int neg_adj = 0; 199 u64 rate; 200 u32 incvalue; 201 202 if (ppb < 0) { 203 neg_adj = 1; 204 ppb = -ppb; 205 } 206 rate = ppb; 207 rate <<= 14; 208 rate = div_u64(rate, 1953125); 209 210 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 211 212 if (neg_adj) 213 incvalue -= rate; 214 else 215 incvalue += rate; 216 217 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 218 219 return 0; 220 } 221 222 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 223 { 224 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 225 ptp_caps); 226 struct e1000_hw *hw = &igb->hw; 227 int neg_adj = 0; 228 u64 rate; 229 u32 inca; 230 231 if (scaled_ppm < 0) { 232 neg_adj = 1; 233 scaled_ppm = -scaled_ppm; 234 } 235 rate = scaled_ppm; 236 rate <<= 13; 237 rate = div_u64(rate, 15625); 238 239 inca = rate & INCVALUE_MASK; 240 if (neg_adj) 241 inca |= ISGN; 242 243 wr32(E1000_TIMINCA, inca); 244 245 return 0; 246 } 247 248 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 249 { 250 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 251 ptp_caps); 252 unsigned long flags; 253 254 spin_lock_irqsave(&igb->tmreg_lock, flags); 255 timecounter_adjtime(&igb->tc, delta); 256 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 257 258 return 0; 259 } 260 261 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 262 { 263 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 264 ptp_caps); 265 unsigned long flags; 266 struct timespec64 now, then = ns_to_timespec64(delta); 267 268 spin_lock_irqsave(&igb->tmreg_lock, flags); 269 270 igb_ptp_read_i210(igb, &now); 271 now = timespec64_add(now, then); 272 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 273 274 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 275 276 return 0; 277 } 278 279 static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, 280 struct timespec64 *ts, 281 struct ptp_system_timestamp *sts) 282 { 283 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 284 ptp_caps); 285 struct e1000_hw *hw = &igb->hw; 286 unsigned long flags; 287 u32 lo, hi; 288 u64 ns; 289 290 spin_lock_irqsave(&igb->tmreg_lock, flags); 291 292 ptp_read_system_prets(sts); 293 lo = rd32(E1000_SYSTIML); 294 ptp_read_system_postts(sts); 295 hi = rd32(E1000_SYSTIMH); 296 297 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 298 299 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 300 301 *ts = ns_to_timespec64(ns); 302 303 return 0; 304 } 305 306 static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, 307 struct timespec64 *ts, 308 struct ptp_system_timestamp *sts) 309 { 310 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 311 ptp_caps); 312 struct e1000_hw *hw = &igb->hw; 313 unsigned long flags; 314 u32 lo, hi; 315 u64 ns; 316 317 spin_lock_irqsave(&igb->tmreg_lock, flags); 318 319 ptp_read_system_prets(sts); 320 rd32(E1000_SYSTIMR); 321 ptp_read_system_postts(sts); 322 lo = rd32(E1000_SYSTIML); 323 hi = rd32(E1000_SYSTIMH); 324 325 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 326 327 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 328 329 *ts = ns_to_timespec64(ns); 330 331 return 0; 332 } 333 334 static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, 335 struct timespec64 *ts, 336 struct ptp_system_timestamp *sts) 337 { 338 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 339 ptp_caps); 340 struct e1000_hw *hw = &igb->hw; 341 unsigned long flags; 342 343 spin_lock_irqsave(&igb->tmreg_lock, flags); 344 345 ptp_read_system_prets(sts); 346 rd32(E1000_SYSTIMR); 347 ptp_read_system_postts(sts); 348 ts->tv_nsec = rd32(E1000_SYSTIML); 349 ts->tv_sec = rd32(E1000_SYSTIMH); 350 351 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 352 353 return 0; 354 } 355 356 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 357 const struct timespec64 *ts) 358 { 359 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 360 ptp_caps); 361 unsigned long flags; 362 u64 ns; 363 364 ns = timespec64_to_ns(ts); 365 366 spin_lock_irqsave(&igb->tmreg_lock, flags); 367 368 timecounter_init(&igb->tc, &igb->cc, ns); 369 370 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 371 372 return 0; 373 } 374 375 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 376 const struct timespec64 *ts) 377 { 378 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 379 ptp_caps); 380 unsigned long flags; 381 382 spin_lock_irqsave(&igb->tmreg_lock, flags); 383 384 igb_ptp_write_i210(igb, ts); 385 386 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 387 388 return 0; 389 } 390 391 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 392 { 393 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 394 static const u32 mask[IGB_N_SDP] = { 395 E1000_CTRL_SDP0_DIR, 396 E1000_CTRL_SDP1_DIR, 397 E1000_CTRL_EXT_SDP2_DIR, 398 E1000_CTRL_EXT_SDP3_DIR, 399 }; 400 401 if (input) 402 *ptr &= ~mask[pin]; 403 else 404 *ptr |= mask[pin]; 405 } 406 407 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 408 { 409 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 410 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 411 }; 412 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 413 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 414 }; 415 static const u32 ts_sdp_en[IGB_N_SDP] = { 416 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 417 }; 418 struct e1000_hw *hw = &igb->hw; 419 u32 ctrl, ctrl_ext, tssdp = 0; 420 421 ctrl = rd32(E1000_CTRL); 422 ctrl_ext = rd32(E1000_CTRL_EXT); 423 tssdp = rd32(E1000_TSSDP); 424 425 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 426 427 /* Make sure this pin is not enabled as an output. */ 428 tssdp &= ~ts_sdp_en[pin]; 429 430 if (chan == 1) { 431 tssdp &= ~AUX1_SEL_SDP3; 432 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 433 } else { 434 tssdp &= ~AUX0_SEL_SDP3; 435 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 436 } 437 438 wr32(E1000_TSSDP, tssdp); 439 wr32(E1000_CTRL, ctrl); 440 wr32(E1000_CTRL_EXT, ctrl_ext); 441 } 442 443 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 444 { 445 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 446 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 447 }; 448 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 449 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 450 }; 451 static const u32 ts_sdp_en[IGB_N_SDP] = { 452 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 453 }; 454 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 455 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 456 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 457 }; 458 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 459 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 460 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 461 }; 462 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 463 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 464 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 465 }; 466 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 467 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 468 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 469 }; 470 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 471 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 472 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 473 }; 474 struct e1000_hw *hw = &igb->hw; 475 u32 ctrl, ctrl_ext, tssdp = 0; 476 477 ctrl = rd32(E1000_CTRL); 478 ctrl_ext = rd32(E1000_CTRL_EXT); 479 tssdp = rd32(E1000_TSSDP); 480 481 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 482 483 /* Make sure this pin is not enabled as an input. */ 484 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 485 tssdp &= ~AUX0_TS_SDP_EN; 486 487 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 488 tssdp &= ~AUX1_TS_SDP_EN; 489 490 tssdp &= ~ts_sdp_sel_clr[pin]; 491 if (freq) { 492 if (chan == 1) 493 tssdp |= ts_sdp_sel_fc1[pin]; 494 else 495 tssdp |= ts_sdp_sel_fc0[pin]; 496 } else { 497 if (chan == 1) 498 tssdp |= ts_sdp_sel_tt1[pin]; 499 else 500 tssdp |= ts_sdp_sel_tt0[pin]; 501 } 502 tssdp |= ts_sdp_en[pin]; 503 504 wr32(E1000_TSSDP, tssdp); 505 wr32(E1000_CTRL, ctrl); 506 wr32(E1000_CTRL_EXT, ctrl_ext); 507 } 508 509 static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp, 510 struct ptp_clock_request *rq, int on) 511 { 512 struct igb_adapter *igb = 513 container_of(ptp, struct igb_adapter, ptp_caps); 514 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml, 515 systimh, level_mask, level, rem; 516 struct e1000_hw *hw = &igb->hw; 517 struct timespec64 ts, start; 518 unsigned long flags; 519 u64 systim, now; 520 int pin = -1; 521 s64 ns; 522 523 switch (rq->type) { 524 case PTP_CLK_REQ_EXTTS: 525 /* Reject requests with unsupported flags */ 526 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 527 PTP_RISING_EDGE | 528 PTP_FALLING_EDGE | 529 PTP_STRICT_FLAGS)) 530 return -EOPNOTSUPP; 531 532 if (on) { 533 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 534 rq->extts.index); 535 if (pin < 0) 536 return -EBUSY; 537 } 538 if (rq->extts.index == 1) { 539 tsauxc_mask = TSAUXC_EN_TS1; 540 tsim_mask = TSINTR_AUTT1; 541 } else { 542 tsauxc_mask = TSAUXC_EN_TS0; 543 tsim_mask = TSINTR_AUTT0; 544 } 545 spin_lock_irqsave(&igb->tmreg_lock, flags); 546 tsauxc = rd32(E1000_TSAUXC); 547 tsim = rd32(E1000_TSIM); 548 if (on) { 549 igb_pin_extts(igb, rq->extts.index, pin); 550 tsauxc |= tsauxc_mask; 551 tsim |= tsim_mask; 552 } else { 553 tsauxc &= ~tsauxc_mask; 554 tsim &= ~tsim_mask; 555 } 556 wr32(E1000_TSAUXC, tsauxc); 557 wr32(E1000_TSIM, tsim); 558 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 559 return 0; 560 561 case PTP_CLK_REQ_PEROUT: 562 /* Reject requests with unsupported flags */ 563 if (rq->perout.flags) 564 return -EOPNOTSUPP; 565 566 if (on) { 567 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 568 rq->perout.index); 569 if (pin < 0) 570 return -EBUSY; 571 } 572 ts.tv_sec = rq->perout.period.sec; 573 ts.tv_nsec = rq->perout.period.nsec; 574 ns = timespec64_to_ns(&ts); 575 ns = ns >> 1; 576 if (on && ns < 8LL) 577 return -EINVAL; 578 ts = ns_to_timespec64(ns); 579 if (rq->perout.index == 1) { 580 tsauxc_mask = TSAUXC_EN_TT1; 581 tsim_mask = TSINTR_TT1; 582 trgttiml = E1000_TRGTTIML1; 583 trgttimh = E1000_TRGTTIMH1; 584 } else { 585 tsauxc_mask = TSAUXC_EN_TT0; 586 tsim_mask = TSINTR_TT0; 587 trgttiml = E1000_TRGTTIML0; 588 trgttimh = E1000_TRGTTIMH0; 589 } 590 spin_lock_irqsave(&igb->tmreg_lock, flags); 591 tsauxc = rd32(E1000_TSAUXC); 592 tsim = rd32(E1000_TSIM); 593 if (rq->perout.index == 1) { 594 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 595 tsim &= ~TSINTR_TT1; 596 } else { 597 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 598 tsim &= ~TSINTR_TT0; 599 } 600 if (on) { 601 int i = rq->perout.index; 602 603 /* read systim registers in sequence */ 604 rd32(E1000_SYSTIMR); 605 systiml = rd32(E1000_SYSTIML); 606 systimh = rd32(E1000_SYSTIMH); 607 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 608 now = timecounter_cyc2time(&igb->tc, systim); 609 610 if (pin < 2) { 611 level_mask = (i == 1) ? 0x80000 : 0x40000; 612 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 613 } else { 614 level_mask = (i == 1) ? 0x80 : 0x40; 615 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 616 } 617 618 div_u64_rem(now, ns, &rem); 619 systim = systim + (ns - rem); 620 621 /* synchronize pin level with rising/falling edges */ 622 div_u64_rem(now, ns << 1, &rem); 623 if (rem < ns) { 624 /* first half of period */ 625 if (level == 0) { 626 /* output is already low, skip this period */ 627 systim += ns; 628 } 629 } else { 630 /* second half of period */ 631 if (level == 1) { 632 /* output is already high, skip this period */ 633 systim += ns; 634 } 635 } 636 637 start = ns_to_timespec64(systim + (ns - rem)); 638 igb_pin_perout(igb, i, pin, 0); 639 igb->perout[i].start.tv_sec = start.tv_sec; 640 igb->perout[i].start.tv_nsec = start.tv_nsec; 641 igb->perout[i].period.tv_sec = ts.tv_sec; 642 igb->perout[i].period.tv_nsec = ts.tv_nsec; 643 644 wr32(trgttiml, (u32)systim); 645 wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF); 646 tsauxc |= tsauxc_mask; 647 tsim |= tsim_mask; 648 } 649 wr32(E1000_TSAUXC, tsauxc); 650 wr32(E1000_TSIM, tsim); 651 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 652 return 0; 653 654 case PTP_CLK_REQ_PPS: 655 return -EOPNOTSUPP; 656 } 657 658 return -EOPNOTSUPP; 659 } 660 661 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 662 struct ptp_clock_request *rq, int on) 663 { 664 struct igb_adapter *igb = 665 container_of(ptp, struct igb_adapter, ptp_caps); 666 struct e1000_hw *hw = &igb->hw; 667 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 668 unsigned long flags; 669 struct timespec64 ts; 670 int use_freq = 0, pin = -1; 671 s64 ns; 672 673 switch (rq->type) { 674 case PTP_CLK_REQ_EXTTS: 675 /* Reject requests with unsupported flags */ 676 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 677 PTP_RISING_EDGE | 678 PTP_FALLING_EDGE | 679 PTP_STRICT_FLAGS)) 680 return -EOPNOTSUPP; 681 682 /* Reject requests failing to enable both edges. */ 683 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 684 (rq->extts.flags & PTP_ENABLE_FEATURE) && 685 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) 686 return -EOPNOTSUPP; 687 688 if (on) { 689 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 690 rq->extts.index); 691 if (pin < 0) 692 return -EBUSY; 693 } 694 if (rq->extts.index == 1) { 695 tsauxc_mask = TSAUXC_EN_TS1; 696 tsim_mask = TSINTR_AUTT1; 697 } else { 698 tsauxc_mask = TSAUXC_EN_TS0; 699 tsim_mask = TSINTR_AUTT0; 700 } 701 spin_lock_irqsave(&igb->tmreg_lock, flags); 702 tsauxc = rd32(E1000_TSAUXC); 703 tsim = rd32(E1000_TSIM); 704 if (on) { 705 igb_pin_extts(igb, rq->extts.index, pin); 706 tsauxc |= tsauxc_mask; 707 tsim |= tsim_mask; 708 } else { 709 tsauxc &= ~tsauxc_mask; 710 tsim &= ~tsim_mask; 711 } 712 wr32(E1000_TSAUXC, tsauxc); 713 wr32(E1000_TSIM, tsim); 714 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 715 return 0; 716 717 case PTP_CLK_REQ_PEROUT: 718 /* Reject requests with unsupported flags */ 719 if (rq->perout.flags) 720 return -EOPNOTSUPP; 721 722 if (on) { 723 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 724 rq->perout.index); 725 if (pin < 0) 726 return -EBUSY; 727 } 728 ts.tv_sec = rq->perout.period.sec; 729 ts.tv_nsec = rq->perout.period.nsec; 730 ns = timespec64_to_ns(&ts); 731 ns = ns >> 1; 732 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 733 (ns == 250000000LL) || (ns == 500000000LL))) { 734 if (ns < 8LL) 735 return -EINVAL; 736 use_freq = 1; 737 } 738 ts = ns_to_timespec64(ns); 739 if (rq->perout.index == 1) { 740 if (use_freq) { 741 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 742 tsim_mask = 0; 743 } else { 744 tsauxc_mask = TSAUXC_EN_TT1; 745 tsim_mask = TSINTR_TT1; 746 } 747 trgttiml = E1000_TRGTTIML1; 748 trgttimh = E1000_TRGTTIMH1; 749 freqout = E1000_FREQOUT1; 750 } else { 751 if (use_freq) { 752 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 753 tsim_mask = 0; 754 } else { 755 tsauxc_mask = TSAUXC_EN_TT0; 756 tsim_mask = TSINTR_TT0; 757 } 758 trgttiml = E1000_TRGTTIML0; 759 trgttimh = E1000_TRGTTIMH0; 760 freqout = E1000_FREQOUT0; 761 } 762 spin_lock_irqsave(&igb->tmreg_lock, flags); 763 tsauxc = rd32(E1000_TSAUXC); 764 tsim = rd32(E1000_TSIM); 765 if (rq->perout.index == 1) { 766 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 767 tsim &= ~TSINTR_TT1; 768 } else { 769 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 770 tsim &= ~TSINTR_TT0; 771 } 772 if (on) { 773 int i = rq->perout.index; 774 igb_pin_perout(igb, i, pin, use_freq); 775 igb->perout[i].start.tv_sec = rq->perout.start.sec; 776 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 777 igb->perout[i].period.tv_sec = ts.tv_sec; 778 igb->perout[i].period.tv_nsec = ts.tv_nsec; 779 wr32(trgttimh, rq->perout.start.sec); 780 wr32(trgttiml, rq->perout.start.nsec); 781 if (use_freq) 782 wr32(freqout, ns); 783 tsauxc |= tsauxc_mask; 784 tsim |= tsim_mask; 785 } 786 wr32(E1000_TSAUXC, tsauxc); 787 wr32(E1000_TSIM, tsim); 788 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 789 return 0; 790 791 case PTP_CLK_REQ_PPS: 792 spin_lock_irqsave(&igb->tmreg_lock, flags); 793 tsim = rd32(E1000_TSIM); 794 if (on) 795 tsim |= TSINTR_SYS_WRAP; 796 else 797 tsim &= ~TSINTR_SYS_WRAP; 798 igb->pps_sys_wrap_on = !!on; 799 wr32(E1000_TSIM, tsim); 800 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 801 return 0; 802 } 803 804 return -EOPNOTSUPP; 805 } 806 807 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 808 struct ptp_clock_request *rq, int on) 809 { 810 return -EOPNOTSUPP; 811 } 812 813 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 814 enum ptp_pin_function func, unsigned int chan) 815 { 816 switch (func) { 817 case PTP_PF_NONE: 818 case PTP_PF_EXTTS: 819 case PTP_PF_PEROUT: 820 break; 821 case PTP_PF_PHYSYNC: 822 return -1; 823 } 824 return 0; 825 } 826 827 /** 828 * igb_ptp_tx_work 829 * @work: pointer to work struct 830 * 831 * This work function polls the TSYNCTXCTL valid bit to determine when a 832 * timestamp has been taken for the current stored skb. 833 **/ 834 static void igb_ptp_tx_work(struct work_struct *work) 835 { 836 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 837 ptp_tx_work); 838 struct e1000_hw *hw = &adapter->hw; 839 u32 tsynctxctl; 840 841 if (!adapter->ptp_tx_skb) 842 return; 843 844 if (time_is_before_jiffies(adapter->ptp_tx_start + 845 IGB_PTP_TX_TIMEOUT)) { 846 dev_kfree_skb_any(adapter->ptp_tx_skb); 847 adapter->ptp_tx_skb = NULL; 848 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 849 adapter->tx_hwtstamp_timeouts++; 850 /* Clear the tx valid bit in TSYNCTXCTL register to enable 851 * interrupt 852 */ 853 rd32(E1000_TXSTMPH); 854 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 855 return; 856 } 857 858 tsynctxctl = rd32(E1000_TSYNCTXCTL); 859 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 860 igb_ptp_tx_hwtstamp(adapter); 861 else 862 /* reschedule to check later */ 863 schedule_work(&adapter->ptp_tx_work); 864 } 865 866 static void igb_ptp_overflow_check(struct work_struct *work) 867 { 868 struct igb_adapter *igb = 869 container_of(work, struct igb_adapter, ptp_overflow_work.work); 870 struct timespec64 ts; 871 u64 ns; 872 873 /* Update the timecounter */ 874 ns = timecounter_read(&igb->tc); 875 876 ts = ns_to_timespec64(ns); 877 pr_debug("igb overflow check at %lld.%09lu\n", 878 (long long) ts.tv_sec, ts.tv_nsec); 879 880 schedule_delayed_work(&igb->ptp_overflow_work, 881 IGB_SYSTIM_OVERFLOW_PERIOD); 882 } 883 884 /** 885 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 886 * @adapter: private network adapter structure 887 * 888 * This watchdog task is scheduled to detect error case where hardware has 889 * dropped an Rx packet that was timestamped when the ring is full. The 890 * particular error is rare but leaves the device in a state unable to timestamp 891 * any future packets. 892 **/ 893 void igb_ptp_rx_hang(struct igb_adapter *adapter) 894 { 895 struct e1000_hw *hw = &adapter->hw; 896 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 897 unsigned long rx_event; 898 899 /* Other hardware uses per-packet timestamps */ 900 if (hw->mac.type != e1000_82576) 901 return; 902 903 /* If we don't have a valid timestamp in the registers, just update the 904 * timeout counter and exit 905 */ 906 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 907 adapter->last_rx_ptp_check = jiffies; 908 return; 909 } 910 911 /* Determine the most recent watchdog or rx_timestamp event */ 912 rx_event = adapter->last_rx_ptp_check; 913 if (time_after(adapter->last_rx_timestamp, rx_event)) 914 rx_event = adapter->last_rx_timestamp; 915 916 /* Only need to read the high RXSTMP register to clear the lock */ 917 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 918 rd32(E1000_RXSTMPH); 919 adapter->last_rx_ptp_check = jiffies; 920 adapter->rx_hwtstamp_cleared++; 921 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 922 } 923 } 924 925 /** 926 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 927 * @adapter: private network adapter structure 928 */ 929 void igb_ptp_tx_hang(struct igb_adapter *adapter) 930 { 931 struct e1000_hw *hw = &adapter->hw; 932 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 933 IGB_PTP_TX_TIMEOUT); 934 935 if (!adapter->ptp_tx_skb) 936 return; 937 938 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 939 return; 940 941 /* If we haven't received a timestamp within the timeout, it is 942 * reasonable to assume that it will never occur, so we can unlock the 943 * timestamp bit when this occurs. 944 */ 945 if (timeout) { 946 cancel_work_sync(&adapter->ptp_tx_work); 947 dev_kfree_skb_any(adapter->ptp_tx_skb); 948 adapter->ptp_tx_skb = NULL; 949 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 950 adapter->tx_hwtstamp_timeouts++; 951 /* Clear the tx valid bit in TSYNCTXCTL register to enable 952 * interrupt 953 */ 954 rd32(E1000_TXSTMPH); 955 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 956 } 957 } 958 959 /** 960 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 961 * @adapter: Board private structure. 962 * 963 * If we were asked to do hardware stamping and such a time stamp is 964 * available, then it must have been for this skb here because we only 965 * allow only one such packet into the queue. 966 **/ 967 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 968 { 969 struct sk_buff *skb = adapter->ptp_tx_skb; 970 struct e1000_hw *hw = &adapter->hw; 971 struct skb_shared_hwtstamps shhwtstamps; 972 u64 regval; 973 int adjust = 0; 974 975 regval = rd32(E1000_TXSTMPL); 976 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 977 978 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 979 /* adjust timestamp for the TX latency based on link speed */ 980 if (adapter->hw.mac.type == e1000_i210) { 981 switch (adapter->link_speed) { 982 case SPEED_10: 983 adjust = IGB_I210_TX_LATENCY_10; 984 break; 985 case SPEED_100: 986 adjust = IGB_I210_TX_LATENCY_100; 987 break; 988 case SPEED_1000: 989 adjust = IGB_I210_TX_LATENCY_1000; 990 break; 991 } 992 } 993 994 shhwtstamps.hwtstamp = 995 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 996 997 /* Clear the lock early before calling skb_tstamp_tx so that 998 * applications are not woken up before the lock bit is clear. We use 999 * a copy of the skb pointer to ensure other threads can't change it 1000 * while we're notifying the stack. 1001 */ 1002 adapter->ptp_tx_skb = NULL; 1003 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1004 1005 /* Notify the stack and free the skb after we've unlocked */ 1006 skb_tstamp_tx(skb, &shhwtstamps); 1007 dev_kfree_skb_any(skb); 1008 } 1009 1010 /** 1011 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 1012 * @q_vector: Pointer to interrupt specific structure 1013 * @va: Pointer to address containing Rx buffer 1014 * @timestamp: Pointer where timestamp will be stored 1015 * 1016 * This function is meant to retrieve a timestamp from the first buffer of an 1017 * incoming frame. The value is stored in little endian format starting on 1018 * byte 8 1019 * 1020 * Returns: The timestamp header length or 0 if not available 1021 **/ 1022 int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 1023 ktime_t *timestamp) 1024 { 1025 struct igb_adapter *adapter = q_vector->adapter; 1026 struct skb_shared_hwtstamps ts; 1027 __le64 *regval = (__le64 *)va; 1028 int adjust = 0; 1029 1030 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1031 return 0; 1032 1033 /* The timestamp is recorded in little endian format. 1034 * DWORD: 0 1 2 3 1035 * Field: Reserved Reserved SYSTIML SYSTIMH 1036 */ 1037 1038 /* check reserved dwords are zero, be/le doesn't matter for zero */ 1039 if (regval[0]) 1040 return 0; 1041 1042 igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1])); 1043 1044 /* adjust timestamp for the RX latency based on link speed */ 1045 if (adapter->hw.mac.type == e1000_i210) { 1046 switch (adapter->link_speed) { 1047 case SPEED_10: 1048 adjust = IGB_I210_RX_LATENCY_10; 1049 break; 1050 case SPEED_100: 1051 adjust = IGB_I210_RX_LATENCY_100; 1052 break; 1053 case SPEED_1000: 1054 adjust = IGB_I210_RX_LATENCY_1000; 1055 break; 1056 } 1057 } 1058 1059 *timestamp = ktime_sub_ns(ts.hwtstamp, adjust); 1060 1061 return IGB_TS_HDR_LEN; 1062 } 1063 1064 /** 1065 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 1066 * @q_vector: Pointer to interrupt specific structure 1067 * @skb: Buffer containing timestamp and packet 1068 * 1069 * This function is meant to retrieve a timestamp from the internal registers 1070 * of the adapter and store it in the skb. 1071 **/ 1072 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) 1073 { 1074 struct igb_adapter *adapter = q_vector->adapter; 1075 struct e1000_hw *hw = &adapter->hw; 1076 int adjust = 0; 1077 u64 regval; 1078 1079 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1080 return; 1081 1082 /* If this bit is set, then the RX registers contain the time stamp. No 1083 * other packet will be time stamped until we read these registers, so 1084 * read the registers to make them available again. Because only one 1085 * packet can be time stamped at a time, we know that the register 1086 * values must belong to this one here and therefore we don't need to 1087 * compare any of the additional attributes stored for it. 1088 * 1089 * If nothing went wrong, then it should have a shared tx_flags that we 1090 * can turn into a skb_shared_hwtstamps. 1091 */ 1092 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 1093 return; 1094 1095 regval = rd32(E1000_RXSTMPL); 1096 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 1097 1098 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 1099 1100 /* adjust timestamp for the RX latency based on link speed */ 1101 if (adapter->hw.mac.type == e1000_i210) { 1102 switch (adapter->link_speed) { 1103 case SPEED_10: 1104 adjust = IGB_I210_RX_LATENCY_10; 1105 break; 1106 case SPEED_100: 1107 adjust = IGB_I210_RX_LATENCY_100; 1108 break; 1109 case SPEED_1000: 1110 adjust = IGB_I210_RX_LATENCY_1000; 1111 break; 1112 } 1113 } 1114 skb_hwtstamps(skb)->hwtstamp = 1115 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 1116 1117 /* Update the last_rx_timestamp timer in order to enable watchdog check 1118 * for error case of latched timestamp on a dropped packet. 1119 */ 1120 adapter->last_rx_timestamp = jiffies; 1121 } 1122 1123 /** 1124 * igb_ptp_get_ts_config - get hardware time stamping config 1125 * @netdev: netdev struct 1126 * @ifr: interface struct 1127 * 1128 * Get the hwtstamp_config settings to return to the user. Rather than attempt 1129 * to deconstruct the settings from the registers, just return a shadow copy 1130 * of the last known settings. 1131 **/ 1132 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 1133 { 1134 struct igb_adapter *adapter = netdev_priv(netdev); 1135 struct hwtstamp_config *config = &adapter->tstamp_config; 1136 1137 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 1138 -EFAULT : 0; 1139 } 1140 1141 /** 1142 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 1143 * @adapter: networking device structure 1144 * @config: hwtstamp configuration 1145 * 1146 * Outgoing time stamping can be enabled and disabled. Play nice and 1147 * disable it when requested, although it shouldn't case any overhead 1148 * when no packet needs it. At most one packet in the queue may be 1149 * marked for time stamping, otherwise it would be impossible to tell 1150 * for sure to which packet the hardware time stamp belongs. 1151 * 1152 * Incoming time stamping has to be configured via the hardware 1153 * filters. Not all combinations are supported, in particular event 1154 * type has to be specified. Matching the kind of event packet is 1155 * not supported, with the exception of "all V2 events regardless of 1156 * level 2 or 4". 1157 */ 1158 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 1159 struct hwtstamp_config *config) 1160 { 1161 struct e1000_hw *hw = &adapter->hw; 1162 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 1163 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1164 u32 tsync_rx_cfg = 0; 1165 bool is_l4 = false; 1166 bool is_l2 = false; 1167 u32 regval; 1168 1169 switch (config->tx_type) { 1170 case HWTSTAMP_TX_OFF: 1171 tsync_tx_ctl = 0; 1172 break; 1173 case HWTSTAMP_TX_ON: 1174 break; 1175 default: 1176 return -ERANGE; 1177 } 1178 1179 switch (config->rx_filter) { 1180 case HWTSTAMP_FILTER_NONE: 1181 tsync_rx_ctl = 0; 1182 break; 1183 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1184 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1185 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 1186 is_l4 = true; 1187 break; 1188 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1189 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1190 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 1191 is_l4 = true; 1192 break; 1193 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1194 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1195 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1196 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1197 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1198 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1199 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1200 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1201 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1202 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 1203 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1204 is_l2 = true; 1205 is_l4 = true; 1206 break; 1207 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1208 case HWTSTAMP_FILTER_NTP_ALL: 1209 case HWTSTAMP_FILTER_ALL: 1210 /* 82576 cannot timestamp all packets, which it needs to do to 1211 * support both V1 Sync and Delay_Req messages 1212 */ 1213 if (hw->mac.type != e1000_82576) { 1214 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1215 config->rx_filter = HWTSTAMP_FILTER_ALL; 1216 break; 1217 } 1218 fallthrough; 1219 default: 1220 config->rx_filter = HWTSTAMP_FILTER_NONE; 1221 return -ERANGE; 1222 } 1223 1224 if (hw->mac.type == e1000_82575) { 1225 if (tsync_rx_ctl | tsync_tx_ctl) 1226 return -EINVAL; 1227 return 0; 1228 } 1229 1230 /* Per-packet timestamping only works if all packets are 1231 * timestamped, so enable timestamping in all packets as 1232 * long as one Rx filter was configured. 1233 */ 1234 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1235 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1236 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1237 config->rx_filter = HWTSTAMP_FILTER_ALL; 1238 is_l2 = true; 1239 is_l4 = true; 1240 1241 if ((hw->mac.type == e1000_i210) || 1242 (hw->mac.type == e1000_i211)) { 1243 regval = rd32(E1000_RXPBS); 1244 regval |= E1000_RXPBS_CFG_TS_EN; 1245 wr32(E1000_RXPBS, regval); 1246 } 1247 } 1248 1249 /* enable/disable TX */ 1250 regval = rd32(E1000_TSYNCTXCTL); 1251 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1252 regval |= tsync_tx_ctl; 1253 wr32(E1000_TSYNCTXCTL, regval); 1254 1255 /* enable/disable RX */ 1256 regval = rd32(E1000_TSYNCRXCTL); 1257 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1258 regval |= tsync_rx_ctl; 1259 wr32(E1000_TSYNCRXCTL, regval); 1260 1261 /* define which PTP packets are time stamped */ 1262 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1263 1264 /* define ethertype filter for timestamped packets */ 1265 if (is_l2) 1266 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1267 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1268 E1000_ETQF_1588 | /* enable timestamping */ 1269 ETH_P_1588)); /* 1588 eth protocol type */ 1270 else 1271 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1272 1273 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1274 if (is_l4) { 1275 u32 ftqf = (IPPROTO_UDP /* UDP */ 1276 | E1000_FTQF_VF_BP /* VF not compared */ 1277 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1278 | E1000_FTQF_MASK); /* mask all inputs */ 1279 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1280 1281 wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT)); 1282 wr32(E1000_IMIREXT(3), 1283 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1284 if (hw->mac.type == e1000_82576) { 1285 /* enable source port check */ 1286 wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT)); 1287 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1288 } 1289 wr32(E1000_FTQF(3), ftqf); 1290 } else { 1291 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1292 } 1293 wrfl(); 1294 1295 /* clear TX/RX time stamp registers, just to be sure */ 1296 regval = rd32(E1000_TXSTMPL); 1297 regval = rd32(E1000_TXSTMPH); 1298 regval = rd32(E1000_RXSTMPL); 1299 regval = rd32(E1000_RXSTMPH); 1300 1301 return 0; 1302 } 1303 1304 /** 1305 * igb_ptp_set_ts_config - set hardware time stamping config 1306 * @netdev: netdev struct 1307 * @ifr: interface struct 1308 * 1309 **/ 1310 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1311 { 1312 struct igb_adapter *adapter = netdev_priv(netdev); 1313 struct hwtstamp_config config; 1314 int err; 1315 1316 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1317 return -EFAULT; 1318 1319 err = igb_ptp_set_timestamp_mode(adapter, &config); 1320 if (err) 1321 return err; 1322 1323 /* save these settings for future reference */ 1324 memcpy(&adapter->tstamp_config, &config, 1325 sizeof(adapter->tstamp_config)); 1326 1327 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1328 -EFAULT : 0; 1329 } 1330 1331 /** 1332 * igb_ptp_init - Initialize PTP functionality 1333 * @adapter: Board private structure 1334 * 1335 * This function is called at device probe to initialize the PTP 1336 * functionality. 1337 */ 1338 void igb_ptp_init(struct igb_adapter *adapter) 1339 { 1340 struct e1000_hw *hw = &adapter->hw; 1341 struct net_device *netdev = adapter->netdev; 1342 1343 switch (hw->mac.type) { 1344 case e1000_82576: 1345 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1346 adapter->ptp_caps.owner = THIS_MODULE; 1347 adapter->ptp_caps.max_adj = 999999881; 1348 adapter->ptp_caps.n_ext_ts = 0; 1349 adapter->ptp_caps.pps = 0; 1350 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1351 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1352 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; 1353 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1354 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1355 adapter->cc.read = igb_ptp_read_82576; 1356 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1357 adapter->cc.mult = 1; 1358 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1359 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1360 break; 1361 case e1000_82580: 1362 case e1000_i354: 1363 case e1000_i350: 1364 igb_ptp_sdp_init(adapter); 1365 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1366 adapter->ptp_caps.owner = THIS_MODULE; 1367 adapter->ptp_caps.max_adj = 62499999; 1368 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1369 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1370 adapter->ptp_caps.n_pins = IGB_N_SDP; 1371 adapter->ptp_caps.pps = 0; 1372 adapter->ptp_caps.pin_config = adapter->sdp_config; 1373 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1374 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1375 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; 1376 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1377 adapter->ptp_caps.enable = igb_ptp_feature_enable_82580; 1378 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1379 adapter->cc.read = igb_ptp_read_82580; 1380 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1381 adapter->cc.mult = 1; 1382 adapter->cc.shift = 0; 1383 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1384 break; 1385 case e1000_i210: 1386 case e1000_i211: 1387 igb_ptp_sdp_init(adapter); 1388 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1389 adapter->ptp_caps.owner = THIS_MODULE; 1390 adapter->ptp_caps.max_adj = 62499999; 1391 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1392 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1393 adapter->ptp_caps.n_pins = IGB_N_SDP; 1394 adapter->ptp_caps.pps = 1; 1395 adapter->ptp_caps.pin_config = adapter->sdp_config; 1396 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1397 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1398 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; 1399 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1400 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1401 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1402 break; 1403 default: 1404 adapter->ptp_clock = NULL; 1405 return; 1406 } 1407 1408 spin_lock_init(&adapter->tmreg_lock); 1409 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1410 1411 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1412 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1413 igb_ptp_overflow_check); 1414 1415 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1416 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1417 1418 igb_ptp_reset(adapter); 1419 1420 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1421 &adapter->pdev->dev); 1422 if (IS_ERR(adapter->ptp_clock)) { 1423 adapter->ptp_clock = NULL; 1424 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1425 } else if (adapter->ptp_clock) { 1426 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1427 adapter->netdev->name); 1428 adapter->ptp_flags |= IGB_PTP_ENABLED; 1429 } 1430 } 1431 1432 /** 1433 * igb_ptp_sdp_init - utility function which inits the SDP config structs 1434 * @adapter: Board private structure. 1435 **/ 1436 void igb_ptp_sdp_init(struct igb_adapter *adapter) 1437 { 1438 int i; 1439 1440 for (i = 0; i < IGB_N_SDP; i++) { 1441 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1442 1443 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1444 ppd->index = i; 1445 ppd->func = PTP_PF_NONE; 1446 } 1447 } 1448 1449 /** 1450 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1451 * @adapter: Board private structure 1452 * 1453 * This function stops the overflow check work and PTP Tx timestamp work, and 1454 * will prepare the device for OS suspend. 1455 */ 1456 void igb_ptp_suspend(struct igb_adapter *adapter) 1457 { 1458 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1459 return; 1460 1461 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1462 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1463 1464 cancel_work_sync(&adapter->ptp_tx_work); 1465 if (adapter->ptp_tx_skb) { 1466 dev_kfree_skb_any(adapter->ptp_tx_skb); 1467 adapter->ptp_tx_skb = NULL; 1468 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1469 } 1470 } 1471 1472 /** 1473 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1474 * @adapter: Board private structure. 1475 * 1476 * This function stops the PTP support and cancels the delayed work. 1477 **/ 1478 void igb_ptp_stop(struct igb_adapter *adapter) 1479 { 1480 igb_ptp_suspend(adapter); 1481 1482 if (adapter->ptp_clock) { 1483 ptp_clock_unregister(adapter->ptp_clock); 1484 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1485 adapter->netdev->name); 1486 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1487 } 1488 } 1489 1490 /** 1491 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1492 * @adapter: Board private structure. 1493 * 1494 * This function handles the reset work required to re-enable the PTP device. 1495 **/ 1496 void igb_ptp_reset(struct igb_adapter *adapter) 1497 { 1498 struct e1000_hw *hw = &adapter->hw; 1499 unsigned long flags; 1500 1501 /* reset the tstamp_config */ 1502 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1503 1504 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1505 1506 switch (adapter->hw.mac.type) { 1507 case e1000_82576: 1508 /* Dial the nominal frequency. */ 1509 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1510 break; 1511 case e1000_82580: 1512 case e1000_i354: 1513 case e1000_i350: 1514 case e1000_i210: 1515 case e1000_i211: 1516 wr32(E1000_TSAUXC, 0x0); 1517 wr32(E1000_TSSDP, 0x0); 1518 wr32(E1000_TSIM, 1519 TSYNC_INTERRUPTS | 1520 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1521 wr32(E1000_IMS, E1000_IMS_TS); 1522 break; 1523 default: 1524 /* No work to do. */ 1525 goto out; 1526 } 1527 1528 /* Re-initialize the timer. */ 1529 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1530 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1531 1532 igb_ptp_write_i210(adapter, &ts); 1533 } else { 1534 timecounter_init(&adapter->tc, &adapter->cc, 1535 ktime_to_ns(ktime_get_real())); 1536 } 1537 out: 1538 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1539 1540 wrfl(); 1541 1542 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1543 schedule_delayed_work(&adapter->ptp_overflow_work, 1544 IGB_SYSTIM_OVERFLOW_PERIOD); 1545 } 1546