1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX8 NWL MIPI DSI host driver 4 * 5 * Copyright (C) 2017 NXP 6 * Copyright (C) 2020 Purism SPC 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/irq.h> 13 #include <linux/math64.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/mux/consumer.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/phy/phy.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 #include <linux/sys_soc.h> 23 #include <linux/time64.h> 24 25 #include <drm/drm_atomic_state_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_panel.h> 30 #include <drm/drm_print.h> 31 32 #include <video/mipi_display.h> 33 34 #include "nwl-dsi.h" 35 36 #define DRV_NAME "nwl-dsi" 37 38 /* i.MX8 NWL quirks */ 39 /* i.MX8MQ errata E11418 */ 40 #define E11418_HS_MODE_QUIRK BIT(0) 41 42 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500) 43 44 enum transfer_direction { 45 DSI_PACKET_SEND, 46 DSI_PACKET_RECEIVE, 47 }; 48 49 #define NWL_DSI_ENDPOINT_LCDIF 0 50 #define NWL_DSI_ENDPOINT_DCSS 1 51 52 struct nwl_dsi_transfer { 53 const struct mipi_dsi_msg *msg; 54 struct mipi_dsi_packet packet; 55 struct completion completed; 56 57 int status; /* status of transmission */ 58 enum transfer_direction direction; 59 bool need_bta; 60 u8 cmd; 61 u16 rx_word_count; 62 size_t tx_len; /* in bytes */ 63 size_t rx_len; /* in bytes */ 64 }; 65 66 struct nwl_dsi { 67 struct drm_bridge bridge; 68 struct mipi_dsi_host dsi_host; 69 struct device *dev; 70 struct phy *phy; 71 union phy_configure_opts phy_cfg; 72 unsigned int quirks; 73 74 struct regmap *regmap; 75 int irq; 76 /* 77 * The DSI host controller needs this reset sequence according to NWL: 78 * 1. Deassert pclk reset to get access to DSI regs 79 * 2. Configure DSI Host and DPHY and enable DPHY 80 * 3. Deassert ESC and BYTE resets to allow host TX operations) 81 * 4. Send DSI cmds to configure peripheral (handled by panel drv) 82 * 5. Deassert DPI reset so DPI receives pixels and starts sending 83 * DSI data 84 * 85 * TODO: Since panel_bridges do their DSI setup in enable we 86 * currently have 4. and 5. swapped. 87 */ 88 struct reset_control *rst_byte; 89 struct reset_control *rst_esc; 90 struct reset_control *rst_dpi; 91 struct reset_control *rst_pclk; 92 struct mux_control *mux; 93 94 /* DSI clocks */ 95 struct clk *phy_ref_clk; 96 struct clk *rx_esc_clk; 97 struct clk *tx_esc_clk; 98 struct clk *core_clk; 99 /* 100 * hardware bug: the i.MX8MQ needs this clock on during reset 101 * even when not using LCDIF. 102 */ 103 struct clk *lcdif_clk; 104 105 /* dsi lanes */ 106 u32 lanes; 107 enum mipi_dsi_pixel_format format; 108 struct drm_display_mode mode; 109 unsigned long dsi_mode_flags; 110 int error; 111 112 struct nwl_dsi_transfer *xfer; 113 }; 114 115 static const struct regmap_config nwl_dsi_regmap_config = { 116 .reg_bits = 16, 117 .val_bits = 32, 118 .reg_stride = 4, 119 .max_register = NWL_DSI_IRQ_MASK2, 120 .name = DRV_NAME, 121 }; 122 123 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge) 124 { 125 return container_of(bridge, struct nwl_dsi, bridge); 126 } 127 128 static int nwl_dsi_clear_error(struct nwl_dsi *dsi) 129 { 130 int ret = dsi->error; 131 132 dsi->error = 0; 133 return ret; 134 } 135 136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val) 137 { 138 int ret; 139 140 if (dsi->error) 141 return; 142 143 ret = regmap_write(dsi->regmap, reg, val); 144 if (ret < 0) { 145 DRM_DEV_ERROR(dsi->dev, 146 "Failed to write NWL DSI reg 0x%x: %d\n", reg, 147 ret); 148 dsi->error = ret; 149 } 150 } 151 152 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg) 153 { 154 unsigned int val; 155 int ret; 156 157 if (dsi->error) 158 return 0; 159 160 ret = regmap_read(dsi->regmap, reg, &val); 161 if (ret < 0) { 162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", 163 reg, ret); 164 dsi->error = ret; 165 } 166 return val; 167 } 168 169 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format) 170 { 171 switch (format) { 172 case MIPI_DSI_FMT_RGB565: 173 return NWL_DSI_PIXEL_FORMAT_16; 174 case MIPI_DSI_FMT_RGB666: 175 return NWL_DSI_PIXEL_FORMAT_18L; 176 case MIPI_DSI_FMT_RGB666_PACKED: 177 return NWL_DSI_PIXEL_FORMAT_18; 178 case MIPI_DSI_FMT_RGB888: 179 return NWL_DSI_PIXEL_FORMAT_24; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 /* 186 * ps2bc - Picoseconds to byte clock cycles 187 */ 188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) 189 { 190 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 191 192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, 193 dsi->lanes * 8ULL * NSEC_PER_SEC); 194 } 195 196 /* 197 * ui2bc - UI time periods to byte clock cycles 198 */ 199 static u32 ui2bc(unsigned int ui) 200 { 201 return DIV_ROUND_UP(ui, BITS_PER_BYTE); 202 } 203 204 /* 205 * us2bc - micro seconds to lp clock cycles 206 */ 207 static u32 us2lp(u32 lp_clk_rate, unsigned long us) 208 { 209 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC); 210 } 211 212 static int nwl_dsi_config_host(struct nwl_dsi *dsi) 213 { 214 u32 cycles; 215 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; 216 217 if (dsi->lanes < 1 || dsi->lanes > 4) 218 return -EINVAL; 219 220 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); 221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); 222 223 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 224 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); 225 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); 226 } else { 227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); 228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); 229 } 230 231 /* values in byte clock cycles */ 232 cycles = ui2bc(cfg->clk_pre); 233 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); 234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); 235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); 236 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); 237 cycles += ui2bc(cfg->clk_pre); 238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); 239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); 240 cycles = ps2bc(dsi, cfg->hs_exit); 241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); 242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); 243 244 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01); 245 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00); 246 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00); 247 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00); 248 /* In LP clock cycles */ 249 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); 250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); 251 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles); 252 253 return nwl_dsi_clear_error(dsi); 254 } 255 256 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) 257 { 258 u32 mode; 259 int color_format; 260 bool burst_mode; 261 int hfront_porch, hback_porch, vfront_porch, vback_porch; 262 int hsync_len, vsync_len; 263 264 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; 265 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; 266 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; 267 268 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; 269 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; 270 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; 271 272 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); 273 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); 274 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); 275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); 276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); 277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); 278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); 279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); 280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); 281 282 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); 283 if (color_format < 0) { 284 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", 285 dsi->format); 286 return color_format; 287 } 288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); 289 290 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); 291 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); 292 /* 293 * Adjusting input polarity based on the video mode results in 294 * a black screen so always pick active low: 295 */ 296 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, 297 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW); 298 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, 299 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW); 300 301 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && 302 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); 303 304 if (burst_mode) { 305 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE); 306 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256); 307 } else { 308 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? 309 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES : 310 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS); 311 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode); 312 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 313 dsi->mode.hdisplay); 314 } 315 316 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); 317 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); 318 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); 319 320 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); 321 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); 322 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0); 323 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0); 324 325 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); 326 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); 327 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch); 328 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch); 329 330 return nwl_dsi_clear_error(dsi); 331 } 332 333 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) 334 { 335 u32 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | 336 NWL_DSI_RX_PKT_HDR_RCVD_MASK | 337 NWL_DSI_TX_FIFO_OVFLW_MASK | 338 NWL_DSI_HS_TX_TIMEOUT_MASK); 339 340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable); 341 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7); 342 343 return nwl_dsi_clear_error(dsi); 344 } 345 346 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host, 347 struct mipi_dsi_device *device) 348 { 349 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 350 struct device *dev = dsi->dev; 351 352 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes, 353 device->format, device->mode_flags); 354 355 if (device->lanes < 1 || device->lanes > 4) 356 return -EINVAL; 357 358 dsi->lanes = device->lanes; 359 dsi->format = device->format; 360 dsi->dsi_mode_flags = device->mode_flags; 361 362 return 0; 363 } 364 365 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) 366 { 367 struct device *dev = dsi->dev; 368 struct nwl_dsi_transfer *xfer = dsi->xfer; 369 int err; 370 u8 *payload = xfer->msg->rx_buf; 371 u32 val; 372 u16 word_count; 373 u8 channel; 374 u8 data_type; 375 376 xfer->status = 0; 377 378 if (xfer->rx_word_count == 0) { 379 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD)) 380 return false; 381 /* Get the RX header and parse it */ 382 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER); 383 err = nwl_dsi_clear_error(dsi); 384 if (err) 385 xfer->status = err; 386 word_count = NWL_DSI_WC(val); 387 channel = NWL_DSI_RX_VC(val); 388 data_type = NWL_DSI_RX_DT(val); 389 390 if (channel != xfer->msg->channel) { 391 DRM_DEV_ERROR(dev, 392 "[%02X] Channel mismatch (%u != %u)\n", 393 xfer->cmd, channel, xfer->msg->channel); 394 xfer->status = -EINVAL; 395 return true; 396 } 397 398 switch (data_type) { 399 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 400 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 401 if (xfer->msg->rx_len > 1) { 402 /* read second byte */ 403 payload[1] = word_count >> 8; 404 ++xfer->rx_len; 405 } 406 fallthrough; 407 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 408 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 409 if (xfer->msg->rx_len > 0) { 410 /* read first byte */ 411 payload[0] = word_count & 0xff; 412 ++xfer->rx_len; 413 } 414 xfer->status = xfer->rx_len; 415 return true; 416 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 417 word_count &= 0xff; 418 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n", 419 xfer->cmd, word_count); 420 xfer->status = -EPROTO; 421 return true; 422 } 423 424 if (word_count > xfer->msg->rx_len) { 425 DRM_DEV_ERROR(dev, 426 "[%02X] Receive buffer too small: %zu (< %u)\n", 427 xfer->cmd, xfer->msg->rx_len, word_count); 428 xfer->status = -EINVAL; 429 return true; 430 } 431 432 xfer->rx_word_count = word_count; 433 } else { 434 /* Set word_count from previous header read */ 435 word_count = xfer->rx_word_count; 436 } 437 438 /* If RX payload is not yet received, wait for it */ 439 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)) 440 return false; 441 442 /* Read the RX payload */ 443 while (word_count >= 4) { 444 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 445 payload[0] = (val >> 0) & 0xff; 446 payload[1] = (val >> 8) & 0xff; 447 payload[2] = (val >> 16) & 0xff; 448 payload[3] = (val >> 24) & 0xff; 449 payload += 4; 450 xfer->rx_len += 4; 451 word_count -= 4; 452 } 453 454 if (word_count > 0) { 455 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 456 switch (word_count) { 457 case 3: 458 payload[2] = (val >> 16) & 0xff; 459 ++xfer->rx_len; 460 fallthrough; 461 case 2: 462 payload[1] = (val >> 8) & 0xff; 463 ++xfer->rx_len; 464 fallthrough; 465 case 1: 466 payload[0] = (val >> 0) & 0xff; 467 ++xfer->rx_len; 468 break; 469 } 470 } 471 472 xfer->status = xfer->rx_len; 473 err = nwl_dsi_clear_error(dsi); 474 if (err) 475 xfer->status = err; 476 477 return true; 478 } 479 480 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) 481 { 482 struct nwl_dsi_transfer *xfer = dsi->xfer; 483 bool end_packet = false; 484 485 if (!xfer) 486 return; 487 488 if (xfer->direction == DSI_PACKET_SEND && 489 status & NWL_DSI_TX_PKT_DONE) { 490 xfer->status = xfer->tx_len; 491 end_packet = true; 492 } else if (status & NWL_DSI_DPHY_DIRECTION && 493 ((status & (NWL_DSI_RX_PKT_HDR_RCVD | 494 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { 495 end_packet = nwl_dsi_read_packet(dsi, status); 496 } 497 498 if (end_packet) 499 complete(&xfer->completed); 500 } 501 502 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi) 503 { 504 struct nwl_dsi_transfer *xfer = dsi->xfer; 505 struct mipi_dsi_packet *pkt = &xfer->packet; 506 const u8 *payload; 507 size_t length; 508 u16 word_count; 509 u8 hs_mode; 510 u32 val; 511 u32 hs_workaround = 0; 512 513 /* Send the payload, if any */ 514 length = pkt->payload_length; 515 payload = pkt->payload; 516 517 while (length >= 4) { 518 val = *(u32 *)payload; 519 hs_workaround |= !(val & 0xFFFF00); 520 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 521 payload += 4; 522 length -= 4; 523 } 524 /* Send the rest of the payload */ 525 val = 0; 526 switch (length) { 527 case 3: 528 val |= payload[2] << 16; 529 fallthrough; 530 case 2: 531 val |= payload[1] << 8; 532 hs_workaround |= !(val & 0xFFFF00); 533 fallthrough; 534 case 1: 535 val |= payload[0]; 536 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 537 break; 538 } 539 xfer->tx_len = pkt->payload_length; 540 541 /* 542 * Send the header 543 * header[0] = Virtual Channel + Data Type 544 * header[1] = Word Count LSB (LP) or first param (SP) 545 * header[2] = Word Count MSB (LP) or second param (SP) 546 */ 547 word_count = pkt->header[1] | (pkt->header[2] << 8); 548 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { 549 DRM_DEV_DEBUG_DRIVER(dsi->dev, 550 "Using hs mode workaround for cmd 0x%x\n", 551 xfer->cmd); 552 hs_mode = 1; 553 } else { 554 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1; 555 } 556 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) | 557 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) | 558 NWL_DSI_BTA_TX(xfer->need_bta); 559 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val); 560 561 /* Send packet command */ 562 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1); 563 } 564 565 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host, 566 const struct mipi_dsi_msg *msg) 567 { 568 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 569 struct nwl_dsi_transfer xfer; 570 ssize_t ret = 0; 571 572 /* Create packet to be sent */ 573 dsi->xfer = &xfer; 574 ret = mipi_dsi_create_packet(&xfer.packet, msg); 575 if (ret < 0) { 576 dsi->xfer = NULL; 577 return ret; 578 } 579 580 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM || 581 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM || 582 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM || 583 msg->type & MIPI_DSI_DCS_READ) && 584 msg->rx_len > 0 && msg->rx_buf) 585 xfer.direction = DSI_PACKET_RECEIVE; 586 else 587 xfer.direction = DSI_PACKET_SEND; 588 589 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE); 590 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0; 591 xfer.msg = msg; 592 xfer.status = -ETIMEDOUT; 593 xfer.rx_word_count = 0; 594 xfer.rx_len = 0; 595 xfer.cmd = 0x00; 596 if (msg->tx_len > 0) 597 xfer.cmd = ((u8 *)(msg->tx_buf))[0]; 598 init_completion(&xfer.completed); 599 600 ret = clk_prepare_enable(dsi->rx_esc_clk); 601 if (ret < 0) { 602 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", 603 ret); 604 return ret; 605 } 606 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", 607 clk_get_rate(dsi->rx_esc_clk)); 608 609 /* Initiate the DSI packet transmision */ 610 nwl_dsi_begin_transmission(dsi); 611 612 if (!wait_for_completion_timeout(&xfer.completed, 613 NWL_DSI_MIPI_FIFO_TIMEOUT)) { 614 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", 615 xfer.cmd); 616 ret = -ETIMEDOUT; 617 } else { 618 ret = xfer.status; 619 } 620 621 clk_disable_unprepare(dsi->rx_esc_clk); 622 623 return ret; 624 } 625 626 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = { 627 .attach = nwl_dsi_host_attach, 628 .transfer = nwl_dsi_host_transfer, 629 }; 630 631 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data) 632 { 633 u32 irq_status; 634 struct nwl_dsi *dsi = data; 635 636 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS); 637 638 if (irq_status & NWL_DSI_TX_FIFO_OVFLW) 639 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); 640 641 if (irq_status & NWL_DSI_HS_TX_TIMEOUT) 642 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); 643 644 if (irq_status & NWL_DSI_TX_PKT_DONE || 645 irq_status & NWL_DSI_RX_PKT_HDR_RCVD || 646 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD) 647 nwl_dsi_finish_transmission(dsi, irq_status); 648 649 return IRQ_HANDLED; 650 } 651 652 static int nwl_dsi_mode_set(struct nwl_dsi *dsi) 653 { 654 struct device *dev = dsi->dev; 655 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; 656 int ret; 657 658 if (!dsi->lanes) { 659 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); 660 return -EINVAL; 661 } 662 663 ret = phy_init(dsi->phy); 664 if (ret < 0) { 665 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret); 666 return ret; 667 } 668 669 ret = phy_configure(dsi->phy, phy_cfg); 670 if (ret < 0) { 671 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); 672 goto uninit_phy; 673 } 674 675 ret = clk_prepare_enable(dsi->tx_esc_clk); 676 if (ret < 0) { 677 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", 678 ret); 679 goto uninit_phy; 680 } 681 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", 682 clk_get_rate(dsi->tx_esc_clk)); 683 684 ret = nwl_dsi_config_host(dsi); 685 if (ret < 0) { 686 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret); 687 goto disable_clock; 688 } 689 690 ret = nwl_dsi_config_dpi(dsi); 691 if (ret < 0) { 692 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret); 693 goto disable_clock; 694 } 695 696 ret = phy_power_on(dsi->phy); 697 if (ret < 0) { 698 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret); 699 goto disable_clock; 700 } 701 702 ret = nwl_dsi_init_interrupts(dsi); 703 if (ret < 0) 704 goto power_off_phy; 705 706 return ret; 707 708 power_off_phy: 709 phy_power_off(dsi->phy); 710 disable_clock: 711 clk_disable_unprepare(dsi->tx_esc_clk); 712 uninit_phy: 713 phy_exit(dsi->phy); 714 715 return ret; 716 } 717 718 static int nwl_dsi_disable(struct nwl_dsi *dsi) 719 { 720 struct device *dev = dsi->dev; 721 722 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n"); 723 724 phy_power_off(dsi->phy); 725 phy_exit(dsi->phy); 726 727 /* Disabling the clock before the phy breaks enabling dsi again */ 728 clk_disable_unprepare(dsi->tx_esc_clk); 729 730 return 0; 731 } 732 733 static void 734 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 735 struct drm_bridge_state *old_bridge_state) 736 { 737 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 738 int ret; 739 740 nwl_dsi_disable(dsi); 741 742 ret = reset_control_assert(dsi->rst_dpi); 743 if (ret < 0) { 744 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); 745 return; 746 } 747 ret = reset_control_assert(dsi->rst_byte); 748 if (ret < 0) { 749 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); 750 return; 751 } 752 ret = reset_control_assert(dsi->rst_esc); 753 if (ret < 0) { 754 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); 755 return; 756 } 757 ret = reset_control_assert(dsi->rst_pclk); 758 if (ret < 0) { 759 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); 760 return; 761 } 762 763 clk_disable_unprepare(dsi->core_clk); 764 clk_disable_unprepare(dsi->lcdif_clk); 765 766 pm_runtime_put(dsi->dev); 767 } 768 769 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, 770 const struct drm_display_mode *mode, 771 union phy_configure_opts *phy_opts) 772 { 773 unsigned long rate; 774 int ret; 775 776 if (dsi->lanes < 1 || dsi->lanes > 4) 777 return -EINVAL; 778 779 /* 780 * So far the DPHY spec minimal timings work for both mixel 781 * dphy and nwl dsi host 782 */ 783 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000, 784 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, 785 &phy_opts->mipi_dphy); 786 if (ret < 0) 787 return ret; 788 789 rate = clk_get_rate(dsi->tx_esc_clk); 790 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); 791 phy_opts->mipi_dphy.lp_clk_rate = rate; 792 793 return 0; 794 } 795 796 static enum drm_mode_status 797 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, 798 const struct drm_display_info *info, 799 const struct drm_display_mode *mode) 800 { 801 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 802 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 803 804 if (mode->clock * bpp > 15000000 * dsi->lanes) 805 return MODE_CLOCK_HIGH; 806 807 if (mode->clock * bpp < 80000 * dsi->lanes) 808 return MODE_CLOCK_LOW; 809 810 return MODE_OK; 811 } 812 813 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge, 814 struct drm_bridge_state *bridge_state, 815 struct drm_crtc_state *crtc_state, 816 struct drm_connector_state *conn_state) 817 { 818 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 819 820 /* At least LCDIF + NWL needs active high sync */ 821 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 822 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 823 824 /* 825 * Do a full modeset if crtc_state->active is changed to be true. 826 * This ensures our ->mode_set() is called to get the DSI controller 827 * and the PHY ready to send DCS commands, when only the connector's 828 * DPMS is brought out of "Off" status. 829 */ 830 if (crtc_state->active_changed && crtc_state->active) 831 crtc_state->mode_changed = true; 832 833 return 0; 834 } 835 836 static void 837 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, 838 const struct drm_display_mode *mode, 839 const struct drm_display_mode *adjusted_mode) 840 { 841 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 842 struct device *dev = dsi->dev; 843 union phy_configure_opts new_cfg; 844 unsigned long phy_ref_rate; 845 int ret; 846 847 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg); 848 if (ret < 0) 849 return; 850 851 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); 852 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); 853 /* Save the new desired phy config */ 854 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); 855 856 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode)); 857 drm_mode_debug_printmodeline(adjusted_mode); 858 859 if (pm_runtime_resume_and_get(dev) < 0) 860 return; 861 862 if (clk_prepare_enable(dsi->lcdif_clk) < 0) 863 goto runtime_put; 864 if (clk_prepare_enable(dsi->core_clk) < 0) 865 goto runtime_put; 866 867 /* Step 1 from DSI reset-out instructions */ 868 ret = reset_control_deassert(dsi->rst_pclk); 869 if (ret < 0) { 870 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret); 871 goto runtime_put; 872 } 873 874 /* Step 2 from DSI reset-out instructions */ 875 nwl_dsi_mode_set(dsi); 876 877 /* Step 3 from DSI reset-out instructions */ 878 ret = reset_control_deassert(dsi->rst_esc); 879 if (ret < 0) { 880 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret); 881 goto runtime_put; 882 } 883 ret = reset_control_deassert(dsi->rst_byte); 884 if (ret < 0) { 885 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret); 886 goto runtime_put; 887 } 888 889 return; 890 891 runtime_put: 892 pm_runtime_put_sync(dev); 893 } 894 895 static void 896 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 897 struct drm_bridge_state *old_bridge_state) 898 { 899 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 900 int ret; 901 902 /* Step 5 from DSI reset-out instructions */ 903 ret = reset_control_deassert(dsi->rst_dpi); 904 if (ret < 0) 905 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); 906 } 907 908 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, 909 enum drm_bridge_attach_flags flags) 910 { 911 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 912 struct drm_bridge *panel_bridge; 913 struct drm_panel *panel; 914 int ret; 915 916 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, 917 &panel_bridge); 918 if (ret) 919 return ret; 920 921 if (panel) { 922 panel_bridge = drm_panel_bridge_add(panel); 923 if (IS_ERR(panel_bridge)) 924 return PTR_ERR(panel_bridge); 925 } 926 927 if (!panel_bridge) 928 return -EPROBE_DEFER; 929 930 return drm_bridge_attach(bridge->encoder, panel_bridge, bridge, flags); 931 } 932 933 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) 934 { struct nwl_dsi *dsi = bridge_to_dsi(bridge); 935 936 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); 937 } 938 939 static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 940 struct drm_bridge_state *bridge_state, 941 struct drm_crtc_state *crtc_state, 942 struct drm_connector_state *conn_state, 943 u32 output_fmt, 944 unsigned int *num_input_fmts) 945 { 946 u32 *input_fmts, input_fmt; 947 948 *num_input_fmts = 0; 949 950 switch (output_fmt) { 951 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 952 case MEDIA_BUS_FMT_FIXED: 953 input_fmt = MEDIA_BUS_FMT_RGB888_1X24; 954 break; 955 case MEDIA_BUS_FMT_RGB888_1X24: 956 case MEDIA_BUS_FMT_RGB666_1X18: 957 case MEDIA_BUS_FMT_RGB565_1X16: 958 input_fmt = output_fmt; 959 break; 960 default: 961 return NULL; 962 } 963 964 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); 965 if (!input_fmts) 966 return NULL; 967 input_fmts[0] = input_fmt; 968 *num_input_fmts = 1; 969 970 return input_fmts; 971 } 972 973 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { 974 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 975 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 976 .atomic_reset = drm_atomic_helper_bridge_reset, 977 .atomic_check = nwl_dsi_bridge_atomic_check, 978 .atomic_enable = nwl_dsi_bridge_atomic_enable, 979 .atomic_disable = nwl_dsi_bridge_atomic_disable, 980 .atomic_get_input_bus_fmts = nwl_bridge_atomic_get_input_bus_fmts, 981 .mode_set = nwl_dsi_bridge_mode_set, 982 .mode_valid = nwl_dsi_bridge_mode_valid, 983 .attach = nwl_dsi_bridge_attach, 984 .detach = nwl_dsi_bridge_detach, 985 }; 986 987 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) 988 { 989 struct platform_device *pdev = to_platform_device(dsi->dev); 990 struct clk *clk; 991 void __iomem *base; 992 int ret; 993 994 dsi->phy = devm_phy_get(dsi->dev, "dphy"); 995 if (IS_ERR(dsi->phy)) { 996 ret = PTR_ERR(dsi->phy); 997 if (ret != -EPROBE_DEFER) 998 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); 999 return ret; 1000 } 1001 1002 clk = devm_clk_get(dsi->dev, "lcdif"); 1003 if (IS_ERR(clk)) { 1004 ret = PTR_ERR(clk); 1005 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", 1006 ret); 1007 return ret; 1008 } 1009 dsi->lcdif_clk = clk; 1010 1011 clk = devm_clk_get(dsi->dev, "core"); 1012 if (IS_ERR(clk)) { 1013 ret = PTR_ERR(clk); 1014 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", 1015 ret); 1016 return ret; 1017 } 1018 dsi->core_clk = clk; 1019 1020 clk = devm_clk_get(dsi->dev, "phy_ref"); 1021 if (IS_ERR(clk)) { 1022 ret = PTR_ERR(clk); 1023 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", 1024 ret); 1025 return ret; 1026 } 1027 dsi->phy_ref_clk = clk; 1028 1029 clk = devm_clk_get(dsi->dev, "rx_esc"); 1030 if (IS_ERR(clk)) { 1031 ret = PTR_ERR(clk); 1032 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", 1033 ret); 1034 return ret; 1035 } 1036 dsi->rx_esc_clk = clk; 1037 1038 clk = devm_clk_get(dsi->dev, "tx_esc"); 1039 if (IS_ERR(clk)) { 1040 ret = PTR_ERR(clk); 1041 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", 1042 ret); 1043 return ret; 1044 } 1045 dsi->tx_esc_clk = clk; 1046 1047 dsi->mux = devm_mux_control_get(dsi->dev, NULL); 1048 if (IS_ERR(dsi->mux)) { 1049 ret = PTR_ERR(dsi->mux); 1050 if (ret != -EPROBE_DEFER) 1051 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); 1052 return ret; 1053 } 1054 1055 base = devm_platform_ioremap_resource(pdev, 0); 1056 if (IS_ERR(base)) 1057 return PTR_ERR(base); 1058 1059 dsi->regmap = 1060 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); 1061 if (IS_ERR(dsi->regmap)) { 1062 ret = PTR_ERR(dsi->regmap); 1063 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", 1064 ret); 1065 return ret; 1066 } 1067 1068 dsi->irq = platform_get_irq(pdev, 0); 1069 if (dsi->irq < 0) { 1070 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", 1071 dsi->irq); 1072 return dsi->irq; 1073 } 1074 1075 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); 1076 if (IS_ERR(dsi->rst_pclk)) { 1077 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", 1078 PTR_ERR(dsi->rst_pclk)); 1079 return PTR_ERR(dsi->rst_pclk); 1080 } 1081 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); 1082 if (IS_ERR(dsi->rst_byte)) { 1083 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", 1084 PTR_ERR(dsi->rst_byte)); 1085 return PTR_ERR(dsi->rst_byte); 1086 } 1087 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); 1088 if (IS_ERR(dsi->rst_esc)) { 1089 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", 1090 PTR_ERR(dsi->rst_esc)); 1091 return PTR_ERR(dsi->rst_esc); 1092 } 1093 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); 1094 if (IS_ERR(dsi->rst_dpi)) { 1095 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", 1096 PTR_ERR(dsi->rst_dpi)); 1097 return PTR_ERR(dsi->rst_dpi); 1098 } 1099 return 0; 1100 } 1101 1102 static int nwl_dsi_select_input(struct nwl_dsi *dsi) 1103 { 1104 struct device_node *remote; 1105 u32 use_dcss = 1; 1106 int ret; 1107 1108 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1109 NWL_DSI_ENDPOINT_LCDIF); 1110 if (remote) { 1111 use_dcss = 0; 1112 } else { 1113 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1114 NWL_DSI_ENDPOINT_DCSS); 1115 if (!remote) { 1116 DRM_DEV_ERROR(dsi->dev, 1117 "No valid input endpoint found\n"); 1118 return -EINVAL; 1119 } 1120 } 1121 1122 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", 1123 (use_dcss) ? "DCSS" : "LCDIF"); 1124 ret = mux_control_try_select(dsi->mux, use_dcss); 1125 if (ret < 0) 1126 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); 1127 1128 of_node_put(remote); 1129 return ret; 1130 } 1131 1132 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi) 1133 { 1134 int ret; 1135 1136 ret = mux_control_deselect(dsi->mux); 1137 if (ret < 0) 1138 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); 1139 1140 return ret; 1141 } 1142 1143 static const struct drm_bridge_timings nwl_dsi_timings = { 1144 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1145 }; 1146 1147 static const struct of_device_id nwl_dsi_dt_ids[] = { 1148 { .compatible = "fsl,imx8mq-nwl-dsi", }, 1149 { /* sentinel */ } 1150 }; 1151 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids); 1152 1153 static const struct soc_device_attribute nwl_dsi_quirks_match[] = { 1154 { .soc_id = "i.MX8MQ", .revision = "2.0", 1155 .data = (void *)E11418_HS_MODE_QUIRK }, 1156 { /* sentinel. */ }, 1157 }; 1158 1159 static int nwl_dsi_probe(struct platform_device *pdev) 1160 { 1161 struct device *dev = &pdev->dev; 1162 const struct soc_device_attribute *attr; 1163 struct nwl_dsi *dsi; 1164 int ret; 1165 1166 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1167 if (!dsi) 1168 return -ENOMEM; 1169 1170 dsi->dev = dev; 1171 1172 ret = nwl_dsi_parse_dt(dsi); 1173 if (ret) 1174 return ret; 1175 1176 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, 1177 dev_name(dev), dsi); 1178 if (ret < 0) { 1179 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, 1180 ret); 1181 return ret; 1182 } 1183 1184 dsi->dsi_host.ops = &nwl_dsi_host_ops; 1185 dsi->dsi_host.dev = dev; 1186 ret = mipi_dsi_host_register(&dsi->dsi_host); 1187 if (ret) { 1188 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret); 1189 return ret; 1190 } 1191 1192 attr = soc_device_match(nwl_dsi_quirks_match); 1193 if (attr) 1194 dsi->quirks = (uintptr_t)attr->data; 1195 1196 dsi->bridge.driver_private = dsi; 1197 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; 1198 dsi->bridge.of_node = dev->of_node; 1199 dsi->bridge.timings = &nwl_dsi_timings; 1200 1201 dev_set_drvdata(dev, dsi); 1202 pm_runtime_enable(dev); 1203 1204 ret = nwl_dsi_select_input(dsi); 1205 if (ret < 0) { 1206 pm_runtime_disable(dev); 1207 mipi_dsi_host_unregister(&dsi->dsi_host); 1208 return ret; 1209 } 1210 1211 drm_bridge_add(&dsi->bridge); 1212 return 0; 1213 } 1214 1215 static int nwl_dsi_remove(struct platform_device *pdev) 1216 { 1217 struct nwl_dsi *dsi = platform_get_drvdata(pdev); 1218 1219 nwl_dsi_deselect_input(dsi); 1220 mipi_dsi_host_unregister(&dsi->dsi_host); 1221 drm_bridge_remove(&dsi->bridge); 1222 pm_runtime_disable(&pdev->dev); 1223 return 0; 1224 } 1225 1226 static struct platform_driver nwl_dsi_driver = { 1227 .probe = nwl_dsi_probe, 1228 .remove = nwl_dsi_remove, 1229 .driver = { 1230 .of_match_table = nwl_dsi_dt_ids, 1231 .name = DRV_NAME, 1232 }, 1233 }; 1234 1235 module_platform_driver(nwl_dsi_driver); 1236 1237 MODULE_AUTHOR("NXP Semiconductor"); 1238 MODULE_AUTHOR("Purism SPC"); 1239 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver"); 1240 MODULE_LICENSE("GPL"); /* GPLv2 or later */ 1241