1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/msi.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/dma-direction.h> 22 #include <scsi/scsi_device.h> 23 #include <scsi/scsi_host.h> 24 #include <ufs/unipro.h> 25 #include <ufs/ufs.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/ufshci.h> 28 29 #define UFSHCD "ufshcd" 30 31 struct scsi_device; 32 struct ufs_hba; 33 34 enum dev_cmd_type { 35 DEV_CMD_TYPE_NOP = 0x0, 36 DEV_CMD_TYPE_QUERY = 0x1, 37 DEV_CMD_TYPE_RPMB = 0x2, 38 }; 39 40 enum ufs_event_type { 41 /* uic specific errors */ 42 UFS_EVT_PA_ERR = 0, 43 UFS_EVT_DL_ERR, 44 UFS_EVT_NL_ERR, 45 UFS_EVT_TL_ERR, 46 UFS_EVT_DME_ERR, 47 48 /* fatal errors */ 49 UFS_EVT_AUTO_HIBERN8_ERR, 50 UFS_EVT_FATAL_ERR, 51 UFS_EVT_LINK_STARTUP_FAIL, 52 UFS_EVT_RESUME_ERR, 53 UFS_EVT_SUSPEND_ERR, 54 UFS_EVT_WL_SUSP_ERR, 55 UFS_EVT_WL_RES_ERR, 56 57 /* abnormal events */ 58 UFS_EVT_DEV_RESET, 59 UFS_EVT_HOST_RESET, 60 UFS_EVT_ABORT, 61 62 UFS_EVT_CNT, 63 }; 64 65 /** 66 * struct uic_command - UIC command structure 67 * @command: UIC command 68 * @argument1: UIC command argument 1 69 * @argument2: UIC command argument 2 70 * @argument3: UIC command argument 3 71 * @cmd_active: Indicate if UIC command is outstanding 72 * @done: UIC command completion 73 */ 74 struct uic_command { 75 u32 command; 76 u32 argument1; 77 u32 argument2; 78 u32 argument3; 79 int cmd_active; 80 struct completion done; 81 }; 82 83 /* Used to differentiate the power management options */ 84 enum ufs_pm_op { 85 UFS_RUNTIME_PM, 86 UFS_SYSTEM_PM, 87 UFS_SHUTDOWN_PM, 88 }; 89 90 /* Host <-> Device UniPro Link state */ 91 enum uic_link_state { 92 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 93 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 94 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 95 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 96 }; 97 98 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 99 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 100 UIC_LINK_ACTIVE_STATE) 101 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 102 UIC_LINK_HIBERN8_STATE) 103 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 104 UIC_LINK_BROKEN_STATE) 105 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 106 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 107 UIC_LINK_ACTIVE_STATE) 108 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 109 UIC_LINK_HIBERN8_STATE) 110 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 111 UIC_LINK_BROKEN_STATE) 112 113 #define ufshcd_set_ufs_dev_active(h) \ 114 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 115 #define ufshcd_set_ufs_dev_sleep(h) \ 116 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 117 #define ufshcd_set_ufs_dev_poweroff(h) \ 118 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 119 #define ufshcd_set_ufs_dev_deepsleep(h) \ 120 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 121 #define ufshcd_is_ufs_dev_active(h) \ 122 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 123 #define ufshcd_is_ufs_dev_sleep(h) \ 124 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 125 #define ufshcd_is_ufs_dev_poweroff(h) \ 126 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 127 #define ufshcd_is_ufs_dev_deepsleep(h) \ 128 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 129 130 /* 131 * UFS Power management levels. 132 * Each level is in increasing order of power savings, except DeepSleep 133 * which is lower than PowerDown with power on but not PowerDown with 134 * power off. 135 */ 136 enum ufs_pm_level { 137 UFS_PM_LVL_0, 138 UFS_PM_LVL_1, 139 UFS_PM_LVL_2, 140 UFS_PM_LVL_3, 141 UFS_PM_LVL_4, 142 UFS_PM_LVL_5, 143 UFS_PM_LVL_6, 144 UFS_PM_LVL_MAX 145 }; 146 147 struct ufs_pm_lvl_states { 148 enum ufs_dev_pwr_mode dev_state; 149 enum uic_link_state link_state; 150 }; 151 152 /** 153 * struct ufshcd_lrb - local reference block 154 * @utr_descriptor_ptr: UTRD address of the command 155 * @ucd_req_ptr: UCD address of the command 156 * @ucd_rsp_ptr: Response UPIU address for this command 157 * @ucd_prdt_ptr: PRDT address of the command 158 * @utrd_dma_addr: UTRD dma address for debug 159 * @ucd_prdt_dma_addr: PRDT dma address for debug 160 * @ucd_rsp_dma_addr: UPIU response dma address for debug 161 * @ucd_req_dma_addr: UPIU request dma address for debug 162 * @cmd: pointer to SCSI command 163 * @scsi_status: SCSI status of the command 164 * @command_type: SCSI, UFS, Query. 165 * @task_tag: Task tag of the command 166 * @lun: LUN of the command 167 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 168 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 169 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 170 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 171 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 172 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 173 * @data_unit_num: the data unit number for the first block for inline crypto 174 * @req_abort_skip: skip request abort task flag 175 */ 176 struct ufshcd_lrb { 177 struct utp_transfer_req_desc *utr_descriptor_ptr; 178 struct utp_upiu_req *ucd_req_ptr; 179 struct utp_upiu_rsp *ucd_rsp_ptr; 180 struct ufshcd_sg_entry *ucd_prdt_ptr; 181 182 dma_addr_t utrd_dma_addr; 183 dma_addr_t ucd_req_dma_addr; 184 dma_addr_t ucd_rsp_dma_addr; 185 dma_addr_t ucd_prdt_dma_addr; 186 187 struct scsi_cmnd *cmd; 188 int scsi_status; 189 190 int command_type; 191 int task_tag; 192 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 193 bool intr_cmd; 194 ktime_t issue_time_stamp; 195 u64 issue_time_stamp_local_clock; 196 ktime_t compl_time_stamp; 197 u64 compl_time_stamp_local_clock; 198 #ifdef CONFIG_SCSI_UFS_CRYPTO 199 int crypto_key_slot; 200 u64 data_unit_num; 201 #endif 202 203 bool req_abort_skip; 204 }; 205 206 /** 207 * struct ufs_query_req - parameters for building a query request 208 * @query_func: UPIU header query function 209 * @upiu_req: the query request data 210 */ 211 struct ufs_query_req { 212 u8 query_func; 213 struct utp_upiu_query upiu_req; 214 }; 215 216 /** 217 * struct ufs_query_resp - UPIU QUERY 218 * @response: device response code 219 * @upiu_res: query response data 220 */ 221 struct ufs_query_res { 222 struct utp_upiu_query upiu_res; 223 }; 224 225 /** 226 * struct ufs_query - holds relevant data structures for query request 227 * @request: request upiu and function 228 * @descriptor: buffer for sending/receiving descriptor 229 * @response: response upiu and response 230 */ 231 struct ufs_query { 232 struct ufs_query_req request; 233 u8 *descriptor; 234 struct ufs_query_res response; 235 }; 236 237 /** 238 * struct ufs_dev_cmd - all assosiated fields with device management commands 239 * @type: device management command type - Query, NOP OUT 240 * @lock: lock to allow one command at a time 241 * @complete: internal commands completion 242 * @query: Device management query information 243 */ 244 struct ufs_dev_cmd { 245 enum dev_cmd_type type; 246 struct mutex lock; 247 struct completion *complete; 248 struct ufs_query query; 249 }; 250 251 /** 252 * struct ufs_clk_info - UFS clock related info 253 * @list: list headed by hba->clk_list_head 254 * @clk: clock node 255 * @name: clock name 256 * @max_freq: maximum frequency supported by the clock 257 * @min_freq: min frequency that can be used for clock scaling 258 * @curr_freq: indicates the current frequency that it is set to 259 * @keep_link_active: indicates that the clk should not be disabled if 260 * link is active 261 * @enabled: variable to check against multiple enable/disable 262 */ 263 struct ufs_clk_info { 264 struct list_head list; 265 struct clk *clk; 266 const char *name; 267 u32 max_freq; 268 u32 min_freq; 269 u32 curr_freq; 270 bool keep_link_active; 271 bool enabled; 272 }; 273 274 enum ufs_notify_change_status { 275 PRE_CHANGE, 276 POST_CHANGE, 277 }; 278 279 struct ufs_pa_layer_attr { 280 u32 gear_rx; 281 u32 gear_tx; 282 u32 lane_rx; 283 u32 lane_tx; 284 u32 pwr_rx; 285 u32 pwr_tx; 286 u32 hs_rate; 287 }; 288 289 struct ufs_pwr_mode_info { 290 bool is_valid; 291 struct ufs_pa_layer_attr info; 292 }; 293 294 /** 295 * struct ufs_hba_variant_ops - variant specific callbacks 296 * @name: variant name 297 * @init: called when the driver is initialized 298 * @exit: called to cleanup everything done in init 299 * @get_ufs_hci_version: called to get UFS HCI version 300 * @clk_scale_notify: notifies that clks are scaled up/down 301 * @setup_clocks: called before touching any of the controller registers 302 * @hce_enable_notify: called before and after HCE enable bit is set to allow 303 * variant specific Uni-Pro initialization. 304 * @link_startup_notify: called before and after Link startup is carried out 305 * to allow variant specific Uni-Pro initialization. 306 * @pwr_change_notify: called before and after a power mode change 307 * is carried out to allow vendor spesific capabilities 308 * to be set. 309 * @setup_xfer_req: called before any transfer request is issued 310 * to set some things 311 * @setup_task_mgmt: called before any task management request is issued 312 * to set some things 313 * @hibern8_notify: called around hibern8 enter/exit 314 * @apply_dev_quirks: called to apply device specific quirks 315 * @fixup_dev_quirks: called to modify device specific quirks 316 * @suspend: called during host controller PM callback 317 * @resume: called during host controller PM callback 318 * @dbg_register_dump: used to dump controller debug information 319 * @phy_initialization: used to initialize phys 320 * @device_reset: called to issue a reset pulse on the UFS device 321 * @config_scaling_param: called to configure clock scaling parameters 322 * @program_key: program or evict an inline encryption key 323 * @event_notify: called to notify important events 324 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 325 * @mcq_config_resource: called to configure MCQ platform resources 326 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 327 * @op_runtime_config: called to config Operation and runtime regs Pointers 328 * @get_outstanding_cqs: called to get outstanding completion queues 329 * @config_esi: called to config Event Specific Interrupt 330 */ 331 struct ufs_hba_variant_ops { 332 const char *name; 333 int (*init)(struct ufs_hba *); 334 void (*exit)(struct ufs_hba *); 335 u32 (*get_ufs_hci_version)(struct ufs_hba *); 336 int (*clk_scale_notify)(struct ufs_hba *, bool, 337 enum ufs_notify_change_status); 338 int (*setup_clocks)(struct ufs_hba *, bool, 339 enum ufs_notify_change_status); 340 int (*hce_enable_notify)(struct ufs_hba *, 341 enum ufs_notify_change_status); 342 int (*link_startup_notify)(struct ufs_hba *, 343 enum ufs_notify_change_status); 344 int (*pwr_change_notify)(struct ufs_hba *, 345 enum ufs_notify_change_status status, 346 struct ufs_pa_layer_attr *, 347 struct ufs_pa_layer_attr *); 348 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 349 bool is_scsi_cmd); 350 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 351 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 352 enum ufs_notify_change_status); 353 int (*apply_dev_quirks)(struct ufs_hba *hba); 354 void (*fixup_dev_quirks)(struct ufs_hba *hba); 355 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 356 enum ufs_notify_change_status); 357 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 358 void (*dbg_register_dump)(struct ufs_hba *hba); 359 int (*phy_initialization)(struct ufs_hba *); 360 int (*device_reset)(struct ufs_hba *hba); 361 void (*config_scaling_param)(struct ufs_hba *hba, 362 struct devfreq_dev_profile *profile, 363 struct devfreq_simple_ondemand_data *data); 364 int (*program_key)(struct ufs_hba *hba, 365 const union ufs_crypto_cfg_entry *cfg, int slot); 366 void (*event_notify)(struct ufs_hba *hba, 367 enum ufs_event_type evt, void *data); 368 void (*reinit_notify)(struct ufs_hba *); 369 int (*mcq_config_resource)(struct ufs_hba *hba); 370 int (*get_hba_mac)(struct ufs_hba *hba); 371 int (*op_runtime_config)(struct ufs_hba *hba); 372 int (*get_outstanding_cqs)(struct ufs_hba *hba, 373 unsigned long *ocqs); 374 int (*config_esi)(struct ufs_hba *hba); 375 void (*config_scsi_dev)(struct scsi_device *sdev); 376 }; 377 378 /* clock gating state */ 379 enum clk_gating_state { 380 CLKS_OFF, 381 CLKS_ON, 382 REQ_CLKS_OFF, 383 REQ_CLKS_ON, 384 }; 385 386 /** 387 * struct ufs_clk_gating - UFS clock gating related info 388 * @gate_work: worker to turn off clocks after some delay as specified in 389 * delay_ms 390 * @ungate_work: worker to turn on clocks that will be used in case of 391 * interrupt context 392 * @state: the current clocks state 393 * @delay_ms: gating delay in ms 394 * @is_suspended: clk gating is suspended when set to 1 which can be used 395 * during suspend/resume 396 * @delay_attr: sysfs attribute to control delay_attr 397 * @enable_attr: sysfs attribute to enable/disable clock gating 398 * @is_enabled: Indicates the current status of clock gating 399 * @is_initialized: Indicates whether clock gating is initialized or not 400 * @active_reqs: number of requests that are pending and should be waited for 401 * completion before gating clocks. 402 * @clk_gating_workq: workqueue for clock gating work. 403 */ 404 struct ufs_clk_gating { 405 struct delayed_work gate_work; 406 struct work_struct ungate_work; 407 enum clk_gating_state state; 408 unsigned long delay_ms; 409 bool is_suspended; 410 struct device_attribute delay_attr; 411 struct device_attribute enable_attr; 412 bool is_enabled; 413 bool is_initialized; 414 int active_reqs; 415 struct workqueue_struct *clk_gating_workq; 416 }; 417 418 /** 419 * struct ufs_clk_scaling - UFS clock scaling related data 420 * @active_reqs: number of requests that are pending. If this is zero when 421 * devfreq ->target() function is called then schedule "suspend_work" to 422 * suspend devfreq. 423 * @tot_busy_t: Total busy time in current polling window 424 * @window_start_t: Start time (in jiffies) of the current polling window 425 * @busy_start_t: Start time of current busy period 426 * @enable_attr: sysfs attribute to enable/disable clock scaling 427 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 428 * one keeps track of previous power mode. 429 * @workq: workqueue to schedule devfreq suspend/resume work 430 * @suspend_work: worker to suspend devfreq 431 * @resume_work: worker to resume devfreq 432 * @target_freq: frequency requested by devfreq framework 433 * @min_gear: lowest HS gear to scale down to 434 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 435 * clkscale_enable sysfs node 436 * @is_allowed: tracks if scaling is currently allowed or not, used to block 437 * clock scaling which is not invoked from devfreq governor 438 * @is_initialized: Indicates whether clock scaling is initialized or not 439 * @is_busy_started: tracks if busy period has started or not 440 * @is_suspended: tracks if devfreq is suspended or not 441 */ 442 struct ufs_clk_scaling { 443 int active_reqs; 444 unsigned long tot_busy_t; 445 ktime_t window_start_t; 446 ktime_t busy_start_t; 447 struct device_attribute enable_attr; 448 struct ufs_pa_layer_attr saved_pwr_info; 449 struct workqueue_struct *workq; 450 struct work_struct suspend_work; 451 struct work_struct resume_work; 452 unsigned long target_freq; 453 u32 min_gear; 454 bool is_enabled; 455 bool is_allowed; 456 bool is_initialized; 457 bool is_busy_started; 458 bool is_suspended; 459 }; 460 461 #define UFS_EVENT_HIST_LENGTH 8 462 /** 463 * struct ufs_event_hist - keeps history of errors 464 * @pos: index to indicate cyclic buffer position 465 * @val: cyclic buffer for registers value 466 * @tstamp: cyclic buffer for time stamp 467 * @cnt: error counter 468 */ 469 struct ufs_event_hist { 470 int pos; 471 u32 val[UFS_EVENT_HIST_LENGTH]; 472 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 473 unsigned long long cnt; 474 }; 475 476 /** 477 * struct ufs_stats - keeps usage/err statistics 478 * @last_intr_status: record the last interrupt status. 479 * @last_intr_ts: record the last interrupt timestamp. 480 * @hibern8_exit_cnt: Counter to keep track of number of exits, 481 * reset this after link-startup. 482 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 483 * Clear after the first successful command completion. 484 * @event: array with event history. 485 */ 486 struct ufs_stats { 487 u32 last_intr_status; 488 u64 last_intr_ts; 489 490 u32 hibern8_exit_cnt; 491 u64 last_hibern8_exit_tstamp; 492 struct ufs_event_hist event[UFS_EVT_CNT]; 493 }; 494 495 /** 496 * enum ufshcd_state - UFS host controller state 497 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 498 * processing. 499 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 500 * SCSI commands. 501 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 502 * SCSI commands may be submitted to the controller. 503 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 504 * newly submitted SCSI commands with error code DID_BAD_TARGET. 505 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 506 * failed. Fail all SCSI commands with error code DID_ERROR. 507 */ 508 enum ufshcd_state { 509 UFSHCD_STATE_RESET, 510 UFSHCD_STATE_OPERATIONAL, 511 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 512 UFSHCD_STATE_EH_SCHEDULED_FATAL, 513 UFSHCD_STATE_ERROR, 514 }; 515 516 enum ufshcd_quirks { 517 /* Interrupt aggregation support is broken */ 518 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 519 520 /* 521 * delay before each dme command is required as the unipro 522 * layer has shown instabilities 523 */ 524 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 525 526 /* 527 * If UFS host controller is having issue in processing LCC (Line 528 * Control Command) coming from device then enable this quirk. 529 * When this quirk is enabled, host controller driver should disable 530 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 531 * attribute of device to 0). 532 */ 533 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 534 535 /* 536 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 537 * inbound Link supports unterminated line in HS mode. Setting this 538 * attribute to 1 fixes moving to HS gear. 539 */ 540 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 541 542 /* 543 * This quirk needs to be enabled if the host controller only allows 544 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 545 * SLOW AUTO). 546 */ 547 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 548 549 /* 550 * This quirk needs to be enabled if the host controller doesn't 551 * advertise the correct version in UFS_VER register. If this quirk 552 * is enabled, standard UFS host driver will call the vendor specific 553 * ops (get_ufs_hci_version) to get the correct version. 554 */ 555 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 556 557 /* 558 * Clear handling for transfer/task request list is just opposite. 559 */ 560 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 561 562 /* 563 * This quirk needs to be enabled if host controller doesn't allow 564 * that the interrupt aggregation timer and counter are reset by s/w. 565 */ 566 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 567 568 /* 569 * This quirks needs to be enabled if host controller cannot be 570 * enabled via HCE register. 571 */ 572 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 573 574 /* 575 * This quirk needs to be enabled if the host controller regards 576 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 577 */ 578 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 579 580 /* 581 * This quirk needs to be enabled if the host controller reports 582 * OCS FATAL ERROR with device error through sense data 583 */ 584 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 585 586 /* 587 * This quirk needs to be enabled if the host controller has 588 * auto-hibernate capability but it doesn't work. 589 */ 590 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 591 592 /* 593 * This quirk needs to disable manual flush for write booster 594 */ 595 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 596 597 /* 598 * This quirk needs to disable unipro timeout values 599 * before power mode change 600 */ 601 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 602 603 /* 604 * This quirk needs to be enabled if the host controller does not 605 * support UIC command 606 */ 607 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 608 609 /* 610 * This quirk needs to be enabled if the host controller cannot 611 * support physical host configuration. 612 */ 613 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 614 615 /* 616 * This quirk needs to be enabled if the host controller has 617 * 64-bit addressing supported capability but it doesn't work. 618 */ 619 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 620 621 /* 622 * This quirk needs to be enabled if the host controller has 623 * auto-hibernate capability but it's FASTAUTO only. 624 */ 625 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 626 627 /* 628 * This quirk needs to be enabled if the host controller needs 629 * to reinit the device after switching to maximum gear. 630 */ 631 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 632 633 /* 634 * Some host raises interrupt (per queue) in addition to 635 * CQES (traditional) when ESI is disabled. 636 * Enable this quirk will disable CQES and use per queue interrupt. 637 */ 638 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 639 640 /* 641 * Some host does not implement SQ Run Time Command (SQRTC) register 642 * thus need this quirk to skip related flow. 643 */ 644 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 645 }; 646 647 enum ufshcd_caps { 648 /* Allow dynamic clk gating */ 649 UFSHCD_CAP_CLK_GATING = 1 << 0, 650 651 /* Allow hiberb8 with clk gating */ 652 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 653 654 /* Allow dynamic clk scaling */ 655 UFSHCD_CAP_CLK_SCALING = 1 << 2, 656 657 /* Allow auto bkops to enabled during runtime suspend */ 658 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 659 660 /* 661 * This capability allows host controller driver to use the UFS HCI's 662 * interrupt aggregation capability. 663 * CAUTION: Enabling this might reduce overall UFS throughput. 664 */ 665 UFSHCD_CAP_INTR_AGGR = 1 << 4, 666 667 /* 668 * This capability allows the device auto-bkops to be always enabled 669 * except during suspend (both runtime and suspend). 670 * Enabling this capability means that device will always be allowed 671 * to do background operation when it's active but it might degrade 672 * the performance of ongoing read/write operations. 673 */ 674 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 675 676 /* 677 * This capability allows host controller driver to automatically 678 * enable runtime power management by itself instead of waiting 679 * for userspace to control the power management. 680 */ 681 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 682 683 /* 684 * This capability allows the host controller driver to turn-on 685 * WriteBooster, if the underlying device supports it and is 686 * provisioned to be used. This would increase the write performance. 687 */ 688 UFSHCD_CAP_WB_EN = 1 << 7, 689 690 /* 691 * This capability allows the host controller driver to use the 692 * inline crypto engine, if it is present 693 */ 694 UFSHCD_CAP_CRYPTO = 1 << 8, 695 696 /* 697 * This capability allows the controller regulators to be put into 698 * lpm mode aggressively during clock gating. 699 * This would increase power savings. 700 */ 701 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 702 703 /* 704 * This capability allows the host controller driver to use DeepSleep, 705 * if it is supported by the UFS device. The host controller driver must 706 * support device hardware reset via the hba->device_reset() callback, 707 * in order to exit DeepSleep state. 708 */ 709 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 710 711 /* 712 * This capability allows the host controller driver to use temperature 713 * notification if it is supported by the UFS device. 714 */ 715 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 716 717 /* 718 * Enable WriteBooster when scaling up the clock and disable 719 * WriteBooster when scaling the clock down. 720 */ 721 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 722 }; 723 724 struct ufs_hba_variant_params { 725 struct devfreq_dev_profile devfreq_profile; 726 struct devfreq_simple_ondemand_data ondemand_data; 727 u16 hba_enable_delay_us; 728 u32 wb_flush_threshold; 729 }; 730 731 struct ufs_hba_monitor { 732 unsigned long chunk_size; 733 734 unsigned long nr_sec_rw[2]; 735 ktime_t total_busy[2]; 736 737 unsigned long nr_req[2]; 738 /* latencies*/ 739 ktime_t lat_sum[2]; 740 ktime_t lat_max[2]; 741 ktime_t lat_min[2]; 742 743 u32 nr_queued[2]; 744 ktime_t busy_start_ts[2]; 745 746 ktime_t enabled_ts; 747 bool enabled; 748 }; 749 750 /** 751 * struct ufshcd_res_info_t - MCQ related resource regions 752 * 753 * @name: resource name 754 * @resource: pointer to resource region 755 * @base: register base address 756 */ 757 struct ufshcd_res_info { 758 const char *name; 759 struct resource *resource; 760 void __iomem *base; 761 }; 762 763 enum ufshcd_res { 764 RES_UFS, 765 RES_MCQ, 766 RES_MCQ_SQD, 767 RES_MCQ_SQIS, 768 RES_MCQ_CQD, 769 RES_MCQ_CQIS, 770 RES_MCQ_VS, 771 RES_MAX, 772 }; 773 774 /** 775 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 776 * 777 * @offset: Doorbell Address Offset 778 * @stride: Steps proportional to queue [0...31] 779 * @base: base address 780 */ 781 struct ufshcd_mcq_opr_info_t { 782 unsigned long offset; 783 unsigned long stride; 784 void __iomem *base; 785 }; 786 787 enum ufshcd_mcq_opr { 788 OPR_SQD, 789 OPR_SQIS, 790 OPR_CQD, 791 OPR_CQIS, 792 OPR_MAX, 793 }; 794 795 /** 796 * struct ufs_hba - per adapter private structure 797 * @mmio_base: UFSHCI base register address 798 * @ucdl_base_addr: UFS Command Descriptor base address 799 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 800 * @utmrdl_base_addr: UTP Task Management Descriptor base address 801 * @ucdl_dma_addr: UFS Command Descriptor DMA address 802 * @utrdl_dma_addr: UTRDL DMA address 803 * @utmrdl_dma_addr: UTMRDL DMA address 804 * @host: Scsi_Host instance of the driver 805 * @dev: device handle 806 * @ufs_device_wlun: WLUN that controls the entire UFS device. 807 * @hwmon_device: device instance registered with the hwmon core. 808 * @curr_dev_pwr_mode: active UFS device power mode. 809 * @uic_link_state: active state of the link to the UFS device. 810 * @rpm_lvl: desired UFS power management level during runtime PM. 811 * @spm_lvl: desired UFS power management level during system PM. 812 * @pm_op_in_progress: whether or not a PM operation is in progress. 813 * @ahit: value of Auto-Hibernate Idle Timer register. 814 * @lrb: local reference block 815 * @outstanding_tasks: Bits representing outstanding task requests 816 * @outstanding_lock: Protects @outstanding_reqs. 817 * @outstanding_reqs: Bits representing outstanding transfer requests 818 * @capabilities: UFS Controller Capabilities 819 * @mcq_capabilities: UFS Multi Circular Queue capabilities 820 * @nutrs: Transfer Request Queue depth supported by controller 821 * @nutmrs: Task Management Queue depth supported by controller 822 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 823 * @ufs_version: UFS Version to which controller complies 824 * @vops: pointer to variant specific operations 825 * @vps: pointer to variant specific parameters 826 * @priv: pointer to variant specific private data 827 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 828 * @irq: Irq number of the controller 829 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 830 * @dev_ref_clk_freq: reference clock frequency 831 * @quirks: bitmask with information about deviations from the UFSHCI standard. 832 * @dev_quirks: bitmask with information about deviations from the UFS standard. 833 * @tmf_tag_set: TMF tag set. 834 * @tmf_queue: Used to allocate TMF tags. 835 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 836 * @active_uic_cmd: handle of active UIC command 837 * @uic_cmd_mutex: mutex for UIC command 838 * @uic_async_done: completion used during UIC processing 839 * @ufshcd_state: UFSHCD state 840 * @eh_flags: Error handling flags 841 * @intr_mask: Interrupt Mask Bits 842 * @ee_ctrl_mask: Exception event control mask 843 * @ee_drv_mask: Exception event mask for driver 844 * @ee_usr_mask: Exception event mask for user (set via debugfs) 845 * @ee_ctrl_mutex: Used to serialize exception event information. 846 * @is_powered: flag to check if HBA is powered 847 * @shutting_down: flag to check if shutdown has been invoked 848 * @host_sem: semaphore used to serialize concurrent contexts 849 * @eh_wq: Workqueue that eh_work works on 850 * @eh_work: Worker to handle UFS errors that require s/w attention 851 * @eeh_work: Worker to handle exception events 852 * @errors: HBA errors 853 * @uic_error: UFS interconnect layer error status 854 * @saved_err: sticky error mask 855 * @saved_uic_err: sticky UIC error mask 856 * @ufs_stats: various error counters 857 * @force_reset: flag to force eh_work perform a full reset 858 * @force_pmc: flag to force a power mode change 859 * @silence_err_logs: flag to silence error logs 860 * @dev_cmd: ufs device management command information 861 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 862 * @nop_out_timeout: NOP OUT timeout value 863 * @dev_info: information about the UFS device 864 * @auto_bkops_enabled: to track whether bkops is enabled in device 865 * @vreg_info: UFS device voltage regulator information 866 * @clk_list_head: UFS host controller clocks list node head 867 * @use_pm_opp: Indicates whether OPP based scaling is used or not 868 * @req_abort_count: number of times ufshcd_abort() has been called 869 * @lanes_per_direction: number of lanes per data direction between the UFS 870 * controller and the UFS device. 871 * @pwr_info: holds current power mode 872 * @max_pwr_info: keeps the device max valid pwm 873 * @clk_gating: information related to clock gating 874 * @caps: bitmask with information about UFS controller capabilities 875 * @devfreq: frequency scaling information owned by the devfreq core 876 * @clk_scaling: frequency scaling information owned by the UFS driver 877 * @system_suspending: system suspend has been started and system resume has 878 * not yet finished. 879 * @is_sys_suspended: UFS device has been suspended because of system suspend 880 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 881 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 882 * device is known or not. 883 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 884 * @clk_scaling_lock: used to serialize device commands and clock scaling 885 * @desc_size: descriptor sizes reported by device 886 * @scsi_block_reqs_cnt: reference counting for scsi block requests 887 * @bsg_dev: struct device associated with the BSG queue 888 * @bsg_queue: BSG queue associated with the UFS controller 889 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 890 * management) after the UFS device has finished a WriteBooster buffer 891 * flush or auto BKOP. 892 * @monitor: statistics about UFS commands 893 * @crypto_capabilities: Content of crypto capabilities register (0x100) 894 * @crypto_cap_array: Array of crypto capabilities 895 * @crypto_cfg_register: Start of the crypto cfg array 896 * @crypto_profile: the crypto profile of this hba (if applicable) 897 * @debugfs_root: UFS controller debugfs root directory 898 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 899 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 900 * ee_ctrl_mask 901 * @luns_avail: number of regular and well known LUNs supported by the UFS 902 * device 903 * @nr_hw_queues: number of hardware queues configured 904 * @nr_queues: number of Queues of different queue types 905 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 906 * ufshcd_resume_complete() 907 * @ext_iid_sup: is EXT_IID is supported by UFSHC 908 * @mcq_sup: is mcq supported by UFSHC 909 * @mcq_enabled: is mcq ready to accept requests 910 * @res: array of resource info of MCQ registers 911 * @mcq_base: Multi circular queue registers base address 912 * @uhq: array of supported hardware queues 913 * @dev_cmd_queue: Queue for issuing device management commands 914 */ 915 struct ufs_hba { 916 void __iomem *mmio_base; 917 918 /* Virtual memory reference */ 919 struct utp_transfer_cmd_desc *ucdl_base_addr; 920 struct utp_transfer_req_desc *utrdl_base_addr; 921 struct utp_task_req_desc *utmrdl_base_addr; 922 923 /* DMA memory reference */ 924 dma_addr_t ucdl_dma_addr; 925 dma_addr_t utrdl_dma_addr; 926 dma_addr_t utmrdl_dma_addr; 927 928 struct Scsi_Host *host; 929 struct device *dev; 930 struct scsi_device *ufs_device_wlun; 931 932 #ifdef CONFIG_SCSI_UFS_HWMON 933 struct device *hwmon_device; 934 #endif 935 936 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 937 enum uic_link_state uic_link_state; 938 /* Desired UFS power management level during runtime PM */ 939 enum ufs_pm_level rpm_lvl; 940 /* Desired UFS power management level during system PM */ 941 enum ufs_pm_level spm_lvl; 942 int pm_op_in_progress; 943 944 /* Auto-Hibernate Idle Timer register value */ 945 u32 ahit; 946 947 struct ufshcd_lrb *lrb; 948 949 unsigned long outstanding_tasks; 950 spinlock_t outstanding_lock; 951 unsigned long outstanding_reqs; 952 953 u32 capabilities; 954 int nutrs; 955 u32 mcq_capabilities; 956 int nutmrs; 957 u32 reserved_slot; 958 u32 ufs_version; 959 const struct ufs_hba_variant_ops *vops; 960 struct ufs_hba_variant_params *vps; 961 void *priv; 962 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 963 size_t sg_entry_size; 964 #endif 965 unsigned int irq; 966 bool is_irq_enabled; 967 enum ufs_ref_clk_freq dev_ref_clk_freq; 968 969 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 970 971 /* Device deviations from standard UFS device spec. */ 972 unsigned int dev_quirks; 973 974 struct blk_mq_tag_set tmf_tag_set; 975 struct request_queue *tmf_queue; 976 struct request **tmf_rqs; 977 978 struct uic_command *active_uic_cmd; 979 struct mutex uic_cmd_mutex; 980 struct completion *uic_async_done; 981 982 enum ufshcd_state ufshcd_state; 983 u32 eh_flags; 984 u32 intr_mask; 985 u16 ee_ctrl_mask; 986 u16 ee_drv_mask; 987 u16 ee_usr_mask; 988 struct mutex ee_ctrl_mutex; 989 bool is_powered; 990 bool shutting_down; 991 struct semaphore host_sem; 992 993 /* Work Queues */ 994 struct workqueue_struct *eh_wq; 995 struct work_struct eh_work; 996 struct work_struct eeh_work; 997 998 /* HBA Errors */ 999 u32 errors; 1000 u32 uic_error; 1001 u32 saved_err; 1002 u32 saved_uic_err; 1003 struct ufs_stats ufs_stats; 1004 bool force_reset; 1005 bool force_pmc; 1006 bool silence_err_logs; 1007 1008 /* Device management request data */ 1009 struct ufs_dev_cmd dev_cmd; 1010 ktime_t last_dme_cmd_tstamp; 1011 int nop_out_timeout; 1012 1013 /* Keeps information of the UFS device connected to this host */ 1014 struct ufs_dev_info dev_info; 1015 bool auto_bkops_enabled; 1016 struct ufs_vreg_info vreg_info; 1017 struct list_head clk_list_head; 1018 bool use_pm_opp; 1019 1020 /* Number of requests aborts */ 1021 int req_abort_count; 1022 1023 /* Number of lanes available (1 or 2) for Rx/Tx */ 1024 u32 lanes_per_direction; 1025 struct ufs_pa_layer_attr pwr_info; 1026 struct ufs_pwr_mode_info max_pwr_info; 1027 1028 struct ufs_clk_gating clk_gating; 1029 /* Control to enable/disable host capabilities */ 1030 u32 caps; 1031 1032 struct devfreq *devfreq; 1033 struct ufs_clk_scaling clk_scaling; 1034 bool system_suspending; 1035 bool is_sys_suspended; 1036 1037 enum bkops_status urgent_bkops_lvl; 1038 bool is_urgent_bkops_lvl_checked; 1039 1040 struct mutex wb_mutex; 1041 struct rw_semaphore clk_scaling_lock; 1042 atomic_t scsi_block_reqs_cnt; 1043 1044 struct device bsg_dev; 1045 struct request_queue *bsg_queue; 1046 struct delayed_work rpm_dev_flush_recheck_work; 1047 1048 struct ufs_hba_monitor monitor; 1049 1050 #ifdef CONFIG_SCSI_UFS_CRYPTO 1051 union ufs_crypto_capabilities crypto_capabilities; 1052 union ufs_crypto_cap_entry *crypto_cap_array; 1053 u32 crypto_cfg_register; 1054 struct blk_crypto_profile crypto_profile; 1055 #endif 1056 #ifdef CONFIG_DEBUG_FS 1057 struct dentry *debugfs_root; 1058 struct delayed_work debugfs_ee_work; 1059 u32 debugfs_ee_rate_limit_ms; 1060 #endif 1061 u32 luns_avail; 1062 unsigned int nr_hw_queues; 1063 unsigned int nr_queues[HCTX_MAX_TYPES]; 1064 bool complete_put; 1065 bool ext_iid_sup; 1066 bool scsi_host_added; 1067 bool mcq_sup; 1068 bool mcq_enabled; 1069 struct ufshcd_res_info res[RES_MAX]; 1070 void __iomem *mcq_base; 1071 struct ufs_hw_queue *uhq; 1072 struct ufs_hw_queue *dev_cmd_queue; 1073 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1074 }; 1075 1076 /** 1077 * struct ufs_hw_queue - per hardware queue structure 1078 * @mcq_sq_head: base address of submission queue head pointer 1079 * @mcq_sq_tail: base address of submission queue tail pointer 1080 * @mcq_cq_head: base address of completion queue head pointer 1081 * @mcq_cq_tail: base address of completion queue tail pointer 1082 * @sqe_base_addr: submission queue entry base address 1083 * @sqe_dma_addr: submission queue dma address 1084 * @cqe_base_addr: completion queue base address 1085 * @cqe_dma_addr: completion queue dma address 1086 * @max_entries: max number of slots in this hardware queue 1087 * @id: hardware queue ID 1088 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1089 * @sq_lock: serialize submission queue access 1090 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1091 * @cq_head_slot: current slot to which CQ head pointer is pointing 1092 * @cq_lock: Synchronize between multiple polling instances 1093 * @sq_mutex: prevent submission queue concurrent access 1094 */ 1095 struct ufs_hw_queue { 1096 void __iomem *mcq_sq_head; 1097 void __iomem *mcq_sq_tail; 1098 void __iomem *mcq_cq_head; 1099 void __iomem *mcq_cq_tail; 1100 1101 struct utp_transfer_req_desc *sqe_base_addr; 1102 dma_addr_t sqe_dma_addr; 1103 struct cq_entry *cqe_base_addr; 1104 dma_addr_t cqe_dma_addr; 1105 u32 max_entries; 1106 u32 id; 1107 u32 sq_tail_slot; 1108 spinlock_t sq_lock; 1109 u32 cq_tail_slot; 1110 u32 cq_head_slot; 1111 spinlock_t cq_lock; 1112 /* prevent concurrent access to submission queue */ 1113 struct mutex sq_mutex; 1114 }; 1115 1116 static inline bool is_mcq_enabled(struct ufs_hba *hba) 1117 { 1118 return hba->mcq_enabled; 1119 } 1120 1121 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1122 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1123 { 1124 return hba->sg_entry_size; 1125 } 1126 1127 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1128 { 1129 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1130 hba->sg_entry_size = sg_entry_size; 1131 } 1132 #else 1133 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1134 { 1135 return sizeof(struct ufshcd_sg_entry); 1136 } 1137 1138 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1139 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1140 #endif 1141 1142 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1143 { 1144 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1145 } 1146 1147 /* Returns true if clocks can be gated. Otherwise false */ 1148 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1149 { 1150 return hba->caps & UFSHCD_CAP_CLK_GATING; 1151 } 1152 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1153 { 1154 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1155 } 1156 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1157 { 1158 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1159 } 1160 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1161 { 1162 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1163 } 1164 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1165 { 1166 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1167 } 1168 1169 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1170 { 1171 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1172 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1173 } 1174 1175 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1176 { 1177 return !!(ufshcd_is_link_hibern8(hba) && 1178 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1179 } 1180 1181 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1182 { 1183 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1184 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1185 } 1186 1187 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1188 { 1189 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1190 } 1191 1192 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1193 { 1194 return hba->caps & UFSHCD_CAP_WB_EN; 1195 } 1196 1197 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1198 { 1199 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1200 } 1201 1202 #define ufsmcq_writel(hba, val, reg) \ 1203 writel((val), (hba)->mcq_base + (reg)) 1204 #define ufsmcq_readl(hba, reg) \ 1205 readl((hba)->mcq_base + (reg)) 1206 1207 #define ufsmcq_writelx(hba, val, reg) \ 1208 writel_relaxed((val), (hba)->mcq_base + (reg)) 1209 #define ufsmcq_readlx(hba, reg) \ 1210 readl_relaxed((hba)->mcq_base + (reg)) 1211 1212 #define ufshcd_writel(hba, val, reg) \ 1213 writel((val), (hba)->mmio_base + (reg)) 1214 #define ufshcd_readl(hba, reg) \ 1215 readl((hba)->mmio_base + (reg)) 1216 1217 /** 1218 * ufshcd_rmwl - perform read/modify/write for a controller register 1219 * @hba: per adapter instance 1220 * @mask: mask to apply on read value 1221 * @val: actual value to write 1222 * @reg: register address 1223 */ 1224 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1225 { 1226 u32 tmp; 1227 1228 tmp = ufshcd_readl(hba, reg); 1229 tmp &= ~mask; 1230 tmp |= (val & mask); 1231 ufshcd_writel(hba, tmp, reg); 1232 } 1233 1234 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1235 void ufshcd_dealloc_host(struct ufs_hba *); 1236 int ufshcd_hba_enable(struct ufs_hba *hba); 1237 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1238 int ufshcd_link_recovery(struct ufs_hba *hba); 1239 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1240 void ufshcd_remove(struct ufs_hba *); 1241 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1242 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1243 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1244 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1245 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1246 void ufshcd_hba_stop(struct ufs_hba *hba); 1247 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1248 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1249 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1250 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1251 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1252 struct ufs_hw_queue *hwq); 1253 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1254 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1255 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1256 1257 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1258 struct dev_pm_opp *opp, void *data, 1259 bool scaling_down); 1260 /** 1261 * ufshcd_set_variant - set variant specific data to the hba 1262 * @hba: per adapter instance 1263 * @variant: pointer to variant specific data 1264 */ 1265 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1266 { 1267 BUG_ON(!hba); 1268 hba->priv = variant; 1269 } 1270 1271 /** 1272 * ufshcd_get_variant - get variant specific data from the hba 1273 * @hba: per adapter instance 1274 */ 1275 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1276 { 1277 BUG_ON(!hba); 1278 return hba->priv; 1279 } 1280 1281 #ifdef CONFIG_PM 1282 extern int ufshcd_runtime_suspend(struct device *dev); 1283 extern int ufshcd_runtime_resume(struct device *dev); 1284 #endif 1285 #ifdef CONFIG_PM_SLEEP 1286 extern int ufshcd_system_suspend(struct device *dev); 1287 extern int ufshcd_system_resume(struct device *dev); 1288 extern int ufshcd_system_freeze(struct device *dev); 1289 extern int ufshcd_system_thaw(struct device *dev); 1290 extern int ufshcd_system_restore(struct device *dev); 1291 #endif 1292 1293 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1294 int agreed_gear, 1295 int adapt_val); 1296 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1297 u8 attr_set, u32 mib_val, u8 peer); 1298 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1299 u32 *mib_val, u8 peer); 1300 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1301 struct ufs_pa_layer_attr *desired_pwr_mode); 1302 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1303 1304 /* UIC command interfaces for DME primitives */ 1305 #define DME_LOCAL 0 1306 #define DME_PEER 1 1307 #define ATTR_SET_NOR 0 /* NORMAL */ 1308 #define ATTR_SET_ST 1 /* STATIC */ 1309 1310 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1311 u32 mib_val) 1312 { 1313 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1314 mib_val, DME_LOCAL); 1315 } 1316 1317 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1318 u32 mib_val) 1319 { 1320 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1321 mib_val, DME_LOCAL); 1322 } 1323 1324 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1325 u32 mib_val) 1326 { 1327 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1328 mib_val, DME_PEER); 1329 } 1330 1331 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1332 u32 mib_val) 1333 { 1334 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1335 mib_val, DME_PEER); 1336 } 1337 1338 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1339 u32 attr_sel, u32 *mib_val) 1340 { 1341 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1342 } 1343 1344 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1345 u32 attr_sel, u32 *mib_val) 1346 { 1347 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1348 } 1349 1350 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1351 { 1352 return (pwr_info->pwr_rx == FAST_MODE || 1353 pwr_info->pwr_rx == FASTAUTO_MODE) && 1354 (pwr_info->pwr_tx == FAST_MODE || 1355 pwr_info->pwr_tx == FASTAUTO_MODE); 1356 } 1357 1358 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1359 { 1360 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1361 } 1362 1363 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1364 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1365 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1366 const struct ufs_dev_quirk *fixups); 1367 #define SD_ASCII_STD true 1368 #define SD_RAW false 1369 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1370 u8 **buf, bool ascii); 1371 1372 void ufshcd_hold(struct ufs_hba *hba); 1373 void ufshcd_release(struct ufs_hba *hba); 1374 1375 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1376 1377 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1378 1379 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1380 1381 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1382 1383 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1384 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1385 struct ufs_ehs *ehs_rsp, int sg_cnt, 1386 struct scatterlist *sg_list, enum dma_data_direction dir); 1387 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1388 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1389 int ufshcd_suspend_prepare(struct device *dev); 1390 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1391 void ufshcd_resume_complete(struct device *dev); 1392 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1393 1394 /* Wrapper functions for safely calling variant operations */ 1395 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1396 { 1397 if (hba->vops && hba->vops->init) 1398 return hba->vops->init(hba); 1399 1400 return 0; 1401 } 1402 1403 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1404 { 1405 if (hba->vops && hba->vops->phy_initialization) 1406 return hba->vops->phy_initialization(hba); 1407 1408 return 0; 1409 } 1410 1411 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1412 1413 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1414 const char *prefix); 1415 1416 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1417 int ufshcd_write_ee_control(struct ufs_hba *hba); 1418 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1419 const u16 *other_mask, u16 set, u16 clr); 1420 1421 #endif /* End of Header */ 1422