d1aae066 | 13-Apr-2023 |
Stephen Boyd <sboyd@kernel.org> |
clk: starfive: Avoid casting iomem pointers
Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip
clk: starfive: Avoid casting iomem pointers
Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip up tools like sparse, and make for some awkward casts that are largely unnecessary. While we're here, change the allocation from devm and actually free the auxiliary_device memory in the release function. This avoids any use after free problems where the parent device driver is unbound from the device but the auxiliuary_device is still in use accessing devm freed memory.
Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: Hal Feng <hal.feng@starfivetech.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230413205528.4044216-1-sboyd@kernel.org
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b6d7406c | 01-Apr-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're on
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries.
There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception.
Switch to 32bit I/O in preparation for supporting these resets too.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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0333103e | 01-Apr-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
For the common code will be shared with the StarFive JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Co
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
For the common code will be shared with the StarFive JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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ed36fcd1 | 01-Apr-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
reset: starfive: Extract the common JH71X0 reset code
Extract the common JH71X0 reset code for reusing them to support JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: C
reset: starfive: Extract the common JH71X0 reset code
Extract the common JH71X0 reset code for reusing them to support JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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1ec3d20e | 01-Apr-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
reset: starfive: Factor out common JH71X0 reset code
The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the rese
reset: starfive: Factor out common JH71X0 reset code
The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the reset registers don't get their own memory range, but instead follow the clock control registers. The registers still follow the same structure though, so let's factor out the common code to handle all these cases.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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