1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver 4 * 5 * Copyright (C) 2014-2017 Broadcom 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/irqdomain.h> 23 #include <linux/irqchip.h> 24 #include <linux/irqchip/chained_irq.h> 25 26 struct brcmstb_intc_init_params { 27 irq_flow_handler_t handler; 28 int cpu_status; 29 int cpu_clear; 30 int cpu_mask_status; 31 int cpu_mask_set; 32 int cpu_mask_clear; 33 }; 34 35 /* Register offsets in the L2 latched interrupt controller */ 36 static const struct brcmstb_intc_init_params l2_edge_intc_init = { 37 .handler = handle_edge_irq, 38 .cpu_status = 0x00, 39 .cpu_clear = 0x08, 40 .cpu_mask_status = 0x0c, 41 .cpu_mask_set = 0x10, 42 .cpu_mask_clear = 0x14 43 }; 44 45 /* Register offsets in the L2 level interrupt controller */ 46 static const struct brcmstb_intc_init_params l2_lvl_intc_init = { 47 .handler = handle_level_irq, 48 .cpu_status = 0x00, 49 .cpu_clear = -1, /* Register not present */ 50 .cpu_mask_status = 0x04, 51 .cpu_mask_set = 0x08, 52 .cpu_mask_clear = 0x0C 53 }; 54 55 /* L2 intc private data structure */ 56 struct brcmstb_l2_intc_data { 57 struct irq_domain *domain; 58 struct irq_chip_generic *gc; 59 int status_offset; 60 int mask_offset; 61 bool can_wake; 62 u32 saved_mask; /* for suspend/resume */ 63 }; 64 65 /** 66 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt 67 * @d: irq_data 68 * 69 * Chip has separate enable/disable registers instead of a single mask 70 * register and pending interrupt is acknowledged by setting a bit. 71 * 72 * Note: This function is generic and could easily be added to the 73 * generic irqchip implementation if there ever becomes a will to do so. 74 * Perhaps with a name like irq_gc_mask_disable_and_ack_set(). 75 * 76 * e.g.: https://patchwork.kernel.org/patch/9831047/ 77 */ 78 static void brcmstb_l2_mask_and_ack(struct irq_data *d) 79 { 80 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 81 struct irq_chip_type *ct = irq_data_get_chip_type(d); 82 u32 mask = d->mask; 83 84 irq_gc_lock(gc); 85 irq_reg_writel(gc, mask, ct->regs.disable); 86 *ct->mask_cache &= ~mask; 87 irq_reg_writel(gc, mask, ct->regs.ack); 88 irq_gc_unlock(gc); 89 } 90 91 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) 92 { 93 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); 94 struct irq_chip *chip = irq_desc_get_chip(desc); 95 unsigned int irq; 96 u32 status; 97 98 chained_irq_enter(chip, desc); 99 100 status = irq_reg_readl(b->gc, b->status_offset) & 101 ~(irq_reg_readl(b->gc, b->mask_offset)); 102 103 if (status == 0) { 104 raw_spin_lock(&desc->lock); 105 handle_bad_irq(desc); 106 raw_spin_unlock(&desc->lock); 107 goto out; 108 } 109 110 do { 111 irq = ffs(status) - 1; 112 status &= ~(1 << irq); 113 generic_handle_domain_irq(b->domain, irq); 114 } while (status); 115 out: 116 chained_irq_exit(chip, desc); 117 } 118 119 static void brcmstb_l2_intc_suspend(struct irq_data *d) 120 { 121 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 122 struct irq_chip_type *ct = irq_data_get_chip_type(d); 123 struct brcmstb_l2_intc_data *b = gc->private; 124 unsigned long flags; 125 126 irq_gc_lock_irqsave(gc, flags); 127 /* Save the current mask */ 128 b->saved_mask = irq_reg_readl(gc, ct->regs.mask); 129 130 if (b->can_wake) { 131 /* Program the wakeup mask */ 132 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); 133 irq_reg_writel(gc, gc->wake_active, ct->regs.enable); 134 } 135 irq_gc_unlock_irqrestore(gc, flags); 136 } 137 138 static void brcmstb_l2_intc_resume(struct irq_data *d) 139 { 140 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 141 struct irq_chip_type *ct = irq_data_get_chip_type(d); 142 struct brcmstb_l2_intc_data *b = gc->private; 143 unsigned long flags; 144 145 irq_gc_lock_irqsave(gc, flags); 146 if (ct->chip.irq_ack) { 147 /* Clear unmasked non-wakeup interrupts */ 148 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, 149 ct->regs.ack); 150 } 151 152 /* Restore the saved mask */ 153 irq_reg_writel(gc, b->saved_mask, ct->regs.disable); 154 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); 155 irq_gc_unlock_irqrestore(gc, flags); 156 } 157 158 static int __init brcmstb_l2_intc_of_init(struct device_node *np, 159 struct device_node *parent, 160 const struct brcmstb_intc_init_params 161 *init_params) 162 { 163 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 164 unsigned int set = 0; 165 struct brcmstb_l2_intc_data *data; 166 struct irq_chip_type *ct; 167 int ret; 168 unsigned int flags; 169 int parent_irq; 170 void __iomem *base; 171 172 data = kzalloc(sizeof(*data), GFP_KERNEL); 173 if (!data) 174 return -ENOMEM; 175 176 base = of_iomap(np, 0); 177 if (!base) { 178 pr_err("failed to remap intc L2 registers\n"); 179 ret = -ENOMEM; 180 goto out_free; 181 } 182 183 /* Disable all interrupts by default */ 184 writel(0xffffffff, base + init_params->cpu_mask_set); 185 186 /* Wakeup interrupts may be retained from S5 (cold boot) */ 187 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); 188 if (!data->can_wake && (init_params->cpu_clear >= 0)) 189 writel(0xffffffff, base + init_params->cpu_clear); 190 191 parent_irq = irq_of_parse_and_map(np, 0); 192 if (!parent_irq) { 193 pr_err("failed to find parent interrupt\n"); 194 ret = -EINVAL; 195 goto out_unmap; 196 } 197 198 data->domain = irq_domain_add_linear(np, 32, 199 &irq_generic_chip_ops, NULL); 200 if (!data->domain) { 201 ret = -ENOMEM; 202 goto out_unmap; 203 } 204 205 /* MIPS chips strapped for BE will automagically configure the 206 * peripheral registers for CPU-native byte order. 207 */ 208 flags = 0; 209 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 210 flags |= IRQ_GC_BE_IO; 211 212 if (init_params->handler == handle_level_irq) 213 set |= IRQ_LEVEL; 214 215 /* Allocate a single Generic IRQ chip for this node */ 216 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, 217 np->full_name, init_params->handler, clr, set, flags); 218 if (ret) { 219 pr_err("failed to allocate generic irq chip\n"); 220 goto out_free_domain; 221 } 222 223 /* Set the IRQ chaining logic */ 224 irq_set_chained_handler_and_data(parent_irq, 225 brcmstb_l2_intc_irq_handle, data); 226 227 data->gc = irq_get_domain_generic_chip(data->domain, 0); 228 data->gc->reg_base = base; 229 data->gc->private = data; 230 data->status_offset = init_params->cpu_status; 231 data->mask_offset = init_params->cpu_mask_status; 232 233 ct = data->gc->chip_types; 234 235 if (init_params->cpu_clear >= 0) { 236 ct->regs.ack = init_params->cpu_clear; 237 ct->chip.irq_ack = irq_gc_ack_set_bit; 238 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack; 239 } else { 240 /* No Ack - but still slightly more efficient to define this */ 241 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 242 } 243 244 ct->chip.irq_mask = irq_gc_mask_disable_reg; 245 ct->regs.disable = init_params->cpu_mask_set; 246 ct->regs.mask = init_params->cpu_mask_status; 247 248 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 249 ct->regs.enable = init_params->cpu_mask_clear; 250 251 ct->chip.irq_suspend = brcmstb_l2_intc_suspend; 252 ct->chip.irq_resume = brcmstb_l2_intc_resume; 253 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend; 254 255 if (data->can_wake) { 256 /* This IRQ chip can wake the system, set all child interrupts 257 * in wake_enabled mask 258 */ 259 data->gc->wake_enabled = 0xffffffff; 260 ct->chip.irq_set_wake = irq_gc_set_wake; 261 enable_irq_wake(parent_irq); 262 } 263 264 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); 265 266 return 0; 267 268 out_free_domain: 269 irq_domain_remove(data->domain); 270 out_unmap: 271 iounmap(base); 272 out_free: 273 kfree(data); 274 return ret; 275 } 276 277 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, 278 struct device_node *parent) 279 { 280 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); 281 } 282 283 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, 284 struct device_node *parent) 285 { 286 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); 287 } 288 289 IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2) 290 IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init) 291 IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init) 292 IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init) 293 IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init) 294 IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2) 295 MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller"); 296 MODULE_LICENSE("GPL v2"); 297