xref: /linux/arch/arm64/boot/dts/marvell/cn9131-db-B.dts (revision 69bfec7548f4c1595bac0e3ddfc0458a5af31f4c)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Device tree for the CN9131-DB board (setup "B").
6 */
7
8#include "cn9131-db.dtsi"
9
10/ {
11	model = "Marvell Armada CN9131-DB setup B";
12};
13
14/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
17 */
18
19&cp0_nand_controller {
20	status = "okay";
21};
22
23