1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 struct ib_qp *ibqp = &hr_qp->ibqp; 377 378 if (unlikely(ibqp->qp_type != IB_QPT_RC && 379 ibqp->qp_type != IB_QPT_GSI && 380 ibqp->qp_type != IB_QPT_UD)) { 381 ibdev_err(ibdev, "not supported QP(0x%x)type!\n", 382 ibqp->qp_type); 383 return -EOPNOTSUPP; 384 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 385 hr_qp->state == IB_QPS_INIT || 386 hr_qp->state == IB_QPS_RTR)) { 387 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 388 hr_qp->state); 389 return -EINVAL; 390 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 391 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 392 hr_dev->state); 393 return -EIO; 394 } 395 396 return 0; 397 } 398 399 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 400 unsigned int *sge_len) 401 { 402 unsigned int valid_num = 0; 403 unsigned int len = 0; 404 int i; 405 406 for (i = 0; i < wr->num_sge; i++) { 407 if (likely(wr->sg_list[i].length)) { 408 len += wr->sg_list[i].length; 409 valid_num++; 410 } 411 } 412 413 *sge_len = len; 414 return valid_num; 415 } 416 417 static __le32 get_immtdata(const struct ib_send_wr *wr) 418 { 419 switch (wr->opcode) { 420 case IB_WR_SEND_WITH_IMM: 421 case IB_WR_RDMA_WRITE_WITH_IMM: 422 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 423 default: 424 return 0; 425 } 426 } 427 428 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 429 const struct ib_send_wr *wr) 430 { 431 u32 ib_op = wr->opcode; 432 433 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 434 return -EINVAL; 435 436 ud_sq_wqe->immtdata = get_immtdata(wr); 437 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 439 440 return 0; 441 } 442 443 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 444 struct hns_roce_ah *ah) 445 { 446 struct ib_device *ib_dev = ah->ibah.device; 447 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 448 449 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 453 454 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 455 return -EINVAL; 456 457 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 458 459 ud_sq_wqe->sgid_index = ah->av.gid_index; 460 461 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 462 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 463 464 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 465 return 0; 466 467 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 468 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 469 470 return 0; 471 } 472 473 static inline int set_ud_wqe(struct hns_roce_qp *qp, 474 const struct ib_send_wr *wr, 475 void *wqe, unsigned int *sge_idx, 476 unsigned int owner_bit) 477 { 478 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 479 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 480 unsigned int curr_idx = *sge_idx; 481 unsigned int valid_num_sge; 482 u32 msg_len = 0; 483 int ret; 484 485 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 486 487 ret = set_ud_opcode(ud_sq_wqe, wr); 488 if (WARN_ON(ret)) 489 return ret; 490 491 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 492 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 494 !!(wr->send_flags & IB_SEND_SIGNALED)); 495 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 496 !!(wr->send_flags & IB_SEND_SOLICITED)); 497 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 499 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 500 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 501 curr_idx & (qp->sge.sge_cnt - 1)); 502 503 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 504 qp->qkey : ud_wr(wr)->remote_qkey); 505 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 506 507 ret = fill_ud_av(ud_sq_wqe, ah); 508 if (ret) 509 return ret; 510 511 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 512 513 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 514 515 /* 516 * The pipeline can sequentially post all valid WQEs into WQ buffer, 517 * including new WQEs waiting for the doorbell to update the PI again. 518 * Therefore, the owner bit of WQE MUST be updated after all fields 519 * and extSGEs have been written into DDR instead of cache. 520 */ 521 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 522 dma_wmb(); 523 524 *sge_idx = curr_idx; 525 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 526 527 return 0; 528 } 529 530 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 531 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 532 const struct ib_send_wr *wr) 533 { 534 u32 ib_op = wr->opcode; 535 int ret = 0; 536 537 rc_sq_wqe->immtdata = get_immtdata(wr); 538 539 switch (ib_op) { 540 case IB_WR_RDMA_READ: 541 case IB_WR_RDMA_WRITE: 542 case IB_WR_RDMA_WRITE_WITH_IMM: 543 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 544 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 545 break; 546 case IB_WR_SEND: 547 case IB_WR_SEND_WITH_IMM: 548 break; 549 case IB_WR_ATOMIC_CMP_AND_SWP: 550 case IB_WR_ATOMIC_FETCH_AND_ADD: 551 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 552 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 553 break; 554 case IB_WR_REG_MR: 555 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 556 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 557 else 558 ret = -EOPNOTSUPP; 559 break; 560 case IB_WR_SEND_WITH_INV: 561 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 562 break; 563 default: 564 ret = -EINVAL; 565 } 566 567 if (unlikely(ret)) 568 return ret; 569 570 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 571 572 return ret; 573 } 574 575 static inline int set_rc_wqe(struct hns_roce_qp *qp, 576 const struct ib_send_wr *wr, 577 void *wqe, unsigned int *sge_idx, 578 unsigned int owner_bit) 579 { 580 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 581 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 582 unsigned int curr_idx = *sge_idx; 583 unsigned int valid_num_sge; 584 u32 msg_len = 0; 585 int ret; 586 587 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 588 589 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 590 591 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 592 if (WARN_ON(ret)) 593 return ret; 594 595 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 596 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 597 598 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 599 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 600 601 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 602 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 603 604 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 605 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 606 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 607 else if (wr->opcode != IB_WR_REG_MR) 608 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 609 &curr_idx, valid_num_sge); 610 611 /* 612 * The pipeline can sequentially post all valid WQEs into WQ buffer, 613 * including new WQEs waiting for the doorbell to update the PI again. 614 * Therefore, the owner bit of WQE MUST be updated after all fields 615 * and extSGEs have been written into DDR instead of cache. 616 */ 617 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 618 dma_wmb(); 619 620 *sge_idx = curr_idx; 621 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 622 623 return ret; 624 } 625 626 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 627 struct hns_roce_qp *qp) 628 { 629 if (unlikely(qp->state == IB_QPS_ERR)) { 630 flush_cqe(hr_dev, qp); 631 } else { 632 struct hns_roce_v2_db sq_db = {}; 633 634 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 635 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 636 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 637 hr_reg_write(&sq_db, DB_SL, qp->sl); 638 639 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 640 } 641 } 642 643 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 644 struct hns_roce_qp *qp) 645 { 646 if (unlikely(qp->state == IB_QPS_ERR)) { 647 flush_cqe(hr_dev, qp); 648 } else { 649 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 650 *qp->rdb.db_record = 651 qp->rq.head & V2_DB_PRODUCER_IDX_M; 652 } else { 653 struct hns_roce_v2_db rq_db = {}; 654 655 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 656 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 657 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 658 659 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 660 qp->rq.db_reg); 661 } 662 } 663 } 664 665 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 666 u64 __iomem *dest) 667 { 668 #define HNS_ROCE_WRITE_TIMES 8 669 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 670 struct hnae3_handle *handle = priv->handle; 671 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 672 int i; 673 674 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 675 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 676 writeq_relaxed(*(val + i), dest + i); 677 } 678 679 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 680 void *wqe) 681 { 682 #define HNS_ROCE_SL_SHIFT 2 683 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 684 685 /* All kinds of DirectWQE have the same header field layout */ 686 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 687 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 689 qp->sl >> HNS_ROCE_SL_SHIFT); 690 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 691 692 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 693 } 694 695 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 696 const struct ib_send_wr *wr, 697 const struct ib_send_wr **bad_wr) 698 { 699 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 700 struct ib_device *ibdev = &hr_dev->ib_dev; 701 struct hns_roce_qp *qp = to_hr_qp(ibqp); 702 unsigned long flags = 0; 703 unsigned int owner_bit; 704 unsigned int sge_idx; 705 unsigned int wqe_idx; 706 void *wqe = NULL; 707 u32 nreq; 708 int ret; 709 710 spin_lock_irqsave(&qp->sq.lock, flags); 711 712 ret = check_send_valid(hr_dev, qp); 713 if (unlikely(ret)) { 714 *bad_wr = wr; 715 nreq = 0; 716 goto out; 717 } 718 719 sge_idx = qp->next_sge; 720 721 for (nreq = 0; wr; ++nreq, wr = wr->next) { 722 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 723 ret = -ENOMEM; 724 *bad_wr = wr; 725 goto out; 726 } 727 728 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 729 730 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 731 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 732 wr->num_sge, qp->sq.max_gs); 733 ret = -EINVAL; 734 *bad_wr = wr; 735 goto out; 736 } 737 738 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 739 qp->sq.wrid[wqe_idx] = wr->wr_id; 740 owner_bit = 741 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 742 743 /* Corresponding to the QP type, wqe process separately */ 744 if (ibqp->qp_type == IB_QPT_RC) 745 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 746 else 747 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 748 749 if (unlikely(ret)) { 750 *bad_wr = wr; 751 goto out; 752 } 753 } 754 755 out: 756 if (likely(nreq)) { 757 qp->sq.head += nreq; 758 qp->next_sge = sge_idx; 759 760 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 761 write_dwqe(hr_dev, qp, wqe); 762 else 763 update_sq_db(hr_dev, qp); 764 } 765 766 spin_unlock_irqrestore(&qp->sq.lock, flags); 767 768 return ret; 769 } 770 771 static int check_recv_valid(struct hns_roce_dev *hr_dev, 772 struct hns_roce_qp *hr_qp) 773 { 774 struct ib_device *ibdev = &hr_dev->ib_dev; 775 struct ib_qp *ibqp = &hr_qp->ibqp; 776 777 if (unlikely(ibqp->qp_type != IB_QPT_RC && 778 ibqp->qp_type != IB_QPT_GSI && 779 ibqp->qp_type != IB_QPT_UD)) { 780 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 781 ibqp->qp_type); 782 return -EOPNOTSUPP; 783 } 784 785 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 786 return -EIO; 787 788 if (hr_qp->state == IB_QPS_RESET) 789 return -EINVAL; 790 791 return 0; 792 } 793 794 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 795 u32 max_sge, bool rsv) 796 { 797 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 798 u32 i, cnt; 799 800 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 801 /* Skip zero-length sge */ 802 if (!wr->sg_list[i].length) 803 continue; 804 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 805 cnt++; 806 } 807 808 /* Fill a reserved sge to make hw stop reading remaining segments */ 809 if (rsv) { 810 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 811 dseg[cnt].addr = 0; 812 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 813 } else { 814 /* Clear remaining segments to make ROCEE ignore sges */ 815 if (cnt < max_sge) 816 memset(dseg + cnt, 0, 817 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 818 } 819 } 820 821 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 822 u32 wqe_idx, u32 max_sge) 823 { 824 void *wqe = NULL; 825 826 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 827 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 828 } 829 830 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 831 const struct ib_recv_wr *wr, 832 const struct ib_recv_wr **bad_wr) 833 { 834 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 835 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 836 struct ib_device *ibdev = &hr_dev->ib_dev; 837 u32 wqe_idx, nreq, max_sge; 838 unsigned long flags; 839 int ret; 840 841 spin_lock_irqsave(&hr_qp->rq.lock, flags); 842 843 ret = check_recv_valid(hr_dev, hr_qp); 844 if (unlikely(ret)) { 845 *bad_wr = wr; 846 nreq = 0; 847 goto out; 848 } 849 850 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 851 for (nreq = 0; wr; ++nreq, wr = wr->next) { 852 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 853 hr_qp->ibqp.recv_cq))) { 854 ret = -ENOMEM; 855 *bad_wr = wr; 856 goto out; 857 } 858 859 if (unlikely(wr->num_sge > max_sge)) { 860 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 861 wr->num_sge, max_sge); 862 ret = -EINVAL; 863 *bad_wr = wr; 864 goto out; 865 } 866 867 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 868 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 869 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 870 } 871 872 out: 873 if (likely(nreq)) { 874 hr_qp->rq.head += nreq; 875 876 update_rq_db(hr_dev, hr_qp); 877 } 878 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 879 880 return ret; 881 } 882 883 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 884 { 885 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 886 } 887 888 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 889 { 890 return hns_roce_buf_offset(idx_que->mtr.kmem, 891 n << idx_que->entry_shift); 892 } 893 894 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 895 { 896 /* always called with interrupts disabled. */ 897 spin_lock(&srq->lock); 898 899 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 900 srq->idx_que.tail++; 901 902 spin_unlock(&srq->lock); 903 } 904 905 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 906 { 907 struct hns_roce_idx_que *idx_que = &srq->idx_que; 908 909 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 910 } 911 912 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 913 const struct ib_recv_wr *wr) 914 { 915 struct ib_device *ib_dev = srq->ibsrq.device; 916 917 if (unlikely(wr->num_sge > max_sge)) { 918 ibdev_err(ib_dev, 919 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 920 wr->num_sge, max_sge); 921 return -EINVAL; 922 } 923 924 if (unlikely(hns_roce_srqwq_overflow(srq))) { 925 ibdev_err(ib_dev, 926 "failed to check srqwq status, srqwq is full.\n"); 927 return -ENOMEM; 928 } 929 930 return 0; 931 } 932 933 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 934 { 935 struct hns_roce_idx_que *idx_que = &srq->idx_que; 936 u32 pos; 937 938 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 939 if (unlikely(pos == srq->wqe_cnt)) 940 return -ENOSPC; 941 942 bitmap_set(idx_que->bitmap, pos, 1); 943 *wqe_idx = pos; 944 return 0; 945 } 946 947 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 948 { 949 struct hns_roce_idx_que *idx_que = &srq->idx_que; 950 unsigned int head; 951 __le32 *buf; 952 953 head = idx_que->head & (srq->wqe_cnt - 1); 954 955 buf = get_idx_buf(idx_que, head); 956 *buf = cpu_to_le32(wqe_idx); 957 958 idx_que->head++; 959 } 960 961 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 962 { 963 hr_reg_write(db, DB_TAG, srq->srqn); 964 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 965 hr_reg_write(db, DB_PI, srq->idx_que.head); 966 } 967 968 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 969 const struct ib_recv_wr *wr, 970 const struct ib_recv_wr **bad_wr) 971 { 972 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 973 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 974 struct hns_roce_v2_db srq_db; 975 unsigned long flags; 976 int ret = 0; 977 u32 max_sge; 978 u32 wqe_idx; 979 void *wqe; 980 u32 nreq; 981 982 spin_lock_irqsave(&srq->lock, flags); 983 984 max_sge = srq->max_gs - srq->rsv_sge; 985 for (nreq = 0; wr; ++nreq, wr = wr->next) { 986 ret = check_post_srq_valid(srq, max_sge, wr); 987 if (ret) { 988 *bad_wr = wr; 989 break; 990 } 991 992 ret = get_srq_wqe_idx(srq, &wqe_idx); 993 if (unlikely(ret)) { 994 *bad_wr = wr; 995 break; 996 } 997 998 wqe = get_srq_wqe_buf(srq, wqe_idx); 999 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1000 fill_wqe_idx(srq, wqe_idx); 1001 srq->wrid[wqe_idx] = wr->wr_id; 1002 } 1003 1004 if (likely(nreq)) { 1005 update_srq_db(&srq_db, srq); 1006 1007 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1008 } 1009 1010 spin_unlock_irqrestore(&srq->lock, flags); 1011 1012 return ret; 1013 } 1014 1015 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1016 unsigned long instance_stage, 1017 unsigned long reset_stage) 1018 { 1019 /* When hardware reset has been completed once or more, we should stop 1020 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1021 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1022 * stage of soft reset process, we should exit with error, and then 1023 * HNAE3_INIT_CLIENT related process can rollback the operation like 1024 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1025 * process will exit with error to notify NIC driver to reschedule soft 1026 * reset process once again. 1027 */ 1028 hr_dev->is_reset = true; 1029 hr_dev->dis_db = true; 1030 1031 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1032 instance_stage == HNS_ROCE_STATE_INIT) 1033 return CMD_RST_PRC_EBUSY; 1034 1035 return CMD_RST_PRC_SUCCESS; 1036 } 1037 1038 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1039 unsigned long instance_stage, 1040 unsigned long reset_stage) 1041 { 1042 #define HW_RESET_TIMEOUT_US 1000000 1043 #define HW_RESET_SLEEP_US 1000 1044 1045 struct hns_roce_v2_priv *priv = hr_dev->priv; 1046 struct hnae3_handle *handle = priv->handle; 1047 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1048 unsigned long val; 1049 int ret; 1050 1051 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1052 * doorbell to hardware. If now in .init_instance() function, we should 1053 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1054 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1055 * related process can rollback the operation like notifing hardware to 1056 * free resources, HNAE3_INIT_CLIENT related process will exit with 1057 * error to notify NIC driver to reschedule soft reset process once 1058 * again. 1059 */ 1060 hr_dev->dis_db = true; 1061 1062 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1063 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1064 HW_RESET_TIMEOUT_US, false, handle); 1065 if (!ret) 1066 hr_dev->is_reset = true; 1067 1068 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1069 instance_stage == HNS_ROCE_STATE_INIT) 1070 return CMD_RST_PRC_EBUSY; 1071 1072 return CMD_RST_PRC_SUCCESS; 1073 } 1074 1075 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1076 { 1077 struct hns_roce_v2_priv *priv = hr_dev->priv; 1078 struct hnae3_handle *handle = priv->handle; 1079 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1080 1081 /* When software reset is detected at .init_instance() function, we 1082 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1083 * with error. 1084 */ 1085 hr_dev->dis_db = true; 1086 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1087 hr_dev->is_reset = true; 1088 1089 return CMD_RST_PRC_EBUSY; 1090 } 1091 1092 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1093 struct hnae3_handle *handle) 1094 { 1095 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1096 unsigned long instance_stage; /* the current instance stage */ 1097 unsigned long reset_stage; /* the current reset stage */ 1098 unsigned long reset_cnt; 1099 bool sw_resetting; 1100 bool hw_resetting; 1101 1102 /* Get information about reset from NIC driver or RoCE driver itself, 1103 * the meaning of the following variables from NIC driver are described 1104 * as below: 1105 * reset_cnt -- The count value of completed hardware reset. 1106 * hw_resetting -- Whether hardware device is resetting now. 1107 * sw_resetting -- Whether NIC's software reset process is running now. 1108 */ 1109 instance_stage = handle->rinfo.instance_state; 1110 reset_stage = handle->rinfo.reset_state; 1111 reset_cnt = ops->ae_dev_reset_cnt(handle); 1112 if (reset_cnt != hr_dev->reset_cnt) 1113 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1114 reset_stage); 1115 1116 hw_resetting = ops->get_cmdq_stat(handle); 1117 if (hw_resetting) 1118 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1119 reset_stage); 1120 1121 sw_resetting = ops->ae_dev_resetting(handle); 1122 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1123 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1124 1125 return CMD_RST_PRC_OTHERS; 1126 } 1127 1128 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1129 { 1130 struct hns_roce_v2_priv *priv = hr_dev->priv; 1131 struct hnae3_handle *handle = priv->handle; 1132 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1133 1134 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1135 return true; 1136 1137 if (ops->get_hw_reset_stat(handle)) 1138 return true; 1139 1140 if (ops->ae_dev_resetting(handle)) 1141 return true; 1142 1143 return false; 1144 } 1145 1146 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1147 { 1148 struct hns_roce_v2_priv *priv = hr_dev->priv; 1149 u32 status; 1150 1151 if (hr_dev->is_reset) 1152 status = CMD_RST_PRC_SUCCESS; 1153 else 1154 status = check_aedev_reset_status(hr_dev, priv->handle); 1155 1156 *busy = (status == CMD_RST_PRC_EBUSY); 1157 1158 return status == CMD_RST_PRC_OTHERS; 1159 } 1160 1161 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_v2_cmq_ring *ring) 1163 { 1164 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1165 1166 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1167 &ring->desc_dma_addr, GFP_KERNEL); 1168 if (!ring->desc) 1169 return -ENOMEM; 1170 1171 return 0; 1172 } 1173 1174 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1175 struct hns_roce_v2_cmq_ring *ring) 1176 { 1177 dma_free_coherent(hr_dev->dev, 1178 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1179 ring->desc, ring->desc_dma_addr); 1180 1181 ring->desc_dma_addr = 0; 1182 } 1183 1184 static int init_csq(struct hns_roce_dev *hr_dev, 1185 struct hns_roce_v2_cmq_ring *csq) 1186 { 1187 dma_addr_t dma; 1188 int ret; 1189 1190 csq->desc_num = CMD_CSQ_DESC_NUM; 1191 spin_lock_init(&csq->lock); 1192 csq->flag = TYPE_CSQ; 1193 csq->head = 0; 1194 1195 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1196 if (ret) 1197 return ret; 1198 1199 dma = csq->desc_dma_addr; 1200 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1201 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1202 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1203 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1204 1205 /* Make sure to write CI first and then PI */ 1206 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1207 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1208 1209 return 0; 1210 } 1211 1212 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1213 { 1214 struct hns_roce_v2_priv *priv = hr_dev->priv; 1215 int ret; 1216 1217 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1218 1219 ret = init_csq(hr_dev, &priv->cmq.csq); 1220 if (ret) 1221 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1222 1223 return ret; 1224 } 1225 1226 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1227 { 1228 struct hns_roce_v2_priv *priv = hr_dev->priv; 1229 1230 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1231 } 1232 1233 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1234 enum hns_roce_opcode_type opcode, 1235 bool is_read) 1236 { 1237 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1238 desc->opcode = cpu_to_le16(opcode); 1239 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1240 if (is_read) 1241 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1242 else 1243 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1244 } 1245 1246 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1247 { 1248 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1249 struct hns_roce_v2_priv *priv = hr_dev->priv; 1250 1251 return tail == priv->cmq.csq.head; 1252 } 1253 1254 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1255 { 1256 struct hns_roce_v2_priv *priv = hr_dev->priv; 1257 struct hnae3_handle *handle = priv->handle; 1258 1259 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1260 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1261 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1262 } 1263 1264 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1265 { 1266 struct hns_roce_cmd_errcode errcode_table[] = { 1267 {CMD_EXEC_SUCCESS, 0}, 1268 {CMD_NO_AUTH, -EPERM}, 1269 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1270 {CMD_CRQ_FULL, -EXFULL}, 1271 {CMD_NEXT_ERR, -ENOSR}, 1272 {CMD_NOT_EXEC, -ENOTBLK}, 1273 {CMD_PARA_ERR, -EINVAL}, 1274 {CMD_RESULT_ERR, -ERANGE}, 1275 {CMD_TIMEOUT, -ETIME}, 1276 {CMD_HILINK_ERR, -ENOLINK}, 1277 {CMD_INFO_ILLEGAL, -ENXIO}, 1278 {CMD_INVALID, -EBADR}, 1279 }; 1280 u16 i; 1281 1282 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1283 if (desc_ret == errcode_table[i].return_status) 1284 return errcode_table[i].errno; 1285 return -EIO; 1286 } 1287 1288 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1289 struct hns_roce_cmq_desc *desc, int num) 1290 { 1291 struct hns_roce_v2_priv *priv = hr_dev->priv; 1292 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1293 u32 timeout = 0; 1294 u16 desc_ret; 1295 u32 tail; 1296 int ret; 1297 int i; 1298 1299 spin_lock_bh(&csq->lock); 1300 1301 tail = csq->head; 1302 1303 for (i = 0; i < num; i++) { 1304 csq->desc[csq->head++] = desc[i]; 1305 if (csq->head == csq->desc_num) 1306 csq->head = 0; 1307 } 1308 1309 /* Write to hardware */ 1310 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1311 1312 do { 1313 if (hns_roce_cmq_csq_done(hr_dev)) 1314 break; 1315 udelay(1); 1316 } while (++timeout < priv->cmq.tx_timeout); 1317 1318 if (hns_roce_cmq_csq_done(hr_dev)) { 1319 ret = 0; 1320 for (i = 0; i < num; i++) { 1321 /* check the result of hardware write back */ 1322 desc[i] = csq->desc[tail++]; 1323 if (tail == csq->desc_num) 1324 tail = 0; 1325 1326 desc_ret = le16_to_cpu(desc[i].retval); 1327 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1328 continue; 1329 1330 dev_err_ratelimited(hr_dev->dev, 1331 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1332 desc->opcode, desc_ret); 1333 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1334 } 1335 } else { 1336 /* FW/HW reset or incorrect number of desc */ 1337 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1338 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1339 csq->head, tail); 1340 csq->head = tail; 1341 1342 update_cmdq_status(hr_dev); 1343 1344 ret = -EAGAIN; 1345 } 1346 1347 spin_unlock_bh(&csq->lock); 1348 1349 return ret; 1350 } 1351 1352 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1353 struct hns_roce_cmq_desc *desc, int num) 1354 { 1355 bool busy; 1356 int ret; 1357 1358 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1359 return -EIO; 1360 1361 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1362 return busy ? -EBUSY : 0; 1363 1364 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1365 if (ret) { 1366 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1367 return busy ? -EBUSY : 0; 1368 } 1369 1370 return ret; 1371 } 1372 1373 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1374 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1375 { 1376 struct hns_roce_cmd_mailbox *mbox; 1377 int ret; 1378 1379 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1380 if (IS_ERR(mbox)) 1381 return PTR_ERR(mbox); 1382 1383 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1384 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1385 return ret; 1386 } 1387 1388 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1389 { 1390 struct hns_roce_query_version *resp; 1391 struct hns_roce_cmq_desc desc; 1392 int ret; 1393 1394 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1395 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1396 if (ret) 1397 return ret; 1398 1399 resp = (struct hns_roce_query_version *)desc.data; 1400 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1401 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1402 1403 return 0; 1404 } 1405 1406 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1407 struct hnae3_handle *handle) 1408 { 1409 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1410 unsigned long end; 1411 1412 hr_dev->dis_db = true; 1413 1414 dev_warn(hr_dev->dev, 1415 "func clear is pending, device in resetting state.\n"); 1416 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1417 while (end) { 1418 if (!ops->get_hw_reset_stat(handle)) { 1419 hr_dev->is_reset = true; 1420 dev_info(hr_dev->dev, 1421 "func clear success after reset.\n"); 1422 return; 1423 } 1424 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1425 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1426 } 1427 1428 dev_warn(hr_dev->dev, "func clear failed.\n"); 1429 } 1430 1431 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1432 struct hnae3_handle *handle) 1433 { 1434 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1435 unsigned long end; 1436 1437 hr_dev->dis_db = true; 1438 1439 dev_warn(hr_dev->dev, 1440 "func clear is pending, device in resetting state.\n"); 1441 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1442 while (end) { 1443 if (ops->ae_dev_reset_cnt(handle) != 1444 hr_dev->reset_cnt) { 1445 hr_dev->is_reset = true; 1446 dev_info(hr_dev->dev, 1447 "func clear success after sw reset\n"); 1448 return; 1449 } 1450 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1451 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1452 } 1453 1454 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1455 } 1456 1457 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1458 int flag) 1459 { 1460 struct hns_roce_v2_priv *priv = hr_dev->priv; 1461 struct hnae3_handle *handle = priv->handle; 1462 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1463 1464 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1465 hr_dev->dis_db = true; 1466 hr_dev->is_reset = true; 1467 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1468 return; 1469 } 1470 1471 if (ops->get_hw_reset_stat(handle)) { 1472 func_clr_hw_resetting_state(hr_dev, handle); 1473 return; 1474 } 1475 1476 if (ops->ae_dev_resetting(handle) && 1477 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1478 func_clr_sw_resetting_state(hr_dev, handle); 1479 return; 1480 } 1481 1482 if (retval && !flag) 1483 dev_warn(hr_dev->dev, 1484 "func clear read failed, ret = %d.\n", retval); 1485 1486 dev_warn(hr_dev->dev, "func clear failed.\n"); 1487 } 1488 1489 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1490 { 1491 bool fclr_write_fail_flag = false; 1492 struct hns_roce_func_clear *resp; 1493 struct hns_roce_cmq_desc desc; 1494 unsigned long end; 1495 int ret = 0; 1496 1497 if (check_device_is_in_reset(hr_dev)) 1498 goto out; 1499 1500 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1501 resp = (struct hns_roce_func_clear *)desc.data; 1502 resp->rst_funcid_en = cpu_to_le32(vf_id); 1503 1504 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1505 if (ret) { 1506 fclr_write_fail_flag = true; 1507 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1508 ret); 1509 goto out; 1510 } 1511 1512 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1513 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1514 while (end) { 1515 if (check_device_is_in_reset(hr_dev)) 1516 goto out; 1517 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1518 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1519 1520 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1521 true); 1522 1523 resp->rst_funcid_en = cpu_to_le32(vf_id); 1524 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1525 if (ret) 1526 continue; 1527 1528 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1529 if (vf_id == 0) 1530 hr_dev->is_reset = true; 1531 return; 1532 } 1533 } 1534 1535 out: 1536 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1537 } 1538 1539 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1540 { 1541 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1542 struct hns_roce_cmq_desc desc[2]; 1543 struct hns_roce_cmq_req *req_a; 1544 1545 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1546 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1547 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1548 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1549 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1550 1551 return hns_roce_cmq_send(hr_dev, desc, 2); 1552 } 1553 1554 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1555 { 1556 int ret; 1557 int i; 1558 1559 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1560 return; 1561 1562 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1563 __hns_roce_function_clear(hr_dev, i); 1564 1565 if (i == 0) 1566 continue; 1567 1568 ret = hns_roce_free_vf_resource(hr_dev, i); 1569 if (ret) 1570 ibdev_err(&hr_dev->ib_dev, 1571 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1572 i, ret); 1573 } 1574 } 1575 1576 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1577 { 1578 struct hns_roce_cmq_desc desc; 1579 int ret; 1580 1581 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1582 false); 1583 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1584 if (ret) 1585 ibdev_err(&hr_dev->ib_dev, 1586 "failed to clear extended doorbell info, ret = %d.\n", 1587 ret); 1588 1589 return ret; 1590 } 1591 1592 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1593 { 1594 struct hns_roce_query_fw_info *resp; 1595 struct hns_roce_cmq_desc desc; 1596 int ret; 1597 1598 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1599 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1600 if (ret) 1601 return ret; 1602 1603 resp = (struct hns_roce_query_fw_info *)desc.data; 1604 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1605 1606 return 0; 1607 } 1608 1609 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1610 { 1611 struct hns_roce_cmq_desc desc; 1612 int ret; 1613 1614 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1615 hr_dev->func_num = 1; 1616 return 0; 1617 } 1618 1619 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1620 true); 1621 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1622 if (ret) { 1623 hr_dev->func_num = 1; 1624 return ret; 1625 } 1626 1627 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1628 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1629 1630 return 0; 1631 } 1632 1633 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1634 { 1635 struct hns_roce_cmq_desc desc; 1636 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1637 u32 clock_cycles_of_1us; 1638 1639 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1640 false); 1641 1642 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1643 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1644 else 1645 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1646 1647 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1648 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1649 1650 return hns_roce_cmq_send(hr_dev, &desc, 1); 1651 } 1652 1653 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1654 { 1655 struct hns_roce_cmq_desc desc[2]; 1656 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1657 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1658 struct hns_roce_caps *caps = &hr_dev->caps; 1659 enum hns_roce_opcode_type opcode; 1660 u32 func_num; 1661 int ret; 1662 1663 if (is_vf) { 1664 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1665 func_num = 1; 1666 } else { 1667 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1668 func_num = hr_dev->func_num; 1669 } 1670 1671 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1672 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1673 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1674 1675 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1676 if (ret) 1677 return ret; 1678 1679 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1680 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1681 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1682 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1683 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1684 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1685 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1686 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1687 1688 if (is_vf) { 1689 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1690 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1691 func_num; 1692 } else { 1693 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1694 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1695 func_num; 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1702 { 1703 struct hns_roce_cmq_desc desc; 1704 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1705 struct hns_roce_caps *caps = &hr_dev->caps; 1706 u32 func_num, qp_num; 1707 int ret; 1708 1709 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1710 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1711 if (ret) 1712 return ret; 1713 1714 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1715 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1716 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1717 1718 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1719 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1720 1721 return 0; 1722 } 1723 1724 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1725 { 1726 struct hns_roce_cmq_desc desc; 1727 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1728 struct hns_roce_caps *caps = &hr_dev->caps; 1729 int ret; 1730 1731 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1732 true); 1733 1734 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1735 if (ret) 1736 return ret; 1737 1738 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1739 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1740 1741 return 0; 1742 } 1743 1744 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1745 { 1746 struct device *dev = hr_dev->dev; 1747 int ret; 1748 1749 ret = load_func_res_caps(hr_dev, is_vf); 1750 if (ret) { 1751 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1752 is_vf ? "vf" : "pf"); 1753 return ret; 1754 } 1755 1756 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1757 ret = load_ext_cfg_caps(hr_dev, is_vf); 1758 if (ret) 1759 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1760 ret, is_vf ? "vf" : "pf"); 1761 } 1762 1763 return ret; 1764 } 1765 1766 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1767 { 1768 struct device *dev = hr_dev->dev; 1769 int ret; 1770 1771 ret = query_func_resource_caps(hr_dev, false); 1772 if (ret) 1773 return ret; 1774 1775 ret = load_pf_timer_res_caps(hr_dev); 1776 if (ret) 1777 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1778 ret); 1779 1780 return ret; 1781 } 1782 1783 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1784 { 1785 return query_func_resource_caps(hr_dev, true); 1786 } 1787 1788 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1789 u32 vf_id) 1790 { 1791 struct hns_roce_vf_switch *swt; 1792 struct hns_roce_cmq_desc desc; 1793 int ret; 1794 1795 swt = (struct hns_roce_vf_switch *)desc.data; 1796 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1797 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1798 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1799 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1800 if (ret) 1801 return ret; 1802 1803 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1804 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1805 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1806 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1807 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1808 1809 return hns_roce_cmq_send(hr_dev, &desc, 1); 1810 } 1811 1812 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1813 { 1814 u32 vf_id; 1815 int ret; 1816 1817 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1818 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1819 if (ret) 1820 return ret; 1821 } 1822 return 0; 1823 } 1824 1825 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1826 { 1827 struct hns_roce_cmq_desc desc[2]; 1828 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1829 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1830 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1831 struct hns_roce_caps *caps = &hr_dev->caps; 1832 1833 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1834 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1835 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1836 1837 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1838 1839 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1840 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1841 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1842 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1843 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1844 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1845 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1846 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1847 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1848 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1849 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1850 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1851 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1852 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1853 1854 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1855 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1856 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1857 vf_id * caps->gmv_bt_num); 1858 } else { 1859 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1860 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1861 vf_id * caps->sgid_bt_num); 1862 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1863 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1864 vf_id * caps->smac_bt_num); 1865 } 1866 1867 return hns_roce_cmq_send(hr_dev, desc, 2); 1868 } 1869 1870 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1871 { 1872 struct hns_roce_cmq_desc desc; 1873 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1874 struct hns_roce_caps *caps = &hr_dev->caps; 1875 1876 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1877 1878 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1879 1880 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1881 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1882 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1883 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1884 1885 return hns_roce_cmq_send(hr_dev, &desc, 1); 1886 } 1887 1888 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1889 { 1890 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1891 u32 vf_id; 1892 int ret; 1893 1894 for (vf_id = 0; vf_id < func_num; vf_id++) { 1895 ret = config_vf_hem_resource(hr_dev, vf_id); 1896 if (ret) { 1897 dev_err(hr_dev->dev, 1898 "failed to config vf-%u hem res, ret = %d.\n", 1899 vf_id, ret); 1900 return ret; 1901 } 1902 1903 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1904 ret = config_vf_ext_resource(hr_dev, vf_id); 1905 if (ret) { 1906 dev_err(hr_dev->dev, 1907 "failed to config vf-%u ext res, ret = %d.\n", 1908 vf_id, ret); 1909 return ret; 1910 } 1911 } 1912 } 1913 1914 return 0; 1915 } 1916 1917 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1918 { 1919 struct hns_roce_cmq_desc desc; 1920 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1921 struct hns_roce_caps *caps = &hr_dev->caps; 1922 1923 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1924 1925 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1926 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1927 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1928 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1930 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1931 1932 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1933 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1934 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1935 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1937 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1938 1939 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1940 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1941 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1942 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1943 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1944 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1945 1946 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1947 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1948 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1949 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1950 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1951 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1952 1953 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1954 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1955 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1956 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1957 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1958 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1959 1960 return hns_roce_cmq_send(hr_dev, &desc, 1); 1961 } 1962 1963 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1964 static void set_default_caps(struct hns_roce_dev *hr_dev) 1965 { 1966 struct hns_roce_caps *caps = &hr_dev->caps; 1967 1968 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1969 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1970 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1971 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1972 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1973 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1974 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1975 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1976 1977 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1978 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1979 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1980 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1981 caps->num_comp_vectors = 0; 1982 1983 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1984 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1985 caps->qpc_timer_bt_num = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM; 1986 caps->cqc_timer_bt_num = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM; 1987 1988 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1989 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1990 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1991 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1992 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1993 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1994 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1995 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1996 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1997 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1998 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1999 caps->reserved_lkey = 0; 2000 caps->reserved_pds = 0; 2001 caps->reserved_mrws = 1; 2002 caps->reserved_uars = 0; 2003 caps->reserved_cqs = 0; 2004 caps->reserved_srqs = 0; 2005 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 2006 2007 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2008 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2009 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2010 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2011 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 2012 2013 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 2014 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 2015 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 2016 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 2017 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 2018 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 2019 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 2020 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 2021 2022 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 2023 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 2024 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 2025 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 2026 2027 caps->pkey_table_len[0] = 1; 2028 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 2029 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 2030 caps->local_ca_ack_delay = 0; 2031 caps->max_mtu = IB_MTU_4096; 2032 2033 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 2034 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 2035 2036 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 2037 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 2038 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; 2039 2040 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 2041 2042 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2043 caps->flags |= HNS_ROCE_CAP_FLAG_STASH | 2044 HNS_ROCE_CAP_FLAG_DIRECT_WQE | 2045 HNS_ROCE_CAP_FLAG_XRC; 2046 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 2047 } else { 2048 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 2049 2050 /* The following configuration are only valid for HIP08 */ 2051 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2052 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 2053 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2054 } 2055 } 2056 2057 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2058 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2059 { 2060 u64 obj_per_chunk; 2061 u64 bt_chunk_size = PAGE_SIZE; 2062 u64 buf_chunk_size = PAGE_SIZE; 2063 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2064 2065 *buf_page_size = 0; 2066 *bt_page_size = 0; 2067 2068 switch (hop_num) { 2069 case 3: 2070 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2071 (bt_chunk_size / BA_BYTE_LEN) * 2072 (bt_chunk_size / BA_BYTE_LEN) * 2073 obj_per_chunk_default; 2074 break; 2075 case 2: 2076 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2077 (bt_chunk_size / BA_BYTE_LEN) * 2078 obj_per_chunk_default; 2079 break; 2080 case 1: 2081 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2082 obj_per_chunk_default; 2083 break; 2084 case HNS_ROCE_HOP_NUM_0: 2085 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2086 break; 2087 default: 2088 pr_err("table %u not support hop_num = %u!\n", hem_type, 2089 hop_num); 2090 return; 2091 } 2092 2093 if (hem_type >= HEM_TYPE_MTT) 2094 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2095 else 2096 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2097 } 2098 2099 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2100 { 2101 struct hns_roce_caps *caps = &hr_dev->caps; 2102 2103 /* EQ */ 2104 caps->eqe_ba_pg_sz = 0; 2105 caps->eqe_buf_pg_sz = 0; 2106 2107 /* Link Table */ 2108 caps->llm_buf_pg_sz = 0; 2109 2110 /* MR */ 2111 caps->mpt_ba_pg_sz = 0; 2112 caps->mpt_buf_pg_sz = 0; 2113 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2114 caps->pbl_buf_pg_sz = 0; 2115 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2116 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2117 HEM_TYPE_MTPT); 2118 2119 /* QP */ 2120 caps->qpc_ba_pg_sz = 0; 2121 caps->qpc_buf_pg_sz = 0; 2122 caps->qpc_timer_ba_pg_sz = 0; 2123 caps->qpc_timer_buf_pg_sz = 0; 2124 caps->sccc_ba_pg_sz = 0; 2125 caps->sccc_buf_pg_sz = 0; 2126 caps->mtt_ba_pg_sz = 0; 2127 caps->mtt_buf_pg_sz = 0; 2128 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2129 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2130 HEM_TYPE_QPC); 2131 2132 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2133 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2134 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2135 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2136 2137 /* CQ */ 2138 caps->cqc_ba_pg_sz = 0; 2139 caps->cqc_buf_pg_sz = 0; 2140 caps->cqc_timer_ba_pg_sz = 0; 2141 caps->cqc_timer_buf_pg_sz = 0; 2142 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2143 caps->cqe_buf_pg_sz = 0; 2144 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2145 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2146 HEM_TYPE_CQC); 2147 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2148 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2149 2150 /* SRQ */ 2151 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2152 caps->srqc_ba_pg_sz = 0; 2153 caps->srqc_buf_pg_sz = 0; 2154 caps->srqwqe_ba_pg_sz = 0; 2155 caps->srqwqe_buf_pg_sz = 0; 2156 caps->idx_ba_pg_sz = 0; 2157 caps->idx_buf_pg_sz = 0; 2158 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2159 caps->srqc_hop_num, caps->srqc_bt_num, 2160 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2161 HEM_TYPE_SRQC); 2162 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2163 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2164 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2165 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2166 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2167 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2168 } 2169 2170 /* GMV */ 2171 caps->gmv_ba_pg_sz = 0; 2172 caps->gmv_buf_pg_sz = 0; 2173 } 2174 2175 /* Apply all loaded caps before setting to hardware */ 2176 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2177 { 2178 struct hns_roce_caps *caps = &hr_dev->caps; 2179 struct hns_roce_v2_priv *priv = hr_dev->priv; 2180 2181 /* The following configurations don't need to be got from firmware. */ 2182 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2183 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2184 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2185 2186 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2187 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2188 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2189 2190 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2191 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2192 2193 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2194 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2195 2196 if (!caps->num_comp_vectors) 2197 caps->num_comp_vectors = 2198 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2199 (u32)priv->handle->rinfo.num_vectors - 2200 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2201 2202 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2203 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2204 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2205 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2206 2207 /* The following configurations will be overwritten */ 2208 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2209 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2210 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2211 2212 /* The following configurations are not got from firmware */ 2213 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2214 2215 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2216 caps->gid_table_len[0] = caps->gmv_bt_num * 2217 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2218 2219 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2220 caps->gmv_entry_sz); 2221 } else { 2222 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2223 2224 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2225 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2226 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2227 caps->gid_table_len[0] /= func_num; 2228 } 2229 2230 if (hr_dev->is_vf) { 2231 caps->default_aeq_arm_st = 0x3; 2232 caps->default_ceq_arm_st = 0x3; 2233 caps->default_ceq_max_cnt = 0x1; 2234 caps->default_ceq_period = 0x10; 2235 caps->default_aeq_max_cnt = 0x1; 2236 caps->default_aeq_period = 0x10; 2237 } 2238 2239 set_hem_page_size(hr_dev); 2240 } 2241 2242 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2243 { 2244 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2245 struct hns_roce_caps *caps = &hr_dev->caps; 2246 struct hns_roce_query_pf_caps_a *resp_a; 2247 struct hns_roce_query_pf_caps_b *resp_b; 2248 struct hns_roce_query_pf_caps_c *resp_c; 2249 struct hns_roce_query_pf_caps_d *resp_d; 2250 struct hns_roce_query_pf_caps_e *resp_e; 2251 int ctx_hop_num; 2252 int pbl_hop_num; 2253 int ret; 2254 int i; 2255 2256 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2257 hns_roce_cmq_setup_basic_desc(&desc[i], 2258 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2259 true); 2260 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2261 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2262 else 2263 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2264 } 2265 2266 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2267 if (ret) 2268 return ret; 2269 2270 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2271 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2272 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2273 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2274 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2275 2276 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2277 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2278 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2279 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2280 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2281 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2282 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2283 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2284 caps->num_other_vectors = resp_a->num_other_vectors; 2285 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2286 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2287 caps->cqe_sz = resp_a->cqe_sz; 2288 2289 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2290 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2291 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2292 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2293 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2294 caps->idx_entry_sz = resp_b->idx_entry_sz; 2295 caps->sccc_sz = resp_b->sccc_sz; 2296 caps->max_mtu = resp_b->max_mtu; 2297 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2298 caps->min_cqes = resp_b->min_cqes; 2299 caps->min_wqes = resp_b->min_wqes; 2300 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2301 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2302 caps->phy_num_uars = resp_b->phy_num_uars; 2303 ctx_hop_num = resp_b->ctx_hop_num; 2304 pbl_hop_num = resp_b->pbl_hop_num; 2305 2306 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2307 2308 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2309 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2310 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2311 2312 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2313 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2314 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2315 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2316 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2317 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2318 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2319 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2320 2321 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2322 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2323 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2324 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2325 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2326 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2327 caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2328 caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2329 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2330 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2331 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2332 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2333 2334 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2335 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2336 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2337 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2338 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2339 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2340 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2341 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2342 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2343 2344 caps->qpc_hop_num = ctx_hop_num; 2345 caps->sccc_hop_num = ctx_hop_num; 2346 caps->srqc_hop_num = ctx_hop_num; 2347 caps->cqc_hop_num = ctx_hop_num; 2348 caps->mpt_hop_num = ctx_hop_num; 2349 caps->mtt_hop_num = pbl_hop_num; 2350 caps->cqe_hop_num = pbl_hop_num; 2351 caps->srqwqe_hop_num = pbl_hop_num; 2352 caps->idx_hop_num = pbl_hop_num; 2353 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2354 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2355 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2356 2357 if (!(caps->page_size_cap & PAGE_SIZE)) 2358 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2359 2360 return 0; 2361 } 2362 2363 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2364 { 2365 struct hns_roce_cmq_desc desc; 2366 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2367 2368 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2369 false); 2370 2371 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2372 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2373 2374 return hns_roce_cmq_send(hr_dev, &desc, 1); 2375 } 2376 2377 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2378 { 2379 struct hns_roce_caps *caps = &hr_dev->caps; 2380 int ret; 2381 2382 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2383 return 0; 2384 2385 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2386 caps->qpc_sz); 2387 if (ret) { 2388 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2389 return ret; 2390 } 2391 2392 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2393 caps->sccc_sz); 2394 if (ret) 2395 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2396 2397 return ret; 2398 } 2399 2400 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2401 { 2402 struct device *dev = hr_dev->dev; 2403 int ret; 2404 2405 hr_dev->func_num = 1; 2406 2407 set_default_caps(hr_dev); 2408 2409 ret = hns_roce_query_vf_resource(hr_dev); 2410 if (ret) { 2411 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2412 return ret; 2413 } 2414 2415 apply_func_caps(hr_dev); 2416 2417 ret = hns_roce_v2_set_bt(hr_dev); 2418 if (ret) 2419 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2420 2421 return ret; 2422 } 2423 2424 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2425 { 2426 struct device *dev = hr_dev->dev; 2427 int ret; 2428 2429 ret = hns_roce_query_func_info(hr_dev); 2430 if (ret) { 2431 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2432 return ret; 2433 } 2434 2435 ret = hns_roce_config_global_param(hr_dev); 2436 if (ret) { 2437 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2438 return ret; 2439 } 2440 2441 ret = hns_roce_set_vf_switch_param(hr_dev); 2442 if (ret) { 2443 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2444 return ret; 2445 } 2446 2447 ret = hns_roce_query_pf_caps(hr_dev); 2448 if (ret) 2449 set_default_caps(hr_dev); 2450 2451 ret = hns_roce_query_pf_resource(hr_dev); 2452 if (ret) { 2453 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2454 return ret; 2455 } 2456 2457 apply_func_caps(hr_dev); 2458 2459 ret = hns_roce_alloc_vf_resource(hr_dev); 2460 if (ret) { 2461 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2462 return ret; 2463 } 2464 2465 ret = hns_roce_v2_set_bt(hr_dev); 2466 if (ret) { 2467 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2468 return ret; 2469 } 2470 2471 /* Configure the size of QPC, SCCC, etc. */ 2472 return hns_roce_config_entry_size(hr_dev); 2473 } 2474 2475 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2476 { 2477 struct device *dev = hr_dev->dev; 2478 int ret; 2479 2480 ret = hns_roce_cmq_query_hw_info(hr_dev); 2481 if (ret) { 2482 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2483 return ret; 2484 } 2485 2486 ret = hns_roce_query_fw_ver(hr_dev); 2487 if (ret) { 2488 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2489 return ret; 2490 } 2491 2492 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2493 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2494 2495 if (hr_dev->is_vf) 2496 return hns_roce_v2_vf_profile(hr_dev); 2497 else 2498 return hns_roce_v2_pf_profile(hr_dev); 2499 } 2500 2501 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2502 { 2503 u32 i, next_ptr, page_num; 2504 __le64 *entry = cfg_buf; 2505 dma_addr_t addr; 2506 u64 val; 2507 2508 page_num = data_buf->npages; 2509 for (i = 0; i < page_num; i++) { 2510 addr = hns_roce_buf_page(data_buf, i); 2511 if (i == (page_num - 1)) 2512 next_ptr = 0; 2513 else 2514 next_ptr = i + 1; 2515 2516 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2517 entry[i] = cpu_to_le64(val); 2518 } 2519 } 2520 2521 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2522 struct hns_roce_link_table *table) 2523 { 2524 struct hns_roce_cmq_desc desc[2]; 2525 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2526 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2527 struct hns_roce_buf *buf = table->buf; 2528 enum hns_roce_opcode_type opcode; 2529 dma_addr_t addr; 2530 2531 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2532 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2533 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2534 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2535 2536 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2537 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2538 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2539 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2540 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2541 2542 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2543 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2544 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2545 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2546 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2547 2548 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2549 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2550 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2551 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2552 2553 return hns_roce_cmq_send(hr_dev, desc, 2); 2554 } 2555 2556 static struct hns_roce_link_table * 2557 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2558 { 2559 struct hns_roce_v2_priv *priv = hr_dev->priv; 2560 struct hns_roce_link_table *link_tbl; 2561 u32 pg_shift, size, min_size; 2562 2563 link_tbl = &priv->ext_llm; 2564 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2565 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2566 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2567 2568 /* Alloc data table */ 2569 size = max(size, min_size); 2570 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2571 if (IS_ERR(link_tbl->buf)) 2572 return ERR_PTR(-ENOMEM); 2573 2574 /* Alloc config table */ 2575 size = link_tbl->buf->npages * sizeof(u64); 2576 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2577 &link_tbl->table.map, 2578 GFP_KERNEL); 2579 if (!link_tbl->table.buf) { 2580 hns_roce_buf_free(hr_dev, link_tbl->buf); 2581 return ERR_PTR(-ENOMEM); 2582 } 2583 2584 return link_tbl; 2585 } 2586 2587 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2588 struct hns_roce_link_table *tbl) 2589 { 2590 if (tbl->buf) { 2591 u32 size = tbl->buf->npages * sizeof(u64); 2592 2593 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2594 tbl->table.map); 2595 } 2596 2597 hns_roce_buf_free(hr_dev, tbl->buf); 2598 } 2599 2600 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2601 { 2602 struct hns_roce_link_table *link_tbl; 2603 int ret; 2604 2605 link_tbl = alloc_link_table_buf(hr_dev); 2606 if (IS_ERR(link_tbl)) 2607 return -ENOMEM; 2608 2609 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2610 ret = -EINVAL; 2611 goto err_alloc; 2612 } 2613 2614 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2615 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2616 if (ret) 2617 goto err_alloc; 2618 2619 return 0; 2620 2621 err_alloc: 2622 free_link_table_buf(hr_dev, link_tbl); 2623 return ret; 2624 } 2625 2626 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2627 { 2628 struct hns_roce_v2_priv *priv = hr_dev->priv; 2629 2630 free_link_table_buf(hr_dev, &priv->ext_llm); 2631 } 2632 2633 static void free_dip_list(struct hns_roce_dev *hr_dev) 2634 { 2635 struct hns_roce_dip *hr_dip; 2636 struct hns_roce_dip *tmp; 2637 unsigned long flags; 2638 2639 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2640 2641 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2642 list_del(&hr_dip->node); 2643 kfree(hr_dip); 2644 } 2645 2646 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2647 } 2648 2649 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2650 { 2651 struct hns_roce_v2_priv *priv = hr_dev->priv; 2652 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2653 struct ib_device *ibdev = &hr_dev->ib_dev; 2654 struct hns_roce_pd *hr_pd; 2655 struct ib_pd *pd; 2656 2657 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2658 if (ZERO_OR_NULL_PTR(hr_pd)) 2659 return NULL; 2660 pd = &hr_pd->ibpd; 2661 pd->device = ibdev; 2662 2663 if (hns_roce_alloc_pd(pd, NULL)) { 2664 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2665 kfree(hr_pd); 2666 return NULL; 2667 } 2668 free_mr->rsv_pd = to_hr_pd(pd); 2669 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2670 free_mr->rsv_pd->ibpd.uobject = NULL; 2671 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2672 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2673 2674 return pd; 2675 } 2676 2677 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2678 { 2679 struct hns_roce_v2_priv *priv = hr_dev->priv; 2680 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2681 struct ib_device *ibdev = &hr_dev->ib_dev; 2682 struct ib_cq_init_attr cq_init_attr = {}; 2683 struct hns_roce_cq *hr_cq; 2684 struct ib_cq *cq; 2685 2686 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2687 2688 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2689 if (ZERO_OR_NULL_PTR(hr_cq)) 2690 return NULL; 2691 2692 cq = &hr_cq->ib_cq; 2693 cq->device = ibdev; 2694 2695 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2696 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2697 kfree(hr_cq); 2698 return NULL; 2699 } 2700 free_mr->rsv_cq = to_hr_cq(cq); 2701 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2702 free_mr->rsv_cq->ib_cq.uobject = NULL; 2703 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2704 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2705 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2706 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2707 2708 return cq; 2709 } 2710 2711 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2712 struct ib_qp_init_attr *init_attr, int i) 2713 { 2714 struct hns_roce_v2_priv *priv = hr_dev->priv; 2715 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2716 struct ib_device *ibdev = &hr_dev->ib_dev; 2717 struct hns_roce_qp *hr_qp; 2718 struct ib_qp *qp; 2719 int ret; 2720 2721 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2722 if (ZERO_OR_NULL_PTR(hr_qp)) 2723 return -ENOMEM; 2724 2725 qp = &hr_qp->ibqp; 2726 qp->device = ibdev; 2727 2728 ret = hns_roce_create_qp(qp, init_attr, NULL); 2729 if (ret) { 2730 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2731 kfree(hr_qp); 2732 return ret; 2733 } 2734 2735 free_mr->rsv_qp[i] = hr_qp; 2736 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2737 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2738 2739 return 0; 2740 } 2741 2742 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2743 { 2744 struct hns_roce_v2_priv *priv = hr_dev->priv; 2745 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2746 struct ib_qp *qp; 2747 int i; 2748 2749 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2750 if (free_mr->rsv_qp[i]) { 2751 qp = &free_mr->rsv_qp[i]->ibqp; 2752 hns_roce_v2_destroy_qp(qp, NULL); 2753 kfree(free_mr->rsv_qp[i]); 2754 free_mr->rsv_qp[i] = NULL; 2755 } 2756 } 2757 2758 if (free_mr->rsv_cq) { 2759 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2760 kfree(free_mr->rsv_cq); 2761 free_mr->rsv_cq = NULL; 2762 } 2763 2764 if (free_mr->rsv_pd) { 2765 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2766 kfree(free_mr->rsv_pd); 2767 free_mr->rsv_pd = NULL; 2768 } 2769 } 2770 2771 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2772 { 2773 struct hns_roce_v2_priv *priv = hr_dev->priv; 2774 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2775 struct ib_qp_init_attr qp_init_attr = {}; 2776 struct ib_pd *pd; 2777 struct ib_cq *cq; 2778 int ret; 2779 int i; 2780 2781 pd = free_mr_init_pd(hr_dev); 2782 if (!pd) 2783 return -ENOMEM; 2784 2785 cq = free_mr_init_cq(hr_dev); 2786 if (!cq) { 2787 ret = -ENOMEM; 2788 goto create_failed_cq; 2789 } 2790 2791 qp_init_attr.qp_type = IB_QPT_RC; 2792 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2793 qp_init_attr.send_cq = cq; 2794 qp_init_attr.recv_cq = cq; 2795 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2796 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2797 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2798 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2799 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2800 2801 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2802 if (ret) 2803 goto create_failed_qp; 2804 } 2805 2806 return 0; 2807 2808 create_failed_qp: 2809 hns_roce_destroy_cq(cq, NULL); 2810 kfree(cq); 2811 2812 create_failed_cq: 2813 hns_roce_dealloc_pd(pd, NULL); 2814 kfree(pd); 2815 2816 return ret; 2817 } 2818 2819 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2820 struct ib_qp_attr *attr, int sl_num) 2821 { 2822 struct hns_roce_v2_priv *priv = hr_dev->priv; 2823 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2824 struct ib_device *ibdev = &hr_dev->ib_dev; 2825 struct hns_roce_qp *hr_qp; 2826 int loopback; 2827 int mask; 2828 int ret; 2829 2830 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2831 hr_qp->free_mr_en = 1; 2832 hr_qp->ibqp.device = ibdev; 2833 hr_qp->ibqp.qp_type = IB_QPT_RC; 2834 2835 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2836 attr->qp_state = IB_QPS_INIT; 2837 attr->port_num = 1; 2838 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2839 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2840 IB_QPS_INIT, NULL); 2841 if (ret) { 2842 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2843 ret); 2844 return ret; 2845 } 2846 2847 loopback = hr_dev->loop_idc; 2848 /* Set qpc lbi = 1 incidate loopback IO */ 2849 hr_dev->loop_idc = 1; 2850 2851 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2852 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2853 attr->qp_state = IB_QPS_RTR; 2854 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2855 attr->path_mtu = IB_MTU_256; 2856 attr->dest_qp_num = hr_qp->qpn; 2857 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2858 2859 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2860 2861 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2862 IB_QPS_RTR, NULL); 2863 hr_dev->loop_idc = loopback; 2864 if (ret) { 2865 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2866 ret); 2867 return ret; 2868 } 2869 2870 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2871 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2872 attr->qp_state = IB_QPS_RTS; 2873 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2874 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2875 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2876 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2877 IB_QPS_RTS, NULL); 2878 if (ret) 2879 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2880 ret); 2881 2882 return ret; 2883 } 2884 2885 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2886 { 2887 struct hns_roce_v2_priv *priv = hr_dev->priv; 2888 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2889 struct ib_qp_attr attr = {}; 2890 int ret; 2891 int i; 2892 2893 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2894 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2895 rdma_ah_set_port_num(&attr.ah_attr, 1); 2896 2897 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2898 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2899 if (ret) 2900 return ret; 2901 } 2902 2903 return 0; 2904 } 2905 2906 static int free_mr_init(struct hns_roce_dev *hr_dev) 2907 { 2908 struct hns_roce_v2_priv *priv = hr_dev->priv; 2909 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2910 int ret; 2911 2912 mutex_init(&free_mr->mutex); 2913 2914 ret = free_mr_alloc_res(hr_dev); 2915 if (ret) 2916 return ret; 2917 2918 ret = free_mr_modify_qp(hr_dev); 2919 if (ret) 2920 goto err_modify_qp; 2921 2922 return 0; 2923 2924 err_modify_qp: 2925 free_mr_exit(hr_dev); 2926 2927 return ret; 2928 } 2929 2930 static int get_hem_table(struct hns_roce_dev *hr_dev) 2931 { 2932 unsigned int qpc_count; 2933 unsigned int cqc_count; 2934 unsigned int gmv_count; 2935 int ret; 2936 int i; 2937 2938 /* Alloc memory for source address table buffer space chunk */ 2939 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2940 gmv_count++) { 2941 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2942 if (ret) 2943 goto err_gmv_failed; 2944 } 2945 2946 if (hr_dev->is_vf) 2947 return 0; 2948 2949 /* Alloc memory for QPC Timer buffer space chunk */ 2950 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2951 qpc_count++) { 2952 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2953 qpc_count); 2954 if (ret) { 2955 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2956 goto err_qpc_timer_failed; 2957 } 2958 } 2959 2960 /* Alloc memory for CQC Timer buffer space chunk */ 2961 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2962 cqc_count++) { 2963 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2964 cqc_count); 2965 if (ret) { 2966 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2967 goto err_cqc_timer_failed; 2968 } 2969 } 2970 2971 return 0; 2972 2973 err_cqc_timer_failed: 2974 for (i = 0; i < cqc_count; i++) 2975 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2976 2977 err_qpc_timer_failed: 2978 for (i = 0; i < qpc_count; i++) 2979 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2980 2981 err_gmv_failed: 2982 for (i = 0; i < gmv_count; i++) 2983 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2984 2985 return ret; 2986 } 2987 2988 static void put_hem_table(struct hns_roce_dev *hr_dev) 2989 { 2990 int i; 2991 2992 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2993 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2994 2995 if (hr_dev->is_vf) 2996 return; 2997 2998 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2999 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 3000 3001 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 3002 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 3003 } 3004 3005 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 3006 { 3007 int ret; 3008 3009 /* The hns ROCEE requires the extdb info to be cleared before using */ 3010 ret = hns_roce_clear_extdb_list_info(hr_dev); 3011 if (ret) 3012 return ret; 3013 3014 ret = get_hem_table(hr_dev); 3015 if (ret) 3016 return ret; 3017 3018 if (hr_dev->is_vf) 3019 return 0; 3020 3021 ret = hns_roce_init_link_table(hr_dev); 3022 if (ret) { 3023 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 3024 goto err_llm_init_failed; 3025 } 3026 3027 return 0; 3028 3029 err_llm_init_failed: 3030 put_hem_table(hr_dev); 3031 3032 return ret; 3033 } 3034 3035 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3036 { 3037 hns_roce_function_clear(hr_dev); 3038 3039 if (!hr_dev->is_vf) 3040 hns_roce_free_link_table(hr_dev); 3041 3042 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 3043 free_dip_list(hr_dev); 3044 } 3045 3046 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3047 struct hns_roce_mbox_msg *mbox_msg) 3048 { 3049 struct hns_roce_cmq_desc desc; 3050 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3051 3052 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3053 3054 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3055 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3056 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3057 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3058 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3059 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3060 mbox_msg->token); 3061 3062 return hns_roce_cmq_send(hr_dev, &desc, 1); 3063 } 3064 3065 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3066 u8 *complete_status) 3067 { 3068 struct hns_roce_mbox_status *mb_st; 3069 struct hns_roce_cmq_desc desc; 3070 unsigned long end; 3071 int ret = -EBUSY; 3072 u32 status; 3073 bool busy; 3074 3075 mb_st = (struct hns_roce_mbox_status *)desc.data; 3076 end = msecs_to_jiffies(timeout) + jiffies; 3077 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3078 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3079 return -EIO; 3080 3081 status = 0; 3082 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3083 true); 3084 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3085 if (!ret) { 3086 status = le32_to_cpu(mb_st->mb_status_hw_run); 3087 /* No pending message exists in ROCEE mbox. */ 3088 if (!(status & MB_ST_HW_RUN_M)) 3089 break; 3090 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3091 break; 3092 } 3093 3094 if (time_after(jiffies, end)) { 3095 dev_err_ratelimited(hr_dev->dev, 3096 "failed to wait mbox status 0x%x\n", 3097 status); 3098 return -ETIMEDOUT; 3099 } 3100 3101 cond_resched(); 3102 ret = -EBUSY; 3103 } 3104 3105 if (!ret) { 3106 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3107 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3108 /* Ignore all errors if the mbox is unavailable. */ 3109 ret = 0; 3110 *complete_status = MB_ST_COMPLETE_M; 3111 } 3112 3113 return ret; 3114 } 3115 3116 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3117 struct hns_roce_mbox_msg *mbox_msg) 3118 { 3119 u8 status = 0; 3120 int ret; 3121 3122 /* Waiting for the mbox to be idle */ 3123 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3124 &status); 3125 if (unlikely(ret)) { 3126 dev_err_ratelimited(hr_dev->dev, 3127 "failed to check post mbox status = 0x%x, ret = %d.\n", 3128 status, ret); 3129 return ret; 3130 } 3131 3132 /* Post new message to mbox */ 3133 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3134 if (ret) 3135 dev_err_ratelimited(hr_dev->dev, 3136 "failed to post mailbox, ret = %d.\n", ret); 3137 3138 return ret; 3139 } 3140 3141 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3142 { 3143 u8 status = 0; 3144 int ret; 3145 3146 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3147 &status); 3148 if (!ret) { 3149 if (status != MB_ST_COMPLETE_SUCC) 3150 return -EBUSY; 3151 } else { 3152 dev_err_ratelimited(hr_dev->dev, 3153 "failed to check mbox status = 0x%x, ret = %d.\n", 3154 status, ret); 3155 } 3156 3157 return ret; 3158 } 3159 3160 static void copy_gid(void *dest, const union ib_gid *gid) 3161 { 3162 #define GID_SIZE 4 3163 const union ib_gid *src = gid; 3164 __le32 (*p)[GID_SIZE] = dest; 3165 int i; 3166 3167 if (!gid) 3168 src = &zgid; 3169 3170 for (i = 0; i < GID_SIZE; i++) 3171 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3172 } 3173 3174 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3175 int gid_index, const union ib_gid *gid, 3176 enum hns_roce_sgid_type sgid_type) 3177 { 3178 struct hns_roce_cmq_desc desc; 3179 struct hns_roce_cfg_sgid_tb *sgid_tb = 3180 (struct hns_roce_cfg_sgid_tb *)desc.data; 3181 3182 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3183 3184 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3185 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3186 3187 copy_gid(&sgid_tb->vf_sgid_l, gid); 3188 3189 return hns_roce_cmq_send(hr_dev, &desc, 1); 3190 } 3191 3192 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3193 int gid_index, const union ib_gid *gid, 3194 enum hns_roce_sgid_type sgid_type, 3195 const struct ib_gid_attr *attr) 3196 { 3197 struct hns_roce_cmq_desc desc[2]; 3198 struct hns_roce_cfg_gmv_tb_a *tb_a = 3199 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3200 struct hns_roce_cfg_gmv_tb_b *tb_b = 3201 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3202 3203 u16 vlan_id = VLAN_CFI_MASK; 3204 u8 mac[ETH_ALEN] = {}; 3205 int ret; 3206 3207 if (gid) { 3208 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3209 if (ret) 3210 return ret; 3211 } 3212 3213 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3214 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3215 3216 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3217 3218 copy_gid(&tb_a->vf_sgid_l, gid); 3219 3220 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3221 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3222 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3223 3224 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3225 3226 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3227 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3228 3229 return hns_roce_cmq_send(hr_dev, desc, 2); 3230 } 3231 3232 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3233 const union ib_gid *gid, 3234 const struct ib_gid_attr *attr) 3235 { 3236 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3237 int ret; 3238 3239 if (gid) { 3240 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3241 if (ipv6_addr_v4mapped((void *)gid)) 3242 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3243 else 3244 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3245 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3246 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3247 } 3248 } 3249 3250 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3251 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3252 else 3253 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3254 3255 if (ret) 3256 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3257 ret); 3258 3259 return ret; 3260 } 3261 3262 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3263 const u8 *addr) 3264 { 3265 struct hns_roce_cmq_desc desc; 3266 struct hns_roce_cfg_smac_tb *smac_tb = 3267 (struct hns_roce_cfg_smac_tb *)desc.data; 3268 u16 reg_smac_h; 3269 u32 reg_smac_l; 3270 3271 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3272 3273 reg_smac_l = *(u32 *)(&addr[0]); 3274 reg_smac_h = *(u16 *)(&addr[4]); 3275 3276 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3277 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3278 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3279 3280 return hns_roce_cmq_send(hr_dev, &desc, 1); 3281 } 3282 3283 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3284 struct hns_roce_v2_mpt_entry *mpt_entry, 3285 struct hns_roce_mr *mr) 3286 { 3287 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3288 struct ib_device *ibdev = &hr_dev->ib_dev; 3289 dma_addr_t pbl_ba; 3290 int i, count; 3291 3292 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3293 min_t(int, ARRAY_SIZE(pages), mr->npages), 3294 &pbl_ba); 3295 if (count < 1) { 3296 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3297 count); 3298 return -ENOBUFS; 3299 } 3300 3301 /* Aligned to the hardware address access unit */ 3302 for (i = 0; i < count; i++) 3303 pages[i] >>= 6; 3304 3305 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3306 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3307 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3308 3309 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3310 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3311 3312 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3313 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3314 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3315 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3316 3317 return 0; 3318 } 3319 3320 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3321 void *mb_buf, struct hns_roce_mr *mr) 3322 { 3323 struct hns_roce_v2_mpt_entry *mpt_entry; 3324 3325 mpt_entry = mb_buf; 3326 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3327 3328 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3329 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3330 3331 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3332 mr->access & IB_ACCESS_MW_BIND); 3333 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3334 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3335 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3336 mr->access & IB_ACCESS_REMOTE_READ); 3337 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3338 mr->access & IB_ACCESS_REMOTE_WRITE); 3339 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3340 mr->access & IB_ACCESS_LOCAL_WRITE); 3341 3342 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3343 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3344 mpt_entry->lkey = cpu_to_le32(mr->key); 3345 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3346 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3347 3348 if (mr->type != MR_TYPE_MR) 3349 hr_reg_enable(mpt_entry, MPT_PA); 3350 3351 if (mr->type == MR_TYPE_DMA) 3352 return 0; 3353 3354 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3355 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3356 3357 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3358 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3359 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3360 3361 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3362 } 3363 3364 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3365 struct hns_roce_mr *mr, int flags, 3366 void *mb_buf) 3367 { 3368 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3369 u32 mr_access_flags = mr->access; 3370 int ret = 0; 3371 3372 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3373 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3374 3375 if (flags & IB_MR_REREG_ACCESS) { 3376 hr_reg_write(mpt_entry, MPT_BIND_EN, 3377 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3378 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3379 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3380 hr_reg_write(mpt_entry, MPT_RR_EN, 3381 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3382 hr_reg_write(mpt_entry, MPT_RW_EN, 3383 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3384 hr_reg_write(mpt_entry, MPT_LW_EN, 3385 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3386 } 3387 3388 if (flags & IB_MR_REREG_TRANS) { 3389 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3390 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3391 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3392 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3393 3394 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3395 } 3396 3397 return ret; 3398 } 3399 3400 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3401 void *mb_buf, struct hns_roce_mr *mr) 3402 { 3403 struct ib_device *ibdev = &hr_dev->ib_dev; 3404 struct hns_roce_v2_mpt_entry *mpt_entry; 3405 dma_addr_t pbl_ba = 0; 3406 3407 mpt_entry = mb_buf; 3408 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3409 3410 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3411 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3412 return -ENOBUFS; 3413 } 3414 3415 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3416 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3417 3418 hr_reg_enable(mpt_entry, MPT_RA_EN); 3419 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3420 3421 hr_reg_enable(mpt_entry, MPT_FRE); 3422 hr_reg_clear(mpt_entry, MPT_MR_MW); 3423 hr_reg_enable(mpt_entry, MPT_BPD); 3424 hr_reg_clear(mpt_entry, MPT_PA); 3425 3426 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3427 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3428 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3429 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3430 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3431 3432 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3433 3434 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3435 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3436 3437 return 0; 3438 } 3439 3440 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3441 { 3442 struct hns_roce_v2_mpt_entry *mpt_entry; 3443 3444 mpt_entry = mb_buf; 3445 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3446 3447 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3448 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3449 3450 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3451 hr_reg_enable(mpt_entry, MPT_LW_EN); 3452 3453 hr_reg_enable(mpt_entry, MPT_MR_MW); 3454 hr_reg_enable(mpt_entry, MPT_BPD); 3455 hr_reg_clear(mpt_entry, MPT_PA); 3456 hr_reg_write(mpt_entry, MPT_BQP, 3457 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3458 3459 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3460 3461 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3462 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3463 mw->pbl_hop_num); 3464 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3465 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3466 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3467 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3468 3469 return 0; 3470 } 3471 3472 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3473 { 3474 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3475 struct ib_device *ibdev = &hr_dev->ib_dev; 3476 const struct ib_send_wr *bad_wr; 3477 struct ib_rdma_wr rdma_wr = {}; 3478 struct ib_send_wr *send_wr; 3479 int ret; 3480 3481 send_wr = &rdma_wr.wr; 3482 send_wr->opcode = IB_WR_RDMA_WRITE; 3483 3484 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3485 if (ret) { 3486 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3487 ret); 3488 return ret; 3489 } 3490 3491 return 0; 3492 } 3493 3494 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3495 struct ib_wc *wc); 3496 3497 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3498 { 3499 struct hns_roce_v2_priv *priv = hr_dev->priv; 3500 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3501 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3502 struct ib_device *ibdev = &hr_dev->ib_dev; 3503 struct hns_roce_qp *hr_qp; 3504 unsigned long end; 3505 int cqe_cnt = 0; 3506 int npolled; 3507 int ret; 3508 int i; 3509 3510 /* 3511 * If the device initialization is not complete or in the uninstall 3512 * process, then there is no need to execute free mr. 3513 */ 3514 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3515 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3516 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3517 return; 3518 3519 mutex_lock(&free_mr->mutex); 3520 3521 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3522 hr_qp = free_mr->rsv_qp[i]; 3523 3524 ret = free_mr_post_send_lp_wqe(hr_qp); 3525 if (ret) { 3526 ibdev_err(ibdev, 3527 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3528 hr_qp->qpn, ret); 3529 break; 3530 } 3531 3532 cqe_cnt++; 3533 } 3534 3535 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3536 while (cqe_cnt) { 3537 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3538 if (npolled < 0) { 3539 ibdev_err(ibdev, 3540 "failed to poll cqe for free mr, remain %d cqe.\n", 3541 cqe_cnt); 3542 goto out; 3543 } 3544 3545 if (time_after(jiffies, end)) { 3546 ibdev_err(ibdev, 3547 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3548 cqe_cnt); 3549 goto out; 3550 } 3551 cqe_cnt -= npolled; 3552 } 3553 3554 out: 3555 mutex_unlock(&free_mr->mutex); 3556 } 3557 3558 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3559 { 3560 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3561 free_mr_send_cmd_to_hw(hr_dev); 3562 } 3563 3564 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3565 { 3566 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3567 } 3568 3569 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3570 { 3571 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3572 3573 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3574 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3575 NULL; 3576 } 3577 3578 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3579 struct hns_roce_cq *hr_cq) 3580 { 3581 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3582 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3583 } else { 3584 struct hns_roce_v2_db cq_db = {}; 3585 3586 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3587 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3588 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3589 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3590 3591 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3592 } 3593 } 3594 3595 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3596 struct hns_roce_srq *srq) 3597 { 3598 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3599 struct hns_roce_v2_cqe *cqe, *dest; 3600 u32 prod_index; 3601 int nfreed = 0; 3602 int wqe_index; 3603 u8 owner_bit; 3604 3605 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3606 ++prod_index) { 3607 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3608 break; 3609 } 3610 3611 /* 3612 * Now backwards through the CQ, removing CQ entries 3613 * that match our QP by overwriting them with next entries. 3614 */ 3615 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3616 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3617 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3618 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3619 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3620 hns_roce_free_srq_wqe(srq, wqe_index); 3621 } 3622 ++nfreed; 3623 } else if (nfreed) { 3624 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3625 hr_cq->ib_cq.cqe); 3626 owner_bit = hr_reg_read(dest, CQE_OWNER); 3627 memcpy(dest, cqe, hr_cq->cqe_size); 3628 hr_reg_write(dest, CQE_OWNER, owner_bit); 3629 } 3630 } 3631 3632 if (nfreed) { 3633 hr_cq->cons_index += nfreed; 3634 update_cq_db(hr_dev, hr_cq); 3635 } 3636 } 3637 3638 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3639 struct hns_roce_srq *srq) 3640 { 3641 spin_lock_irq(&hr_cq->lock); 3642 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3643 spin_unlock_irq(&hr_cq->lock); 3644 } 3645 3646 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3647 struct hns_roce_cq *hr_cq, void *mb_buf, 3648 u64 *mtts, dma_addr_t dma_handle) 3649 { 3650 struct hns_roce_v2_cq_context *cq_context; 3651 3652 cq_context = mb_buf; 3653 memset(cq_context, 0, sizeof(*cq_context)); 3654 3655 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3656 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3657 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3658 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3659 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3660 3661 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3662 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3663 3664 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3665 hr_reg_enable(cq_context, CQC_STASH); 3666 3667 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3668 to_hr_hw_page_addr(mtts[0])); 3669 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3670 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3671 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3672 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3673 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3674 to_hr_hw_page_addr(mtts[1])); 3675 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3676 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3677 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3678 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3679 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3680 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3681 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3682 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3683 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3684 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3685 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3686 ((u32)hr_cq->db.dma) >> 1); 3687 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3688 hr_cq->db.dma >> 32); 3689 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3690 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3691 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3692 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3693 } 3694 3695 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3696 enum ib_cq_notify_flags flags) 3697 { 3698 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3699 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3700 struct hns_roce_v2_db cq_db = {}; 3701 u32 notify_flag; 3702 3703 /* 3704 * flags = 0, then notify_flag : next 3705 * flags = 1, then notify flag : solocited 3706 */ 3707 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3708 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3709 3710 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3711 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3712 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3713 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3714 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3715 3716 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3717 3718 return 0; 3719 } 3720 3721 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3722 int num_entries, struct ib_wc *wc) 3723 { 3724 unsigned int left; 3725 int npolled = 0; 3726 3727 left = wq->head - wq->tail; 3728 if (left == 0) 3729 return 0; 3730 3731 left = min_t(unsigned int, (unsigned int)num_entries, left); 3732 while (npolled < left) { 3733 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3734 wc->status = IB_WC_WR_FLUSH_ERR; 3735 wc->vendor_err = 0; 3736 wc->qp = &hr_qp->ibqp; 3737 3738 wq->tail++; 3739 wc++; 3740 npolled++; 3741 } 3742 3743 return npolled; 3744 } 3745 3746 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3747 struct ib_wc *wc) 3748 { 3749 struct hns_roce_qp *hr_qp; 3750 int npolled = 0; 3751 3752 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3753 npolled += sw_comp(hr_qp, &hr_qp->sq, 3754 num_entries - npolled, wc + npolled); 3755 if (npolled >= num_entries) 3756 goto out; 3757 } 3758 3759 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3760 npolled += sw_comp(hr_qp, &hr_qp->rq, 3761 num_entries - npolled, wc + npolled); 3762 if (npolled >= num_entries) 3763 goto out; 3764 } 3765 3766 out: 3767 return npolled; 3768 } 3769 3770 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3771 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3772 struct ib_wc *wc) 3773 { 3774 static const struct { 3775 u32 cqe_status; 3776 enum ib_wc_status wc_status; 3777 } map[] = { 3778 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3779 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3780 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3781 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3782 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3783 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3784 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3785 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3786 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3787 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3788 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3789 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3790 IB_WC_RETRY_EXC_ERR }, 3791 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3792 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3793 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3794 }; 3795 3796 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3797 int i; 3798 3799 wc->status = IB_WC_GENERAL_ERR; 3800 for (i = 0; i < ARRAY_SIZE(map); i++) 3801 if (cqe_status == map[i].cqe_status) { 3802 wc->status = map[i].wc_status; 3803 break; 3804 } 3805 3806 if (likely(wc->status == IB_WC_SUCCESS || 3807 wc->status == IB_WC_WR_FLUSH_ERR)) 3808 return; 3809 3810 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3811 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3812 cq->cqe_size, false); 3813 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3814 3815 /* 3816 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3817 * the standard protocol, the driver must ignore it and needn't to set 3818 * the QP to an error state. 3819 */ 3820 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3821 return; 3822 3823 flush_cqe(hr_dev, qp); 3824 } 3825 3826 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3827 struct hns_roce_qp **cur_qp) 3828 { 3829 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3830 struct hns_roce_qp *hr_qp = *cur_qp; 3831 u32 qpn; 3832 3833 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3834 3835 if (!hr_qp || qpn != hr_qp->qpn) { 3836 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3837 if (unlikely(!hr_qp)) { 3838 ibdev_err(&hr_dev->ib_dev, 3839 "CQ %06lx with entry for unknown QPN %06x\n", 3840 hr_cq->cqn, qpn); 3841 return -EINVAL; 3842 } 3843 *cur_qp = hr_qp; 3844 } 3845 3846 return 0; 3847 } 3848 3849 /* 3850 * mapped-value = 1 + real-value 3851 * The ib wc opcode's real value is start from 0, In order to distinguish 3852 * between initialized and uninitialized map values, we plus 1 to the actual 3853 * value when defining the mapping, so that the validity can be identified by 3854 * checking whether the mapped value is greater than 0. 3855 */ 3856 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3857 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3858 3859 static const u32 wc_send_op_map[] = { 3860 HR_WC_OP_MAP(SEND, SEND), 3861 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3862 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3863 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3864 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3865 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3866 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3867 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3868 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3869 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3870 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3871 HR_WC_OP_MAP(BIND_MW, REG_MR), 3872 }; 3873 3874 static int to_ib_wc_send_op(u32 hr_opcode) 3875 { 3876 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3877 return -EINVAL; 3878 3879 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3880 -EINVAL; 3881 } 3882 3883 static const u32 wc_recv_op_map[] = { 3884 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3885 HR_WC_OP_MAP(SEND, RECV), 3886 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3887 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3888 }; 3889 3890 static int to_ib_wc_recv_op(u32 hr_opcode) 3891 { 3892 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3893 return -EINVAL; 3894 3895 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3896 -EINVAL; 3897 } 3898 3899 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3900 { 3901 u32 hr_opcode; 3902 int ib_opcode; 3903 3904 wc->wc_flags = 0; 3905 3906 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3907 switch (hr_opcode) { 3908 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3909 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3910 break; 3911 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3912 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3913 wc->wc_flags |= IB_WC_WITH_IMM; 3914 break; 3915 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3916 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3917 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3918 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3919 wc->byte_len = 8; 3920 break; 3921 default: 3922 break; 3923 } 3924 3925 ib_opcode = to_ib_wc_send_op(hr_opcode); 3926 if (ib_opcode < 0) 3927 wc->status = IB_WC_GENERAL_ERR; 3928 else 3929 wc->opcode = ib_opcode; 3930 } 3931 3932 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3933 { 3934 u32 hr_opcode; 3935 int ib_opcode; 3936 3937 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3938 3939 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3940 switch (hr_opcode) { 3941 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3942 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3943 wc->wc_flags = IB_WC_WITH_IMM; 3944 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3945 break; 3946 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3947 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3948 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3949 break; 3950 default: 3951 wc->wc_flags = 0; 3952 } 3953 3954 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3955 if (ib_opcode < 0) 3956 wc->status = IB_WC_GENERAL_ERR; 3957 else 3958 wc->opcode = ib_opcode; 3959 3960 wc->sl = hr_reg_read(cqe, CQE_SL); 3961 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3962 wc->slid = 0; 3963 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3964 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3965 wc->pkey_index = 0; 3966 3967 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3968 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3969 wc->wc_flags |= IB_WC_WITH_VLAN; 3970 } else { 3971 wc->vlan_id = 0xffff; 3972 } 3973 3974 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3975 3976 return 0; 3977 } 3978 3979 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3980 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3981 { 3982 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3983 struct hns_roce_qp *qp = *cur_qp; 3984 struct hns_roce_srq *srq = NULL; 3985 struct hns_roce_v2_cqe *cqe; 3986 struct hns_roce_wq *wq; 3987 int is_send; 3988 u16 wqe_idx; 3989 int ret; 3990 3991 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3992 if (!cqe) 3993 return -EAGAIN; 3994 3995 ++hr_cq->cons_index; 3996 /* Memory barrier */ 3997 rmb(); 3998 3999 ret = get_cur_qp(hr_cq, cqe, &qp); 4000 if (ret) 4001 return ret; 4002 4003 wc->qp = &qp->ibqp; 4004 wc->vendor_err = 0; 4005 4006 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 4007 4008 is_send = !hr_reg_read(cqe, CQE_S_R); 4009 if (is_send) { 4010 wq = &qp->sq; 4011 4012 /* If sg_signal_bit is set, tail pointer will be updated to 4013 * the WQE corresponding to the current CQE. 4014 */ 4015 if (qp->sq_signal_bits) 4016 wq->tail += (wqe_idx - (u16)wq->tail) & 4017 (wq->wqe_cnt - 1); 4018 4019 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4020 ++wq->tail; 4021 4022 fill_send_wc(wc, cqe); 4023 } else { 4024 if (qp->ibqp.srq) { 4025 srq = to_hr_srq(qp->ibqp.srq); 4026 wc->wr_id = srq->wrid[wqe_idx]; 4027 hns_roce_free_srq_wqe(srq, wqe_idx); 4028 } else { 4029 wq = &qp->rq; 4030 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4031 ++wq->tail; 4032 } 4033 4034 ret = fill_recv_wc(wc, cqe); 4035 } 4036 4037 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4038 if (unlikely(wc->status != IB_WC_SUCCESS)) 4039 return 0; 4040 4041 return ret; 4042 } 4043 4044 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4045 struct ib_wc *wc) 4046 { 4047 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4048 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4049 struct hns_roce_qp *cur_qp = NULL; 4050 unsigned long flags; 4051 int npolled; 4052 4053 spin_lock_irqsave(&hr_cq->lock, flags); 4054 4055 /* 4056 * When the device starts to reset, the state is RST_DOWN. At this time, 4057 * there may still be some valid CQEs in the hardware that are not 4058 * polled. Therefore, it is not allowed to switch to the software mode 4059 * immediately. When the state changes to UNINIT, CQE no longer exists 4060 * in the hardware, and then switch to software mode. 4061 */ 4062 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4063 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4064 goto out; 4065 } 4066 4067 for (npolled = 0; npolled < num_entries; ++npolled) { 4068 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4069 break; 4070 } 4071 4072 if (npolled) 4073 update_cq_db(hr_dev, hr_cq); 4074 4075 out: 4076 spin_unlock_irqrestore(&hr_cq->lock, flags); 4077 4078 return npolled; 4079 } 4080 4081 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4082 u32 step_idx, u8 *mbox_cmd) 4083 { 4084 u8 cmd; 4085 4086 switch (type) { 4087 case HEM_TYPE_QPC: 4088 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4089 break; 4090 case HEM_TYPE_MTPT: 4091 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4092 break; 4093 case HEM_TYPE_CQC: 4094 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4095 break; 4096 case HEM_TYPE_SRQC: 4097 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4098 break; 4099 case HEM_TYPE_SCCC: 4100 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4101 break; 4102 case HEM_TYPE_QPC_TIMER: 4103 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4104 break; 4105 case HEM_TYPE_CQC_TIMER: 4106 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4107 break; 4108 default: 4109 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4110 return -EINVAL; 4111 } 4112 4113 *mbox_cmd = cmd + step_idx; 4114 4115 return 0; 4116 } 4117 4118 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4119 dma_addr_t base_addr) 4120 { 4121 struct hns_roce_cmq_desc desc; 4122 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4123 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4124 u64 addr = to_hr_hw_page_addr(base_addr); 4125 4126 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4127 4128 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4129 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4130 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4131 4132 return hns_roce_cmq_send(hr_dev, &desc, 1); 4133 } 4134 4135 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4136 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4137 { 4138 int ret; 4139 u8 cmd; 4140 4141 if (unlikely(hem_type == HEM_TYPE_GMV)) 4142 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4143 4144 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4145 return 0; 4146 4147 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4148 if (ret < 0) 4149 return ret; 4150 4151 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4152 } 4153 4154 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4155 struct hns_roce_hem_table *table, int obj, 4156 u32 step_idx) 4157 { 4158 struct hns_roce_hem_iter iter; 4159 struct hns_roce_hem_mhop mhop; 4160 struct hns_roce_hem *hem; 4161 unsigned long mhop_obj = obj; 4162 int i, j, k; 4163 int ret = 0; 4164 u64 hem_idx = 0; 4165 u64 l1_idx = 0; 4166 u64 bt_ba = 0; 4167 u32 chunk_ba_num; 4168 u32 hop_num; 4169 4170 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4171 return 0; 4172 4173 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4174 i = mhop.l0_idx; 4175 j = mhop.l1_idx; 4176 k = mhop.l2_idx; 4177 hop_num = mhop.hop_num; 4178 chunk_ba_num = mhop.bt_chunk_size / 8; 4179 4180 if (hop_num == 2) { 4181 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4182 k; 4183 l1_idx = i * chunk_ba_num + j; 4184 } else if (hop_num == 1) { 4185 hem_idx = i * chunk_ba_num + j; 4186 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4187 hem_idx = i; 4188 } 4189 4190 if (table->type == HEM_TYPE_SCCC) 4191 obj = mhop.l0_idx; 4192 4193 if (check_whether_last_step(hop_num, step_idx)) { 4194 hem = table->hem[hem_idx]; 4195 for (hns_roce_hem_first(hem, &iter); 4196 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4197 bt_ba = hns_roce_hem_addr(&iter); 4198 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4199 step_idx); 4200 } 4201 } else { 4202 if (step_idx == 0) 4203 bt_ba = table->bt_l0_dma_addr[i]; 4204 else if (step_idx == 1 && hop_num == 2) 4205 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4206 4207 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4208 } 4209 4210 return ret; 4211 } 4212 4213 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4214 struct hns_roce_hem_table *table, 4215 int tag, u32 step_idx) 4216 { 4217 struct hns_roce_cmd_mailbox *mailbox; 4218 struct device *dev = hr_dev->dev; 4219 u8 cmd = 0xff; 4220 int ret; 4221 4222 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4223 return 0; 4224 4225 switch (table->type) { 4226 case HEM_TYPE_QPC: 4227 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4228 break; 4229 case HEM_TYPE_MTPT: 4230 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4231 break; 4232 case HEM_TYPE_CQC: 4233 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4234 break; 4235 case HEM_TYPE_SRQC: 4236 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4237 break; 4238 case HEM_TYPE_SCCC: 4239 case HEM_TYPE_QPC_TIMER: 4240 case HEM_TYPE_CQC_TIMER: 4241 case HEM_TYPE_GMV: 4242 return 0; 4243 default: 4244 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4245 table->type); 4246 return 0; 4247 } 4248 4249 cmd += step_idx; 4250 4251 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4252 if (IS_ERR(mailbox)) 4253 return PTR_ERR(mailbox); 4254 4255 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4256 4257 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4258 return ret; 4259 } 4260 4261 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4262 struct hns_roce_v2_qp_context *context, 4263 struct hns_roce_v2_qp_context *qpc_mask, 4264 struct hns_roce_qp *hr_qp) 4265 { 4266 struct hns_roce_cmd_mailbox *mailbox; 4267 int qpc_size; 4268 int ret; 4269 4270 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4271 if (IS_ERR(mailbox)) 4272 return PTR_ERR(mailbox); 4273 4274 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4275 qpc_size = hr_dev->caps.qpc_sz; 4276 memcpy(mailbox->buf, context, qpc_size); 4277 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4278 4279 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4280 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4281 4282 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4283 4284 return ret; 4285 } 4286 4287 static void set_access_flags(struct hns_roce_qp *hr_qp, 4288 struct hns_roce_v2_qp_context *context, 4289 struct hns_roce_v2_qp_context *qpc_mask, 4290 const struct ib_qp_attr *attr, int attr_mask) 4291 { 4292 u8 dest_rd_atomic; 4293 u32 access_flags; 4294 4295 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4296 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4297 4298 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4299 attr->qp_access_flags : hr_qp->atomic_rd_en; 4300 4301 if (!dest_rd_atomic) 4302 access_flags &= IB_ACCESS_REMOTE_WRITE; 4303 4304 hr_reg_write_bool(context, QPC_RRE, 4305 access_flags & IB_ACCESS_REMOTE_READ); 4306 hr_reg_clear(qpc_mask, QPC_RRE); 4307 4308 hr_reg_write_bool(context, QPC_RWE, 4309 access_flags & IB_ACCESS_REMOTE_WRITE); 4310 hr_reg_clear(qpc_mask, QPC_RWE); 4311 4312 hr_reg_write_bool(context, QPC_ATE, 4313 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4314 hr_reg_clear(qpc_mask, QPC_ATE); 4315 hr_reg_write_bool(context, QPC_EXT_ATE, 4316 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4317 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4318 } 4319 4320 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4321 struct hns_roce_v2_qp_context *context, 4322 struct hns_roce_v2_qp_context *qpc_mask) 4323 { 4324 hr_reg_write(context, QPC_SGE_SHIFT, 4325 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4326 hr_qp->sge.sge_shift)); 4327 4328 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4329 4330 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4331 } 4332 4333 static inline int get_cqn(struct ib_cq *ib_cq) 4334 { 4335 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4336 } 4337 4338 static inline int get_pdn(struct ib_pd *ib_pd) 4339 { 4340 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4341 } 4342 4343 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4344 const struct ib_qp_attr *attr, 4345 struct hns_roce_v2_qp_context *context, 4346 struct hns_roce_v2_qp_context *qpc_mask) 4347 { 4348 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4349 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4350 4351 /* 4352 * In v2 engine, software pass context and context mask to hardware 4353 * when modifying qp. If software need modify some fields in context, 4354 * we should set all bits of the relevant fields in context mask to 4355 * 0 at the same time, else set them to 0x1. 4356 */ 4357 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4358 4359 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4360 4361 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4362 4363 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4364 4365 /* No VLAN need to set 0xFFF */ 4366 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4367 4368 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4369 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4370 4371 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4372 } 4373 4374 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4375 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4376 4377 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4378 hr_reg_enable(context, QPC_OWNER_MODE); 4379 4380 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4381 lower_32_bits(hr_qp->rdb.dma) >> 1); 4382 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4383 upper_32_bits(hr_qp->rdb.dma)); 4384 4385 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4386 4387 if (ibqp->srq) { 4388 hr_reg_enable(context, QPC_SRQ_EN); 4389 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4390 } 4391 4392 hr_reg_enable(context, QPC_FRE); 4393 4394 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4395 4396 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4397 return; 4398 4399 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4400 hr_reg_enable(&context->ext, QPCEX_STASH); 4401 } 4402 4403 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4404 const struct ib_qp_attr *attr, 4405 struct hns_roce_v2_qp_context *context, 4406 struct hns_roce_v2_qp_context *qpc_mask) 4407 { 4408 /* 4409 * In v2 engine, software pass context and context mask to hardware 4410 * when modifying qp. If software need modify some fields in context, 4411 * we should set all bits of the relevant fields in context mask to 4412 * 0 at the same time, else set them to 0x1. 4413 */ 4414 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4415 hr_reg_clear(qpc_mask, QPC_TST); 4416 4417 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4418 hr_reg_clear(qpc_mask, QPC_PD); 4419 4420 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4421 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4422 4423 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4424 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4425 4426 if (ibqp->srq) { 4427 hr_reg_enable(context, QPC_SRQ_EN); 4428 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4429 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4430 hr_reg_clear(qpc_mask, QPC_SRQN); 4431 } 4432 } 4433 4434 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4435 struct hns_roce_qp *hr_qp, 4436 struct hns_roce_v2_qp_context *context, 4437 struct hns_roce_v2_qp_context *qpc_mask) 4438 { 4439 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4440 u64 wqe_sge_ba; 4441 int count; 4442 4443 /* Search qp buf's mtts */ 4444 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4445 MTT_MIN_COUNT, &wqe_sge_ba); 4446 if (hr_qp->rq.wqe_cnt && count < 1) { 4447 ibdev_err(&hr_dev->ib_dev, 4448 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4449 return -EINVAL; 4450 } 4451 4452 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4453 qpc_mask->wqe_sge_ba = 0; 4454 4455 /* 4456 * In v2 engine, software pass context and context mask to hardware 4457 * when modifying qp. If software need modify some fields in context, 4458 * we should set all bits of the relevant fields in context mask to 4459 * 0 at the same time, else set them to 0x1. 4460 */ 4461 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4462 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4463 4464 hr_reg_write(context, QPC_SQ_HOP_NUM, 4465 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4466 hr_qp->sq.wqe_cnt)); 4467 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4468 4469 hr_reg_write(context, QPC_SGE_HOP_NUM, 4470 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4471 hr_qp->sge.sge_cnt)); 4472 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4473 4474 hr_reg_write(context, QPC_RQ_HOP_NUM, 4475 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4476 hr_qp->rq.wqe_cnt)); 4477 4478 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4479 4480 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4481 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4482 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4483 4484 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4485 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4486 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4487 4488 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4489 qpc_mask->rq_cur_blk_addr = 0; 4490 4491 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4492 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4493 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4494 4495 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4496 qpc_mask->rq_nxt_blk_addr = 0; 4497 4498 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4499 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4500 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4501 4502 return 0; 4503 } 4504 4505 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4506 struct hns_roce_qp *hr_qp, 4507 struct hns_roce_v2_qp_context *context, 4508 struct hns_roce_v2_qp_context *qpc_mask) 4509 { 4510 struct ib_device *ibdev = &hr_dev->ib_dev; 4511 u64 sge_cur_blk = 0; 4512 u64 sq_cur_blk = 0; 4513 int count; 4514 4515 /* search qp buf's mtts */ 4516 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4517 if (count < 1) { 4518 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4519 hr_qp->qpn); 4520 return -EINVAL; 4521 } 4522 if (hr_qp->sge.sge_cnt > 0) { 4523 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4524 hr_qp->sge.offset, 4525 &sge_cur_blk, 1, NULL); 4526 if (count < 1) { 4527 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4528 hr_qp->qpn); 4529 return -EINVAL; 4530 } 4531 } 4532 4533 /* 4534 * In v2 engine, software pass context and context mask to hardware 4535 * when modifying qp. If software need modify some fields in context, 4536 * we should set all bits of the relevant fields in context mask to 4537 * 0 at the same time, else set them to 0x1. 4538 */ 4539 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4540 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4541 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4542 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4543 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4544 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4545 4546 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4547 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4548 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4549 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4550 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4551 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4552 4553 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4554 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4555 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4556 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4557 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4558 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4559 4560 return 0; 4561 } 4562 4563 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4564 const struct ib_qp_attr *attr) 4565 { 4566 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4567 return IB_MTU_4096; 4568 4569 return attr->path_mtu; 4570 } 4571 4572 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4573 const struct ib_qp_attr *attr, int attr_mask, 4574 struct hns_roce_v2_qp_context *context, 4575 struct hns_roce_v2_qp_context *qpc_mask, 4576 struct ib_udata *udata) 4577 { 4578 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4579 struct hns_roce_ucontext, ibucontext); 4580 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4581 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4582 struct ib_device *ibdev = &hr_dev->ib_dev; 4583 dma_addr_t trrl_ba; 4584 dma_addr_t irrl_ba; 4585 enum ib_mtu ib_mtu; 4586 const u8 *smac; 4587 u8 lp_pktn_ini; 4588 u64 *mtts; 4589 u8 *dmac; 4590 u32 port; 4591 int mtu; 4592 int ret; 4593 4594 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4595 if (ret) { 4596 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4597 return ret; 4598 } 4599 4600 /* Search IRRL's mtts */ 4601 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4602 hr_qp->qpn, &irrl_ba); 4603 if (!mtts) { 4604 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4605 return -EINVAL; 4606 } 4607 4608 /* Search TRRL's mtts */ 4609 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4610 hr_qp->qpn, &trrl_ba); 4611 if (!mtts) { 4612 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4613 return -EINVAL; 4614 } 4615 4616 if (attr_mask & IB_QP_ALT_PATH) { 4617 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4618 attr_mask); 4619 return -EINVAL; 4620 } 4621 4622 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4623 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4624 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4625 qpc_mask->trrl_ba = 0; 4626 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4627 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4628 4629 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4630 qpc_mask->irrl_ba = 0; 4631 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4632 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4633 4634 hr_reg_enable(context, QPC_RMT_E2E); 4635 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4636 4637 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4638 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4639 4640 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4641 4642 smac = (const u8 *)hr_dev->dev_addr[port]; 4643 dmac = (u8 *)attr->ah_attr.roce.dmac; 4644 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4645 if (ether_addr_equal_unaligned(dmac, smac) || 4646 hr_dev->loop_idc == 0x1) { 4647 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4648 hr_reg_clear(qpc_mask, QPC_LBI); 4649 } 4650 4651 if (attr_mask & IB_QP_DEST_QPN) { 4652 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4653 hr_reg_clear(qpc_mask, QPC_DQPN); 4654 } 4655 4656 memcpy(&context->dmac, dmac, sizeof(u32)); 4657 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4658 qpc_mask->dmac = 0; 4659 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4660 4661 ib_mtu = get_mtu(ibqp, attr); 4662 hr_qp->path_mtu = ib_mtu; 4663 4664 mtu = ib_mtu_enum_to_int(ib_mtu); 4665 if (WARN_ON(mtu <= 0)) 4666 return -EINVAL; 4667 #define MAX_LP_MSG_LEN 16384 4668 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */ 4669 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4670 if (WARN_ON(lp_pktn_ini >= 0xF)) 4671 return -EINVAL; 4672 4673 if (attr_mask & IB_QP_PATH_MTU) { 4674 hr_reg_write(context, QPC_MTU, ib_mtu); 4675 hr_reg_clear(qpc_mask, QPC_MTU); 4676 } 4677 4678 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4679 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4680 4681 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4682 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4683 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4684 4685 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4686 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4687 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4688 4689 context->rq_rnr_timer = 0; 4690 qpc_mask->rq_rnr_timer = 0; 4691 4692 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4693 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4694 4695 /* rocee send 2^lp_sgen_ini segs every time */ 4696 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4697 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4698 4699 if (udata && ibqp->qp_type == IB_QPT_RC && 4700 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4701 hr_reg_write_bool(context, QPC_RQIE, 4702 hr_dev->caps.flags & 4703 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4704 hr_reg_clear(qpc_mask, QPC_RQIE); 4705 } 4706 4707 if (udata && 4708 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4709 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4710 hr_reg_write_bool(context, QPC_CQEIE, 4711 hr_dev->caps.flags & 4712 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4713 hr_reg_clear(qpc_mask, QPC_CQEIE); 4714 4715 hr_reg_write(context, QPC_CQEIS, 0); 4716 hr_reg_clear(qpc_mask, QPC_CQEIS); 4717 } 4718 4719 return 0; 4720 } 4721 4722 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4723 const struct ib_qp_attr *attr, int attr_mask, 4724 struct hns_roce_v2_qp_context *context, 4725 struct hns_roce_v2_qp_context *qpc_mask) 4726 { 4727 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4728 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4729 struct ib_device *ibdev = &hr_dev->ib_dev; 4730 int ret; 4731 4732 /* Not support alternate path and path migration */ 4733 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4734 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4735 return -EINVAL; 4736 } 4737 4738 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4739 if (ret) { 4740 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4741 return ret; 4742 } 4743 4744 /* 4745 * Set some fields in context to zero, Because the default values 4746 * of all fields in context are zero, we need not set them to 0 again. 4747 * but we should set the relevant fields of context mask to 0. 4748 */ 4749 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4750 4751 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4752 4753 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4754 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4755 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4756 4757 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4758 4759 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4760 4761 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4762 4763 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4764 4765 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4766 4767 return 0; 4768 } 4769 4770 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4771 u32 *dip_idx) 4772 { 4773 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4774 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4775 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4776 u32 *head = &hr_dev->qp_table.idx_table.head; 4777 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4778 struct hns_roce_dip *hr_dip; 4779 unsigned long flags; 4780 int ret = 0; 4781 4782 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4783 4784 spare_idx[*tail] = ibqp->qp_num; 4785 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4786 4787 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4788 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4789 *dip_idx = hr_dip->dip_idx; 4790 goto out; 4791 } 4792 } 4793 4794 /* If no dgid is found, a new dip and a mapping between dgid and 4795 * dip_idx will be created. 4796 */ 4797 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4798 if (!hr_dip) { 4799 ret = -ENOMEM; 4800 goto out; 4801 } 4802 4803 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4804 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4805 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4806 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4807 4808 out: 4809 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4810 return ret; 4811 } 4812 4813 enum { 4814 CONG_DCQCN, 4815 CONG_WINDOW, 4816 }; 4817 4818 enum { 4819 UNSUPPORT_CONG_LEVEL, 4820 SUPPORT_CONG_LEVEL, 4821 }; 4822 4823 enum { 4824 CONG_LDCP, 4825 CONG_HC3, 4826 }; 4827 4828 enum { 4829 DIP_INVALID, 4830 DIP_VALID, 4831 }; 4832 4833 enum { 4834 WND_LIMIT, 4835 WND_UNLIMIT, 4836 }; 4837 4838 static int check_cong_type(struct ib_qp *ibqp, 4839 struct hns_roce_congestion_algorithm *cong_alg) 4840 { 4841 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4842 4843 /* different congestion types match different configurations */ 4844 switch (hr_dev->caps.cong_type) { 4845 case CONG_TYPE_DCQCN: 4846 cong_alg->alg_sel = CONG_DCQCN; 4847 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4848 cong_alg->dip_vld = DIP_INVALID; 4849 cong_alg->wnd_mode_sel = WND_LIMIT; 4850 break; 4851 case CONG_TYPE_LDCP: 4852 cong_alg->alg_sel = CONG_WINDOW; 4853 cong_alg->alg_sub_sel = CONG_LDCP; 4854 cong_alg->dip_vld = DIP_INVALID; 4855 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4856 break; 4857 case CONG_TYPE_HC3: 4858 cong_alg->alg_sel = CONG_WINDOW; 4859 cong_alg->alg_sub_sel = CONG_HC3; 4860 cong_alg->dip_vld = DIP_INVALID; 4861 cong_alg->wnd_mode_sel = WND_LIMIT; 4862 break; 4863 case CONG_TYPE_DIP: 4864 cong_alg->alg_sel = CONG_DCQCN; 4865 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4866 cong_alg->dip_vld = DIP_VALID; 4867 cong_alg->wnd_mode_sel = WND_LIMIT; 4868 break; 4869 default: 4870 ibdev_err(&hr_dev->ib_dev, 4871 "error type(%u) for congestion selection.\n", 4872 hr_dev->caps.cong_type); 4873 return -EINVAL; 4874 } 4875 4876 return 0; 4877 } 4878 4879 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4880 struct hns_roce_v2_qp_context *context, 4881 struct hns_roce_v2_qp_context *qpc_mask) 4882 { 4883 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4884 struct hns_roce_congestion_algorithm cong_field; 4885 struct ib_device *ibdev = ibqp->device; 4886 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4887 u32 dip_idx = 0; 4888 int ret; 4889 4890 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4891 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4892 return 0; 4893 4894 ret = check_cong_type(ibqp, &cong_field); 4895 if (ret) 4896 return ret; 4897 4898 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4899 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4900 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4901 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4902 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4903 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4904 cong_field.alg_sub_sel); 4905 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4906 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4907 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4908 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4909 cong_field.wnd_mode_sel); 4910 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4911 4912 /* if dip is disabled, there is no need to set dip idx */ 4913 if (cong_field.dip_vld == 0) 4914 return 0; 4915 4916 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4917 if (ret) { 4918 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4919 return ret; 4920 } 4921 4922 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4923 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4924 4925 return 0; 4926 } 4927 4928 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4929 const struct ib_qp_attr *attr, 4930 int attr_mask, 4931 struct hns_roce_v2_qp_context *context, 4932 struct hns_roce_v2_qp_context *qpc_mask) 4933 { 4934 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4935 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4936 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4937 struct ib_device *ibdev = &hr_dev->ib_dev; 4938 const struct ib_gid_attr *gid_attr = NULL; 4939 int is_roce_protocol; 4940 u16 vlan_id = 0xffff; 4941 bool is_udp = false; 4942 u8 ib_port; 4943 u8 hr_port; 4944 int ret; 4945 4946 /* 4947 * If free_mr_en of qp is set, it means that this qp comes from 4948 * free mr. This qp will perform the loopback operation. 4949 * In the loopback scenario, only sl needs to be set. 4950 */ 4951 if (hr_qp->free_mr_en) { 4952 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4953 hr_reg_clear(qpc_mask, QPC_SL); 4954 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4955 return 0; 4956 } 4957 4958 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4959 hr_port = ib_port - 1; 4960 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4961 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4962 4963 if (is_roce_protocol) { 4964 gid_attr = attr->ah_attr.grh.sgid_attr; 4965 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4966 if (ret) 4967 return ret; 4968 4969 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4970 } 4971 4972 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4973 if (vlan_id < VLAN_N_VID && 4974 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4975 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4976 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4977 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4978 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4979 } 4980 4981 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4982 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4983 4984 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4985 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4986 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4987 return -EINVAL; 4988 } 4989 4990 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4991 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4992 return -EINVAL; 4993 } 4994 4995 hr_reg_write(context, QPC_UDPSPN, 4996 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4997 attr->dest_qp_num) : 4998 0); 4999 5000 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5001 5002 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5003 5004 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5005 5006 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5007 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5008 5009 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5010 if (ret) 5011 return ret; 5012 5013 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5014 hr_reg_clear(qpc_mask, QPC_TC); 5015 5016 hr_reg_write(context, QPC_FL, grh->flow_label); 5017 hr_reg_clear(qpc_mask, QPC_FL); 5018 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5019 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5020 5021 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 5022 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 5023 ibdev_err(ibdev, 5024 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 5025 hr_qp->sl, MAX_SERVICE_LEVEL); 5026 return -EINVAL; 5027 } 5028 5029 hr_reg_write(context, QPC_SL, hr_qp->sl); 5030 hr_reg_clear(qpc_mask, QPC_SL); 5031 5032 return 0; 5033 } 5034 5035 static bool check_qp_state(enum ib_qp_state cur_state, 5036 enum ib_qp_state new_state) 5037 { 5038 static const bool sm[][IB_QPS_ERR + 1] = { 5039 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5040 [IB_QPS_INIT] = true }, 5041 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5042 [IB_QPS_INIT] = true, 5043 [IB_QPS_RTR] = true, 5044 [IB_QPS_ERR] = true }, 5045 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5046 [IB_QPS_RTS] = true, 5047 [IB_QPS_ERR] = true }, 5048 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5049 [IB_QPS_RTS] = true, 5050 [IB_QPS_ERR] = true }, 5051 [IB_QPS_SQD] = {}, 5052 [IB_QPS_SQE] = {}, 5053 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5054 [IB_QPS_ERR] = true } 5055 }; 5056 5057 return sm[cur_state][new_state]; 5058 } 5059 5060 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5061 const struct ib_qp_attr *attr, 5062 int attr_mask, 5063 enum ib_qp_state cur_state, 5064 enum ib_qp_state new_state, 5065 struct hns_roce_v2_qp_context *context, 5066 struct hns_roce_v2_qp_context *qpc_mask, 5067 struct ib_udata *udata) 5068 { 5069 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5070 int ret = 0; 5071 5072 if (!check_qp_state(cur_state, new_state)) { 5073 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 5074 return -EINVAL; 5075 } 5076 5077 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5078 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5079 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 5080 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5081 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 5082 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5083 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5084 qpc_mask, udata); 5085 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5086 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 5087 qpc_mask); 5088 } 5089 5090 return ret; 5091 } 5092 5093 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5094 { 5095 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5096 #define QP_ACK_TIMEOUT_OFFSET 10 5097 #define QP_ACK_TIMEOUT_MAX 31 5098 5099 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5100 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5101 ibdev_warn(&hr_dev->ib_dev, 5102 "local ACK timeout shall be 0 to 20.\n"); 5103 return false; 5104 } 5105 *timeout += QP_ACK_TIMEOUT_OFFSET; 5106 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5107 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5108 ibdev_warn(&hr_dev->ib_dev, 5109 "local ACK timeout shall be 0 to 31.\n"); 5110 return false; 5111 } 5112 } 5113 5114 return true; 5115 } 5116 5117 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5118 const struct ib_qp_attr *attr, 5119 int attr_mask, 5120 struct hns_roce_v2_qp_context *context, 5121 struct hns_roce_v2_qp_context *qpc_mask) 5122 { 5123 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5124 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5125 int ret = 0; 5126 u8 timeout; 5127 5128 if (attr_mask & IB_QP_AV) { 5129 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5130 qpc_mask); 5131 if (ret) 5132 return ret; 5133 } 5134 5135 if (attr_mask & IB_QP_TIMEOUT) { 5136 timeout = attr->timeout; 5137 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5138 hr_reg_write(context, QPC_AT, timeout); 5139 hr_reg_clear(qpc_mask, QPC_AT); 5140 } 5141 } 5142 5143 if (attr_mask & IB_QP_RETRY_CNT) { 5144 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5145 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5146 5147 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5148 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5149 } 5150 5151 if (attr_mask & IB_QP_RNR_RETRY) { 5152 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5153 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5154 5155 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5156 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5157 } 5158 5159 if (attr_mask & IB_QP_SQ_PSN) { 5160 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5161 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5162 5163 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5164 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5165 5166 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5167 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5168 5169 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5170 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5171 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5172 5173 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5174 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5175 5176 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5177 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5178 } 5179 5180 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5181 attr->max_dest_rd_atomic) { 5182 hr_reg_write(context, QPC_RR_MAX, 5183 fls(attr->max_dest_rd_atomic - 1)); 5184 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5185 } 5186 5187 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5188 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5189 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5190 } 5191 5192 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5193 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5194 5195 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5196 hr_reg_write(context, QPC_MIN_RNR_TIME, 5197 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5198 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5199 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5200 } 5201 5202 if (attr_mask & IB_QP_RQ_PSN) { 5203 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5204 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5205 5206 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5207 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5208 } 5209 5210 if (attr_mask & IB_QP_QKEY) { 5211 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5212 qpc_mask->qkey_xrcd = 0; 5213 hr_qp->qkey = attr->qkey; 5214 } 5215 5216 return ret; 5217 } 5218 5219 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5220 const struct ib_qp_attr *attr, 5221 int attr_mask) 5222 { 5223 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5224 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5225 5226 if (attr_mask & IB_QP_ACCESS_FLAGS) 5227 hr_qp->atomic_rd_en = attr->qp_access_flags; 5228 5229 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5230 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5231 if (attr_mask & IB_QP_PORT) { 5232 hr_qp->port = attr->port_num - 1; 5233 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5234 } 5235 } 5236 5237 static void clear_qp(struct hns_roce_qp *hr_qp) 5238 { 5239 struct ib_qp *ibqp = &hr_qp->ibqp; 5240 5241 if (ibqp->send_cq) 5242 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5243 hr_qp->qpn, NULL); 5244 5245 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5246 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5247 hr_qp->qpn, ibqp->srq ? 5248 to_hr_srq(ibqp->srq) : NULL); 5249 5250 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5251 *hr_qp->rdb.db_record = 0; 5252 5253 hr_qp->rq.head = 0; 5254 hr_qp->rq.tail = 0; 5255 hr_qp->sq.head = 0; 5256 hr_qp->sq.tail = 0; 5257 hr_qp->next_sge = 0; 5258 } 5259 5260 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5261 struct hns_roce_v2_qp_context *context, 5262 struct hns_roce_v2_qp_context *qpc_mask) 5263 { 5264 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5265 unsigned long sq_flag = 0; 5266 unsigned long rq_flag = 0; 5267 5268 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5269 return; 5270 5271 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5272 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5273 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5274 hr_qp->state = IB_QPS_ERR; 5275 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5276 5277 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5278 return; 5279 5280 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5281 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5282 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5283 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5284 } 5285 5286 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5287 const struct ib_qp_attr *attr, 5288 int attr_mask, enum ib_qp_state cur_state, 5289 enum ib_qp_state new_state, struct ib_udata *udata) 5290 { 5291 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5292 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5293 struct hns_roce_v2_qp_context ctx[2]; 5294 struct hns_roce_v2_qp_context *context = ctx; 5295 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5296 struct ib_device *ibdev = &hr_dev->ib_dev; 5297 int ret; 5298 5299 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5300 return -EOPNOTSUPP; 5301 5302 /* 5303 * In v2 engine, software pass context and context mask to hardware 5304 * when modifying qp. If software need modify some fields in context, 5305 * we should set all bits of the relevant fields in context mask to 5306 * 0 at the same time, else set them to 0x1. 5307 */ 5308 memset(context, 0, hr_dev->caps.qpc_sz); 5309 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5310 5311 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5312 new_state, context, qpc_mask, udata); 5313 if (ret) 5314 goto out; 5315 5316 /* When QP state is err, SQ and RQ WQE should be flushed */ 5317 if (new_state == IB_QPS_ERR) 5318 v2_set_flushed_fields(ibqp, context, qpc_mask); 5319 5320 /* Configure the optional fields */ 5321 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5322 qpc_mask); 5323 if (ret) 5324 goto out; 5325 5326 hr_reg_write_bool(context, QPC_INV_CREDIT, 5327 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5328 ibqp->srq); 5329 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5330 5331 /* Every status migrate must change state */ 5332 hr_reg_write(context, QPC_QP_ST, new_state); 5333 hr_reg_clear(qpc_mask, QPC_QP_ST); 5334 5335 /* SW pass context to HW */ 5336 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5337 if (ret) { 5338 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5339 goto out; 5340 } 5341 5342 hr_qp->state = new_state; 5343 5344 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5345 5346 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5347 clear_qp(hr_qp); 5348 5349 out: 5350 return ret; 5351 } 5352 5353 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5354 { 5355 static const enum ib_qp_state map[] = { 5356 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5357 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5358 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5359 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5360 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5361 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5362 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5363 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5364 }; 5365 5366 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5367 } 5368 5369 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5370 void *buffer) 5371 { 5372 struct hns_roce_cmd_mailbox *mailbox; 5373 int ret; 5374 5375 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5376 if (IS_ERR(mailbox)) 5377 return PTR_ERR(mailbox); 5378 5379 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5380 qpn); 5381 if (ret) 5382 goto out; 5383 5384 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5385 5386 out: 5387 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5388 return ret; 5389 } 5390 5391 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5392 int qp_attr_mask, 5393 struct ib_qp_init_attr *qp_init_attr) 5394 { 5395 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5396 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5397 struct hns_roce_v2_qp_context context = {}; 5398 struct ib_device *ibdev = &hr_dev->ib_dev; 5399 int tmp_qp_state; 5400 int state; 5401 int ret; 5402 5403 memset(qp_attr, 0, sizeof(*qp_attr)); 5404 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5405 5406 mutex_lock(&hr_qp->mutex); 5407 5408 if (hr_qp->state == IB_QPS_RESET) { 5409 qp_attr->qp_state = IB_QPS_RESET; 5410 ret = 0; 5411 goto done; 5412 } 5413 5414 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5415 if (ret) { 5416 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5417 ret = -EINVAL; 5418 goto out; 5419 } 5420 5421 state = hr_reg_read(&context, QPC_QP_ST); 5422 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5423 if (tmp_qp_state == -1) { 5424 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5425 ret = -EINVAL; 5426 goto out; 5427 } 5428 hr_qp->state = (u8)tmp_qp_state; 5429 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5430 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5431 qp_attr->path_mig_state = IB_MIG_ARMED; 5432 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5433 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5434 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5435 5436 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5437 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5438 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5439 qp_attr->qp_access_flags = 5440 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5441 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5442 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5443 5444 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5445 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5446 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5447 struct ib_global_route *grh = 5448 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5449 5450 rdma_ah_set_sl(&qp_attr->ah_attr, 5451 hr_reg_read(&context, QPC_SL)); 5452 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5453 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5454 grh->flow_label = hr_reg_read(&context, QPC_FL); 5455 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5456 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5457 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5458 5459 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5460 } 5461 5462 qp_attr->port_num = hr_qp->port + 1; 5463 qp_attr->sq_draining = 0; 5464 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5465 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5466 5467 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5468 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5469 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5470 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5471 5472 done: 5473 qp_attr->cur_qp_state = qp_attr->qp_state; 5474 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5475 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5476 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5477 5478 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5479 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5480 5481 qp_init_attr->qp_context = ibqp->qp_context; 5482 qp_init_attr->qp_type = ibqp->qp_type; 5483 qp_init_attr->recv_cq = ibqp->recv_cq; 5484 qp_init_attr->send_cq = ibqp->send_cq; 5485 qp_init_attr->srq = ibqp->srq; 5486 qp_init_attr->cap = qp_attr->cap; 5487 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5488 5489 out: 5490 mutex_unlock(&hr_qp->mutex); 5491 return ret; 5492 } 5493 5494 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5495 { 5496 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5497 hr_qp->ibqp.qp_type == IB_QPT_UD || 5498 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5499 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5500 hr_qp->state != IB_QPS_RESET); 5501 } 5502 5503 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5504 struct hns_roce_qp *hr_qp, 5505 struct ib_udata *udata) 5506 { 5507 struct ib_device *ibdev = &hr_dev->ib_dev; 5508 struct hns_roce_cq *send_cq, *recv_cq; 5509 unsigned long flags; 5510 int ret = 0; 5511 5512 if (modify_qp_is_ok(hr_qp)) { 5513 /* Modify qp to reset before destroying qp */ 5514 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5515 hr_qp->state, IB_QPS_RESET, udata); 5516 if (ret) 5517 ibdev_err(ibdev, 5518 "failed to modify QP to RST, ret = %d.\n", 5519 ret); 5520 } 5521 5522 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5523 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5524 5525 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5526 hns_roce_lock_cqs(send_cq, recv_cq); 5527 5528 if (!udata) { 5529 if (recv_cq) 5530 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5531 (hr_qp->ibqp.srq ? 5532 to_hr_srq(hr_qp->ibqp.srq) : 5533 NULL)); 5534 5535 if (send_cq && send_cq != recv_cq) 5536 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5537 } 5538 5539 hns_roce_qp_remove(hr_dev, hr_qp); 5540 5541 hns_roce_unlock_cqs(send_cq, recv_cq); 5542 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5543 5544 return ret; 5545 } 5546 5547 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5548 { 5549 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5550 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5551 int ret; 5552 5553 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5554 if (ret) 5555 ibdev_err(&hr_dev->ib_dev, 5556 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5557 hr_qp->qpn, ret); 5558 5559 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5560 5561 return 0; 5562 } 5563 5564 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5565 struct hns_roce_qp *hr_qp) 5566 { 5567 struct ib_device *ibdev = &hr_dev->ib_dev; 5568 struct hns_roce_sccc_clr_done *resp; 5569 struct hns_roce_sccc_clr *clr; 5570 struct hns_roce_cmq_desc desc; 5571 int ret, i; 5572 5573 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5574 return 0; 5575 5576 mutex_lock(&hr_dev->qp_table.scc_mutex); 5577 5578 /* set scc ctx clear done flag */ 5579 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5580 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5581 if (ret) { 5582 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5583 goto out; 5584 } 5585 5586 /* clear scc context */ 5587 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5588 clr = (struct hns_roce_sccc_clr *)desc.data; 5589 clr->qpn = cpu_to_le32(hr_qp->qpn); 5590 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5591 if (ret) { 5592 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5593 goto out; 5594 } 5595 5596 /* query scc context clear is done or not */ 5597 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5598 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5599 hns_roce_cmq_setup_basic_desc(&desc, 5600 HNS_ROCE_OPC_QUERY_SCCC, true); 5601 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5602 if (ret) { 5603 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5604 ret); 5605 goto out; 5606 } 5607 5608 if (resp->clr_done) 5609 goto out; 5610 5611 msleep(20); 5612 } 5613 5614 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5615 ret = -ETIMEDOUT; 5616 5617 out: 5618 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5619 return ret; 5620 } 5621 5622 #define DMA_IDX_SHIFT 3 5623 #define DMA_WQE_SHIFT 3 5624 5625 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5626 struct hns_roce_srq_context *ctx) 5627 { 5628 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5629 struct ib_device *ibdev = srq->ibsrq.device; 5630 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5631 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5632 dma_addr_t dma_handle_idx = 0; 5633 int ret; 5634 5635 /* Get physical address of idx que buf */ 5636 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5637 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5638 if (ret < 1) { 5639 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5640 ret); 5641 return -ENOBUFS; 5642 } 5643 5644 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5645 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5646 5647 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5648 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5649 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5650 5651 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5652 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5653 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5654 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5655 5656 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5657 to_hr_hw_page_addr(mtts_idx[0])); 5658 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5659 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5660 5661 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5662 to_hr_hw_page_addr(mtts_idx[1])); 5663 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5664 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5665 5666 return 0; 5667 } 5668 5669 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5670 { 5671 struct ib_device *ibdev = srq->ibsrq.device; 5672 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5673 struct hns_roce_srq_context *ctx = mb_buf; 5674 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5675 dma_addr_t dma_handle_wqe = 0; 5676 int ret; 5677 5678 memset(ctx, 0, sizeof(*ctx)); 5679 5680 /* Get the physical address of srq buf */ 5681 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5682 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5683 if (ret < 1) { 5684 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5685 ret); 5686 return -ENOBUFS; 5687 } 5688 5689 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5690 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5691 srq->ibsrq.srq_type == IB_SRQT_XRC); 5692 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5693 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5694 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5695 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5696 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5697 hr_reg_write(ctx, SRQC_RQWS, 5698 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5699 5700 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5701 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5702 srq->wqe_cnt)); 5703 5704 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5705 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5706 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5707 5708 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5709 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5710 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5711 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5712 5713 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5714 } 5715 5716 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5717 struct ib_srq_attr *srq_attr, 5718 enum ib_srq_attr_mask srq_attr_mask, 5719 struct ib_udata *udata) 5720 { 5721 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5722 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5723 struct hns_roce_srq_context *srq_context; 5724 struct hns_roce_srq_context *srqc_mask; 5725 struct hns_roce_cmd_mailbox *mailbox; 5726 int ret; 5727 5728 /* Resizing SRQs is not supported yet */ 5729 if (srq_attr_mask & IB_SRQ_MAX_WR) 5730 return -EINVAL; 5731 5732 if (srq_attr_mask & IB_SRQ_LIMIT) { 5733 if (srq_attr->srq_limit > srq->wqe_cnt) 5734 return -EINVAL; 5735 5736 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5737 if (IS_ERR(mailbox)) 5738 return PTR_ERR(mailbox); 5739 5740 srq_context = mailbox->buf; 5741 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5742 5743 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5744 5745 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5746 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5747 5748 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5749 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5750 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5751 if (ret) { 5752 ibdev_err(&hr_dev->ib_dev, 5753 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5754 ret); 5755 return ret; 5756 } 5757 } 5758 5759 return 0; 5760 } 5761 5762 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5763 { 5764 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5765 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5766 struct hns_roce_srq_context *srq_context; 5767 struct hns_roce_cmd_mailbox *mailbox; 5768 int ret; 5769 5770 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5771 if (IS_ERR(mailbox)) 5772 return PTR_ERR(mailbox); 5773 5774 srq_context = mailbox->buf; 5775 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5776 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5777 if (ret) { 5778 ibdev_err(&hr_dev->ib_dev, 5779 "failed to process cmd of querying SRQ, ret = %d.\n", 5780 ret); 5781 goto out; 5782 } 5783 5784 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5785 attr->max_wr = srq->wqe_cnt; 5786 attr->max_sge = srq->max_gs - srq->rsv_sge; 5787 5788 out: 5789 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5790 return ret; 5791 } 5792 5793 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5794 { 5795 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5796 struct hns_roce_v2_cq_context *cq_context; 5797 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5798 struct hns_roce_v2_cq_context *cqc_mask; 5799 struct hns_roce_cmd_mailbox *mailbox; 5800 int ret; 5801 5802 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5803 if (IS_ERR(mailbox)) 5804 return PTR_ERR(mailbox); 5805 5806 cq_context = mailbox->buf; 5807 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5808 5809 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5810 5811 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5812 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5813 5814 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5815 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5816 dev_info(hr_dev->dev, 5817 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5818 cq_period); 5819 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5820 } 5821 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5822 } 5823 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5824 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5825 5826 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5827 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5828 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5829 if (ret) 5830 ibdev_err(&hr_dev->ib_dev, 5831 "failed to process cmd when modifying CQ, ret = %d.\n", 5832 ret); 5833 5834 return ret; 5835 } 5836 5837 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5838 void *buffer) 5839 { 5840 struct hns_roce_v2_cq_context *context; 5841 struct hns_roce_cmd_mailbox *mailbox; 5842 int ret; 5843 5844 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5845 if (IS_ERR(mailbox)) 5846 return PTR_ERR(mailbox); 5847 5848 context = mailbox->buf; 5849 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5850 HNS_ROCE_CMD_QUERY_CQC, cqn); 5851 if (ret) { 5852 ibdev_err(&hr_dev->ib_dev, 5853 "failed to process cmd when querying CQ, ret = %d.\n", 5854 ret); 5855 goto err_mailbox; 5856 } 5857 5858 memcpy(buffer, context, sizeof(*context)); 5859 5860 err_mailbox: 5861 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5862 5863 return ret; 5864 } 5865 5866 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5867 void *buffer) 5868 { 5869 struct hns_roce_v2_mpt_entry *context; 5870 struct hns_roce_cmd_mailbox *mailbox; 5871 int ret; 5872 5873 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5874 if (IS_ERR(mailbox)) 5875 return PTR_ERR(mailbox); 5876 5877 context = mailbox->buf; 5878 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5879 key_to_hw_index(key)); 5880 if (ret) { 5881 ibdev_err(&hr_dev->ib_dev, 5882 "failed to process cmd when querying MPT, ret = %d.\n", 5883 ret); 5884 goto err_mailbox; 5885 } 5886 5887 memcpy(buffer, context, sizeof(*context)); 5888 5889 err_mailbox: 5890 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5891 5892 return ret; 5893 } 5894 5895 static void hns_roce_irq_work_handle(struct work_struct *work) 5896 { 5897 struct hns_roce_work *irq_work = 5898 container_of(work, struct hns_roce_work, work); 5899 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5900 5901 switch (irq_work->event_type) { 5902 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5903 ibdev_info(ibdev, "path migrated succeeded.\n"); 5904 break; 5905 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5906 ibdev_warn(ibdev, "path migration failed.\n"); 5907 break; 5908 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5909 break; 5910 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5911 ibdev_warn(ibdev, "send queue drained.\n"); 5912 break; 5913 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5914 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5915 irq_work->queue_num, irq_work->sub_type); 5916 break; 5917 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5918 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5919 irq_work->queue_num); 5920 break; 5921 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5922 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5923 irq_work->queue_num, irq_work->sub_type); 5924 break; 5925 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5926 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5927 break; 5928 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5929 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5930 break; 5931 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5932 ibdev_err(ibdev, "SRQ catas error.\n"); 5933 break; 5934 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5935 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5936 break; 5937 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5938 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5939 break; 5940 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5941 ibdev_warn(ibdev, "DB overflow.\n"); 5942 break; 5943 case HNS_ROCE_EVENT_TYPE_FLR: 5944 ibdev_warn(ibdev, "function level reset.\n"); 5945 break; 5946 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5947 ibdev_err(ibdev, "xrc domain violation error.\n"); 5948 break; 5949 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5950 ibdev_err(ibdev, "invalid xrceth error.\n"); 5951 break; 5952 default: 5953 break; 5954 } 5955 5956 kfree(irq_work); 5957 } 5958 5959 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5960 struct hns_roce_eq *eq, u32 queue_num) 5961 { 5962 struct hns_roce_work *irq_work; 5963 5964 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5965 if (!irq_work) 5966 return; 5967 5968 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5969 irq_work->hr_dev = hr_dev; 5970 irq_work->event_type = eq->event_type; 5971 irq_work->sub_type = eq->sub_type; 5972 irq_work->queue_num = queue_num; 5973 queue_work(hr_dev->irq_workq, &irq_work->work); 5974 } 5975 5976 static void update_eq_db(struct hns_roce_eq *eq) 5977 { 5978 struct hns_roce_dev *hr_dev = eq->hr_dev; 5979 struct hns_roce_v2_db eq_db = {}; 5980 5981 if (eq->type_flag == HNS_ROCE_AEQ) { 5982 hr_reg_write(&eq_db, EQ_DB_CMD, 5983 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5984 HNS_ROCE_EQ_DB_CMD_AEQ : 5985 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5986 } else { 5987 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5988 5989 hr_reg_write(&eq_db, EQ_DB_CMD, 5990 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5991 HNS_ROCE_EQ_DB_CMD_CEQ : 5992 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5993 } 5994 5995 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5996 5997 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5998 } 5999 6000 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6001 { 6002 struct hns_roce_aeqe *aeqe; 6003 6004 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6005 (eq->cons_index & (eq->entries - 1)) * 6006 eq->eqe_size); 6007 6008 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6009 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6010 } 6011 6012 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6013 struct hns_roce_eq *eq) 6014 { 6015 struct device *dev = hr_dev->dev; 6016 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6017 irqreturn_t aeqe_found = IRQ_NONE; 6018 int event_type; 6019 u32 queue_num; 6020 int sub_type; 6021 6022 while (aeqe) { 6023 /* Make sure we read AEQ entry after we have checked the 6024 * ownership bit 6025 */ 6026 dma_rmb(); 6027 6028 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6029 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6030 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6031 6032 switch (event_type) { 6033 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6034 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6035 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6036 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6037 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6038 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6039 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6040 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6041 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6042 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6043 hns_roce_qp_event(hr_dev, queue_num, event_type); 6044 break; 6045 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6046 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6047 hns_roce_srq_event(hr_dev, queue_num, event_type); 6048 break; 6049 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6050 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6051 hns_roce_cq_event(hr_dev, queue_num, event_type); 6052 break; 6053 case HNS_ROCE_EVENT_TYPE_MB: 6054 hns_roce_cmd_event(hr_dev, 6055 le16_to_cpu(aeqe->event.cmd.token), 6056 aeqe->event.cmd.status, 6057 le64_to_cpu(aeqe->event.cmd.out_param)); 6058 break; 6059 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6060 case HNS_ROCE_EVENT_TYPE_FLR: 6061 break; 6062 default: 6063 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 6064 event_type, eq->eqn, eq->cons_index); 6065 break; 6066 } 6067 6068 eq->event_type = event_type; 6069 eq->sub_type = sub_type; 6070 ++eq->cons_index; 6071 aeqe_found = IRQ_HANDLED; 6072 6073 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6074 6075 aeqe = next_aeqe_sw_v2(eq); 6076 } 6077 6078 update_eq_db(eq); 6079 6080 return IRQ_RETVAL(aeqe_found); 6081 } 6082 6083 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6084 { 6085 struct hns_roce_ceqe *ceqe; 6086 6087 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6088 (eq->cons_index & (eq->entries - 1)) * 6089 eq->eqe_size); 6090 6091 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6092 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6093 } 6094 6095 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6096 struct hns_roce_eq *eq) 6097 { 6098 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6099 irqreturn_t ceqe_found = IRQ_NONE; 6100 u32 cqn; 6101 6102 while (ceqe) { 6103 /* Make sure we read CEQ entry after we have checked the 6104 * ownership bit 6105 */ 6106 dma_rmb(); 6107 6108 cqn = hr_reg_read(ceqe, CEQE_CQN); 6109 6110 hns_roce_cq_completion(hr_dev, cqn); 6111 6112 ++eq->cons_index; 6113 ceqe_found = IRQ_HANDLED; 6114 6115 ceqe = next_ceqe_sw_v2(eq); 6116 } 6117 6118 update_eq_db(eq); 6119 6120 return IRQ_RETVAL(ceqe_found); 6121 } 6122 6123 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6124 { 6125 struct hns_roce_eq *eq = eq_ptr; 6126 struct hns_roce_dev *hr_dev = eq->hr_dev; 6127 irqreturn_t int_work; 6128 6129 if (eq->type_flag == HNS_ROCE_CEQ) 6130 /* Completion event interrupt */ 6131 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6132 else 6133 /* Asynchronous event interrupt */ 6134 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6135 6136 return IRQ_RETVAL(int_work); 6137 } 6138 6139 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6140 u32 int_st) 6141 { 6142 struct pci_dev *pdev = hr_dev->pci_dev; 6143 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6144 const struct hnae3_ae_ops *ops = ae_dev->ops; 6145 irqreturn_t int_work = IRQ_NONE; 6146 u32 int_en; 6147 6148 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6149 6150 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6151 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6152 6153 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6154 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6155 6156 /* Set reset level for reset_event() */ 6157 if (ops->set_default_reset_request) 6158 ops->set_default_reset_request(ae_dev, 6159 HNAE3_FUNC_RESET); 6160 if (ops->reset_event) 6161 ops->reset_event(pdev, NULL); 6162 6163 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6164 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6165 6166 int_work = IRQ_HANDLED; 6167 } else { 6168 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6169 } 6170 6171 return IRQ_RETVAL(int_work); 6172 } 6173 6174 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6175 struct fmea_ram_ecc *ecc_info) 6176 { 6177 struct hns_roce_cmq_desc desc; 6178 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6179 int ret; 6180 6181 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6182 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6183 if (ret) 6184 return ret; 6185 6186 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6187 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6188 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6189 6190 return 0; 6191 } 6192 6193 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6194 { 6195 struct hns_roce_cmq_desc desc; 6196 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6197 u32 addr_upper; 6198 u32 addr_low; 6199 int ret; 6200 6201 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6202 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6203 6204 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6205 if (ret) { 6206 dev_err(hr_dev->dev, 6207 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6208 return ret; 6209 } 6210 6211 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6212 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6213 6214 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6215 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6216 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6217 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6218 6219 return hns_roce_cmq_send(hr_dev, &desc, 1); 6220 } 6221 6222 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6223 { 6224 if (res_type == ECC_RESOURCE_QPC_TIMER || 6225 res_type == ECC_RESOURCE_CQC_TIMER || 6226 res_type == ECC_RESOURCE_SCCC) 6227 return le64_to_cpu(*data); 6228 6229 return le64_to_cpu(*data) << PAGE_SHIFT; 6230 } 6231 6232 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6233 u32 index) 6234 { 6235 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6236 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6237 struct hns_roce_cmd_mailbox *mailbox; 6238 u64 addr; 6239 int ret; 6240 6241 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6242 if (IS_ERR(mailbox)) 6243 return PTR_ERR(mailbox); 6244 6245 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6246 if (ret) { 6247 dev_err(hr_dev->dev, 6248 "failed to execute cmd to read fmea ram, ret = %d.\n", 6249 ret); 6250 goto out; 6251 } 6252 6253 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6254 6255 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6256 if (ret) 6257 dev_err(hr_dev->dev, 6258 "failed to execute cmd to write fmea ram, ret = %d.\n", 6259 ret); 6260 6261 out: 6262 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6263 return ret; 6264 } 6265 6266 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6267 struct fmea_ram_ecc *ecc_info) 6268 { 6269 u32 res_type = ecc_info->res_type; 6270 u32 index = ecc_info->index; 6271 int ret; 6272 6273 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6274 6275 if (res_type >= ECC_RESOURCE_COUNT) { 6276 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6277 res_type); 6278 return; 6279 } 6280 6281 if (res_type == ECC_RESOURCE_GMV) 6282 ret = fmea_recover_gmv(hr_dev, index); 6283 else 6284 ret = fmea_recover_others(hr_dev, res_type, index); 6285 if (ret) 6286 dev_err(hr_dev->dev, 6287 "failed to recover %s, index = %u, ret = %d.\n", 6288 fmea_ram_res[res_type].name, index, ret); 6289 } 6290 6291 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6292 { 6293 struct hns_roce_dev *hr_dev = 6294 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6295 struct fmea_ram_ecc ecc_info = {}; 6296 6297 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6298 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6299 return; 6300 } 6301 6302 if (!ecc_info.is_ecc_err) { 6303 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6304 return; 6305 } 6306 6307 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6308 } 6309 6310 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6311 { 6312 struct hns_roce_dev *hr_dev = dev_id; 6313 irqreturn_t int_work = IRQ_NONE; 6314 u32 int_st; 6315 6316 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6317 6318 if (int_st) { 6319 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6320 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6321 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6322 int_work = IRQ_HANDLED; 6323 } else { 6324 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6325 } 6326 6327 return IRQ_RETVAL(int_work); 6328 } 6329 6330 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6331 int eq_num, u32 enable_flag) 6332 { 6333 int i; 6334 6335 for (i = 0; i < eq_num; i++) 6336 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6337 i * EQ_REG_OFFSET, enable_flag); 6338 6339 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6340 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6341 } 6342 6343 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6344 { 6345 struct device *dev = hr_dev->dev; 6346 int ret; 6347 u8 cmd; 6348 6349 if (eqn < hr_dev->caps.num_comp_vectors) 6350 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6351 else 6352 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6353 6354 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6355 if (ret) 6356 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6357 } 6358 6359 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6360 { 6361 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6362 } 6363 6364 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6365 { 6366 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6367 eq->cons_index = 0; 6368 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6369 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6370 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6371 eq->shift = ilog2((unsigned int)eq->entries); 6372 } 6373 6374 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6375 void *mb_buf) 6376 { 6377 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6378 struct hns_roce_eq_context *eqc; 6379 u64 bt_ba = 0; 6380 int count; 6381 6382 eqc = mb_buf; 6383 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6384 6385 init_eq_config(hr_dev, eq); 6386 6387 /* if not multi-hop, eqe buffer only use one trunk */ 6388 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6389 &bt_ba); 6390 if (count < 1) { 6391 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6392 return -ENOBUFS; 6393 } 6394 6395 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6396 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6397 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6398 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6399 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6400 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6401 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6402 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6403 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6404 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6405 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6406 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6407 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6408 6409 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6410 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6411 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6412 eq->eq_period); 6413 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6414 } 6415 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6416 } 6417 6418 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6419 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6420 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6421 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6422 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6423 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6424 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6425 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6426 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6427 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6428 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6429 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6430 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6431 6432 return 0; 6433 } 6434 6435 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6436 { 6437 struct hns_roce_buf_attr buf_attr = {}; 6438 int err; 6439 6440 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6441 eq->hop_num = 0; 6442 else 6443 eq->hop_num = hr_dev->caps.eqe_hop_num; 6444 6445 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6446 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6447 buf_attr.region[0].hopnum = eq->hop_num; 6448 buf_attr.region_count = 1; 6449 6450 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6451 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6452 0); 6453 if (err) 6454 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6455 6456 return err; 6457 } 6458 6459 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6460 struct hns_roce_eq *eq, u8 eq_cmd) 6461 { 6462 struct hns_roce_cmd_mailbox *mailbox; 6463 int ret; 6464 6465 /* Allocate mailbox memory */ 6466 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6467 if (IS_ERR(mailbox)) 6468 return PTR_ERR(mailbox); 6469 6470 ret = alloc_eq_buf(hr_dev, eq); 6471 if (ret) 6472 goto free_cmd_mbox; 6473 6474 ret = config_eqc(hr_dev, eq, mailbox->buf); 6475 if (ret) 6476 goto err_cmd_mbox; 6477 6478 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6479 if (ret) { 6480 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6481 goto err_cmd_mbox; 6482 } 6483 6484 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6485 6486 return 0; 6487 6488 err_cmd_mbox: 6489 free_eq_buf(hr_dev, eq); 6490 6491 free_cmd_mbox: 6492 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6493 6494 return ret; 6495 } 6496 6497 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6498 int comp_num, int aeq_num, int other_num) 6499 { 6500 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6501 int i, j; 6502 int ret; 6503 6504 for (i = 0; i < irq_num; i++) { 6505 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6506 GFP_KERNEL); 6507 if (!hr_dev->irq_names[i]) { 6508 ret = -ENOMEM; 6509 goto err_kzalloc_failed; 6510 } 6511 } 6512 6513 /* irq contains: abnormal + AEQ + CEQ */ 6514 for (j = 0; j < other_num; j++) 6515 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6516 "hns-abn-%d", j); 6517 6518 for (j = other_num; j < (other_num + aeq_num); j++) 6519 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6520 "hns-aeq-%d", j - other_num); 6521 6522 for (j = (other_num + aeq_num); j < irq_num; j++) 6523 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6524 "hns-ceq-%d", j - other_num - aeq_num); 6525 6526 for (j = 0; j < irq_num; j++) { 6527 if (j < other_num) 6528 ret = request_irq(hr_dev->irq[j], 6529 hns_roce_v2_msix_interrupt_abn, 6530 0, hr_dev->irq_names[j], hr_dev); 6531 6532 else if (j < (other_num + comp_num)) 6533 ret = request_irq(eq_table->eq[j - other_num].irq, 6534 hns_roce_v2_msix_interrupt_eq, 6535 0, hr_dev->irq_names[j + aeq_num], 6536 &eq_table->eq[j - other_num]); 6537 else 6538 ret = request_irq(eq_table->eq[j - other_num].irq, 6539 hns_roce_v2_msix_interrupt_eq, 6540 0, hr_dev->irq_names[j - comp_num], 6541 &eq_table->eq[j - other_num]); 6542 if (ret) { 6543 dev_err(hr_dev->dev, "request irq error!\n"); 6544 goto err_request_failed; 6545 } 6546 } 6547 6548 return 0; 6549 6550 err_request_failed: 6551 for (j -= 1; j >= 0; j--) 6552 if (j < other_num) 6553 free_irq(hr_dev->irq[j], hr_dev); 6554 else 6555 free_irq(eq_table->eq[j - other_num].irq, 6556 &eq_table->eq[j - other_num]); 6557 6558 err_kzalloc_failed: 6559 for (i -= 1; i >= 0; i--) 6560 kfree(hr_dev->irq_names[i]); 6561 6562 return ret; 6563 } 6564 6565 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6566 { 6567 int irq_num; 6568 int eq_num; 6569 int i; 6570 6571 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6572 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6573 6574 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6575 free_irq(hr_dev->irq[i], hr_dev); 6576 6577 for (i = 0; i < eq_num; i++) 6578 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6579 6580 for (i = 0; i < irq_num; i++) 6581 kfree(hr_dev->irq_names[i]); 6582 } 6583 6584 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6585 { 6586 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6587 struct device *dev = hr_dev->dev; 6588 struct hns_roce_eq *eq; 6589 int other_num; 6590 int comp_num; 6591 int aeq_num; 6592 int irq_num; 6593 int eq_num; 6594 u8 eq_cmd; 6595 int ret; 6596 int i; 6597 6598 other_num = hr_dev->caps.num_other_vectors; 6599 comp_num = hr_dev->caps.num_comp_vectors; 6600 aeq_num = hr_dev->caps.num_aeq_vectors; 6601 6602 eq_num = comp_num + aeq_num; 6603 irq_num = eq_num + other_num; 6604 6605 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6606 if (!eq_table->eq) 6607 return -ENOMEM; 6608 6609 /* create eq */ 6610 for (i = 0; i < eq_num; i++) { 6611 eq = &eq_table->eq[i]; 6612 eq->hr_dev = hr_dev; 6613 eq->eqn = i; 6614 if (i < comp_num) { 6615 /* CEQ */ 6616 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6617 eq->type_flag = HNS_ROCE_CEQ; 6618 eq->entries = hr_dev->caps.ceqe_depth; 6619 eq->eqe_size = hr_dev->caps.ceqe_size; 6620 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6621 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6622 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6623 } else { 6624 /* AEQ */ 6625 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6626 eq->type_flag = HNS_ROCE_AEQ; 6627 eq->entries = hr_dev->caps.aeqe_depth; 6628 eq->eqe_size = hr_dev->caps.aeqe_size; 6629 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6630 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6631 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6632 } 6633 6634 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6635 if (ret) { 6636 dev_err(dev, "failed to create eq.\n"); 6637 goto err_create_eq_fail; 6638 } 6639 } 6640 6641 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6642 6643 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6644 if (!hr_dev->irq_workq) { 6645 dev_err(dev, "failed to create irq workqueue.\n"); 6646 ret = -ENOMEM; 6647 goto err_create_eq_fail; 6648 } 6649 6650 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6651 other_num); 6652 if (ret) { 6653 dev_err(dev, "failed to request irq.\n"); 6654 goto err_request_irq_fail; 6655 } 6656 6657 /* enable irq */ 6658 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6659 6660 return 0; 6661 6662 err_request_irq_fail: 6663 destroy_workqueue(hr_dev->irq_workq); 6664 6665 err_create_eq_fail: 6666 for (i -= 1; i >= 0; i--) 6667 free_eq_buf(hr_dev, &eq_table->eq[i]); 6668 kfree(eq_table->eq); 6669 6670 return ret; 6671 } 6672 6673 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6674 { 6675 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6676 int eq_num; 6677 int i; 6678 6679 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6680 6681 /* Disable irq */ 6682 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6683 6684 __hns_roce_free_irq(hr_dev); 6685 destroy_workqueue(hr_dev->irq_workq); 6686 6687 for (i = 0; i < eq_num; i++) { 6688 hns_roce_v2_destroy_eqc(hr_dev, i); 6689 6690 free_eq_buf(hr_dev, &eq_table->eq[i]); 6691 } 6692 6693 kfree(eq_table->eq); 6694 } 6695 6696 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6697 .destroy_qp = hns_roce_v2_destroy_qp, 6698 .modify_cq = hns_roce_v2_modify_cq, 6699 .poll_cq = hns_roce_v2_poll_cq, 6700 .post_recv = hns_roce_v2_post_recv, 6701 .post_send = hns_roce_v2_post_send, 6702 .query_qp = hns_roce_v2_query_qp, 6703 .req_notify_cq = hns_roce_v2_req_notify_cq, 6704 }; 6705 6706 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6707 .modify_srq = hns_roce_v2_modify_srq, 6708 .post_srq_recv = hns_roce_v2_post_srq_recv, 6709 .query_srq = hns_roce_v2_query_srq, 6710 }; 6711 6712 static const struct hns_roce_hw hns_roce_hw_v2 = { 6713 .cmq_init = hns_roce_v2_cmq_init, 6714 .cmq_exit = hns_roce_v2_cmq_exit, 6715 .hw_profile = hns_roce_v2_profile, 6716 .hw_init = hns_roce_v2_init, 6717 .hw_exit = hns_roce_v2_exit, 6718 .post_mbox = v2_post_mbox, 6719 .poll_mbox_done = v2_poll_mbox_done, 6720 .chk_mbox_avail = v2_chk_mbox_is_avail, 6721 .set_gid = hns_roce_v2_set_gid, 6722 .set_mac = hns_roce_v2_set_mac, 6723 .write_mtpt = hns_roce_v2_write_mtpt, 6724 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6725 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6726 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6727 .write_cqc = hns_roce_v2_write_cqc, 6728 .set_hem = hns_roce_v2_set_hem, 6729 .clear_hem = hns_roce_v2_clear_hem, 6730 .modify_qp = hns_roce_v2_modify_qp, 6731 .dereg_mr = hns_roce_v2_dereg_mr, 6732 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6733 .init_eq = hns_roce_v2_init_eq_table, 6734 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6735 .write_srqc = hns_roce_v2_write_srqc, 6736 .query_cqc = hns_roce_v2_query_cqc, 6737 .query_qpc = hns_roce_v2_query_qpc, 6738 .query_mpt = hns_roce_v2_query_mpt, 6739 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6740 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6741 }; 6742 6743 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6744 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6745 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6746 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6747 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6748 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6749 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6750 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6751 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6752 /* required last entry */ 6753 {0, } 6754 }; 6755 6756 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6757 6758 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6759 struct hnae3_handle *handle) 6760 { 6761 struct hns_roce_v2_priv *priv = hr_dev->priv; 6762 const struct pci_device_id *id; 6763 int i; 6764 6765 hr_dev->pci_dev = handle->pdev; 6766 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6767 hr_dev->is_vf = id->driver_data; 6768 hr_dev->dev = &handle->pdev->dev; 6769 hr_dev->hw = &hns_roce_hw_v2; 6770 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6771 hr_dev->odb_offset = hr_dev->sdb_offset; 6772 6773 /* Get info from NIC driver. */ 6774 hr_dev->reg_base = handle->rinfo.roce_io_base; 6775 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6776 hr_dev->caps.num_ports = 1; 6777 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6778 hr_dev->iboe.phy_port[0] = 0; 6779 6780 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6781 hr_dev->iboe.netdevs[0]->dev_addr); 6782 6783 for (i = 0; i < handle->rinfo.num_vectors; i++) 6784 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6785 i + handle->rinfo.base_vector); 6786 6787 /* cmd issue mode: 0 is poll, 1 is event */ 6788 hr_dev->cmd_mod = 1; 6789 hr_dev->loop_idc = 0; 6790 6791 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6792 priv->handle = handle; 6793 } 6794 6795 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6796 { 6797 struct hns_roce_dev *hr_dev; 6798 int ret; 6799 6800 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6801 if (!hr_dev) 6802 return -ENOMEM; 6803 6804 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6805 if (!hr_dev->priv) { 6806 ret = -ENOMEM; 6807 goto error_failed_kzalloc; 6808 } 6809 6810 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6811 6812 ret = hns_roce_init(hr_dev); 6813 if (ret) { 6814 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6815 goto error_failed_cfg; 6816 } 6817 6818 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6819 ret = free_mr_init(hr_dev); 6820 if (ret) { 6821 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6822 goto error_failed_roce_init; 6823 } 6824 } 6825 6826 handle->priv = hr_dev; 6827 6828 return 0; 6829 6830 error_failed_roce_init: 6831 hns_roce_exit(hr_dev); 6832 6833 error_failed_cfg: 6834 kfree(hr_dev->priv); 6835 6836 error_failed_kzalloc: 6837 ib_dealloc_device(&hr_dev->ib_dev); 6838 6839 return ret; 6840 } 6841 6842 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6843 bool reset) 6844 { 6845 struct hns_roce_dev *hr_dev = handle->priv; 6846 6847 if (!hr_dev) 6848 return; 6849 6850 handle->priv = NULL; 6851 6852 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6853 hns_roce_handle_device_err(hr_dev); 6854 6855 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6856 free_mr_exit(hr_dev); 6857 6858 hns_roce_exit(hr_dev); 6859 kfree(hr_dev->priv); 6860 ib_dealloc_device(&hr_dev->ib_dev); 6861 } 6862 6863 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6864 { 6865 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6866 const struct pci_device_id *id; 6867 struct device *dev = &handle->pdev->dev; 6868 int ret; 6869 6870 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6871 6872 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6873 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6874 goto reset_chk_err; 6875 } 6876 6877 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6878 if (!id) 6879 return 0; 6880 6881 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6882 return 0; 6883 6884 ret = __hns_roce_hw_v2_init_instance(handle); 6885 if (ret) { 6886 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6887 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6888 if (ops->ae_dev_resetting(handle) || 6889 ops->get_hw_reset_stat(handle)) 6890 goto reset_chk_err; 6891 else 6892 return ret; 6893 } 6894 6895 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6896 6897 return 0; 6898 6899 reset_chk_err: 6900 dev_err(dev, "Device is busy in resetting state.\n" 6901 "please retry later.\n"); 6902 6903 return -EBUSY; 6904 } 6905 6906 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6907 bool reset) 6908 { 6909 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6910 return; 6911 6912 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6913 6914 __hns_roce_hw_v2_uninit_instance(handle, reset); 6915 6916 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6917 } 6918 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6919 { 6920 struct hns_roce_dev *hr_dev; 6921 6922 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6923 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6924 return 0; 6925 } 6926 6927 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6928 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6929 6930 hr_dev = handle->priv; 6931 if (!hr_dev) 6932 return 0; 6933 6934 hr_dev->active = false; 6935 hr_dev->dis_db = true; 6936 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6937 6938 return 0; 6939 } 6940 6941 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6942 { 6943 struct device *dev = &handle->pdev->dev; 6944 int ret; 6945 6946 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6947 &handle->rinfo.state)) { 6948 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6949 return 0; 6950 } 6951 6952 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6953 6954 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6955 ret = __hns_roce_hw_v2_init_instance(handle); 6956 if (ret) { 6957 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6958 * callback function, RoCE Engine reinitialize. If RoCE reinit 6959 * failed, we should inform NIC driver. 6960 */ 6961 handle->priv = NULL; 6962 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6963 } else { 6964 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6965 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6966 } 6967 6968 return ret; 6969 } 6970 6971 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6972 { 6973 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6974 return 0; 6975 6976 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6977 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6978 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6979 __hns_roce_hw_v2_uninit_instance(handle, false); 6980 6981 return 0; 6982 } 6983 6984 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6985 enum hnae3_reset_notify_type type) 6986 { 6987 int ret = 0; 6988 6989 switch (type) { 6990 case HNAE3_DOWN_CLIENT: 6991 ret = hns_roce_hw_v2_reset_notify_down(handle); 6992 break; 6993 case HNAE3_INIT_CLIENT: 6994 ret = hns_roce_hw_v2_reset_notify_init(handle); 6995 break; 6996 case HNAE3_UNINIT_CLIENT: 6997 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6998 break; 6999 default: 7000 break; 7001 } 7002 7003 return ret; 7004 } 7005 7006 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7007 .init_instance = hns_roce_hw_v2_init_instance, 7008 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7009 .reset_notify = hns_roce_hw_v2_reset_notify, 7010 }; 7011 7012 static struct hnae3_client hns_roce_hw_v2_client = { 7013 .name = "hns_roce_hw_v2", 7014 .type = HNAE3_CLIENT_ROCE, 7015 .ops = &hns_roce_hw_v2_ops, 7016 }; 7017 7018 static int __init hns_roce_hw_v2_init(void) 7019 { 7020 return hnae3_register_client(&hns_roce_hw_v2_client); 7021 } 7022 7023 static void __exit hns_roce_hw_v2_exit(void) 7024 { 7025 hnae3_unregister_client(&hns_roce_hw_v2_client); 7026 } 7027 7028 module_init(hns_roce_hw_v2_init); 7029 module_exit(hns_roce_hw_v2_exit); 7030 7031 MODULE_LICENSE("Dual BSD/GPL"); 7032 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7033 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7034 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7035 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7036