1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2006-2015, Intel Corporation. 4 * 5 * Authors: Ashok Raj <ashok.raj@intel.com> 6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 7 * David Woodhouse <David.Woodhouse@intel.com> 8 */ 9 10 #ifndef _INTEL_IOMMU_H_ 11 #define _INTEL_IOMMU_H_ 12 13 #include <linux/types.h> 14 #include <linux/iova.h> 15 #include <linux/io.h> 16 #include <linux/idr.h> 17 #include <linux/mmu_notifier.h> 18 #include <linux/list.h> 19 #include <linux/iommu.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/dmar.h> 22 #include <linux/ioasid.h> 23 #include <linux/bitfield.h> 24 #include <linux/xarray.h> 25 #include <linux/perf_event.h> 26 27 #include <asm/cacheflush.h> 28 #include <asm/iommu.h> 29 30 /* 31 * VT-d hardware uses 4KiB page size regardless of host page size. 32 */ 33 #define VTD_PAGE_SHIFT (12) 34 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) 35 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) 36 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) 37 38 #define VTD_STRIDE_SHIFT (9) 39 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) 40 41 #define DMA_PTE_READ BIT_ULL(0) 42 #define DMA_PTE_WRITE BIT_ULL(1) 43 #define DMA_PTE_LARGE_PAGE BIT_ULL(7) 44 #define DMA_PTE_SNP BIT_ULL(11) 45 46 #define DMA_FL_PTE_PRESENT BIT_ULL(0) 47 #define DMA_FL_PTE_US BIT_ULL(2) 48 #define DMA_FL_PTE_ACCESS BIT_ULL(5) 49 #define DMA_FL_PTE_DIRTY BIT_ULL(6) 50 #define DMA_FL_PTE_XD BIT_ULL(63) 51 52 #define ADDR_WIDTH_5LEVEL (57) 53 #define ADDR_WIDTH_4LEVEL (48) 54 55 #define CONTEXT_TT_MULTI_LEVEL 0 56 #define CONTEXT_TT_DEV_IOTLB 1 57 #define CONTEXT_TT_PASS_THROUGH 2 58 #define CONTEXT_PASIDE BIT_ULL(3) 59 60 /* 61 * Intel IOMMU register specification per version 1.0 public spec. 62 */ 63 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ 64 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ 65 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ 66 #define DMAR_GCMD_REG 0x18 /* Global command register */ 67 #define DMAR_GSTS_REG 0x1c /* Global status register */ 68 #define DMAR_RTADDR_REG 0x20 /* Root entry table */ 69 #define DMAR_CCMD_REG 0x28 /* Context command reg */ 70 #define DMAR_FSTS_REG 0x34 /* Fault Status register */ 71 #define DMAR_FECTL_REG 0x38 /* Fault control register */ 72 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ 73 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ 74 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ 75 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ 76 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ 77 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ 78 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ 79 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ 80 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ 81 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ 82 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ 83 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ 84 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ 85 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ 86 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */ 87 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ 88 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ 89 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ 90 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ 91 #define DMAR_PRS_REG 0xdc /* Page request status register */ 92 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ 93 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ 94 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ 95 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ 96 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */ 97 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */ 98 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */ 99 #define DMAR_MTRR_FIX16K_80000_REG 0x128 100 #define DMAR_MTRR_FIX16K_A0000_REG 0x130 101 #define DMAR_MTRR_FIX4K_C0000_REG 0x138 102 #define DMAR_MTRR_FIX4K_C8000_REG 0x140 103 #define DMAR_MTRR_FIX4K_D0000_REG 0x148 104 #define DMAR_MTRR_FIX4K_D8000_REG 0x150 105 #define DMAR_MTRR_FIX4K_E0000_REG 0x158 106 #define DMAR_MTRR_FIX4K_E8000_REG 0x160 107 #define DMAR_MTRR_FIX4K_F0000_REG 0x168 108 #define DMAR_MTRR_FIX4K_F8000_REG 0x170 109 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */ 110 #define DMAR_MTRR_PHYSMASK0_REG 0x188 111 #define DMAR_MTRR_PHYSBASE1_REG 0x190 112 #define DMAR_MTRR_PHYSMASK1_REG 0x198 113 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0 114 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8 115 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0 116 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8 117 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0 118 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8 119 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0 120 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8 121 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0 122 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8 123 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0 124 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8 125 #define DMAR_MTRR_PHYSBASE8_REG 0x200 126 #define DMAR_MTRR_PHYSMASK8_REG 0x208 127 #define DMAR_MTRR_PHYSBASE9_REG 0x210 128 #define DMAR_MTRR_PHYSMASK9_REG 0x218 129 #define DMAR_PERFCAP_REG 0x300 130 #define DMAR_PERFCFGOFF_REG 0x310 131 #define DMAR_PERFOVFOFF_REG 0x318 132 #define DMAR_PERFCNTROFF_REG 0x31c 133 #define DMAR_PERFINTRSTS_REG 0x324 134 #define DMAR_PERFINTRCTL_REG 0x328 135 #define DMAR_PERFEVNTCAP_REG 0x380 136 #define DMAR_ECMD_REG 0x400 137 #define DMAR_ECEO_REG 0x408 138 #define DMAR_ECRSP_REG 0x410 139 #define DMAR_ECCAP_REG 0x430 140 #define DMAR_VCCAP_REG 0xe30 /* Virtual command capability register */ 141 #define DMAR_VCMD_REG 0xe00 /* Virtual command register */ 142 #define DMAR_VCRSP_REG 0xe10 /* Virtual command response register */ 143 144 #define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg) 145 #define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg) 146 #define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg) 147 148 #define OFFSET_STRIDE (9) 149 150 #define dmar_readq(a) readq(a) 151 #define dmar_writeq(a,v) writeq(v,a) 152 #define dmar_readl(a) readl(a) 153 #define dmar_writel(a, v) writel(v, a) 154 155 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) 156 #define DMAR_VER_MINOR(v) ((v) & 0x0f) 157 158 /* 159 * Decoding Capability Register 160 */ 161 #define cap_esrtps(c) (((c) >> 63) & 1) 162 #define cap_esirtps(c) (((c) >> 62) & 1) 163 #define cap_ecmds(c) (((c) >> 61) & 1) 164 #define cap_fl5lp_support(c) (((c) >> 60) & 1) 165 #define cap_pi_support(c) (((c) >> 59) & 1) 166 #define cap_fl1gp_support(c) (((c) >> 56) & 1) 167 #define cap_read_drain(c) (((c) >> 55) & 1) 168 #define cap_write_drain(c) (((c) >> 54) & 1) 169 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) 170 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) 171 #define cap_pgsel_inv(c) (((c) >> 39) & 1) 172 173 #define cap_super_page_val(c) (((c) >> 34) & 0xf) 174 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ 175 * OFFSET_STRIDE) + 21) 176 177 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) 178 #define cap_max_fault_reg_offset(c) \ 179 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) 180 181 #define cap_zlr(c) (((c) >> 22) & 1) 182 #define cap_isoch(c) (((c) >> 23) & 1) 183 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) 184 #define cap_sagaw(c) (((c) >> 8) & 0x1f) 185 #define cap_caching_mode(c) (((c) >> 7) & 1) 186 #define cap_phmr(c) (((c) >> 6) & 1) 187 #define cap_plmr(c) (((c) >> 5) & 1) 188 #define cap_rwbf(c) (((c) >> 4) & 1) 189 #define cap_afl(c) (((c) >> 3) & 1) 190 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) 191 /* 192 * Extended Capability Register 193 */ 194 195 #define ecap_pms(e) (((e) >> 51) & 0x1) 196 #define ecap_rps(e) (((e) >> 49) & 0x1) 197 #define ecap_smpwc(e) (((e) >> 48) & 0x1) 198 #define ecap_flts(e) (((e) >> 47) & 0x1) 199 #define ecap_slts(e) (((e) >> 46) & 0x1) 200 #define ecap_slads(e) (((e) >> 45) & 0x1) 201 #define ecap_vcs(e) (((e) >> 44) & 0x1) 202 #define ecap_smts(e) (((e) >> 43) & 0x1) 203 #define ecap_dit(e) (((e) >> 41) & 0x1) 204 #define ecap_pds(e) (((e) >> 42) & 0x1) 205 #define ecap_pasid(e) (((e) >> 40) & 0x1) 206 #define ecap_pss(e) (((e) >> 35) & 0x1f) 207 #define ecap_eafs(e) (((e) >> 34) & 0x1) 208 #define ecap_nwfs(e) (((e) >> 33) & 0x1) 209 #define ecap_srs(e) (((e) >> 31) & 0x1) 210 #define ecap_ers(e) (((e) >> 30) & 0x1) 211 #define ecap_prs(e) (((e) >> 29) & 0x1) 212 #define ecap_broken_pasid(e) (((e) >> 28) & 0x1) 213 #define ecap_dis(e) (((e) >> 27) & 0x1) 214 #define ecap_nest(e) (((e) >> 26) & 0x1) 215 #define ecap_mts(e) (((e) >> 25) & 0x1) 216 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) 217 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) 218 #define ecap_coherent(e) ((e) & 0x1) 219 #define ecap_qis(e) ((e) & 0x2) 220 #define ecap_pass_through(e) (((e) >> 6) & 0x1) 221 #define ecap_eim_support(e) (((e) >> 4) & 0x1) 222 #define ecap_ir_support(e) (((e) >> 3) & 0x1) 223 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) 224 #define ecap_max_handle_mask(e) (((e) >> 20) & 0xf) 225 #define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */ 226 227 /* 228 * Decoding Perf Capability Register 229 */ 230 #define pcap_num_cntr(p) ((p) & 0xffff) 231 #define pcap_cntr_width(p) (((p) >> 16) & 0x7f) 232 #define pcap_num_event_group(p) (((p) >> 24) & 0x1f) 233 #define pcap_filters_mask(p) (((p) >> 32) & 0x1f) 234 #define pcap_interrupt(p) (((p) >> 50) & 0x1) 235 /* The counter stride is calculated as 2 ^ (x+10) bytes */ 236 #define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10)) 237 238 /* 239 * Decoding Perf Event Capability Register 240 */ 241 #define pecap_es(p) ((p) & 0xfffffff) 242 243 /* Virtual command interface capability */ 244 #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */ 245 246 /* IOTLB_REG */ 247 #define DMA_TLB_FLUSH_GRANU_OFFSET 60 248 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) 249 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) 250 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) 251 #define DMA_TLB_IIRG(type) ((type >> 60) & 3) 252 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) 253 #define DMA_TLB_READ_DRAIN (((u64)1) << 49) 254 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) 255 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) 256 #define DMA_TLB_IVT (((u64)1) << 63) 257 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) 258 #define DMA_TLB_MAX_SIZE (0x3f) 259 260 /* INVALID_DESC */ 261 #define DMA_CCMD_INVL_GRANU_OFFSET 61 262 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) 263 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) 264 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) 265 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) 266 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) 267 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) 268 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) 269 #define DMA_ID_TLB_ADDR(addr) (addr) 270 #define DMA_ID_TLB_ADDR_MASK(mask) (mask) 271 272 /* PMEN_REG */ 273 #define DMA_PMEN_EPM (((u32)1)<<31) 274 #define DMA_PMEN_PRS (((u32)1)<<0) 275 276 /* GCMD_REG */ 277 #define DMA_GCMD_TE (((u32)1) << 31) 278 #define DMA_GCMD_SRTP (((u32)1) << 30) 279 #define DMA_GCMD_SFL (((u32)1) << 29) 280 #define DMA_GCMD_EAFL (((u32)1) << 28) 281 #define DMA_GCMD_WBF (((u32)1) << 27) 282 #define DMA_GCMD_QIE (((u32)1) << 26) 283 #define DMA_GCMD_SIRTP (((u32)1) << 24) 284 #define DMA_GCMD_IRE (((u32) 1) << 25) 285 #define DMA_GCMD_CFI (((u32) 1) << 23) 286 287 /* GSTS_REG */ 288 #define DMA_GSTS_TES (((u32)1) << 31) 289 #define DMA_GSTS_RTPS (((u32)1) << 30) 290 #define DMA_GSTS_FLS (((u32)1) << 29) 291 #define DMA_GSTS_AFLS (((u32)1) << 28) 292 #define DMA_GSTS_WBFS (((u32)1) << 27) 293 #define DMA_GSTS_QIES (((u32)1) << 26) 294 #define DMA_GSTS_IRTPS (((u32)1) << 24) 295 #define DMA_GSTS_IRES (((u32)1) << 25) 296 #define DMA_GSTS_CFIS (((u32)1) << 23) 297 298 /* DMA_RTADDR_REG */ 299 #define DMA_RTADDR_SMT (((u64)1) << 10) 300 301 /* CCMD_REG */ 302 #define DMA_CCMD_ICC (((u64)1) << 63) 303 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) 304 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) 305 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) 306 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) 307 #define DMA_CCMD_MASK_NOBIT 0 308 #define DMA_CCMD_MASK_1BIT 1 309 #define DMA_CCMD_MASK_2BIT 2 310 #define DMA_CCMD_MASK_3BIT 3 311 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) 312 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) 313 314 /* ECMD_REG */ 315 #define DMA_MAX_NUM_ECMD 256 316 #define DMA_MAX_NUM_ECMDCAP (DMA_MAX_NUM_ECMD / 64) 317 #define DMA_ECMD_REG_STEP 8 318 #define DMA_ECMD_ENABLE 0xf0 319 #define DMA_ECMD_DISABLE 0xf1 320 #define DMA_ECMD_FREEZE 0xf4 321 #define DMA_ECMD_UNFREEZE 0xf5 322 #define DMA_ECMD_OA_SHIFT 16 323 #define DMA_ECMD_ECRSP_IP 0x1 324 #define DMA_ECMD_ECCAP3 3 325 #define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48) 326 #define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49) 327 #define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52) 328 #define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53) 329 #define DMA_ECMD_ECCAP3_ESSENTIAL (DMA_ECMD_ECCAP3_ECNTS | \ 330 DMA_ECMD_ECCAP3_DCNTS | \ 331 DMA_ECMD_ECCAP3_FCNTS | \ 332 DMA_ECMD_ECCAP3_UFCNTS) 333 334 /* FECTL_REG */ 335 #define DMA_FECTL_IM (((u32)1) << 31) 336 337 /* FSTS_REG */ 338 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ 339 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ 340 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ 341 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ 342 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ 343 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ 344 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) 345 346 /* FRCD_REG, 32 bits access */ 347 #define DMA_FRCD_F (((u32)1) << 31) 348 #define dma_frcd_type(d) ((d >> 30) & 1) 349 #define dma_frcd_fault_reason(c) (c & 0xff) 350 #define dma_frcd_source_id(c) (c & 0xffff) 351 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff) 352 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1) 353 /* low 64 bit */ 354 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) 355 356 /* PRS_REG */ 357 #define DMA_PRS_PPR ((u32)1) 358 #define DMA_PRS_PRO ((u32)2) 359 360 #define DMA_VCS_PAS ((u64)1) 361 362 /* PERFINTRSTS_REG */ 363 #define DMA_PERFINTRSTS_PIS ((u32)1) 364 365 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ 366 do { \ 367 cycles_t start_time = get_cycles(); \ 368 while (1) { \ 369 sts = op(iommu->reg + offset); \ 370 if (cond) \ 371 break; \ 372 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ 373 panic("DMAR hardware is malfunctioning\n"); \ 374 cpu_relax(); \ 375 } \ 376 } while (0) 377 378 #define QI_LENGTH 256 /* queue length */ 379 380 enum { 381 QI_FREE, 382 QI_IN_USE, 383 QI_DONE, 384 QI_ABORT 385 }; 386 387 #define QI_CC_TYPE 0x1 388 #define QI_IOTLB_TYPE 0x2 389 #define QI_DIOTLB_TYPE 0x3 390 #define QI_IEC_TYPE 0x4 391 #define QI_IWD_TYPE 0x5 392 #define QI_EIOTLB_TYPE 0x6 393 #define QI_PC_TYPE 0x7 394 #define QI_DEIOTLB_TYPE 0x8 395 #define QI_PGRP_RESP_TYPE 0x9 396 #define QI_PSTRM_RESP_TYPE 0xa 397 398 #define QI_IEC_SELECTIVE (((u64)1) << 4) 399 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) 400 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) 401 402 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) 403 #define QI_IWD_STATUS_WRITE (((u64)1) << 5) 404 #define QI_IWD_FENCE (((u64)1) << 6) 405 #define QI_IWD_PRQ_DRAIN (((u64)1) << 7) 406 407 #define QI_IOTLB_DID(did) (((u64)did) << 16) 408 #define QI_IOTLB_DR(dr) (((u64)dr) << 7) 409 #define QI_IOTLB_DW(dw) (((u64)dw) << 6) 410 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) 411 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) 412 #define QI_IOTLB_IH(ih) (((u64)ih) << 6) 413 #define QI_IOTLB_AM(am) (((u8)am) & 0x3f) 414 415 #define QI_CC_FM(fm) (((u64)fm) << 48) 416 #define QI_CC_SID(sid) (((u64)sid) << 32) 417 #define QI_CC_DID(did) (((u64)did) << 16) 418 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) 419 420 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) 421 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) 422 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 423 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 424 ((u64)((pfsid >> 4) & 0xfff) << 52)) 425 #define QI_DEV_IOTLB_SIZE 1 426 #define QI_DEV_IOTLB_MAX_INVS 32 427 428 #define QI_PC_PASID(pasid) (((u64)pasid) << 32) 429 #define QI_PC_DID(did) (((u64)did) << 16) 430 #define QI_PC_GRAN(gran) (((u64)gran) << 4) 431 432 /* PASID cache invalidation granu */ 433 #define QI_PC_ALL_PASIDS 0 434 #define QI_PC_PASID_SEL 1 435 #define QI_PC_GLOBAL 3 436 437 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 438 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) 439 #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) 440 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) 441 #define QI_EIOTLB_DID(did) (((u64)did) << 16) 442 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) 443 444 /* QI Dev-IOTLB inv granu */ 445 #define QI_DEV_IOTLB_GRAN_ALL 1 446 #define QI_DEV_IOTLB_GRAN_PASID_SEL 0 447 448 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) 449 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) 450 #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) 451 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) 452 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) 453 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 454 ((u64)((pfsid >> 4) & 0xfff) << 52)) 455 #define QI_DEV_EIOTLB_MAX_INVS 32 456 457 /* Page group response descriptor QW0 */ 458 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) 459 #define QI_PGRP_PDP(p) (((u64)(p)) << 5) 460 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) 461 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) 462 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) 463 464 /* Page group response descriptor QW1 */ 465 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2) 466 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3) 467 468 469 #define QI_RESP_SUCCESS 0x0 470 #define QI_RESP_INVALID 0x1 471 #define QI_RESP_FAILURE 0xf 472 473 #define QI_GRAN_NONG_PASID 2 474 #define QI_GRAN_PSI_PASID 3 475 476 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap)) 477 478 struct qi_desc { 479 u64 qw0; 480 u64 qw1; 481 u64 qw2; 482 u64 qw3; 483 }; 484 485 struct q_inval { 486 raw_spinlock_t q_lock; 487 void *desc; /* invalidation queue */ 488 int *desc_status; /* desc status */ 489 int free_head; /* first free entry */ 490 int free_tail; /* last free entry */ 491 int free_cnt; 492 }; 493 494 /* Page Request Queue depth */ 495 #define PRQ_ORDER 4 496 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) 497 #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) 498 499 struct dmar_pci_notify_info; 500 501 #ifdef CONFIG_IRQ_REMAP 502 /* 1MB - maximum possible interrupt remapping table size */ 503 #define INTR_REMAP_PAGE_ORDER 8 504 #define INTR_REMAP_TABLE_REG_SIZE 0xf 505 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf 506 507 #define INTR_REMAP_TABLE_ENTRIES 65536 508 509 struct irq_domain; 510 511 struct ir_table { 512 struct irte *base; 513 unsigned long *bitmap; 514 }; 515 516 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info); 517 #else 518 static inline void 519 intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { } 520 #endif 521 522 struct iommu_flush { 523 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, 524 u8 fm, u64 type); 525 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, 526 unsigned int size_order, u64 type); 527 }; 528 529 enum { 530 SR_DMAR_FECTL_REG, 531 SR_DMAR_FEDATA_REG, 532 SR_DMAR_FEADDR_REG, 533 SR_DMAR_FEUADDR_REG, 534 MAX_SR_DMAR_REGS 535 }; 536 537 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) 538 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) 539 #define VTD_FLAG_SVM_CAPABLE (1 << 2) 540 541 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) 542 #define pasid_supported(iommu) (sm_supported(iommu) && \ 543 ecap_pasid((iommu)->ecap)) 544 545 struct pasid_entry; 546 struct pasid_state_entry; 547 struct page_req_dsc; 548 549 /* 550 * 0: Present 551 * 1-11: Reserved 552 * 12-63: Context Ptr (12 - (haw-1)) 553 * 64-127: Reserved 554 */ 555 struct root_entry { 556 u64 lo; 557 u64 hi; 558 }; 559 560 /* 561 * low 64 bits: 562 * 0: present 563 * 1: fault processing disable 564 * 2-3: translation type 565 * 12-63: address space root 566 * high 64 bits: 567 * 0-2: address width 568 * 3-6: aval 569 * 8-23: domain id 570 */ 571 struct context_entry { 572 u64 lo; 573 u64 hi; 574 }; 575 576 struct iommu_domain_info { 577 struct intel_iommu *iommu; 578 unsigned int refcnt; /* Refcount of devices per iommu */ 579 u16 did; /* Domain ids per IOMMU. Use u16 since 580 * domain ids are 16 bit wide according 581 * to VT-d spec, section 9.3 */ 582 }; 583 584 struct dmar_domain { 585 int nid; /* node id */ 586 struct xarray iommu_array; /* Attached IOMMU array */ 587 588 u8 has_iotlb_device: 1; 589 u8 iommu_coherency: 1; /* indicate coherency of iommu access */ 590 u8 force_snooping : 1; /* Create IOPTEs with snoop control */ 591 u8 set_pte_snp:1; 592 u8 use_first_level:1; /* DMA translation for the domain goes 593 * through the first level page table, 594 * otherwise, goes through the second 595 * level. 596 */ 597 598 spinlock_t lock; /* Protect device tracking lists */ 599 struct list_head devices; /* all devices' list */ 600 601 struct dma_pte *pgd; /* virtual address */ 602 int gaw; /* max guest address width */ 603 604 /* adjusted guest address width, 0 is level 2 30-bit */ 605 int agaw; 606 int iommu_superpage;/* Level of superpages supported: 607 0 == 4KiB (no superpages), 1 == 2MiB, 608 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ 609 u64 max_addr; /* maximum mapped address */ 610 611 struct iommu_domain domain; /* generic domain data structure for 612 iommu core */ 613 }; 614 615 /* 616 * In theory, the VT-d 4.0 spec can support up to 2 ^ 16 counters. 617 * But in practice, there are only 14 counters for the existing 618 * platform. Setting the max number of counters to 64 should be good 619 * enough for a long time. Also, supporting more than 64 counters 620 * requires more extras, e.g., extra freeze and overflow registers, 621 * which is not necessary for now. 622 */ 623 #define IOMMU_PMU_IDX_MAX 64 624 625 struct iommu_pmu { 626 struct intel_iommu *iommu; 627 u32 num_cntr; /* Number of counters */ 628 u32 num_eg; /* Number of event group */ 629 u32 cntr_width; /* Counter width */ 630 u32 cntr_stride; /* Counter Stride */ 631 u32 filter; /* Bitmask of filter support */ 632 void __iomem *base; /* the PerfMon base address */ 633 void __iomem *cfg_reg; /* counter configuration base address */ 634 void __iomem *cntr_reg; /* counter 0 address*/ 635 void __iomem *overflow; /* overflow status register */ 636 637 u64 *evcap; /* Indicates all supported events */ 638 u32 **cntr_evcap; /* Supported events of each counter. */ 639 640 struct pmu pmu; 641 DECLARE_BITMAP(used_mask, IOMMU_PMU_IDX_MAX); 642 struct perf_event *event_list[IOMMU_PMU_IDX_MAX]; 643 unsigned char irq_name[16]; 644 }; 645 646 #define IOMMU_IRQ_ID_OFFSET_PRQ (DMAR_UNITS_SUPPORTED) 647 #define IOMMU_IRQ_ID_OFFSET_PERF (2 * DMAR_UNITS_SUPPORTED) 648 649 struct intel_iommu { 650 void __iomem *reg; /* Pointer to hardware regs, virtual addr */ 651 u64 reg_phys; /* physical address of hw register set */ 652 u64 reg_size; /* size of hw register set */ 653 u64 cap; 654 u64 ecap; 655 u64 vccap; 656 u64 ecmdcap[DMA_MAX_NUM_ECMDCAP]; 657 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ 658 raw_spinlock_t register_lock; /* protect register handling */ 659 int seq_id; /* sequence id of the iommu */ 660 int agaw; /* agaw of this iommu */ 661 int msagaw; /* max sagaw of this iommu */ 662 unsigned int irq, pr_irq, perf_irq; 663 u16 segment; /* PCI segment# */ 664 unsigned char name[13]; /* Device Name */ 665 666 #ifdef CONFIG_INTEL_IOMMU 667 unsigned long *domain_ids; /* bitmap of domains */ 668 unsigned long *copied_tables; /* bitmap of copied tables */ 669 spinlock_t lock; /* protect context, domain ids */ 670 struct root_entry *root_entry; /* virtual address */ 671 672 struct iommu_flush flush; 673 #endif 674 #ifdef CONFIG_INTEL_IOMMU_SVM 675 struct page_req_dsc *prq; 676 unsigned char prq_name[16]; /* Name for PRQ interrupt */ 677 unsigned long prq_seq_number; 678 struct completion prq_complete; 679 struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */ 680 #endif 681 struct iopf_queue *iopf_queue; 682 unsigned char iopfq_name[16]; 683 struct q_inval *qi; /* Queued invalidation info */ 684 u32 *iommu_state; /* Store iommu states between suspend and resume.*/ 685 686 #ifdef CONFIG_IRQ_REMAP 687 struct ir_table *ir_table; /* Interrupt remapping info */ 688 struct irq_domain *ir_domain; 689 #endif 690 struct iommu_device iommu; /* IOMMU core code handle */ 691 int node; 692 u32 flags; /* Software defined flags */ 693 694 struct dmar_drhd_unit *drhd; 695 void *perf_statistic; 696 697 struct iommu_pmu *pmu; 698 }; 699 700 /* PCI domain-device relationship */ 701 struct device_domain_info { 702 struct list_head link; /* link to domain siblings */ 703 u32 segment; /* PCI segment number */ 704 u8 bus; /* PCI bus number */ 705 u8 devfn; /* PCI devfn number */ 706 u16 pfsid; /* SRIOV physical function source ID */ 707 u8 pasid_supported:3; 708 u8 pasid_enabled:1; 709 u8 pri_supported:1; 710 u8 pri_enabled:1; 711 u8 ats_supported:1; 712 u8 ats_enabled:1; 713 u8 dtlb_extra_inval:1; /* Quirk for devices need extra flush */ 714 u8 ats_qdep; 715 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ 716 struct intel_iommu *iommu; /* IOMMU used by this device */ 717 struct dmar_domain *domain; /* pointer to domain */ 718 struct pasid_table *pasid_table; /* pasid table */ 719 }; 720 721 static inline void __iommu_flush_cache( 722 struct intel_iommu *iommu, void *addr, int size) 723 { 724 if (!ecap_coherent(iommu->ecap)) 725 clflush_cache_range(addr, size); 726 } 727 728 /* Convert generic struct iommu_domain to private struct dmar_domain */ 729 static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) 730 { 731 return container_of(dom, struct dmar_domain, domain); 732 } 733 734 /* Retrieve the domain ID which has allocated to the domain */ 735 static inline u16 736 domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) 737 { 738 struct iommu_domain_info *info = 739 xa_load(&domain->iommu_array, iommu->seq_id); 740 741 return info->did; 742 } 743 744 /* 745 * 0: readable 746 * 1: writable 747 * 2-6: reserved 748 * 7: super page 749 * 8-10: available 750 * 11: snoop behavior 751 * 12-63: Host physical address 752 */ 753 struct dma_pte { 754 u64 val; 755 }; 756 757 static inline void dma_clear_pte(struct dma_pte *pte) 758 { 759 pte->val = 0; 760 } 761 762 static inline u64 dma_pte_addr(struct dma_pte *pte) 763 { 764 #ifdef CONFIG_64BIT 765 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); 766 #else 767 /* Must have a full atomic 64-bit read */ 768 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & 769 VTD_PAGE_MASK & (~DMA_FL_PTE_XD); 770 #endif 771 } 772 773 static inline bool dma_pte_present(struct dma_pte *pte) 774 { 775 return (pte->val & 3) != 0; 776 } 777 778 static inline bool dma_pte_superpage(struct dma_pte *pte) 779 { 780 return (pte->val & DMA_PTE_LARGE_PAGE); 781 } 782 783 static inline bool first_pte_in_page(struct dma_pte *pte) 784 { 785 return IS_ALIGNED((unsigned long)pte, VTD_PAGE_SIZE); 786 } 787 788 static inline int nr_pte_to_next_page(struct dma_pte *pte) 789 { 790 return first_pte_in_page(pte) ? BIT_ULL(VTD_STRIDE_SHIFT) : 791 (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte; 792 } 793 794 static inline bool context_present(struct context_entry *context) 795 { 796 return (context->lo & 1); 797 } 798 799 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); 800 801 extern int dmar_enable_qi(struct intel_iommu *iommu); 802 extern void dmar_disable_qi(struct intel_iommu *iommu); 803 extern int dmar_reenable_qi(struct intel_iommu *iommu); 804 extern void qi_global_iec(struct intel_iommu *iommu); 805 806 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, 807 u8 fm, u64 type); 808 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, 809 unsigned int size_order, u64 type); 810 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, 811 u16 qdep, u64 addr, unsigned mask); 812 813 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 814 unsigned long npages, bool ih); 815 816 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, 817 u32 pasid, u16 qdep, u64 addr, 818 unsigned int size_order); 819 void quirk_extra_dev_tlb_flush(struct device_domain_info *info, 820 unsigned long address, unsigned long pages, 821 u32 pasid, u16 qdep); 822 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, 823 u32 pasid); 824 825 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, 826 unsigned int count, unsigned long options); 827 /* 828 * Options used in qi_submit_sync: 829 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8. 830 */ 831 #define QI_OPT_WAIT_DRAIN BIT(0) 832 833 extern int dmar_ir_support(void); 834 835 void *alloc_pgtable_page(int node, gfp_t gfp); 836 void free_pgtable_page(void *vaddr); 837 void iommu_flush_write_buffer(struct intel_iommu *iommu); 838 struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn); 839 840 #ifdef CONFIG_INTEL_IOMMU_SVM 841 extern void intel_svm_check(struct intel_iommu *iommu); 842 extern int intel_svm_enable_prq(struct intel_iommu *iommu); 843 extern int intel_svm_finish_prq(struct intel_iommu *iommu); 844 int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt, 845 struct iommu_page_response *msg); 846 struct iommu_domain *intel_svm_domain_alloc(void); 847 void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid); 848 849 struct intel_svm_dev { 850 struct list_head list; 851 struct rcu_head rcu; 852 struct device *dev; 853 struct intel_iommu *iommu; 854 u16 did; 855 u16 sid, qdep; 856 }; 857 858 struct intel_svm { 859 struct mmu_notifier notifier; 860 struct mm_struct *mm; 861 u32 pasid; 862 struct list_head devs; 863 }; 864 #else 865 static inline void intel_svm_check(struct intel_iommu *iommu) {} 866 static inline struct iommu_domain *intel_svm_domain_alloc(void) 867 { 868 return NULL; 869 } 870 871 static inline void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid) 872 { 873 } 874 #endif 875 876 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS 877 void intel_iommu_debugfs_init(void); 878 #else 879 static inline void intel_iommu_debugfs_init(void) {} 880 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */ 881 882 extern const struct attribute_group *intel_iommu_groups[]; 883 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, 884 u8 devfn, int alloc); 885 886 extern const struct iommu_ops intel_iommu_ops; 887 888 #ifdef CONFIG_INTEL_IOMMU 889 extern int intel_iommu_sm; 890 extern int iommu_calculate_agaw(struct intel_iommu *iommu); 891 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu); 892 int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob); 893 894 static inline bool ecmd_has_pmu_essential(struct intel_iommu *iommu) 895 { 896 return (iommu->ecmdcap[DMA_ECMD_ECCAP3] & DMA_ECMD_ECCAP3_ESSENTIAL) == 897 DMA_ECMD_ECCAP3_ESSENTIAL; 898 } 899 900 extern int dmar_disabled; 901 extern int intel_iommu_enabled; 902 #else 903 static inline int iommu_calculate_agaw(struct intel_iommu *iommu) 904 { 905 return 0; 906 } 907 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) 908 { 909 return 0; 910 } 911 #define dmar_disabled (1) 912 #define intel_iommu_enabled (0) 913 #define intel_iommu_sm (0) 914 #endif 915 916 static inline const char *decode_prq_descriptor(char *str, size_t size, 917 u64 dw0, u64 dw1, u64 dw2, u64 dw3) 918 { 919 char *buf = str; 920 int bytes; 921 922 bytes = snprintf(buf, size, 923 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx", 924 FIELD_GET(GENMASK_ULL(31, 16), dw0), 925 FIELD_GET(GENMASK_ULL(63, 12), dw1), 926 dw1 & BIT_ULL(0) ? 'r' : '-', 927 dw1 & BIT_ULL(1) ? 'w' : '-', 928 dw0 & BIT_ULL(52) ? 'x' : '-', 929 dw0 & BIT_ULL(53) ? 'p' : '-', 930 dw1 & BIT_ULL(2) ? 'l' : '-', 931 FIELD_GET(GENMASK_ULL(51, 32), dw0), 932 FIELD_GET(GENMASK_ULL(11, 3), dw1)); 933 934 /* Private Data */ 935 if (dw0 & BIT_ULL(9)) { 936 size -= bytes; 937 buf += bytes; 938 snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3); 939 } 940 941 return str; 942 } 943 944 #endif 945