1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 16 #ifdef CONFIG_RTW89_DEBUGMSG 17 unsigned int rtw89_debug_mask; 18 EXPORT_SYMBOL(rtw89_debug_mask); 19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 20 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 21 #endif 22 23 #ifdef CONFIG_RTW89_DEBUGFS 24 struct rtw89_debugfs_priv { 25 struct rtw89_dev *rtwdev; 26 int (*cb_read)(struct seq_file *m, void *v); 27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 28 size_t count, loff_t *loff); 29 union { 30 u32 cb_data; 31 struct { 32 u32 addr; 33 u32 len; 34 } read_reg; 35 struct { 36 u32 addr; 37 u32 mask; 38 u8 path; 39 } read_rf; 40 struct { 41 u8 ss_dbg:1; 42 u8 dle_dbg:1; 43 u8 dmac_dbg:1; 44 u8 cmac_dbg:1; 45 u8 dbg_port:1; 46 } dbgpkg_en; 47 struct { 48 u32 start; 49 u32 len; 50 u8 sel; 51 } mac_mem; 52 }; 53 }; 54 55 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 56 [RATE_INFO_BW_20] = 20, 57 [RATE_INFO_BW_40] = 40, 58 [RATE_INFO_BW_80] = 80, 59 [RATE_INFO_BW_160] = 160, 60 [RATE_INFO_BW_320] = 320, 61 }; 62 63 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 64 { 65 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 66 return rtw89_rate_info_bw_to_mhz_map[bw]; 67 68 return 0; 69 } 70 71 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 72 { 73 struct rtw89_debugfs_priv *debugfs_priv = m->private; 74 75 return debugfs_priv->cb_read(m, v); 76 } 77 78 static ssize_t rtw89_debugfs_single_write(struct file *filp, 79 const char __user *buffer, 80 size_t count, loff_t *loff) 81 { 82 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 83 84 return debugfs_priv->cb_write(filp, buffer, count, loff); 85 } 86 87 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 88 const char __user *buffer, 89 size_t count, loff_t *loff) 90 { 91 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 92 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 93 94 return debugfs_priv->cb_write(filp, buffer, count, loff); 95 } 96 97 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 98 { 99 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 100 } 101 102 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 103 { 104 return 0; 105 } 106 107 static const struct file_operations file_ops_single_r = { 108 .owner = THIS_MODULE, 109 .open = rtw89_debugfs_single_open, 110 .read = seq_read, 111 .llseek = seq_lseek, 112 .release = single_release, 113 }; 114 115 static const struct file_operations file_ops_common_rw = { 116 .owner = THIS_MODULE, 117 .open = rtw89_debugfs_single_open, 118 .release = single_release, 119 .read = seq_read, 120 .llseek = seq_lseek, 121 .write = rtw89_debugfs_seq_file_write, 122 }; 123 124 static const struct file_operations file_ops_single_w = { 125 .owner = THIS_MODULE, 126 .write = rtw89_debugfs_single_write, 127 .open = simple_open, 128 .release = rtw89_debugfs_close, 129 }; 130 131 static ssize_t 132 rtw89_debug_priv_read_reg_select(struct file *filp, 133 const char __user *user_buf, 134 size_t count, loff_t *loff) 135 { 136 struct seq_file *m = (struct seq_file *)filp->private_data; 137 struct rtw89_debugfs_priv *debugfs_priv = m->private; 138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 139 char buf[32]; 140 size_t buf_size; 141 u32 addr, len; 142 int num; 143 144 buf_size = min(count, sizeof(buf) - 1); 145 if (copy_from_user(buf, user_buf, buf_size)) 146 return -EFAULT; 147 148 buf[buf_size] = '\0'; 149 num = sscanf(buf, "%x %x", &addr, &len); 150 if (num != 2) { 151 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 152 return -EINVAL; 153 } 154 155 debugfs_priv->read_reg.addr = addr; 156 debugfs_priv->read_reg.len = len; 157 158 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 159 160 return count; 161 } 162 163 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 164 { 165 struct rtw89_debugfs_priv *debugfs_priv = m->private; 166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 167 u32 addr, end, data, k; 168 u32 len; 169 170 len = debugfs_priv->read_reg.len; 171 addr = debugfs_priv->read_reg.addr; 172 173 if (len > 4) 174 goto ndata; 175 176 switch (len) { 177 case 1: 178 data = rtw89_read8(rtwdev, addr); 179 break; 180 case 2: 181 data = rtw89_read16(rtwdev, addr); 182 break; 183 case 4: 184 data = rtw89_read32(rtwdev, addr); 185 break; 186 default: 187 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 188 return -EINVAL; 189 } 190 191 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 192 193 return 0; 194 195 ndata: 196 end = addr + len; 197 198 for (; addr < end; addr += 16) { 199 seq_printf(m, "%08xh : ", 0x18600000 + addr); 200 for (k = 0; k < 16; k += 4) { 201 data = rtw89_read32(rtwdev, addr + k); 202 seq_printf(m, "%08x ", data); 203 } 204 seq_puts(m, "\n"); 205 } 206 207 return 0; 208 } 209 210 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 211 const char __user *user_buf, 212 size_t count, loff_t *loff) 213 { 214 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 215 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 216 char buf[32]; 217 size_t buf_size; 218 u32 addr, val, len; 219 int num; 220 221 buf_size = min(count, sizeof(buf) - 1); 222 if (copy_from_user(buf, user_buf, buf_size)) 223 return -EFAULT; 224 225 buf[buf_size] = '\0'; 226 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 227 if (num != 3) { 228 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 229 return -EINVAL; 230 } 231 232 switch (len) { 233 case 1: 234 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 235 rtw89_write8(rtwdev, addr, (u8)val); 236 break; 237 case 2: 238 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 239 rtw89_write16(rtwdev, addr, (u16)val); 240 break; 241 case 4: 242 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 243 rtw89_write32(rtwdev, addr, (u32)val); 244 break; 245 default: 246 rtw89_info(rtwdev, "invalid read write len %d\n", len); 247 break; 248 } 249 250 return count; 251 } 252 253 static ssize_t 254 rtw89_debug_priv_read_rf_select(struct file *filp, 255 const char __user *user_buf, 256 size_t count, loff_t *loff) 257 { 258 struct seq_file *m = (struct seq_file *)filp->private_data; 259 struct rtw89_debugfs_priv *debugfs_priv = m->private; 260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 261 char buf[32]; 262 size_t buf_size; 263 u32 addr, mask; 264 u8 path; 265 int num; 266 267 buf_size = min(count, sizeof(buf) - 1); 268 if (copy_from_user(buf, user_buf, buf_size)) 269 return -EFAULT; 270 271 buf[buf_size] = '\0'; 272 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 273 if (num != 3) { 274 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 275 return -EINVAL; 276 } 277 278 if (path >= rtwdev->chip->rf_path_num) { 279 rtw89_info(rtwdev, "wrong rf path\n"); 280 return -EINVAL; 281 } 282 debugfs_priv->read_rf.addr = addr; 283 debugfs_priv->read_rf.mask = mask; 284 debugfs_priv->read_rf.path = path; 285 286 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 287 288 return count; 289 } 290 291 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 292 { 293 struct rtw89_debugfs_priv *debugfs_priv = m->private; 294 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 295 u32 addr, data, mask; 296 u8 path; 297 298 addr = debugfs_priv->read_rf.addr; 299 mask = debugfs_priv->read_rf.mask; 300 path = debugfs_priv->read_rf.path; 301 302 data = rtw89_read_rf(rtwdev, path, addr, mask); 303 304 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 305 306 return 0; 307 } 308 309 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 310 const char __user *user_buf, 311 size_t count, loff_t *loff) 312 { 313 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 314 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 315 char buf[32]; 316 size_t buf_size; 317 u32 addr, val, mask; 318 u8 path; 319 int num; 320 321 buf_size = min(count, sizeof(buf) - 1); 322 if (copy_from_user(buf, user_buf, buf_size)) 323 return -EFAULT; 324 325 buf[buf_size] = '\0'; 326 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 327 if (num != 4) { 328 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 329 return -EINVAL; 330 } 331 332 if (path >= rtwdev->chip->rf_path_num) { 333 rtw89_info(rtwdev, "wrong rf path\n"); 334 return -EINVAL; 335 } 336 337 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 338 path, addr, val, mask); 339 rtw89_write_rf(rtwdev, path, addr, mask, val); 340 341 return count; 342 } 343 344 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 345 { 346 struct rtw89_debugfs_priv *debugfs_priv = m->private; 347 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 348 const struct rtw89_chip_info *chip = rtwdev->chip; 349 u32 addr, offset, data; 350 u8 path; 351 352 for (path = 0; path < chip->rf_path_num; path++) { 353 seq_printf(m, "RF path %d:\n\n", path); 354 for (addr = 0; addr < 0x100; addr += 4) { 355 seq_printf(m, "0x%08x: ", addr); 356 for (offset = 0; offset < 4; offset++) { 357 data = rtw89_read_rf(rtwdev, path, 358 addr + offset, RFREG_MASK); 359 seq_printf(m, "0x%05x ", data); 360 } 361 seq_puts(m, "\n"); 362 } 363 seq_puts(m, "\n"); 364 } 365 366 return 0; 367 } 368 369 struct txpwr_ent { 370 const char *txt; 371 u8 len; 372 }; 373 374 struct txpwr_map { 375 const struct txpwr_ent *ent; 376 u8 size; 377 u32 addr_from; 378 u32 addr_to; 379 u32 addr_to_1ss; 380 }; 381 382 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 383 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 384 385 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 386 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 387 388 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 389 { .len = 8, .txt = _t "\t- " \ 390 _e0 " " _e1 " " _e2 " " _e3 " " \ 391 _e4 " " _e5 " " _e6 " " _e7 } 392 393 static const struct txpwr_ent __txpwr_ent_byr[] = { 394 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 395 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 396 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 397 /* 1NSS */ 398 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 399 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 400 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 401 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 402 /* 2NSS */ 403 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 404 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 405 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 406 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 407 }; 408 409 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 410 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 411 412 static const struct txpwr_map __txpwr_map_byr = { 413 .ent = __txpwr_ent_byr, 414 .size = ARRAY_SIZE(__txpwr_ent_byr), 415 .addr_from = R_AX_PWR_BY_RATE, 416 .addr_to = R_AX_PWR_BY_RATE_MAX, 417 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 418 }; 419 420 static const struct txpwr_ent __txpwr_ent_lmt[] = { 421 /* 1TX */ 422 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 427 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 428 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 429 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 430 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 431 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 432 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 433 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 434 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 435 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 440 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 441 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 442 /* 2TX */ 443 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 444 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 445 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 446 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 447 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 448 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 449 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 450 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 451 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 452 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 453 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 454 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 455 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 456 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 457 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 458 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 459 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 460 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 461 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 462 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 463 }; 464 465 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 466 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 467 468 static const struct txpwr_map __txpwr_map_lmt = { 469 .ent = __txpwr_ent_lmt, 470 .size = ARRAY_SIZE(__txpwr_ent_lmt), 471 .addr_from = R_AX_PWR_LMT, 472 .addr_to = R_AX_PWR_LMT_MAX, 473 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 474 }; 475 476 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 477 /* 1TX */ 478 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 479 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 480 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 481 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 482 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 483 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 484 /* 2TX */ 485 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 486 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 487 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 488 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 489 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 490 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 491 }; 492 493 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 494 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 495 496 static const struct txpwr_map __txpwr_map_lmt_ru = { 497 .ent = __txpwr_ent_lmt_ru, 498 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 499 .addr_from = R_AX_PWR_RU_LMT, 500 .addr_to = R_AX_PWR_RU_LMT_MAX, 501 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 502 }; 503 504 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 505 const s8 *buf, const u8 cur) 506 { 507 char *fmt; 508 509 switch (ent->len) { 510 case 2: 511 fmt = "%s\t| %3d, %3d,\tdBm\n"; 512 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 513 return 2; 514 case 4: 515 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 516 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 517 buf[cur + 2], buf[cur + 3]); 518 return 4; 519 case 8: 520 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 521 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 522 buf[cur + 2], buf[cur + 3], buf[cur + 4], 523 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 524 return 8; 525 default: 526 return 0; 527 } 528 } 529 530 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 531 const struct txpwr_map *map) 532 { 533 u8 fct = rtwdev->chip->txpwr_factor_mac; 534 u8 path_num = rtwdev->chip->rf_path_num; 535 u32 max_valid_addr; 536 u32 val, addr; 537 s8 *buf, tmp; 538 u8 cur, i; 539 int ret; 540 541 buf = vzalloc(map->addr_to - map->addr_from + 4); 542 if (!buf) 543 return -ENOMEM; 544 545 if (path_num == 1) 546 max_valid_addr = map->addr_to_1ss; 547 else 548 max_valid_addr = map->addr_to; 549 550 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 551 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 552 if (ret) 553 val = MASKDWORD; 554 555 cur = addr - map->addr_from; 556 for (i = 0; i < 4; i++, val >>= 8) { 557 /* signed 7 bits, and reserved BIT(7) */ 558 tmp = sign_extend32(val, 6); 559 buf[cur + i] = tmp >> fct; 560 } 561 } 562 563 for (cur = 0, i = 0; i < map->size; i++) 564 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 565 566 vfree(buf); 567 return 0; 568 } 569 570 #define case_REGD(_regd) \ 571 case RTW89_ ## _regd: \ 572 seq_puts(m, #_regd "\n"); \ 573 break 574 575 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 576 { 577 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 578 u8 band = chan->band_type; 579 u8 regd = rtw89_regd_get(rtwdev, band); 580 581 switch (regd) { 582 default: 583 seq_printf(m, "UNKNOWN: %d\n", regd); 584 break; 585 case_REGD(WW); 586 case_REGD(ETSI); 587 case_REGD(FCC); 588 case_REGD(MKK); 589 case_REGD(NA); 590 case_REGD(IC); 591 case_REGD(KCC); 592 case_REGD(NCC); 593 case_REGD(CHILE); 594 case_REGD(ACMA); 595 case_REGD(MEXICO); 596 case_REGD(UKRAINE); 597 case_REGD(CN); 598 } 599 } 600 601 #undef case_REGD 602 603 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 604 { 605 struct rtw89_debugfs_priv *debugfs_priv = m->private; 606 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 607 int ret = 0; 608 609 mutex_lock(&rtwdev->mutex); 610 rtw89_leave_ps_mode(rtwdev); 611 612 seq_puts(m, "[Regulatory] "); 613 __print_regd(m, rtwdev); 614 615 seq_puts(m, "[SAR]\n"); 616 rtw89_print_sar(m, rtwdev); 617 618 seq_puts(m, "\n[TX power byrate]\n"); 619 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 620 if (ret) 621 goto err; 622 623 seq_puts(m, "\n[TX power limit]\n"); 624 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 625 if (ret) 626 goto err; 627 628 seq_puts(m, "\n[TX power limit_ru]\n"); 629 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 630 if (ret) 631 goto err; 632 633 err: 634 mutex_unlock(&rtwdev->mutex); 635 return ret; 636 } 637 638 static ssize_t 639 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 640 const char __user *user_buf, 641 size_t count, loff_t *loff) 642 { 643 struct seq_file *m = (struct seq_file *)filp->private_data; 644 struct rtw89_debugfs_priv *debugfs_priv = m->private; 645 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 646 const struct rtw89_chip_info *chip = rtwdev->chip; 647 char buf[32]; 648 size_t buf_size; 649 int sel; 650 int ret; 651 652 buf_size = min(count, sizeof(buf) - 1); 653 if (copy_from_user(buf, user_buf, buf_size)) 654 return -EFAULT; 655 656 buf[buf_size] = '\0'; 657 ret = kstrtoint(buf, 0, &sel); 658 if (ret) 659 return ret; 660 661 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 662 rtw89_info(rtwdev, "invalid args: %d\n", sel); 663 return -EINVAL; 664 } 665 666 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 667 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 668 chip->chip_id); 669 return -EINVAL; 670 } 671 672 debugfs_priv->cb_data = sel; 673 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 674 675 return count; 676 } 677 678 #define RTW89_MAC_PAGE_SIZE 0x100 679 680 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 681 { 682 struct rtw89_debugfs_priv *debugfs_priv = m->private; 683 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 684 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 685 u32 start, end; 686 u32 i, j, k, page; 687 u32 val; 688 689 switch (reg_sel) { 690 case RTW89_DBG_SEL_MAC_00: 691 seq_puts(m, "Debug selected MAC page 0x00\n"); 692 start = 0x000; 693 end = 0x014; 694 break; 695 case RTW89_DBG_SEL_MAC_30: 696 seq_puts(m, "Debug selected MAC page 0x30\n"); 697 start = 0x030; 698 end = 0x033; 699 break; 700 case RTW89_DBG_SEL_MAC_40: 701 seq_puts(m, "Debug selected MAC page 0x40\n"); 702 start = 0x040; 703 end = 0x07f; 704 break; 705 case RTW89_DBG_SEL_MAC_80: 706 seq_puts(m, "Debug selected MAC page 0x80\n"); 707 start = 0x080; 708 end = 0x09f; 709 break; 710 case RTW89_DBG_SEL_MAC_C0: 711 seq_puts(m, "Debug selected MAC page 0xc0\n"); 712 start = 0x0c0; 713 end = 0x0df; 714 break; 715 case RTW89_DBG_SEL_MAC_E0: 716 seq_puts(m, "Debug selected MAC page 0xe0\n"); 717 start = 0x0e0; 718 end = 0x0ff; 719 break; 720 case RTW89_DBG_SEL_BB: 721 seq_puts(m, "Debug selected BB register\n"); 722 start = 0x100; 723 end = 0x17f; 724 break; 725 case RTW89_DBG_SEL_IQK: 726 seq_puts(m, "Debug selected IQK register\n"); 727 start = 0x180; 728 end = 0x1bf; 729 break; 730 case RTW89_DBG_SEL_RFC: 731 seq_puts(m, "Debug selected RFC register\n"); 732 start = 0x1c0; 733 end = 0x1ff; 734 break; 735 default: 736 seq_puts(m, "Selected invalid register page\n"); 737 return -EINVAL; 738 } 739 740 for (i = start; i <= end; i++) { 741 page = i << 8; 742 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 743 seq_printf(m, "%08xh : ", 0x18600000 + j); 744 for (k = 0; k < 4; k++) { 745 val = rtw89_read32(rtwdev, j + (k << 2)); 746 seq_printf(m, "%08x ", val); 747 } 748 seq_puts(m, "\n"); 749 } 750 } 751 752 return 0; 753 } 754 755 static ssize_t 756 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 757 const char __user *user_buf, 758 size_t count, loff_t *loff) 759 { 760 struct seq_file *m = (struct seq_file *)filp->private_data; 761 struct rtw89_debugfs_priv *debugfs_priv = m->private; 762 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 763 char buf[32]; 764 size_t buf_size; 765 u32 sel, start_addr, len; 766 int num; 767 768 buf_size = min(count, sizeof(buf) - 1); 769 if (copy_from_user(buf, user_buf, buf_size)) 770 return -EFAULT; 771 772 buf[buf_size] = '\0'; 773 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 774 if (num != 3) { 775 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 776 return -EINVAL; 777 } 778 779 debugfs_priv->mac_mem.sel = sel; 780 debugfs_priv->mac_mem.start = start_addr; 781 debugfs_priv->mac_mem.len = len; 782 783 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 784 sel, start_addr, len); 785 786 return count; 787 } 788 789 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 790 struct rtw89_dev *rtwdev, 791 u8 sel, u32 start_addr, u32 len) 792 { 793 u32 base_addr, start_page, residue; 794 u32 i, j, p, pages; 795 u32 dump_len, remain; 796 u32 val; 797 798 remain = len; 799 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 800 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 801 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 802 base_addr = rtw89_mac_mem_base_addrs[sel]; 803 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 804 805 for (p = 0; p < pages; p++) { 806 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 807 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 808 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 809 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 810 seq_printf(m, "%08xh:", i); 811 for (j = 0; 812 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 813 j++, i += 4) { 814 val = rtw89_read32(rtwdev, i); 815 seq_printf(m, " %08x", val); 816 remain -= 4; 817 } 818 seq_puts(m, "\n"); 819 } 820 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 821 } 822 } 823 824 static int 825 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 826 { 827 struct rtw89_debugfs_priv *debugfs_priv = m->private; 828 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 829 bool grant_read = false; 830 831 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 832 return -ENOENT; 833 834 if (rtwdev->chip->chip_id == RTL8852C) { 835 switch (debugfs_priv->mac_mem.sel) { 836 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 837 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 838 case RTW89_MAC_MEM_TXDATA_FIFO_0: 839 case RTW89_MAC_MEM_TXDATA_FIFO_1: 840 grant_read = true; 841 break; 842 default: 843 break; 844 } 845 } 846 847 mutex_lock(&rtwdev->mutex); 848 rtw89_leave_ps_mode(rtwdev); 849 if (grant_read) 850 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 851 rtw89_debug_dump_mac_mem(m, rtwdev, 852 debugfs_priv->mac_mem.sel, 853 debugfs_priv->mac_mem.start, 854 debugfs_priv->mac_mem.len); 855 if (grant_read) 856 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 857 mutex_unlock(&rtwdev->mutex); 858 859 return 0; 860 } 861 862 static ssize_t 863 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 864 const char __user *user_buf, 865 size_t count, loff_t *loff) 866 { 867 struct seq_file *m = (struct seq_file *)filp->private_data; 868 struct rtw89_debugfs_priv *debugfs_priv = m->private; 869 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 870 char buf[32]; 871 size_t buf_size; 872 int sel, set; 873 int num; 874 bool enable; 875 876 buf_size = min(count, sizeof(buf) - 1); 877 if (copy_from_user(buf, user_buf, buf_size)) 878 return -EFAULT; 879 880 buf[buf_size] = '\0'; 881 num = sscanf(buf, "%d %d", &sel, &set); 882 if (num != 2) { 883 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 884 return -EINVAL; 885 } 886 887 enable = set != 0; 888 switch (sel) { 889 case 0: 890 debugfs_priv->dbgpkg_en.ss_dbg = enable; 891 break; 892 case 1: 893 debugfs_priv->dbgpkg_en.dle_dbg = enable; 894 break; 895 case 2: 896 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 897 break; 898 case 3: 899 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 900 break; 901 case 4: 902 debugfs_priv->dbgpkg_en.dbg_port = enable; 903 break; 904 default: 905 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 906 return -EINVAL; 907 } 908 909 rtw89_info(rtwdev, "%s debug port dump %d\n", 910 enable ? "Enable" : "Disable", sel); 911 912 return count; 913 } 914 915 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 916 struct seq_file *m) 917 { 918 return 0; 919 } 920 921 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 922 struct seq_file *m) 923 { 924 #define DLE_DFI_DUMP(__type, __target, __sel) \ 925 ({ \ 926 u32 __ctrl; \ 927 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 928 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 929 u32 __data, __val32; \ 930 int __ret; \ 931 \ 932 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 933 DLE_DFI_TYPE_##__target) | \ 934 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 935 B_AX_WDE_DFI_ACTIVE; \ 936 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 937 __ret = read_poll_timeout(rtw89_read32, __val32, \ 938 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 939 1000, 50000, false, \ 940 rtwdev, __reg_ctrl); \ 941 if (__ret) { \ 942 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 943 #__type, #__target, __sel); \ 944 return __ret; \ 945 } \ 946 \ 947 __data = rtw89_read32(rtwdev, __reg_data); \ 948 __data; \ 949 }) 950 951 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 952 ({ \ 953 u32 __freepg, __pubpg; \ 954 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 955 \ 956 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 957 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 958 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 959 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 960 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 961 seq_printf(__m, "[%s] freepg head: %d\n", \ 962 #__type, __freepg_head); \ 963 seq_printf(__m, "[%s] freepg tail: %d\n", \ 964 #__type, __freepg_tail); \ 965 seq_printf(__m, "[%s] pubpg num : %d\n", \ 966 #__type, __pubpg_num); \ 967 }) 968 969 #define case_QUOTA(__m, __type, __id) \ 970 case __type##_QTAID_##__id: \ 971 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 972 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 973 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 974 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 975 #__type, #__id, rsv_pgnum); \ 976 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 977 #__type, #__id, use_pgnum); \ 978 break 979 u32 quota_id; 980 u32 val32; 981 u16 rsv_pgnum, use_pgnum; 982 int ret; 983 984 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 985 if (ret) { 986 seq_puts(m, "[DLE] : DMAC not enabled\n"); 987 return ret; 988 } 989 990 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 991 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 992 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 993 switch (quota_id) { 994 case_QUOTA(m, WDE, HOST_IF); 995 case_QUOTA(m, WDE, WLAN_CPU); 996 case_QUOTA(m, WDE, DATA_CPU); 997 case_QUOTA(m, WDE, PKTIN); 998 case_QUOTA(m, WDE, CPUIO); 999 } 1000 } 1001 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1002 switch (quota_id) { 1003 case_QUOTA(m, PLE, B0_TXPL); 1004 case_QUOTA(m, PLE, B1_TXPL); 1005 case_QUOTA(m, PLE, C2H); 1006 case_QUOTA(m, PLE, H2C); 1007 case_QUOTA(m, PLE, WLAN_CPU); 1008 case_QUOTA(m, PLE, MPDU); 1009 case_QUOTA(m, PLE, CMAC0_RX); 1010 case_QUOTA(m, PLE, CMAC1_RX); 1011 case_QUOTA(m, PLE, CMAC1_BBRPT); 1012 case_QUOTA(m, PLE, WDRLS); 1013 case_QUOTA(m, PLE, CPUIO); 1014 } 1015 } 1016 1017 return 0; 1018 1019 #undef case_QUOTA 1020 #undef DLE_DFI_DUMP 1021 #undef DLE_DFI_FREE_PAGE_DUMP 1022 } 1023 1024 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1025 struct seq_file *m) 1026 { 1027 const struct rtw89_chip_info *chip = rtwdev->chip; 1028 u32 dmac_err; 1029 int i, ret; 1030 1031 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1032 if (ret) { 1033 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1034 return ret; 1035 } 1036 1037 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1038 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1039 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1040 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1041 1042 if (dmac_err) { 1043 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1044 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1045 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1046 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1047 if (chip->chip_id == RTL8852C) { 1048 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1049 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1050 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1051 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1052 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1053 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1054 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1055 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1056 } 1057 } 1058 1059 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1060 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1061 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1062 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1063 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1064 if (chip->chip_id == RTL8852C) 1065 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1066 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1067 else 1068 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1069 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1070 } 1071 1072 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1073 if (chip->chip_id == RTL8852C) { 1074 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1075 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1076 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1077 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1078 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1079 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1080 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1081 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1082 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1083 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1084 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1085 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1086 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1087 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1088 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1089 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1090 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1091 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1092 1093 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1094 B_AX_DBG_SEL0, 0x8B); 1095 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1096 B_AX_DBG_SEL1, 0x8B); 1097 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1098 B_AX_SEL_0XC0_MASK, 1); 1099 for (i = 0; i < 0x10; i++) { 1100 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1101 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1102 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1103 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1104 } 1105 } else { 1106 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1107 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1108 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1109 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1110 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1111 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1112 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1113 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1114 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1115 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1116 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1117 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1118 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1119 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1120 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1121 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1122 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1123 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1124 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1125 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1126 } 1127 } 1128 1129 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1130 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1131 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1132 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1133 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1134 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1135 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1136 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1137 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1138 } 1139 1140 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1141 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1142 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1143 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1144 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1145 } 1146 1147 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1148 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1149 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1150 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1151 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1152 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1153 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1154 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1155 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1156 } 1157 1158 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1159 if (chip->chip_id == RTL8852C) { 1160 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1161 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1162 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1163 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1164 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1165 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1166 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1167 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1168 } else { 1169 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1170 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1171 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1172 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1173 } 1174 } 1175 1176 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1177 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1178 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1179 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1180 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1181 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1182 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1183 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1184 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1185 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1186 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1187 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1188 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1189 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1190 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1191 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1192 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1193 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1194 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1195 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1196 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1197 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1198 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1199 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1200 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1201 if (chip->chip_id == RTL8852C) { 1202 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1203 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1204 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1205 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1206 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1207 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1208 } else { 1209 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1210 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1211 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1212 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1213 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1214 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1215 } 1216 } 1217 1218 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1219 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1220 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1221 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1222 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1223 } 1224 1225 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1226 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1227 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1228 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1229 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1230 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1231 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1232 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1233 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1234 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1235 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1236 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1237 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1238 } 1239 1240 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1241 if (chip->chip_id == RTL8852C) { 1242 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1243 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1244 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1245 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1246 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1247 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1248 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1249 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1250 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1251 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1252 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1253 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1254 } else { 1255 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1256 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1257 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1258 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1259 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1260 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1261 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1262 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1263 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1264 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1265 } 1266 } 1267 1268 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1269 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1270 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1271 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1272 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1279 struct seq_file *m, 1280 enum rtw89_mac_idx band) 1281 { 1282 const struct rtw89_chip_info *chip = rtwdev->chip; 1283 u32 offset = 0; 1284 u32 cmac_err; 1285 int ret; 1286 1287 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1288 if (ret) { 1289 if (band) 1290 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1291 else 1292 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1293 return ret; 1294 } 1295 1296 if (band) 1297 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1298 1299 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1300 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1301 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1302 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1303 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1304 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1305 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1306 1307 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1308 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1309 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1310 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1311 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1312 } 1313 1314 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1315 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1316 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1317 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1318 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1319 } 1320 1321 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1322 if (chip->chip_id == RTL8852C) { 1323 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1324 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1325 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1326 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1327 } else { 1328 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1329 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1330 } 1331 } 1332 1333 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1334 if (chip->chip_id == RTL8852C) { 1335 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1336 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1337 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1338 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1339 } else { 1340 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1341 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1342 } 1343 } 1344 1345 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1346 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1347 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1348 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1349 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1350 } 1351 1352 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1353 if (chip->chip_id == RTL8852C) { 1354 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1355 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1356 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1357 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1358 } else { 1359 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1360 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1361 } 1362 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1363 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1364 } 1365 1366 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1367 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1368 1369 return 0; 1370 } 1371 1372 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1373 struct seq_file *m) 1374 { 1375 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1376 if (rtwdev->dbcc_en) 1377 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1378 1379 return 0; 1380 } 1381 1382 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1383 .sel_addr = R_AX_PTCL_DBG, 1384 .sel_byte = 1, 1385 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1386 .srt = 0x00, 1387 .end = 0x3F, 1388 .rd_addr = R_AX_PTCL_DBG_INFO, 1389 .rd_byte = 4, 1390 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1391 }; 1392 1393 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1394 .sel_addr = R_AX_PTCL_DBG_C1, 1395 .sel_byte = 1, 1396 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1397 .srt = 0x00, 1398 .end = 0x3F, 1399 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1400 .rd_byte = 4, 1401 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1402 }; 1403 1404 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1405 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1406 .sel_byte = 2, 1407 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1408 .srt = 0x0, 1409 .end = 0xD, 1410 .rd_addr = R_AX_DBG_PORT_SEL, 1411 .rd_byte = 4, 1412 .rd_msk = B_AX_DEBUG_ST_MASK 1413 }; 1414 1415 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1416 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1417 .sel_byte = 2, 1418 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1419 .srt = 0x0, 1420 .end = 0x5, 1421 .rd_addr = R_AX_DBG_PORT_SEL, 1422 .rd_byte = 4, 1423 .rd_msk = B_AX_DEBUG_ST_MASK 1424 }; 1425 1426 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1427 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1428 .sel_byte = 2, 1429 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1430 .srt = 0x0, 1431 .end = 0x9, 1432 .rd_addr = R_AX_DBG_PORT_SEL, 1433 .rd_byte = 4, 1434 .rd_msk = B_AX_DEBUG_ST_MASK 1435 }; 1436 1437 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1438 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1439 .sel_byte = 2, 1440 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1441 .srt = 0x0, 1442 .end = 0x3, 1443 .rd_addr = R_AX_DBG_PORT_SEL, 1444 .rd_byte = 4, 1445 .rd_msk = B_AX_DEBUG_ST_MASK 1446 }; 1447 1448 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1449 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1450 .sel_byte = 2, 1451 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1452 .srt = 0x0, 1453 .end = 0x1, 1454 .rd_addr = R_AX_DBG_PORT_SEL, 1455 .rd_byte = 4, 1456 .rd_msk = B_AX_DEBUG_ST_MASK 1457 }; 1458 1459 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1460 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1461 .sel_byte = 2, 1462 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1463 .srt = 0x0, 1464 .end = 0x0, 1465 .rd_addr = R_AX_DBG_PORT_SEL, 1466 .rd_byte = 4, 1467 .rd_msk = B_AX_DEBUG_ST_MASK 1468 }; 1469 1470 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1471 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1472 .sel_byte = 2, 1473 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1474 .srt = 0x0, 1475 .end = 0xB, 1476 .rd_addr = R_AX_DBG_PORT_SEL, 1477 .rd_byte = 4, 1478 .rd_msk = B_AX_DEBUG_ST_MASK 1479 }; 1480 1481 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1482 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1483 .sel_byte = 2, 1484 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1485 .srt = 0x0, 1486 .end = 0x4, 1487 .rd_addr = R_AX_DBG_PORT_SEL, 1488 .rd_byte = 4, 1489 .rd_msk = B_AX_DEBUG_ST_MASK 1490 }; 1491 1492 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1493 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1494 .sel_byte = 2, 1495 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1496 .srt = 0x0, 1497 .end = 0x8, 1498 .rd_addr = R_AX_DBG_PORT_SEL, 1499 .rd_byte = 4, 1500 .rd_msk = B_AX_DEBUG_ST_MASK 1501 }; 1502 1503 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1504 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1505 .sel_byte = 2, 1506 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1507 .srt = 0x0, 1508 .end = 0x7, 1509 .rd_addr = R_AX_DBG_PORT_SEL, 1510 .rd_byte = 4, 1511 .rd_msk = B_AX_DEBUG_ST_MASK 1512 }; 1513 1514 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1515 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1516 .sel_byte = 2, 1517 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1518 .srt = 0x0, 1519 .end = 0x1, 1520 .rd_addr = R_AX_DBG_PORT_SEL, 1521 .rd_byte = 4, 1522 .rd_msk = B_AX_DEBUG_ST_MASK 1523 }; 1524 1525 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1526 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1527 .sel_byte = 2, 1528 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1529 .srt = 0x0, 1530 .end = 0x3, 1531 .rd_addr = R_AX_DBG_PORT_SEL, 1532 .rd_byte = 4, 1533 .rd_msk = B_AX_DEBUG_ST_MASK 1534 }; 1535 1536 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1537 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1538 .sel_byte = 2, 1539 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1540 .srt = 0x0, 1541 .end = 0x0, 1542 .rd_addr = R_AX_DBG_PORT_SEL, 1543 .rd_byte = 4, 1544 .rd_msk = B_AX_DEBUG_ST_MASK 1545 }; 1546 1547 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1548 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1549 .sel_byte = 2, 1550 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1551 .srt = 0x0, 1552 .end = 0x8, 1553 .rd_addr = R_AX_DBG_PORT_SEL, 1554 .rd_byte = 4, 1555 .rd_msk = B_AX_DEBUG_ST_MASK 1556 }; 1557 1558 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1559 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1560 .sel_byte = 2, 1561 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1562 .srt = 0x0, 1563 .end = 0x0, 1564 .rd_addr = R_AX_DBG_PORT_SEL, 1565 .rd_byte = 4, 1566 .rd_msk = B_AX_DEBUG_ST_MASK 1567 }; 1568 1569 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1570 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1571 .sel_byte = 2, 1572 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1573 .srt = 0x0, 1574 .end = 0x6, 1575 .rd_addr = R_AX_DBG_PORT_SEL, 1576 .rd_byte = 4, 1577 .rd_msk = B_AX_DEBUG_ST_MASK 1578 }; 1579 1580 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1581 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1582 .sel_byte = 2, 1583 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1584 .srt = 0x0, 1585 .end = 0x0, 1586 .rd_addr = R_AX_DBG_PORT_SEL, 1587 .rd_byte = 4, 1588 .rd_msk = B_AX_DEBUG_ST_MASK 1589 }; 1590 1591 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1592 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1593 .sel_byte = 2, 1594 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1595 .srt = 0x0, 1596 .end = 0x0, 1597 .rd_addr = R_AX_DBG_PORT_SEL, 1598 .rd_byte = 4, 1599 .rd_msk = B_AX_DEBUG_ST_MASK 1600 }; 1601 1602 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1603 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1604 .sel_byte = 1, 1605 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1606 .srt = 0x0, 1607 .end = 0x3, 1608 .rd_addr = R_AX_DBG_PORT_SEL, 1609 .rd_byte = 4, 1610 .rd_msk = B_AX_DEBUG_ST_MASK 1611 }; 1612 1613 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1614 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1615 .sel_byte = 1, 1616 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1617 .srt = 0x0, 1618 .end = 0x6, 1619 .rd_addr = R_AX_DBG_PORT_SEL, 1620 .rd_byte = 4, 1621 .rd_msk = B_AX_DEBUG_ST_MASK 1622 }; 1623 1624 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1625 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1626 .sel_byte = 1, 1627 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1628 .srt = 0x0, 1629 .end = 0x0, 1630 .rd_addr = R_AX_DBG_PORT_SEL, 1631 .rd_byte = 4, 1632 .rd_msk = B_AX_DEBUG_ST_MASK 1633 }; 1634 1635 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1636 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1637 .sel_byte = 1, 1638 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1639 .srt = 0x8, 1640 .end = 0xE, 1641 .rd_addr = R_AX_DBG_PORT_SEL, 1642 .rd_byte = 4, 1643 .rd_msk = B_AX_DEBUG_ST_MASK 1644 }; 1645 1646 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1647 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1648 .sel_byte = 1, 1649 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1650 .srt = 0x0, 1651 .end = 0x5, 1652 .rd_addr = R_AX_DBG_PORT_SEL, 1653 .rd_byte = 4, 1654 .rd_msk = B_AX_DEBUG_ST_MASK 1655 }; 1656 1657 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1658 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1659 .sel_byte = 1, 1660 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1661 .srt = 0x0, 1662 .end = 0x6, 1663 .rd_addr = R_AX_DBG_PORT_SEL, 1664 .rd_byte = 4, 1665 .rd_msk = B_AX_DEBUG_ST_MASK 1666 }; 1667 1668 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1669 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1670 .sel_byte = 1, 1671 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1672 .srt = 0x0, 1673 .end = 0xF, 1674 .rd_addr = R_AX_DBG_PORT_SEL, 1675 .rd_byte = 4, 1676 .rd_msk = B_AX_DEBUG_ST_MASK 1677 }; 1678 1679 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1680 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1681 .sel_byte = 1, 1682 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1683 .srt = 0x0, 1684 .end = 0x9, 1685 .rd_addr = R_AX_DBG_PORT_SEL, 1686 .rd_byte = 4, 1687 .rd_msk = B_AX_DEBUG_ST_MASK 1688 }; 1689 1690 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1691 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1692 .sel_byte = 1, 1693 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1694 .srt = 0x0, 1695 .end = 0x3, 1696 .rd_addr = R_AX_DBG_PORT_SEL, 1697 .rd_byte = 4, 1698 .rd_msk = B_AX_DEBUG_ST_MASK 1699 }; 1700 1701 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1702 .sel_addr = R_AX_SCH_DBG_SEL, 1703 .sel_byte = 1, 1704 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1705 .srt = 0x00, 1706 .end = 0x2F, 1707 .rd_addr = R_AX_SCH_DBG, 1708 .rd_byte = 4, 1709 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1710 }; 1711 1712 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1713 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1714 .sel_byte = 1, 1715 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1716 .srt = 0x00, 1717 .end = 0x2F, 1718 .rd_addr = R_AX_SCH_DBG_C1, 1719 .rd_byte = 4, 1720 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1721 }; 1722 1723 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1724 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1725 .sel_byte = 1, 1726 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1727 .srt = 0x00, 1728 .end = 0x19, 1729 .rd_addr = R_AX_DBG_PORT_SEL, 1730 .rd_byte = 4, 1731 .rd_msk = B_AX_DEBUG_ST_MASK 1732 }; 1733 1734 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1735 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1736 .sel_byte = 1, 1737 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1738 .srt = 0x00, 1739 .end = 0x19, 1740 .rd_addr = R_AX_DBG_PORT_SEL, 1741 .rd_byte = 4, 1742 .rd_msk = B_AX_DEBUG_ST_MASK 1743 }; 1744 1745 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1746 .sel_addr = R_AX_RX_DEBUG_SELECT, 1747 .sel_byte = 1, 1748 .sel_msk = B_AX_DEBUG_SEL_MASK, 1749 .srt = 0x00, 1750 .end = 0x58, 1751 .rd_addr = R_AX_DBG_PORT_SEL, 1752 .rd_byte = 4, 1753 .rd_msk = B_AX_DEBUG_ST_MASK 1754 }; 1755 1756 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1757 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1758 .sel_byte = 1, 1759 .sel_msk = B_AX_DEBUG_SEL_MASK, 1760 .srt = 0x00, 1761 .end = 0x58, 1762 .rd_addr = R_AX_DBG_PORT_SEL, 1763 .rd_byte = 4, 1764 .rd_msk = B_AX_DEBUG_ST_MASK 1765 }; 1766 1767 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1768 .sel_addr = R_AX_RX_STATE_MONITOR, 1769 .sel_byte = 1, 1770 .sel_msk = B_AX_STATE_SEL_MASK, 1771 .srt = 0x00, 1772 .end = 0x17, 1773 .rd_addr = R_AX_RX_STATE_MONITOR, 1774 .rd_byte = 4, 1775 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1776 }; 1777 1778 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1779 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1780 .sel_byte = 1, 1781 .sel_msk = B_AX_STATE_SEL_MASK, 1782 .srt = 0x00, 1783 .end = 0x17, 1784 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1785 .rd_byte = 4, 1786 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1787 }; 1788 1789 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1790 .sel_addr = R_AX_RMAC_PLCP_MON, 1791 .sel_byte = 4, 1792 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1793 .srt = 0x0, 1794 .end = 0xF, 1795 .rd_addr = R_AX_RMAC_PLCP_MON, 1796 .rd_byte = 4, 1797 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1798 }; 1799 1800 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1801 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1802 .sel_byte = 4, 1803 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1804 .srt = 0x0, 1805 .end = 0xF, 1806 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1807 .rd_byte = 4, 1808 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1809 }; 1810 1811 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1812 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1813 .sel_byte = 1, 1814 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1815 .srt = 0x08, 1816 .end = 0x10, 1817 .rd_addr = R_AX_DBG_PORT_SEL, 1818 .rd_byte = 4, 1819 .rd_msk = B_AX_DEBUG_ST_MASK 1820 }; 1821 1822 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1823 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1824 .sel_byte = 1, 1825 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1826 .srt = 0x08, 1827 .end = 0x10, 1828 .rd_addr = R_AX_DBG_PORT_SEL, 1829 .rd_byte = 4, 1830 .rd_msk = B_AX_DEBUG_ST_MASK 1831 }; 1832 1833 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1834 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1835 .sel_byte = 1, 1836 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1837 .srt = 0x00, 1838 .end = 0x07, 1839 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1840 .rd_byte = 4, 1841 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1842 }; 1843 1844 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1845 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1846 .sel_byte = 1, 1847 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1848 .srt = 0x00, 1849 .end = 0x07, 1850 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1851 .rd_byte = 4, 1852 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1853 }; 1854 1855 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1856 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1857 .sel_byte = 1, 1858 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1859 .srt = 0x00, 1860 .end = 0x07, 1861 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1862 .rd_byte = 4, 1863 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1864 }; 1865 1866 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1867 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1868 .sel_byte = 1, 1869 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1870 .srt = 0x00, 1871 .end = 0x07, 1872 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1873 .rd_byte = 4, 1874 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1875 }; 1876 1877 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1878 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1879 .sel_byte = 1, 1880 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1881 .srt = 0x00, 1882 .end = 0x04, 1883 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1884 .rd_byte = 4, 1885 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1886 }; 1887 1888 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1889 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1890 .sel_byte = 1, 1891 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1892 .srt = 0x00, 1893 .end = 0x04, 1894 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1895 .rd_byte = 4, 1896 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1897 }; 1898 1899 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1900 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1901 .sel_byte = 1, 1902 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1903 .srt = 0x00, 1904 .end = 0x04, 1905 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1906 .rd_byte = 4, 1907 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1908 }; 1909 1910 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1911 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1912 .sel_byte = 1, 1913 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1914 .srt = 0x00, 1915 .end = 0x04, 1916 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1917 .rd_byte = 4, 1918 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1919 }; 1920 1921 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1922 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1923 .sel_byte = 4, 1924 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1925 .srt = 0x80000000, 1926 .end = 0x80000001, 1927 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1928 .rd_byte = 4, 1929 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1930 }; 1931 1932 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1933 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1934 .sel_byte = 4, 1935 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1936 .srt = 0x80010000, 1937 .end = 0x80010004, 1938 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1939 .rd_byte = 4, 1940 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1941 }; 1942 1943 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1944 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1945 .sel_byte = 4, 1946 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1947 .srt = 0x80020000, 1948 .end = 0x80020FFF, 1949 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1950 .rd_byte = 4, 1951 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1952 }; 1953 1954 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1955 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1956 .sel_byte = 4, 1957 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1958 .srt = 0x80030000, 1959 .end = 0x80030FFF, 1960 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1961 .rd_byte = 4, 1962 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1963 }; 1964 1965 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1966 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1967 .sel_byte = 4, 1968 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1969 .srt = 0x80040000, 1970 .end = 0x80040FFF, 1971 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1972 .rd_byte = 4, 1973 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1974 }; 1975 1976 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1977 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1978 .sel_byte = 4, 1979 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1980 .srt = 0x80050000, 1981 .end = 0x80050FFF, 1982 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1983 .rd_byte = 4, 1984 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1985 }; 1986 1987 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1988 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1989 .sel_byte = 4, 1990 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1991 .srt = 0x80060000, 1992 .end = 0x80060453, 1993 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1994 .rd_byte = 4, 1995 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1996 }; 1997 1998 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1999 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2000 .sel_byte = 4, 2001 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2002 .srt = 0x80070000, 2003 .end = 0x80070011, 2004 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2005 .rd_byte = 4, 2006 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2007 }; 2008 2009 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2010 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2011 .sel_byte = 4, 2012 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2013 .srt = 0x80000000, 2014 .end = 0x80000001, 2015 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2016 .rd_byte = 4, 2017 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2018 }; 2019 2020 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2021 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2022 .sel_byte = 4, 2023 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2024 .srt = 0x80010000, 2025 .end = 0x8001000A, 2026 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2027 .rd_byte = 4, 2028 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2029 }; 2030 2031 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2032 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2033 .sel_byte = 4, 2034 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2035 .srt = 0x80020000, 2036 .end = 0x80020DBF, 2037 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2038 .rd_byte = 4, 2039 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2040 }; 2041 2042 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2043 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2044 .sel_byte = 4, 2045 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2046 .srt = 0x80030000, 2047 .end = 0x80030DBF, 2048 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2049 .rd_byte = 4, 2050 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2051 }; 2052 2053 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2054 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2055 .sel_byte = 4, 2056 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2057 .srt = 0x80040000, 2058 .end = 0x80040DBF, 2059 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2060 .rd_byte = 4, 2061 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2062 }; 2063 2064 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2065 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2066 .sel_byte = 4, 2067 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2068 .srt = 0x80050000, 2069 .end = 0x80050DBF, 2070 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2071 .rd_byte = 4, 2072 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2073 }; 2074 2075 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2076 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2077 .sel_byte = 4, 2078 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2079 .srt = 0x80060000, 2080 .end = 0x80060041, 2081 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2082 .rd_byte = 4, 2083 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2084 }; 2085 2086 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2087 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2088 .sel_byte = 4, 2089 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2090 .srt = 0x80070000, 2091 .end = 0x80070001, 2092 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2093 .rd_byte = 4, 2094 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2095 }; 2096 2097 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2098 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2099 .sel_byte = 4, 2100 .sel_msk = B_AX_DFI_DATA_MASK, 2101 .srt = 0x80000000, 2102 .end = 0x8000017f, 2103 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2104 .rd_byte = 4, 2105 .rd_msk = B_AX_DFI_DATA_MASK 2106 }; 2107 2108 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2109 .sel_addr = R_AX_PCIE_DBG_CTRL, 2110 .sel_byte = 2, 2111 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2112 .srt = 0x00, 2113 .end = 0x03, 2114 .rd_addr = R_AX_DBG_PORT_SEL, 2115 .rd_byte = 4, 2116 .rd_msk = B_AX_DEBUG_ST_MASK 2117 }; 2118 2119 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2120 .sel_addr = R_AX_PCIE_DBG_CTRL, 2121 .sel_byte = 2, 2122 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2123 .srt = 0x00, 2124 .end = 0x04, 2125 .rd_addr = R_AX_DBG_PORT_SEL, 2126 .rd_byte = 4, 2127 .rd_msk = B_AX_DEBUG_ST_MASK 2128 }; 2129 2130 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2131 .sel_addr = R_AX_PCIE_DBG_CTRL, 2132 .sel_byte = 2, 2133 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2134 .srt = 0x00, 2135 .end = 0x01, 2136 .rd_addr = R_AX_DBG_PORT_SEL, 2137 .rd_byte = 4, 2138 .rd_msk = B_AX_DEBUG_ST_MASK 2139 }; 2140 2141 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2142 .sel_addr = R_AX_PCIE_DBG_CTRL, 2143 .sel_byte = 2, 2144 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2145 .srt = 0x00, 2146 .end = 0x05, 2147 .rd_addr = R_AX_DBG_PORT_SEL, 2148 .rd_byte = 4, 2149 .rd_msk = B_AX_DEBUG_ST_MASK 2150 }; 2151 2152 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2153 .sel_addr = R_AX_PCIE_DBG_CTRL, 2154 .sel_byte = 2, 2155 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2156 .srt = 0x00, 2157 .end = 0x05, 2158 .rd_addr = R_AX_DBG_PORT_SEL, 2159 .rd_byte = 4, 2160 .rd_msk = B_AX_DEBUG_ST_MASK 2161 }; 2162 2163 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2164 .sel_addr = R_AX_PCIE_DBG_CTRL, 2165 .sel_byte = 2, 2166 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2167 .srt = 0x00, 2168 .end = 0x06, 2169 .rd_addr = R_AX_DBG_PORT_SEL, 2170 .rd_byte = 4, 2171 .rd_msk = B_AX_DEBUG_ST_MASK 2172 }; 2173 2174 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2175 .sel_addr = R_AX_DBG_CTRL, 2176 .sel_byte = 1, 2177 .sel_msk = B_AX_DBG_SEL0, 2178 .srt = 0x34, 2179 .end = 0x3C, 2180 .rd_addr = R_AX_DBG_PORT_SEL, 2181 .rd_byte = 4, 2182 .rd_msk = B_AX_DEBUG_ST_MASK 2183 }; 2184 2185 static const struct rtw89_mac_dbg_port_info * 2186 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2187 struct rtw89_dev *rtwdev, u32 sel) 2188 { 2189 const struct rtw89_mac_dbg_port_info *info; 2190 u32 index; 2191 u32 val32; 2192 u16 val16; 2193 u8 val8; 2194 2195 switch (sel) { 2196 case RTW89_DBG_PORT_SEL_PTCL_C0: 2197 info = &dbg_port_ptcl_c0; 2198 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2199 val16 |= B_AX_PTCL_DBG_EN; 2200 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2201 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2202 break; 2203 case RTW89_DBG_PORT_SEL_PTCL_C1: 2204 info = &dbg_port_ptcl_c1; 2205 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2206 val16 |= B_AX_PTCL_DBG_EN; 2207 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2208 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2209 break; 2210 case RTW89_DBG_PORT_SEL_SCH_C0: 2211 info = &dbg_port_sch_c0; 2212 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2213 val32 |= B_AX_SCH_DBG_EN; 2214 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2215 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2216 break; 2217 case RTW89_DBG_PORT_SEL_SCH_C1: 2218 info = &dbg_port_sch_c1; 2219 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2220 val32 |= B_AX_SCH_DBG_EN; 2221 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2222 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2223 break; 2224 case RTW89_DBG_PORT_SEL_TMAC_C0: 2225 info = &dbg_port_tmac_c0; 2226 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2227 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2228 B_AX_DBGSEL_TRXPTCL_MASK); 2229 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2230 2231 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2232 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2233 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2234 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2235 2236 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2237 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2238 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2239 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2240 break; 2241 case RTW89_DBG_PORT_SEL_TMAC_C1: 2242 info = &dbg_port_tmac_c1; 2243 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2244 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2245 B_AX_DBGSEL_TRXPTCL_MASK); 2246 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2247 2248 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2249 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2250 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2251 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2252 2253 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2254 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2255 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2256 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2257 break; 2258 case RTW89_DBG_PORT_SEL_RMAC_C0: 2259 info = &dbg_port_rmac_c0; 2260 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2261 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2262 B_AX_DBGSEL_TRXPTCL_MASK); 2263 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2264 2265 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2266 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2267 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2268 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2269 2270 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2271 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2272 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2273 2274 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2275 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2276 B_AX_DBGSEL_TRXPTCL_MASK); 2277 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2278 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2279 break; 2280 case RTW89_DBG_PORT_SEL_RMAC_C1: 2281 info = &dbg_port_rmac_c1; 2282 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2283 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2284 B_AX_DBGSEL_TRXPTCL_MASK); 2285 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2286 2287 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2288 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2289 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2290 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2291 2292 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2293 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2294 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2295 2296 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2297 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2298 B_AX_DBGSEL_TRXPTCL_MASK); 2299 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2300 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2301 break; 2302 case RTW89_DBG_PORT_SEL_RMACST_C0: 2303 info = &dbg_port_rmacst_c0; 2304 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2305 break; 2306 case RTW89_DBG_PORT_SEL_RMACST_C1: 2307 info = &dbg_port_rmacst_c1; 2308 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2309 break; 2310 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2311 info = &dbg_port_rmac_plcp_c0; 2312 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2313 break; 2314 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2315 info = &dbg_port_rmac_plcp_c1; 2316 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2317 break; 2318 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2319 info = &dbg_port_trxptcl_c0; 2320 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2321 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2322 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2323 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2324 2325 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2326 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2327 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2328 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2329 break; 2330 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2331 info = &dbg_port_trxptcl_c1; 2332 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2333 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2334 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2335 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2336 2337 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2338 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2339 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2340 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2341 break; 2342 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2343 info = &dbg_port_tx_infol_c0; 2344 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2345 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2346 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2347 seq_puts(m, "Enable tx infol dump.\n"); 2348 break; 2349 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2350 info = &dbg_port_tx_infoh_c0; 2351 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2352 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2353 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2354 seq_puts(m, "Enable tx infoh dump.\n"); 2355 break; 2356 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2357 info = &dbg_port_tx_infol_c1; 2358 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2359 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2360 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2361 seq_puts(m, "Enable tx infol dump.\n"); 2362 break; 2363 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2364 info = &dbg_port_tx_infoh_c1; 2365 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2366 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2367 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2368 seq_puts(m, "Enable tx infoh dump.\n"); 2369 break; 2370 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2371 info = &dbg_port_txtf_infol_c0; 2372 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2373 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2374 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2375 seq_puts(m, "Enable tx tf infol dump.\n"); 2376 break; 2377 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2378 info = &dbg_port_txtf_infoh_c0; 2379 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2380 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2381 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2382 seq_puts(m, "Enable tx tf infoh dump.\n"); 2383 break; 2384 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2385 info = &dbg_port_txtf_infol_c1; 2386 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2387 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2388 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2389 seq_puts(m, "Enable tx tf infol dump.\n"); 2390 break; 2391 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2392 info = &dbg_port_txtf_infoh_c1; 2393 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2394 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2395 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2396 seq_puts(m, "Enable tx tf infoh dump.\n"); 2397 break; 2398 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2399 info = &dbg_port_wde_bufmgn_freepg; 2400 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2401 break; 2402 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2403 info = &dbg_port_wde_bufmgn_quota; 2404 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2405 break; 2406 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2407 info = &dbg_port_wde_bufmgn_pagellt; 2408 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2409 break; 2410 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2411 info = &dbg_port_wde_bufmgn_pktinfo; 2412 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2413 break; 2414 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2415 info = &dbg_port_wde_quemgn_prepkt; 2416 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2417 break; 2418 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2419 info = &dbg_port_wde_quemgn_nxtpkt; 2420 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2421 break; 2422 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2423 info = &dbg_port_wde_quemgn_qlnktbl; 2424 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2425 break; 2426 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2427 info = &dbg_port_wde_quemgn_qempty; 2428 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2429 break; 2430 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2431 info = &dbg_port_ple_bufmgn_freepg; 2432 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2433 break; 2434 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2435 info = &dbg_port_ple_bufmgn_quota; 2436 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2437 break; 2438 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2439 info = &dbg_port_ple_bufmgn_pagellt; 2440 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2441 break; 2442 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2443 info = &dbg_port_ple_bufmgn_pktinfo; 2444 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2445 break; 2446 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2447 info = &dbg_port_ple_quemgn_prepkt; 2448 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2449 break; 2450 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2451 info = &dbg_port_ple_quemgn_nxtpkt; 2452 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2453 break; 2454 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2455 info = &dbg_port_ple_quemgn_qlnktbl; 2456 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2457 break; 2458 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2459 info = &dbg_port_ple_quemgn_qempty; 2460 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2461 break; 2462 case RTW89_DBG_PORT_SEL_PKTINFO: 2463 info = &dbg_port_pktinfo; 2464 seq_puts(m, "Enable pktinfo dump.\n"); 2465 break; 2466 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2467 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2468 B_AX_DBG_SEL0, 0x80); 2469 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2470 B_AX_SEL_0XC0_MASK, 1); 2471 fallthrough; 2472 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2473 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2474 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2475 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2476 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2477 info = &dbg_port_dspt_hdt_tx0_5; 2478 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2479 rtw89_write16_mask(rtwdev, info->sel_addr, 2480 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2481 rtw89_write16_mask(rtwdev, info->sel_addr, 2482 B_AX_DISPATCHER_CH_SEL_MASK, index); 2483 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2484 break; 2485 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2486 info = &dbg_port_dspt_hdt_tx6; 2487 rtw89_write16_mask(rtwdev, info->sel_addr, 2488 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2489 rtw89_write16_mask(rtwdev, info->sel_addr, 2490 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2491 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2492 break; 2493 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2494 info = &dbg_port_dspt_hdt_tx7; 2495 rtw89_write16_mask(rtwdev, info->sel_addr, 2496 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2497 rtw89_write16_mask(rtwdev, info->sel_addr, 2498 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2499 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2500 break; 2501 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2502 info = &dbg_port_dspt_hdt_tx8; 2503 rtw89_write16_mask(rtwdev, info->sel_addr, 2504 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2505 rtw89_write16_mask(rtwdev, info->sel_addr, 2506 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2507 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2508 break; 2509 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2510 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2511 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2512 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2513 info = &dbg_port_dspt_hdt_tx9_C; 2514 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2515 rtw89_write16_mask(rtwdev, info->sel_addr, 2516 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2517 rtw89_write16_mask(rtwdev, info->sel_addr, 2518 B_AX_DISPATCHER_CH_SEL_MASK, index); 2519 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2520 break; 2521 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2522 info = &dbg_port_dspt_hdt_txD; 2523 rtw89_write16_mask(rtwdev, info->sel_addr, 2524 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2525 rtw89_write16_mask(rtwdev, info->sel_addr, 2526 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2527 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2528 break; 2529 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2530 info = &dbg_port_dspt_cdt_tx0; 2531 rtw89_write16_mask(rtwdev, info->sel_addr, 2532 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2533 rtw89_write16_mask(rtwdev, info->sel_addr, 2534 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2535 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2536 break; 2537 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2538 info = &dbg_port_dspt_cdt_tx1; 2539 rtw89_write16_mask(rtwdev, info->sel_addr, 2540 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2541 rtw89_write16_mask(rtwdev, info->sel_addr, 2542 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2543 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2544 break; 2545 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2546 info = &dbg_port_dspt_cdt_tx3; 2547 rtw89_write16_mask(rtwdev, info->sel_addr, 2548 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2549 rtw89_write16_mask(rtwdev, info->sel_addr, 2550 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2551 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2552 break; 2553 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2554 info = &dbg_port_dspt_cdt_tx4; 2555 rtw89_write16_mask(rtwdev, info->sel_addr, 2556 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2557 rtw89_write16_mask(rtwdev, info->sel_addr, 2558 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2559 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2560 break; 2561 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2562 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2563 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2564 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2565 info = &dbg_port_dspt_cdt_tx5_8; 2566 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2567 rtw89_write16_mask(rtwdev, info->sel_addr, 2568 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2569 rtw89_write16_mask(rtwdev, info->sel_addr, 2570 B_AX_DISPATCHER_CH_SEL_MASK, index); 2571 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2572 break; 2573 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2574 info = &dbg_port_dspt_cdt_tx9; 2575 rtw89_write16_mask(rtwdev, info->sel_addr, 2576 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2577 rtw89_write16_mask(rtwdev, info->sel_addr, 2578 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2579 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2580 break; 2581 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2582 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2583 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2584 info = &dbg_port_dspt_cdt_txA_C; 2585 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2586 rtw89_write16_mask(rtwdev, info->sel_addr, 2587 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2588 rtw89_write16_mask(rtwdev, info->sel_addr, 2589 B_AX_DISPATCHER_CH_SEL_MASK, index); 2590 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2591 break; 2592 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2593 info = &dbg_port_dspt_hdt_rx0; 2594 rtw89_write16_mask(rtwdev, info->sel_addr, 2595 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2596 rtw89_write16_mask(rtwdev, info->sel_addr, 2597 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2598 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2599 break; 2600 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2601 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2602 info = &dbg_port_dspt_hdt_rx1_2; 2603 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2604 rtw89_write16_mask(rtwdev, info->sel_addr, 2605 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2606 rtw89_write16_mask(rtwdev, info->sel_addr, 2607 B_AX_DISPATCHER_CH_SEL_MASK, index); 2608 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2609 break; 2610 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2611 info = &dbg_port_dspt_hdt_rx3; 2612 rtw89_write16_mask(rtwdev, info->sel_addr, 2613 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2614 rtw89_write16_mask(rtwdev, info->sel_addr, 2615 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2616 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2617 break; 2618 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2619 info = &dbg_port_dspt_hdt_rx4; 2620 rtw89_write16_mask(rtwdev, info->sel_addr, 2621 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2622 rtw89_write16_mask(rtwdev, info->sel_addr, 2623 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2624 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2625 break; 2626 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2627 info = &dbg_port_dspt_hdt_rx5; 2628 rtw89_write16_mask(rtwdev, info->sel_addr, 2629 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2630 rtw89_write16_mask(rtwdev, info->sel_addr, 2631 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2632 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2633 break; 2634 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2635 info = &dbg_port_dspt_cdt_rx_p0_0; 2636 rtw89_write16_mask(rtwdev, info->sel_addr, 2637 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2638 rtw89_write16_mask(rtwdev, info->sel_addr, 2639 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2640 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2641 break; 2642 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2643 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2644 info = &dbg_port_dspt_cdt_rx_p0_1; 2645 rtw89_write16_mask(rtwdev, info->sel_addr, 2646 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2647 rtw89_write16_mask(rtwdev, info->sel_addr, 2648 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2649 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2650 break; 2651 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2652 info = &dbg_port_dspt_cdt_rx_p0_2; 2653 rtw89_write16_mask(rtwdev, info->sel_addr, 2654 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2655 rtw89_write16_mask(rtwdev, info->sel_addr, 2656 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2657 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2658 break; 2659 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2660 info = &dbg_port_dspt_cdt_rx_p1; 2661 rtw89_write8_mask(rtwdev, info->sel_addr, 2662 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2663 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2664 break; 2665 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2666 info = &dbg_port_dspt_stf_ctrl; 2667 rtw89_write8_mask(rtwdev, info->sel_addr, 2668 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2669 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2670 break; 2671 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2672 info = &dbg_port_dspt_addr_ctrl; 2673 rtw89_write8_mask(rtwdev, info->sel_addr, 2674 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2675 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2676 break; 2677 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2678 info = &dbg_port_dspt_wde_intf; 2679 rtw89_write8_mask(rtwdev, info->sel_addr, 2680 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2681 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2682 break; 2683 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2684 info = &dbg_port_dspt_ple_intf; 2685 rtw89_write8_mask(rtwdev, info->sel_addr, 2686 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2687 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2688 break; 2689 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2690 info = &dbg_port_dspt_flow_ctrl; 2691 rtw89_write8_mask(rtwdev, info->sel_addr, 2692 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2693 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2694 break; 2695 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2696 info = &dbg_port_pcie_txdma; 2697 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2698 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2699 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2700 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2701 seq_puts(m, "Enable pcie txdma dump.\n"); 2702 break; 2703 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2704 info = &dbg_port_pcie_rxdma; 2705 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2706 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2707 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2708 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2709 seq_puts(m, "Enable pcie rxdma dump.\n"); 2710 break; 2711 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2712 info = &dbg_port_pcie_cvt; 2713 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2714 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2715 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2716 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2717 seq_puts(m, "Enable pcie cvt dump.\n"); 2718 break; 2719 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 2720 info = &dbg_port_pcie_cxpl; 2721 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2722 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 2723 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 2724 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2725 seq_puts(m, "Enable pcie cxpl dump.\n"); 2726 break; 2727 case RTW89_DBG_PORT_SEL_PCIE_IO: 2728 info = &dbg_port_pcie_io; 2729 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2730 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 2731 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 2732 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2733 seq_puts(m, "Enable pcie io dump.\n"); 2734 break; 2735 case RTW89_DBG_PORT_SEL_PCIE_MISC: 2736 info = &dbg_port_pcie_misc; 2737 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2738 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 2739 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 2740 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2741 seq_puts(m, "Enable pcie misc dump.\n"); 2742 break; 2743 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 2744 info = &dbg_port_pcie_misc2; 2745 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 2746 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 2747 B_AX_PCIE_DBG_SEL_MASK); 2748 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 2749 seq_puts(m, "Enable pcie misc2 dump.\n"); 2750 break; 2751 default: 2752 seq_puts(m, "Dbg port select err\n"); 2753 return NULL; 2754 } 2755 2756 return info; 2757 } 2758 2759 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 2760 { 2761 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 2762 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 2763 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 2764 return false; 2765 if (rtwdev->chip->chip_id == RTL8852B && 2766 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2767 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2768 return false; 2769 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2770 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 2771 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 2772 return false; 2773 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2774 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 2775 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 2776 return false; 2777 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 2778 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 2779 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 2780 return false; 2781 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 2782 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2783 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2784 return false; 2785 2786 return true; 2787 } 2788 2789 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 2790 struct seq_file *m, u32 sel) 2791 { 2792 const struct rtw89_mac_dbg_port_info *info; 2793 u8 val8; 2794 u16 val16; 2795 u32 val32; 2796 u32 i; 2797 2798 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 2799 if (!info) { 2800 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 2801 return -EINVAL; 2802 } 2803 2804 #define case_DBG_SEL(__sel) \ 2805 case RTW89_DBG_PORT_SEL_##__sel: \ 2806 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 2807 break 2808 2809 switch (sel) { 2810 case_DBG_SEL(PTCL_C0); 2811 case_DBG_SEL(PTCL_C1); 2812 case_DBG_SEL(SCH_C0); 2813 case_DBG_SEL(SCH_C1); 2814 case_DBG_SEL(TMAC_C0); 2815 case_DBG_SEL(TMAC_C1); 2816 case_DBG_SEL(RMAC_C0); 2817 case_DBG_SEL(RMAC_C1); 2818 case_DBG_SEL(RMACST_C0); 2819 case_DBG_SEL(RMACST_C1); 2820 case_DBG_SEL(TRXPTCL_C0); 2821 case_DBG_SEL(TRXPTCL_C1); 2822 case_DBG_SEL(TX_INFOL_C0); 2823 case_DBG_SEL(TX_INFOH_C0); 2824 case_DBG_SEL(TX_INFOL_C1); 2825 case_DBG_SEL(TX_INFOH_C1); 2826 case_DBG_SEL(TXTF_INFOL_C0); 2827 case_DBG_SEL(TXTF_INFOH_C0); 2828 case_DBG_SEL(TXTF_INFOL_C1); 2829 case_DBG_SEL(TXTF_INFOH_C1); 2830 case_DBG_SEL(WDE_BUFMGN_FREEPG); 2831 case_DBG_SEL(WDE_BUFMGN_QUOTA); 2832 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 2833 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 2834 case_DBG_SEL(WDE_QUEMGN_PREPKT); 2835 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 2836 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 2837 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2838 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2839 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2840 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2841 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2842 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2843 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2844 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2845 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2846 case_DBG_SEL(PKTINFO); 2847 case_DBG_SEL(DSPT_HDT_TX0); 2848 case_DBG_SEL(DSPT_HDT_TX1); 2849 case_DBG_SEL(DSPT_HDT_TX2); 2850 case_DBG_SEL(DSPT_HDT_TX3); 2851 case_DBG_SEL(DSPT_HDT_TX4); 2852 case_DBG_SEL(DSPT_HDT_TX5); 2853 case_DBG_SEL(DSPT_HDT_TX6); 2854 case_DBG_SEL(DSPT_HDT_TX7); 2855 case_DBG_SEL(DSPT_HDT_TX8); 2856 case_DBG_SEL(DSPT_HDT_TX9); 2857 case_DBG_SEL(DSPT_HDT_TXA); 2858 case_DBG_SEL(DSPT_HDT_TXB); 2859 case_DBG_SEL(DSPT_HDT_TXC); 2860 case_DBG_SEL(DSPT_HDT_TXD); 2861 case_DBG_SEL(DSPT_HDT_TXE); 2862 case_DBG_SEL(DSPT_HDT_TXF); 2863 case_DBG_SEL(DSPT_CDT_TX0); 2864 case_DBG_SEL(DSPT_CDT_TX1); 2865 case_DBG_SEL(DSPT_CDT_TX3); 2866 case_DBG_SEL(DSPT_CDT_TX4); 2867 case_DBG_SEL(DSPT_CDT_TX5); 2868 case_DBG_SEL(DSPT_CDT_TX6); 2869 case_DBG_SEL(DSPT_CDT_TX7); 2870 case_DBG_SEL(DSPT_CDT_TX8); 2871 case_DBG_SEL(DSPT_CDT_TX9); 2872 case_DBG_SEL(DSPT_CDT_TXA); 2873 case_DBG_SEL(DSPT_CDT_TXB); 2874 case_DBG_SEL(DSPT_CDT_TXC); 2875 case_DBG_SEL(DSPT_HDT_RX0); 2876 case_DBG_SEL(DSPT_HDT_RX1); 2877 case_DBG_SEL(DSPT_HDT_RX2); 2878 case_DBG_SEL(DSPT_HDT_RX3); 2879 case_DBG_SEL(DSPT_HDT_RX4); 2880 case_DBG_SEL(DSPT_HDT_RX5); 2881 case_DBG_SEL(DSPT_CDT_RX_P0); 2882 case_DBG_SEL(DSPT_CDT_RX_P0_0); 2883 case_DBG_SEL(DSPT_CDT_RX_P0_1); 2884 case_DBG_SEL(DSPT_CDT_RX_P0_2); 2885 case_DBG_SEL(DSPT_CDT_RX_P1); 2886 case_DBG_SEL(DSPT_STF_CTRL); 2887 case_DBG_SEL(DSPT_ADDR_CTRL); 2888 case_DBG_SEL(DSPT_WDE_INTF); 2889 case_DBG_SEL(DSPT_PLE_INTF); 2890 case_DBG_SEL(DSPT_FLOW_CTRL); 2891 case_DBG_SEL(PCIE_TXDMA); 2892 case_DBG_SEL(PCIE_RXDMA); 2893 case_DBG_SEL(PCIE_CVT); 2894 case_DBG_SEL(PCIE_CXPL); 2895 case_DBG_SEL(PCIE_IO); 2896 case_DBG_SEL(PCIE_MISC); 2897 case_DBG_SEL(PCIE_MISC2); 2898 } 2899 2900 #undef case_DBG_SEL 2901 2902 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2903 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2904 2905 for (i = info->srt; i <= info->end; i++) { 2906 switch (info->sel_byte) { 2907 case 1: 2908 default: 2909 rtw89_write8_mask(rtwdev, info->sel_addr, 2910 info->sel_msk, i); 2911 seq_printf(m, "0x%02X: ", i); 2912 break; 2913 case 2: 2914 rtw89_write16_mask(rtwdev, info->sel_addr, 2915 info->sel_msk, i); 2916 seq_printf(m, "0x%04X: ", i); 2917 break; 2918 case 4: 2919 rtw89_write32_mask(rtwdev, info->sel_addr, 2920 info->sel_msk, i); 2921 seq_printf(m, "0x%04X: ", i); 2922 break; 2923 } 2924 2925 udelay(10); 2926 2927 switch (info->rd_byte) { 2928 case 1: 2929 default: 2930 val8 = rtw89_read8_mask(rtwdev, 2931 info->rd_addr, info->rd_msk); 2932 seq_printf(m, "0x%02X\n", val8); 2933 break; 2934 case 2: 2935 val16 = rtw89_read16_mask(rtwdev, 2936 info->rd_addr, info->rd_msk); 2937 seq_printf(m, "0x%04X\n", val16); 2938 break; 2939 case 4: 2940 val32 = rtw89_read32_mask(rtwdev, 2941 info->rd_addr, info->rd_msk); 2942 seq_printf(m, "0x%08X\n", val32); 2943 break; 2944 } 2945 } 2946 2947 return 0; 2948 } 2949 2950 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2951 struct seq_file *m) 2952 { 2953 u32 sel; 2954 int ret = 0; 2955 2956 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2957 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2958 if (!is_dbg_port_valid(rtwdev, sel)) 2959 continue; 2960 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2961 if (ret) { 2962 rtw89_err(rtwdev, 2963 "failed to dump debug port %d\n", sel); 2964 break; 2965 } 2966 } 2967 2968 return ret; 2969 } 2970 2971 static int 2972 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2973 { 2974 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2975 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2976 2977 if (debugfs_priv->dbgpkg_en.ss_dbg) 2978 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2979 if (debugfs_priv->dbgpkg_en.dle_dbg) 2980 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2981 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2982 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2983 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2984 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2985 if (debugfs_priv->dbgpkg_en.dbg_port) 2986 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2987 2988 return 0; 2989 }; 2990 2991 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2992 const char __user *user_buf, size_t count) 2993 { 2994 char *buf; 2995 u8 *bin; 2996 int num; 2997 int err = 0; 2998 2999 buf = memdup_user(user_buf, count); 3000 if (IS_ERR(buf)) 3001 return buf; 3002 3003 num = count / 2; 3004 bin = kmalloc(num, GFP_KERNEL); 3005 if (!bin) { 3006 err = -EFAULT; 3007 goto out; 3008 } 3009 3010 if (hex2bin(bin, buf, num)) { 3011 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3012 kfree(bin); 3013 err = -EINVAL; 3014 } 3015 3016 out: 3017 kfree(buf); 3018 3019 return err ? ERR_PTR(err) : bin; 3020 } 3021 3022 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3023 const char __user *user_buf, 3024 size_t count, loff_t *loff) 3025 { 3026 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3027 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3028 u8 *h2c; 3029 u16 h2c_len = count / 2; 3030 3031 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3032 if (IS_ERR(h2c)) 3033 return -EFAULT; 3034 3035 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3036 3037 kfree(h2c); 3038 3039 return count; 3040 } 3041 3042 static int 3043 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3044 { 3045 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3046 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3047 struct rtw89_early_h2c *early_h2c; 3048 int seq = 0; 3049 3050 mutex_lock(&rtwdev->mutex); 3051 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3052 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3053 mutex_unlock(&rtwdev->mutex); 3054 3055 return 0; 3056 } 3057 3058 static ssize_t 3059 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3060 size_t count, loff_t *loff) 3061 { 3062 struct seq_file *m = (struct seq_file *)filp->private_data; 3063 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3064 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3065 struct rtw89_early_h2c *early_h2c; 3066 u8 *h2c; 3067 u16 h2c_len = count / 2; 3068 3069 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3070 if (IS_ERR(h2c)) 3071 return -EFAULT; 3072 3073 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3074 kfree(h2c); 3075 rtw89_fw_free_all_early_h2c(rtwdev); 3076 goto out; 3077 } 3078 3079 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3080 if (!early_h2c) { 3081 kfree(h2c); 3082 return -EFAULT; 3083 } 3084 3085 early_h2c->h2c = h2c; 3086 early_h2c->h2c_len = h2c_len; 3087 3088 mutex_lock(&rtwdev->mutex); 3089 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3090 mutex_unlock(&rtwdev->mutex); 3091 3092 out: 3093 return count; 3094 } 3095 3096 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3097 { 3098 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3099 u16 pkt_id; 3100 int ret; 3101 3102 rtw89_leave_ps_mode(rtwdev); 3103 3104 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3105 if (ret) 3106 return ret; 3107 3108 /* intentionally, enqueue two pkt, but has only one pkt id */ 3109 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3110 ctrl_para.start_pktid = pkt_id; 3111 ctrl_para.end_pktid = pkt_id; 3112 ctrl_para.pkt_num = 1; /* start from 0 */ 3113 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3114 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3115 3116 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true)) 3117 return -EFAULT; 3118 3119 return 0; 3120 } 3121 3122 static int 3123 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3124 { 3125 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3126 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3127 3128 seq_printf(m, "%d\n", 3129 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3130 return 0; 3131 } 3132 3133 enum rtw89_dbg_crash_simulation_type { 3134 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3135 RTW89_DBG_SIM_CTRL_ERROR = 2, 3136 }; 3137 3138 static ssize_t 3139 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3140 size_t count, loff_t *loff) 3141 { 3142 struct seq_file *m = (struct seq_file *)filp->private_data; 3143 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3144 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3145 int (*sim)(struct rtw89_dev *rtwdev); 3146 u8 crash_type; 3147 int ret; 3148 3149 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3150 if (ret) 3151 return -EINVAL; 3152 3153 switch (crash_type) { 3154 case RTW89_DBG_SIM_CPU_EXCEPTION: 3155 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3156 return -EOPNOTSUPP; 3157 sim = rtw89_fw_h2c_trigger_cpu_exception; 3158 break; 3159 case RTW89_DBG_SIM_CTRL_ERROR: 3160 sim = rtw89_dbg_trigger_ctrl_error; 3161 break; 3162 default: 3163 return -EINVAL; 3164 } 3165 3166 mutex_lock(&rtwdev->mutex); 3167 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3168 ret = sim(rtwdev); 3169 mutex_unlock(&rtwdev->mutex); 3170 3171 if (ret) 3172 return ret; 3173 3174 return count; 3175 } 3176 3177 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3178 { 3179 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3180 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3181 3182 rtw89_btc_dump_info(rtwdev, m); 3183 3184 return 0; 3185 } 3186 3187 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3188 const char __user *user_buf, 3189 size_t count, loff_t *loff) 3190 { 3191 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3192 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3193 struct rtw89_btc *btc = &rtwdev->btc; 3194 bool btc_manual; 3195 3196 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 3197 goto out; 3198 3199 btc->ctrl.manual = btc_manual; 3200 out: 3201 return count; 3202 } 3203 3204 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 3205 const char __user *user_buf, 3206 size_t count, loff_t *loff) 3207 { 3208 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3209 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3210 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3211 bool fw_log_manual; 3212 3213 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3214 goto out; 3215 3216 mutex_lock(&rtwdev->mutex); 3217 fw_info->fw_log_enable = fw_log_manual; 3218 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3219 mutex_unlock(&rtwdev->mutex); 3220 out: 3221 return count; 3222 } 3223 3224 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3225 { 3226 static const char * const he_gi_str[] = { 3227 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3228 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3229 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3230 }; 3231 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3232 struct rate_info *rate = &rtwsta->ra_report.txrate; 3233 struct ieee80211_rx_status *status = &rtwsta->rx_status; 3234 struct seq_file *m = (struct seq_file *)data; 3235 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3236 struct rtw89_hal *hal = &rtwdev->hal; 3237 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3238 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3239 u8 evm_min, evm_max; 3240 u8 rssi; 3241 u8 snr; 3242 int i; 3243 3244 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 3245 3246 if (rate->flags & RATE_INFO_FLAGS_MCS) 3247 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3248 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3249 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3250 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3251 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3252 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3253 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3254 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3255 he_gi_str[rate->he_gi] : "N/A"); 3256 else 3257 seq_printf(m, "Legacy %d", rate->legacy); 3258 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 3259 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3260 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 3261 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 3262 sta->deflink.agg.max_rc_amsdu_len); 3263 3264 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 3265 3266 switch (status->encoding) { 3267 case RX_ENC_LEGACY: 3268 seq_printf(m, "Legacy %d", status->rate_idx + 3269 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3270 break; 3271 case RX_ENC_HT: 3272 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3273 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3274 break; 3275 case RX_ENC_VHT: 3276 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3277 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3278 break; 3279 case RX_ENC_HE: 3280 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3281 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3282 he_gi_str[rate->he_gi] : "N/A"); 3283 break; 3284 } 3285 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3286 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 3287 3288 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 3289 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3290 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 3291 for (i = 0; i < ant_num; i++) { 3292 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 3293 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3294 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3295 i + 1 == ant_num ? "" : ", "); 3296 } 3297 seq_puts(m, "]\n"); 3298 3299 seq_puts(m, "EVM: ["); 3300 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3301 evm_min = ewma_evm_read(&rtwsta->evm_min[i]); 3302 evm_max = ewma_evm_read(&rtwsta->evm_max[i]); 3303 3304 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3305 evm_min >> 2, (evm_min & 0x3) * 25, 3306 evm_max >> 2, (evm_max & 0x3) * 25); 3307 } 3308 seq_puts(m, "]\t"); 3309 3310 snr = ewma_snr_read(&rtwsta->avg_snr); 3311 seq_printf(m, "SNR: %u\n", snr); 3312 } 3313 3314 static void 3315 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3316 enum rtw89_hw_rate first_rate, int len) 3317 { 3318 int i; 3319 3320 for (i = 0; i < len; i++) 3321 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3322 pkt_stat->rx_rate_cnt[first_rate + i]); 3323 } 3324 3325 static const struct rtw89_rx_rate_cnt_info { 3326 enum rtw89_hw_rate first_rate; 3327 int len; 3328 int ext; 3329 const char *rate_mode; 3330 } rtw89_rx_rate_cnt_infos[] = { 3331 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 3332 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 3333 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 3334 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 3335 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 3336 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 3337 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 3338 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 3339 }; 3340 3341 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3342 { 3343 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3344 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3345 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3346 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3347 const struct rtw89_rx_rate_cnt_info *info; 3348 int i; 3349 3350 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 3351 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 3352 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3353 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 3354 stats->rx_tf_periodic); 3355 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3356 stats->rx_avg_len); 3357 3358 seq_puts(m, "RX count:\n"); 3359 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3360 info = &rtw89_rx_rate_cnt_infos[i]; 3361 seq_printf(m, "%10s [", info->rate_mode); 3362 rtw89_debug_append_rx_rate(m, pkt_stat, 3363 info->first_rate, info->len); 3364 if (info->ext) { 3365 seq_puts(m, "]["); 3366 rtw89_debug_append_rx_rate(m, pkt_stat, 3367 info->first_rate + info->len, info->ext); 3368 } 3369 seq_puts(m, "]\n"); 3370 } 3371 3372 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3373 3374 return 0; 3375 } 3376 3377 static void rtw89_dump_addr_cam(struct seq_file *m, 3378 struct rtw89_addr_cam_entry *addr_cam) 3379 { 3380 struct rtw89_sec_cam_entry *sec_entry; 3381 int i; 3382 3383 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3384 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3385 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3386 addr_cam->sec_cam_map); 3387 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 3388 sec_entry = addr_cam->sec_entries[i]; 3389 if (!sec_entry) 3390 continue; 3391 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3392 if (sec_entry->ext_key) 3393 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3394 seq_puts(m, "\n"); 3395 } 3396 } 3397 3398 __printf(3, 4) 3399 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3400 const char *fmt, ...) 3401 { 3402 struct rtw89_pktofld_info *info; 3403 struct va_format vaf; 3404 va_list args; 3405 3406 if (list_empty(pkt_list)) 3407 return; 3408 3409 va_start(args, fmt); 3410 vaf.va = &args; 3411 vaf.fmt = fmt; 3412 3413 seq_printf(m, "%pV", &vaf); 3414 3415 va_end(args); 3416 3417 list_for_each_entry(info, pkt_list, list) 3418 seq_printf(m, "%d ", info->id); 3419 3420 seq_puts(m, "\n"); 3421 } 3422 3423 static 3424 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3425 { 3426 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3427 struct seq_file *m = (struct seq_file *)data; 3428 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 3429 3430 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 3431 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3432 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 3433 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: "); 3434 } 3435 3436 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 3437 { 3438 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3439 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3440 struct rtw89_ba_cam_entry *entry; 3441 bool first = true; 3442 3443 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 3444 if (first) { 3445 seq_puts(m, "\tba_cam "); 3446 first = false; 3447 } else { 3448 seq_puts(m, ", "); 3449 } 3450 seq_printf(m, "tid[%u]=%d", entry->tid, 3451 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3452 } 3453 seq_puts(m, "\n"); 3454 } 3455 3456 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3457 { 3458 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3459 struct seq_file *m = (struct seq_file *)data; 3460 3461 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 3462 sta->tdls ? "(TDLS)" : ""); 3463 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 3464 rtw89_dump_ba_cam(m, rtwsta); 3465 } 3466 3467 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3468 { 3469 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3470 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3471 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3472 u8 idx; 3473 3474 mutex_lock(&rtwdev->mutex); 3475 3476 seq_puts(m, "map:\n"); 3477 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3478 rtwdev->mac_id_map); 3479 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3480 cam_info->addr_cam_map); 3481 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3482 cam_info->bssid_cam_map); 3483 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3484 cam_info->sec_cam_map); 3485 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3486 cam_info->ba_cam_map); 3487 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3488 rtwdev->pkt_offload); 3489 3490 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3491 if (!(rtwdev->chip->support_bands & BIT(idx))) 3492 continue; 3493 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3494 "\t\t[SCAN %u]: ", idx); 3495 } 3496 3497 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3498 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3499 3500 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3501 3502 mutex_unlock(&rtwdev->mutex); 3503 3504 return 0; 3505 } 3506 3507 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 3508 .cb_read = rtw89_debug_priv_read_reg_get, 3509 .cb_write = rtw89_debug_priv_read_reg_select, 3510 }; 3511 3512 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 3513 .cb_write = rtw89_debug_priv_write_reg_set, 3514 }; 3515 3516 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 3517 .cb_read = rtw89_debug_priv_read_rf_get, 3518 .cb_write = rtw89_debug_priv_read_rf_select, 3519 }; 3520 3521 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 3522 .cb_write = rtw89_debug_priv_write_rf_set, 3523 }; 3524 3525 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 3526 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 3527 }; 3528 3529 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 3530 .cb_read = rtw89_debug_priv_txpwr_table_get, 3531 }; 3532 3533 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 3534 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 3535 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 3536 }; 3537 3538 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 3539 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 3540 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 3541 }; 3542 3543 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 3544 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 3545 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 3546 }; 3547 3548 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 3549 .cb_write = rtw89_debug_priv_send_h2c_set, 3550 }; 3551 3552 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 3553 .cb_read = rtw89_debug_priv_early_h2c_get, 3554 .cb_write = rtw89_debug_priv_early_h2c_set, 3555 }; 3556 3557 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 3558 .cb_read = rtw89_debug_priv_fw_crash_get, 3559 .cb_write = rtw89_debug_priv_fw_crash_set, 3560 }; 3561 3562 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 3563 .cb_read = rtw89_debug_priv_btc_info_get, 3564 }; 3565 3566 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 3567 .cb_write = rtw89_debug_priv_btc_manual_set, 3568 }; 3569 3570 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 3571 .cb_write = rtw89_debug_fw_log_btc_manual_set, 3572 }; 3573 3574 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 3575 .cb_read = rtw89_debug_priv_phy_info_get, 3576 }; 3577 3578 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 3579 .cb_read = rtw89_debug_priv_stations_get, 3580 }; 3581 3582 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3583 do { \ 3584 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 3585 if (!debugfs_create_file(#name, mode, \ 3586 parent, &rtw89_debug_priv_ ##name, \ 3587 &file_ops_ ##fopname)) \ 3588 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3589 } while (0) 3590 3591 #define rtw89_debugfs_add_w(name) \ 3592 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3593 #define rtw89_debugfs_add_rw(name) \ 3594 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 3595 #define rtw89_debugfs_add_r(name) \ 3596 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 3597 3598 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 3599 { 3600 struct dentry *debugfs_topdir; 3601 3602 debugfs_topdir = debugfs_create_dir("rtw89", 3603 rtwdev->hw->wiphy->debugfsdir); 3604 3605 rtw89_debugfs_add_rw(read_reg); 3606 rtw89_debugfs_add_w(write_reg); 3607 rtw89_debugfs_add_rw(read_rf); 3608 rtw89_debugfs_add_w(write_rf); 3609 rtw89_debugfs_add_r(rf_reg_dump); 3610 rtw89_debugfs_add_r(txpwr_table); 3611 rtw89_debugfs_add_rw(mac_reg_dump); 3612 rtw89_debugfs_add_rw(mac_mem_dump); 3613 rtw89_debugfs_add_rw(mac_dbg_port_dump); 3614 rtw89_debugfs_add_w(send_h2c); 3615 rtw89_debugfs_add_rw(early_h2c); 3616 rtw89_debugfs_add_rw(fw_crash); 3617 rtw89_debugfs_add_r(btc_info); 3618 rtw89_debugfs_add_w(btc_manual); 3619 rtw89_debugfs_add_w(fw_log_manual); 3620 rtw89_debugfs_add_r(phy_info); 3621 rtw89_debugfs_add_r(stations); 3622 } 3623 #endif 3624 3625 #ifdef CONFIG_RTW89_DEBUGMSG 3626 void __rtw89_debug(struct rtw89_dev *rtwdev, 3627 enum rtw89_debug_mask mask, 3628 const char *fmt, ...) 3629 { 3630 struct va_format vaf = { 3631 .fmt = fmt, 3632 }; 3633 3634 va_list args; 3635 3636 va_start(args, fmt); 3637 vaf.va = &args; 3638 3639 if (rtw89_debug_mask & mask) 3640 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 3641 3642 va_end(args); 3643 } 3644 EXPORT_SYMBOL(__rtw89_debug); 3645 #endif 3646