1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_edid.h> 7 8 #include "i915_drv.h" 9 #include "intel_crtc_state_dump.h" 10 #include "intel_display_types.h" 11 #include "intel_hdmi.h" 12 #include "intel_vrr.h" 13 14 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 15 const struct drm_display_mode *mode) 16 { 17 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 18 "type: 0x%x flags: 0x%x\n", 19 mode->crtc_clock, 20 mode->crtc_hdisplay, mode->crtc_hsync_start, 21 mode->crtc_hsync_end, mode->crtc_htotal, 22 mode->crtc_vdisplay, mode->crtc_vsync_start, 23 mode->crtc_vsync_end, mode->crtc_vtotal, 24 mode->type, mode->flags); 25 } 26 27 static void 28 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 29 const char *id, unsigned int lane_count, 30 const struct intel_link_m_n *m_n) 31 { 32 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 33 34 drm_dbg_kms(&i915->drm, 35 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 36 id, lane_count, 37 m_n->data_m, m_n->data_n, 38 m_n->link_m, m_n->link_n, m_n->tu); 39 } 40 41 static void 42 intel_dump_infoframe(struct drm_i915_private *i915, 43 const union hdmi_infoframe *frame) 44 { 45 if (!drm_debug_enabled(DRM_UT_KMS)) 46 return; 47 48 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); 49 } 50 51 static void 52 intel_dump_dp_vsc_sdp(struct drm_i915_private *i915, 53 const struct drm_dp_vsc_sdp *vsc) 54 { 55 if (!drm_debug_enabled(DRM_UT_KMS)) 56 return; 57 58 drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc); 59 } 60 61 static void 62 intel_dump_buffer(struct drm_i915_private *i915, 63 const char *prefix, const u8 *buf, size_t len) 64 { 65 if (!drm_debug_enabled(DRM_UT_KMS)) 66 return; 67 68 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE, 69 16, 0, buf, len, false); 70 } 71 72 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 73 74 static const char * const output_type_str[] = { 75 OUTPUT_TYPE(UNUSED), 76 OUTPUT_TYPE(ANALOG), 77 OUTPUT_TYPE(DVO), 78 OUTPUT_TYPE(SDVO), 79 OUTPUT_TYPE(LVDS), 80 OUTPUT_TYPE(TVOUT), 81 OUTPUT_TYPE(HDMI), 82 OUTPUT_TYPE(DP), 83 OUTPUT_TYPE(EDP), 84 OUTPUT_TYPE(DSI), 85 OUTPUT_TYPE(DDI), 86 OUTPUT_TYPE(DP_MST), 87 }; 88 89 #undef OUTPUT_TYPE 90 91 static void snprintf_output_types(char *buf, size_t len, 92 unsigned int output_types) 93 { 94 char *str = buf; 95 int i; 96 97 str[0] = '\0'; 98 99 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 100 int r; 101 102 if ((output_types & BIT(i)) == 0) 103 continue; 104 105 r = snprintf(str, len, "%s%s", 106 str != buf ? "," : "", output_type_str[i]); 107 if (r >= len) 108 break; 109 str += r; 110 len -= r; 111 112 output_types &= ~BIT(i); 113 } 114 115 WARN_ON_ONCE(output_types != 0); 116 } 117 118 static const char * const output_format_str[] = { 119 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 120 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 121 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 122 }; 123 124 static const char *output_formats(enum intel_output_format format) 125 { 126 if (format >= ARRAY_SIZE(output_format_str)) 127 return "invalid"; 128 return output_format_str[format]; 129 } 130 131 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 132 { 133 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 134 struct drm_i915_private *i915 = to_i915(plane->base.dev); 135 const struct drm_framebuffer *fb = plane_state->hw.fb; 136 137 if (!fb) { 138 drm_dbg_kms(&i915->drm, 139 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 140 plane->base.base.id, plane->base.name, 141 str_yes_no(plane_state->uapi.visible)); 142 return; 143 } 144 145 drm_dbg_kms(&i915->drm, 146 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 147 plane->base.base.id, plane->base.name, 148 fb->base.id, fb->width, fb->height, &fb->format->format, 149 fb->modifier, str_yes_no(plane_state->uapi.visible)); 150 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", 151 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); 152 if (plane_state->uapi.visible) 153 drm_dbg_kms(&i915->drm, 154 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 155 DRM_RECT_FP_ARG(&plane_state->uapi.src), 156 DRM_RECT_ARG(&plane_state->uapi.dst)); 157 } 158 159 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 160 struct intel_atomic_state *state, 161 const char *context) 162 { 163 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 164 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 165 const struct intel_plane_state *plane_state; 166 struct intel_plane *plane; 167 char buf[64]; 168 int i; 169 170 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n", 171 crtc->base.base.id, crtc->base.name, 172 str_yes_no(pipe_config->hw.enable), context); 173 174 if (!pipe_config->hw.enable) 175 goto dump_planes; 176 177 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 178 drm_dbg_kms(&i915->drm, 179 "active: %s, output_types: %s (0x%x), output format: %s\n", 180 str_yes_no(pipe_config->hw.active), 181 buf, pipe_config->output_types, 182 output_formats(pipe_config->output_format)); 183 184 drm_dbg_kms(&i915->drm, 185 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 186 transcoder_name(pipe_config->cpu_transcoder), 187 pipe_config->pipe_bpp, pipe_config->dither); 188 189 drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n", 190 transcoder_name(pipe_config->mst_master_transcoder)); 191 192 drm_dbg_kms(&i915->drm, 193 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 194 transcoder_name(pipe_config->master_transcoder), 195 pipe_config->sync_mode_slaves_mask); 196 197 drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n", 198 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 199 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 200 pipe_config->bigjoiner_pipes); 201 202 drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n", 203 str_enabled_disabled(pipe_config->splitter.enable), 204 pipe_config->splitter.link_count, 205 pipe_config->splitter.pixel_overlap); 206 207 if (pipe_config->has_pch_encoder) 208 intel_dump_m_n_config(pipe_config, "fdi", 209 pipe_config->fdi_lanes, 210 &pipe_config->fdi_m_n); 211 212 if (intel_crtc_has_dp_encoder(pipe_config)) { 213 intel_dump_m_n_config(pipe_config, "dp m_n", 214 pipe_config->lane_count, 215 &pipe_config->dp_m_n); 216 intel_dump_m_n_config(pipe_config, "dp m2_n2", 217 pipe_config->lane_count, 218 &pipe_config->dp_m2_n2); 219 } 220 221 drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n", 222 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 223 224 drm_dbg_kms(&i915->drm, 225 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 226 pipe_config->has_audio, pipe_config->has_infoframe, 227 pipe_config->infoframes.enable); 228 229 if (pipe_config->infoframes.enable & 230 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 231 drm_dbg_kms(&i915->drm, "GCP: 0x%x\n", 232 pipe_config->infoframes.gcp); 233 if (pipe_config->infoframes.enable & 234 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 235 intel_dump_infoframe(i915, &pipe_config->infoframes.avi); 236 if (pipe_config->infoframes.enable & 237 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 238 intel_dump_infoframe(i915, &pipe_config->infoframes.spd); 239 if (pipe_config->infoframes.enable & 240 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 241 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi); 242 if (pipe_config->infoframes.enable & 243 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 244 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 245 if (pipe_config->infoframes.enable & 246 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 247 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 248 if (pipe_config->infoframes.enable & 249 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 250 intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc); 251 252 if (pipe_config->has_audio) 253 intel_dump_buffer(i915, "ELD: ", pipe_config->eld, 254 drm_eld_size(pipe_config->eld)); 255 256 drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 257 str_yes_no(pipe_config->vrr.enable), 258 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 259 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 260 pipe_config->vrr.flipline, 261 intel_vrr_vmin_vblank_start(pipe_config), 262 intel_vrr_vmax_vblank_start(pipe_config)); 263 264 drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n", 265 DRM_MODE_ARG(&pipe_config->hw.mode)); 266 drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n", 267 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 268 intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode); 269 drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n", 270 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 271 intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode); 272 drm_dbg_kms(&i915->drm, 273 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 274 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 275 pipe_config->pixel_rate); 276 277 drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n", 278 pipe_config->linetime, pipe_config->ips_linetime); 279 280 if (DISPLAY_VER(i915) >= 9) 281 drm_dbg_kms(&i915->drm, 282 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", 283 crtc->num_scalers, 284 pipe_config->scaler_state.scaler_users, 285 pipe_config->scaler_state.scaler_id, 286 pipe_config->hw.scaling_filter); 287 288 if (HAS_GMCH(i915)) 289 drm_dbg_kms(&i915->drm, 290 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 291 pipe_config->gmch_pfit.control, 292 pipe_config->gmch_pfit.pgm_ratios, 293 pipe_config->gmch_pfit.lvds_border_bits); 294 else 295 drm_dbg_kms(&i915->drm, 296 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 297 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 298 str_enabled_disabled(pipe_config->pch_pfit.enabled), 299 str_yes_no(pipe_config->pch_pfit.force_thru)); 300 301 drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n", 302 pipe_config->ips_enabled, pipe_config->double_wide, 303 pipe_config->has_drrs); 304 305 intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state); 306 307 if (IS_CHERRYVIEW(i915)) 308 drm_dbg_kms(&i915->drm, 309 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 310 pipe_config->cgm_mode, pipe_config->gamma_mode, 311 pipe_config->gamma_enable, pipe_config->csc_enable); 312 else 313 drm_dbg_kms(&i915->drm, 314 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 315 pipe_config->csc_mode, pipe_config->gamma_mode, 316 pipe_config->gamma_enable, pipe_config->csc_enable); 317 318 drm_dbg_kms(&i915->drm, "pre csc lut: %s%d entries, post csc lut: %d entries\n", 319 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut == 320 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "", 321 pipe_config->pre_csc_lut ? 322 drm_color_lut_size(pipe_config->pre_csc_lut) : 0, 323 pipe_config->post_csc_lut ? 324 drm_color_lut_size(pipe_config->post_csc_lut) : 0); 325 326 dump_planes: 327 if (!state) 328 return; 329 330 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 331 if (plane->pipe == crtc->pipe) 332 intel_dump_plane_state(plane_state); 333 } 334 } 335