1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_macvlan.h> 31 #include <linux/if_bridge.h> 32 #include <linux/clocksource.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <net/pkt_cls.h> 36 #include <net/pkt_sched.h> 37 #include <net/tc_act/tc_gact.h> 38 #include <net/tc_act/tc_mirred.h> 39 #include <net/udp_tunnel.h> 40 #include <net/xdp_sock.h> 41 #include <linux/bitfield.h> 42 #include "i40e_type.h" 43 #include "i40e_prototype.h" 44 #include <linux/net/intel/i40e_client.h> 45 #include <linux/avf/virtchnl.h> 46 #include "i40e_virtchnl_pf.h" 47 #include "i40e_txrx.h" 48 #include "i40e_dcb.h" 49 50 /* Useful i40e defaults */ 51 #define I40E_MAX_VEB 16 52 53 #define I40E_MAX_NUM_DESCRIPTORS 4096 54 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 55 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 56 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 57 #define I40E_MIN_NUM_DESCRIPTORS 64 58 #define I40E_MIN_MSIX 2 59 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 60 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 61 /* max 16 qps */ 62 #define i40e_default_queues_per_vmdq(pf) \ 63 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 64 #define I40E_DEFAULT_QUEUES_PER_VF 4 65 #define I40E_MAX_VF_QUEUES 16 66 #define i40e_pf_get_max_q_per_tc(pf) \ 67 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 68 #define I40E_FDIR_RING_COUNT 32 69 #define I40E_MAX_AQ_BUF_SIZE 4096 70 #define I40E_AQ_LEN 256 71 #define I40E_MIN_ARQ_LEN 1 72 #define I40E_MIN_ASQ_LEN 2 73 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 74 #define I40E_MAX_USER_PRIORITY 8 75 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 76 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 77 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 78 79 #define I40E_NVM_VERSION_LO_SHIFT 0 80 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 81 #define I40E_NVM_VERSION_HI_SHIFT 12 82 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 83 #define I40E_OEM_VER_BUILD_MASK 0xffff 84 #define I40E_OEM_VER_PATCH_MASK 0xff 85 #define I40E_OEM_VER_BUILD_SHIFT 8 86 #define I40E_OEM_VER_SHIFT 24 87 #define I40E_PHY_DEBUG_ALL \ 88 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 89 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 90 91 #define I40E_OEM_EETRACK_ID 0xffffffff 92 #define I40E_OEM_GEN_SHIFT 24 93 #define I40E_OEM_SNAP_MASK 0x00ff0000 94 #define I40E_OEM_SNAP_SHIFT 16 95 #define I40E_OEM_RELEASE_MASK 0x0000ffff 96 97 #define I40E_RX_DESC(R, i) \ 98 (&(((union i40e_rx_desc *)((R)->desc))[i])) 99 #define I40E_TX_DESC(R, i) \ 100 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 101 #define I40E_TX_CTXTDESC(R, i) \ 102 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 103 #define I40E_TX_FDIRDESC(R, i) \ 104 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 105 106 /* BW rate limiting */ 107 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 108 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 109 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 110 111 /* driver state flags */ 112 enum i40e_state_t { 113 __I40E_TESTING, 114 __I40E_CONFIG_BUSY, 115 __I40E_CONFIG_DONE, 116 __I40E_DOWN, 117 __I40E_SERVICE_SCHED, 118 __I40E_ADMINQ_EVENT_PENDING, 119 __I40E_MDD_EVENT_PENDING, 120 __I40E_VFLR_EVENT_PENDING, 121 __I40E_RESET_RECOVERY_PENDING, 122 __I40E_TIMEOUT_RECOVERY_PENDING, 123 __I40E_MISC_IRQ_REQUESTED, 124 __I40E_RESET_INTR_RECEIVED, 125 __I40E_REINIT_REQUESTED, 126 __I40E_PF_RESET_REQUESTED, 127 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 128 __I40E_CORE_RESET_REQUESTED, 129 __I40E_GLOBAL_RESET_REQUESTED, 130 __I40E_EMP_RESET_INTR_RECEIVED, 131 __I40E_SUSPENDED, 132 __I40E_PTP_TX_IN_PROGRESS, 133 __I40E_BAD_EEPROM, 134 __I40E_DOWN_REQUESTED, 135 __I40E_FD_FLUSH_REQUESTED, 136 __I40E_FD_ATR_AUTO_DISABLED, 137 __I40E_FD_SB_AUTO_DISABLED, 138 __I40E_RESET_FAILED, 139 __I40E_PORT_SUSPENDED, 140 __I40E_VF_DISABLE, 141 __I40E_MACVLAN_SYNC_PENDING, 142 __I40E_TEMP_LINK_POLLING, 143 __I40E_CLIENT_SERVICE_REQUESTED, 144 __I40E_CLIENT_L2_CHANGE, 145 __I40E_CLIENT_RESET, 146 __I40E_VIRTCHNL_OP_PENDING, 147 __I40E_RECOVERY_MODE, 148 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 149 __I40E_IN_REMOVE, 150 __I40E_VFS_RELEASING, 151 /* This must be last as it determines the size of the BITMAP */ 152 __I40E_STATE_SIZE__, 153 }; 154 155 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 156 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 157 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 158 159 /* VSI state flags */ 160 enum i40e_vsi_state_t { 161 __I40E_VSI_DOWN, 162 __I40E_VSI_NEEDS_RESTART, 163 __I40E_VSI_SYNCING_FILTERS, 164 __I40E_VSI_OVERFLOW_PROMISC, 165 __I40E_VSI_REINIT_REQUESTED, 166 __I40E_VSI_DOWN_REQUESTED, 167 __I40E_VSI_RELEASING, 168 /* This must be last as it determines the size of the BITMAP */ 169 __I40E_VSI_STATE_SIZE__, 170 }; 171 172 enum i40e_interrupt_policy { 173 I40E_INTERRUPT_BEST_CASE, 174 I40E_INTERRUPT_MEDIUM, 175 I40E_INTERRUPT_LOWEST 176 }; 177 178 struct i40e_lump_tracking { 179 u16 num_entries; 180 u16 list[]; 181 #define I40E_PILE_VALID_BIT 0x8000 182 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 183 }; 184 185 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 186 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 187 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 188 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 189 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 190 191 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 192 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 193 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 194 195 enum i40e_fd_stat_idx { 196 I40E_FD_STAT_ATR, 197 I40E_FD_STAT_SB, 198 I40E_FD_STAT_ATR_TUNNEL, 199 I40E_FD_STAT_PF_COUNT 200 }; 201 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 202 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 204 #define I40E_FD_SB_STAT_IDX(pf_id) \ 205 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 206 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 207 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 208 209 /* The following structure contains the data parsed from the user-defined 210 * field of the ethtool_rx_flow_spec structure. 211 */ 212 struct i40e_rx_flow_userdef { 213 bool flex_filter; 214 u16 flex_word; 215 u16 flex_offset; 216 }; 217 218 struct i40e_fdir_filter { 219 struct hlist_node fdir_node; 220 /* filter ipnut set */ 221 u8 flow_type; 222 u8 ipl4_proto; 223 /* TX packet view of src and dst */ 224 __be32 dst_ip; 225 __be32 src_ip; 226 __be32 dst_ip6[4]; 227 __be32 src_ip6[4]; 228 __be16 src_port; 229 __be16 dst_port; 230 __be32 sctp_v_tag; 231 232 __be16 vlan_etype; 233 __be16 vlan_tag; 234 /* Flexible data to match within the packet payload */ 235 __be16 flex_word; 236 u16 flex_offset; 237 bool flex_filter; 238 239 /* filter control */ 240 u16 q_index; 241 u8 flex_off; 242 u8 pctype; 243 u16 dest_vsi; 244 u8 dest_ctl; 245 u8 fd_status; 246 u16 cnt_index; 247 u32 fd_id; 248 }; 249 250 #define I40E_CLOUD_FIELD_OMAC BIT(0) 251 #define I40E_CLOUD_FIELD_IMAC BIT(1) 252 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 253 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 254 #define I40E_CLOUD_FIELD_IIP BIT(4) 255 256 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 257 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 258 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 259 I40E_CLOUD_FIELD_IVLAN) 260 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 261 I40E_CLOUD_FIELD_TEN_ID) 262 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 263 I40E_CLOUD_FIELD_IMAC | \ 264 I40E_CLOUD_FIELD_TEN_ID) 265 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 266 I40E_CLOUD_FIELD_IVLAN | \ 267 I40E_CLOUD_FIELD_TEN_ID) 268 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 269 270 struct i40e_cloud_filter { 271 struct hlist_node cloud_node; 272 unsigned long cookie; 273 /* cloud filter input set follows */ 274 u8 dst_mac[ETH_ALEN]; 275 u8 src_mac[ETH_ALEN]; 276 __be16 vlan_id; 277 u16 seid; /* filter control */ 278 __be16 dst_port; 279 __be16 src_port; 280 u32 tenant_id; 281 union { 282 struct { 283 struct in_addr dst_ip; 284 struct in_addr src_ip; 285 } v4; 286 struct { 287 struct in6_addr dst_ip6; 288 struct in6_addr src_ip6; 289 } v6; 290 } ip; 291 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 292 #define src_ipv6 ip.v6.src_ip6.s6_addr32 293 #define dst_ipv4 ip.v4.dst_ip.s_addr 294 #define src_ipv4 ip.v4.src_ip.s_addr 295 u16 n_proto; /* Ethernet Protocol */ 296 u8 ip_proto; /* IPPROTO value */ 297 u8 flags; 298 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 299 u8 tunnel_type; 300 }; 301 302 #define I40E_DCB_PRIO_TYPE_STRICT 0 303 #define I40E_DCB_PRIO_TYPE_ETS 1 304 #define I40E_DCB_STRICT_PRIO_CREDITS 127 305 /* DCB per TC information data structure */ 306 struct i40e_tc_info { 307 u16 qoffset; /* Queue offset from base queue */ 308 u16 qcount; /* Total Queues */ 309 u8 netdev_tc; /* Netdev TC index if netdev associated */ 310 }; 311 312 /* TC configuration data structure */ 313 struct i40e_tc_configuration { 314 u8 numtc; /* Total number of enabled TCs */ 315 u8 enabled_tc; /* TC map */ 316 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 317 }; 318 319 #define I40E_UDP_PORT_INDEX_UNUSED 255 320 struct i40e_udp_port_config { 321 /* AdminQ command interface expects port number in Host byte order */ 322 u16 port; 323 u8 type; 324 u8 filter_index; 325 }; 326 327 #define I40_DDP_FLASH_REGION 100 328 #define I40E_PROFILE_INFO_SIZE 48 329 #define I40E_MAX_PROFILE_NUM 16 330 #define I40E_PROFILE_LIST_SIZE \ 331 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 332 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 333 #define I40E_DDP_PROFILE_NAME_MAX 64 334 335 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 336 bool is_add); 337 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 338 339 struct i40e_ddp_profile_list { 340 u32 p_count; 341 struct i40e_profile_info p_info[]; 342 }; 343 344 struct i40e_ddp_old_profile_list { 345 struct list_head list; 346 size_t old_ddp_size; 347 u8 old_ddp_buf[]; 348 }; 349 350 /* macros related to FLX_PIT */ 351 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 352 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 353 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 354 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 355 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 356 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 357 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 358 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 360 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 361 I40E_FLEX_SET_FSIZE(fsize) | \ 362 I40E_FLEX_SET_SRC_WORD(src)) 363 364 365 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 366 367 /* macros related to GLQF_ORT */ 368 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 369 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 370 I40E_GLQF_ORT_PIT_INDX_MASK) 371 372 #define I40E_ORT_SET_COUNT(count) (((count) << \ 373 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 374 I40E_GLQF_ORT_FIELD_CNT_MASK) 375 376 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 377 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 378 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 379 380 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 381 I40E_ORT_SET_COUNT(count) | \ 382 I40E_ORT_SET_PAYLOAD(payload)) 383 384 #define I40E_L3_GLQF_ORT_IDX 34 385 #define I40E_L4_GLQF_ORT_IDX 35 386 387 /* Flex PIT register index */ 388 #define I40E_FLEX_PIT_IDX_START_L3 3 389 #define I40E_FLEX_PIT_IDX_START_L4 6 390 391 #define I40E_FLEX_PIT_TABLE_SIZE 3 392 393 #define I40E_FLEX_DEST_UNUSED 63 394 395 #define I40E_FLEX_INDEX_ENTRIES 8 396 397 /* Flex MASK to disable all flexible entries */ 398 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 399 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 400 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 401 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 402 403 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 404 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 405 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 406 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 407 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 408 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 409 410 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 411 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 412 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 413 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 414 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 415 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 416 417 struct i40e_flex_pit { 418 struct list_head list; 419 u16 src_offset; 420 u8 pit_index; 421 }; 422 423 struct i40e_fwd_adapter { 424 struct net_device *netdev; 425 int bit_no; 426 }; 427 428 struct i40e_channel { 429 struct list_head list; 430 bool initialized; 431 u8 type; 432 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 433 u16 stat_counter_idx; 434 u16 base_queue; 435 u16 num_queue_pairs; /* Requested by user */ 436 u16 seid; 437 438 u8 enabled_tc; 439 struct i40e_aqc_vsi_properties_data info; 440 441 u64 max_tx_rate; 442 struct i40e_fwd_adapter *fwd; 443 444 /* track this channel belongs to which VSI */ 445 struct i40e_vsi *parent_vsi; 446 }; 447 448 struct i40e_ptp_pins_settings; 449 450 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 451 { 452 return !!ch->fwd; 453 } 454 455 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 456 { 457 if (i40e_is_channel_macvlan(ch)) 458 return ch->fwd->netdev->dev_addr; 459 else 460 return NULL; 461 } 462 463 /* struct that defines the Ethernet device */ 464 struct i40e_pf { 465 struct pci_dev *pdev; 466 struct i40e_hw hw; 467 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 468 struct msix_entry *msix_entries; 469 bool fc_autoneg_status; 470 471 u16 eeprom_version; 472 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 473 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 474 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 475 u16 num_req_vfs; /* num VFs requested for this PF */ 476 u16 num_vf_qps; /* num queue pairs per VF */ 477 u16 num_lan_qps; /* num lan queues this PF has set up */ 478 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 479 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 480 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 481 int iwarp_base_vector; 482 int queues_left; /* queues left unclaimed */ 483 u16 alloc_rss_size; /* allocated RSS queues */ 484 u16 rss_size_max; /* HW defined max RSS queues */ 485 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 486 u16 num_alloc_vsi; /* num VSIs this driver supports */ 487 u8 atr_sample_rate; 488 bool wol_en; 489 490 struct hlist_head fdir_filter_list; 491 u16 fdir_pf_active_filters; 492 unsigned long fd_flush_timestamp; 493 u32 fd_flush_cnt; 494 u32 fd_add_err; 495 u32 fd_atr_cnt; 496 497 /* Book-keeping of side-band filter count per flow-type. 498 * This is used to detect and handle input set changes for 499 * respective flow-type. 500 */ 501 u16 fd_tcp4_filter_cnt; 502 u16 fd_udp4_filter_cnt; 503 u16 fd_sctp4_filter_cnt; 504 u16 fd_ip4_filter_cnt; 505 506 u16 fd_tcp6_filter_cnt; 507 u16 fd_udp6_filter_cnt; 508 u16 fd_sctp6_filter_cnt; 509 u16 fd_ip6_filter_cnt; 510 511 /* Flexible filter table values that need to be programmed into 512 * hardware, which expects L3 and L4 to be programmed separately. We 513 * need to ensure that the values are in ascended order and don't have 514 * duplicates, so we track each L3 and L4 values in separate lists. 515 */ 516 struct list_head l3_flex_pit_list; 517 struct list_head l4_flex_pit_list; 518 519 struct udp_tunnel_nic_shared udp_tunnel_shared; 520 struct udp_tunnel_nic_info udp_tunnel_nic; 521 522 struct hlist_head cloud_filter_list; 523 u16 num_cloud_filters; 524 525 enum i40e_interrupt_policy int_policy; 526 u16 rx_itr_default; 527 u16 tx_itr_default; 528 u32 msg_enable; 529 char int_name[I40E_INT_NAME_STR_LEN]; 530 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 531 unsigned long service_timer_period; 532 unsigned long service_timer_previous; 533 struct timer_list service_timer; 534 struct work_struct service_task; 535 536 u32 hw_features; 537 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 538 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 539 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 540 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 541 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 542 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 543 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 544 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 545 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 546 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 547 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 548 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 549 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 550 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 551 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 552 #define I40E_HW_STOP_FW_LLDP BIT(16) 553 #define I40E_HW_PORT_ID_VALID BIT(17) 554 #define I40E_HW_RESTART_AUTONEG BIT(18) 555 556 u32 flags; 557 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 558 #define I40E_FLAG_MSI_ENABLED BIT(1) 559 #define I40E_FLAG_MSIX_ENABLED BIT(2) 560 #define I40E_FLAG_RSS_ENABLED BIT(3) 561 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 562 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 563 #define I40E_FLAG_DCB_CAPABLE BIT(6) 564 #define I40E_FLAG_DCB_ENABLED BIT(7) 565 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 566 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 567 #define I40E_FLAG_MFP_ENABLED BIT(10) 568 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 569 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 570 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 571 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 572 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 573 #define I40E_FLAG_LEGACY_RX BIT(16) 574 #define I40E_FLAG_PTP BIT(17) 575 #define I40E_FLAG_IWARP_ENABLED BIT(18) 576 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 577 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 578 #define I40E_FLAG_TC_MQPRIO BIT(21) 579 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 580 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 581 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 582 #define I40E_FLAG_RS_FEC BIT(25) 583 #define I40E_FLAG_BASE_R_FEC BIT(26) 584 #define I40E_FLAG_VF_VLAN_PRUNING BIT(27) 585 /* TOTAL_PORT_SHUTDOWN 586 * Allows to physically disable the link on the NIC's port. 587 * If enabled, (after link down request from the OS) 588 * no link, traffic or led activity is possible on that port. 589 * 590 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 591 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 592 * and cannot be disabled by system admin at that time. 593 * The functionalities are exclusive in terms of configuration, but they also 594 * have similar behavior (allowing to disable physical link of the port), 595 * with following differences: 596 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 597 * supported by whole family of 7xx Intel Ethernet Controllers 598 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 599 * only if motherboard's BIOS and NIC's FW has support of it 600 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 601 * by sending phy_type=0 to NIC's FW 602 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 603 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 604 * in abilities field of i40e_aq_set_phy_config structure 605 */ 606 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 607 608 struct i40e_client_instance *cinst; 609 bool stat_offsets_loaded; 610 struct i40e_hw_port_stats stats; 611 struct i40e_hw_port_stats stats_offsets; 612 u32 tx_timeout_count; 613 u32 tx_timeout_recovery_level; 614 unsigned long tx_timeout_last_recovery; 615 u32 tx_sluggish_count; 616 u32 hw_csum_rx_error; 617 u32 led_status; 618 u16 corer_count; /* Core reset count */ 619 u16 globr_count; /* Global reset count */ 620 u16 empr_count; /* EMP reset count */ 621 u16 pfr_count; /* PF reset count */ 622 u16 sw_int_count; /* SW interrupt count */ 623 624 struct mutex switch_mutex; 625 u16 lan_vsi; /* our default LAN VSI */ 626 u16 lan_veb; /* initial relay, if exists */ 627 #define I40E_NO_VEB 0xffff 628 #define I40E_NO_VSI 0xffff 629 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 630 struct i40e_vsi **vsi; 631 struct i40e_veb *veb[I40E_MAX_VEB]; 632 633 struct i40e_lump_tracking *qp_pile; 634 struct i40e_lump_tracking *irq_pile; 635 636 /* switch config info */ 637 u16 pf_seid; 638 u16 main_vsi_seid; 639 u16 mac_seid; 640 struct kobject *switch_kobj; 641 #ifdef CONFIG_DEBUG_FS 642 struct dentry *i40e_dbg_pf; 643 #endif /* CONFIG_DEBUG_FS */ 644 bool cur_promisc; 645 646 u16 instance; /* A unique number per i40e_pf instance in the system */ 647 648 /* sr-iov config info */ 649 struct i40e_vf *vf; 650 int num_alloc_vfs; /* actual number of VFs allocated */ 651 u32 vf_aq_requests; 652 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 653 654 /* DCBx/DCBNL capability for PF that indicates 655 * whether DCBx is managed by firmware or host 656 * based agent (LLDPAD). Also, indicates what 657 * flavor of DCBx protocol (IEEE/CEE) is supported 658 * by the device. For now we're supporting IEEE 659 * mode only. 660 */ 661 u16 dcbx_cap; 662 663 struct i40e_filter_control_settings filter_settings; 664 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 665 struct i40e_dcbx_config tmp_cfg; 666 667 /* GPIO defines used by PTP */ 668 #define I40E_SDP3_2 18 669 #define I40E_SDP3_3 19 670 #define I40E_GPIO_4 20 671 #define I40E_LED2_0 26 672 #define I40E_LED2_1 27 673 #define I40E_LED3_0 28 674 #define I40E_LED3_1 29 675 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 676 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 677 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 678 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 679 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 680 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 681 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 682 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 683 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 684 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 685 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 686 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 687 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 688 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 689 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 690 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 691 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 692 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 693 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 694 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 695 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 696 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 697 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 698 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 699 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 700 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 701 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 702 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 703 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 704 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 705 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 706 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 707 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 708 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 709 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 710 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 711 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 712 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 713 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 714 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 715 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 716 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 717 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 718 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 719 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 720 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 721 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 722 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 723 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 724 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 725 #define I40E_PRTTSYN_AUX_1_INSTNT \ 726 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 727 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 728 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 729 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 730 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 731 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 732 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 733 #define I40E_PTP_2_SEC_DELAY 2 734 735 struct ptp_clock *ptp_clock; 736 struct ptp_clock_info ptp_caps; 737 struct sk_buff *ptp_tx_skb; 738 unsigned long ptp_tx_start; 739 struct hwtstamp_config tstamp_config; 740 struct timespec64 ptp_prev_hw_time; 741 struct work_struct ptp_pps_work; 742 struct work_struct ptp_extts0_work; 743 struct work_struct ptp_extts1_work; 744 ktime_t ptp_reset_start; 745 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 746 u32 ptp_adj_mult; 747 u32 tx_hwtstamp_timeouts; 748 u32 tx_hwtstamp_skipped; 749 u32 rx_hwtstamp_cleared; 750 u32 latch_event_flags; 751 u64 ptp_pps_start; 752 u32 pps_delay; 753 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 754 struct ptp_pin_desc ptp_pin[3]; 755 unsigned long latch_events[4]; 756 bool ptp_tx; 757 bool ptp_rx; 758 struct i40e_ptp_pins_settings *ptp_pins; 759 u16 rss_table_size; /* HW RSS table size */ 760 u32 max_bw; 761 u32 min_bw; 762 763 u32 ioremap_len; 764 u32 fd_inv; 765 u16 phy_led_val; 766 767 u16 override_q_count; 768 u16 last_sw_conf_flags; 769 u16 last_sw_conf_valid_flags; 770 /* List to keep previous DDP profiles to be rolled back in the future */ 771 struct list_head ddp_old_prof; 772 }; 773 774 /** 775 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 776 * @macaddr: the MAC Address as the base key 777 * 778 * Simply copies the address and returns it as a u64 for hashing 779 **/ 780 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 781 { 782 u64 key = 0; 783 784 ether_addr_copy((u8 *)&key, macaddr); 785 return key; 786 } 787 788 enum i40e_filter_state { 789 I40E_FILTER_INVALID = 0, /* Invalid state */ 790 I40E_FILTER_NEW, /* New, not sent to FW yet */ 791 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 792 I40E_FILTER_FAILED, /* Rejected by FW */ 793 I40E_FILTER_REMOVE, /* To be removed */ 794 /* There is no 'removed' state; the filter struct is freed */ 795 }; 796 struct i40e_mac_filter { 797 struct hlist_node hlist; 798 u8 macaddr[ETH_ALEN]; 799 #define I40E_VLAN_ANY -1 800 s16 vlan; 801 enum i40e_filter_state state; 802 }; 803 804 /* Wrapper structure to keep track of filters while we are preparing to send 805 * firmware commands. We cannot send firmware commands while holding a 806 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 807 * a separate structure, which will track the state change and update the real 808 * filter while under lock. We can't simply hold the filters in a separate 809 * list, as this opens a window for a race condition when adding new MAC 810 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 811 */ 812 struct i40e_new_mac_filter { 813 struct hlist_node hlist; 814 struct i40e_mac_filter *f; 815 816 /* Track future changes to state separately */ 817 enum i40e_filter_state state; 818 }; 819 820 struct i40e_veb { 821 struct i40e_pf *pf; 822 u16 idx; 823 u16 veb_idx; /* index of VEB parent */ 824 u16 seid; 825 u16 uplink_seid; 826 u16 stats_idx; /* index of VEB parent */ 827 u8 enabled_tc; 828 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 829 u16 flags; 830 u16 bw_limit; 831 u8 bw_max_quanta; 832 bool is_abs_credits; 833 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 834 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 835 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 836 struct kobject *kobj; 837 bool stat_offsets_loaded; 838 struct i40e_eth_stats stats; 839 struct i40e_eth_stats stats_offsets; 840 struct i40e_veb_tc_stats tc_stats; 841 struct i40e_veb_tc_stats tc_stats_offsets; 842 }; 843 844 /* struct that defines a VSI, associated with a dev */ 845 struct i40e_vsi { 846 struct net_device *netdev; 847 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 848 bool netdev_registered; 849 bool stat_offsets_loaded; 850 851 u32 current_netdev_flags; 852 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 853 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 854 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 855 unsigned long flags; 856 857 /* Per VSI lock to protect elements/hash (MAC filter) */ 858 spinlock_t mac_filter_hash_lock; 859 /* Fixed size hash table with 2^8 buckets for MAC filters */ 860 DECLARE_HASHTABLE(mac_filter_hash, 8); 861 bool has_vlan_filter; 862 863 /* VSI stats */ 864 struct rtnl_link_stats64 net_stats; 865 struct rtnl_link_stats64 net_stats_offsets; 866 struct i40e_eth_stats eth_stats; 867 struct i40e_eth_stats eth_stats_offsets; 868 u64 tx_restart; 869 u64 tx_busy; 870 u64 tx_linearize; 871 u64 tx_force_wb; 872 u64 tx_stopped; 873 u64 rx_buf_failed; 874 u64 rx_page_failed; 875 u64 rx_page_reuse; 876 u64 rx_page_alloc; 877 u64 rx_page_waive; 878 u64 rx_page_busy; 879 880 /* These are containers of ring pointers, allocated at run-time */ 881 struct i40e_ring **rx_rings; 882 struct i40e_ring **tx_rings; 883 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 884 885 u32 active_filters; 886 u32 promisc_threshold; 887 888 u16 work_limit; 889 u16 int_rate_limit; /* value in usecs */ 890 891 u16 rss_table_size; /* HW RSS table size */ 892 u16 rss_size; /* Allocated RSS queues */ 893 u8 *rss_hkey_user; /* User configured hash keys */ 894 u8 *rss_lut_user; /* User configured lookup table entries */ 895 896 897 u16 max_frame; 898 u16 rx_buf_len; 899 900 struct bpf_prog *xdp_prog; 901 902 /* List of q_vectors allocated to this VSI */ 903 struct i40e_q_vector **q_vectors; 904 int num_q_vectors; 905 int base_vector; 906 bool irqs_ready; 907 908 u16 seid; /* HW index of this VSI (absolute index) */ 909 u16 id; /* VSI number */ 910 u16 uplink_seid; 911 912 u16 base_queue; /* vsi's first queue in hw array */ 913 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 914 u16 req_queue_pairs; /* User requested queue pairs */ 915 u16 num_queue_pairs; /* Used tx and rx pairs */ 916 u16 num_tx_desc; 917 u16 num_rx_desc; 918 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 919 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 920 921 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 922 struct i40e_tc_configuration tc_config; 923 struct i40e_aqc_vsi_properties_data info; 924 925 /* VSI BW limit (absolute across all TCs) */ 926 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 927 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 928 929 /* Relative TC credits across VSIs */ 930 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 931 /* TC BW limit credits within VSI */ 932 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 933 /* TC BW limit max quanta within VSI */ 934 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 935 936 struct i40e_pf *back; /* Backreference to associated PF */ 937 u16 idx; /* index in pf->vsi[] */ 938 u16 veb_idx; /* index of VEB parent */ 939 struct kobject *kobj; /* sysfs object */ 940 bool current_isup; /* Sync 'link up' logging */ 941 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 942 943 /* channel specific fields */ 944 u16 cnt_q_avail; /* num of queues available for channel usage */ 945 u16 orig_rss_size; 946 u16 current_rss_size; 947 bool reconfig_rss; 948 949 u16 next_base_queue; /* next queue to be used for channel setup */ 950 951 struct list_head ch_list; 952 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 953 954 /* macvlan fields */ 955 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 956 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 957 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 958 struct list_head macvlan_list; 959 int macvlan_cnt; 960 961 void *priv; /* client driver data reference. */ 962 963 /* VSI specific handlers */ 964 irqreturn_t (*irq_handler)(int irq, void *data); 965 966 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 967 } ____cacheline_internodealigned_in_smp; 968 969 struct i40e_netdev_priv { 970 struct i40e_vsi *vsi; 971 }; 972 973 extern struct ida i40e_client_ida; 974 975 /* struct that defines an interrupt vector */ 976 struct i40e_q_vector { 977 struct i40e_vsi *vsi; 978 979 u16 v_idx; /* index in the vsi->q_vector array. */ 980 u16 reg_idx; /* register index of the interrupt */ 981 982 struct napi_struct napi; 983 984 struct i40e_ring_container rx; 985 struct i40e_ring_container tx; 986 987 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 988 u8 num_ringpairs; /* total number of ring pairs in vector */ 989 990 cpumask_t affinity_mask; 991 struct irq_affinity_notify affinity_notify; 992 993 struct rcu_head rcu; /* to avoid race with update stats on free */ 994 char name[I40E_INT_NAME_STR_LEN]; 995 bool arm_wb_state; 996 int irq_num; /* IRQ assigned to this q_vector */ 997 } ____cacheline_internodealigned_in_smp; 998 999 /* lan device */ 1000 struct i40e_device { 1001 struct list_head list; 1002 struct i40e_pf *pf; 1003 }; 1004 1005 /** 1006 * i40e_nvm_version_str - format the NVM version strings 1007 * @hw: ptr to the hardware info 1008 **/ 1009 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 1010 { 1011 static char buf[32]; 1012 u32 full_ver; 1013 1014 full_ver = hw->nvm.oem_ver; 1015 1016 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 1017 u8 gen, snap; 1018 u16 release; 1019 1020 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 1021 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 1022 I40E_OEM_SNAP_SHIFT); 1023 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 1024 1025 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 1026 } else { 1027 u8 ver, patch; 1028 u16 build; 1029 1030 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 1031 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 1032 I40E_OEM_VER_BUILD_MASK); 1033 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 1034 1035 snprintf(buf, sizeof(buf), 1036 "%x.%02x 0x%x %d.%d.%d", 1037 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 1038 I40E_NVM_VERSION_HI_SHIFT, 1039 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 1040 I40E_NVM_VERSION_LO_SHIFT, 1041 hw->nvm.eetrack, ver, build, patch); 1042 } 1043 1044 return buf; 1045 } 1046 1047 /** 1048 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 1049 * @netdev: the corresponding netdev 1050 * 1051 * Return the PF struct for the given netdev 1052 **/ 1053 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1054 { 1055 struct i40e_netdev_priv *np = netdev_priv(netdev); 1056 struct i40e_vsi *vsi = np->vsi; 1057 1058 return vsi->back; 1059 } 1060 1061 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1062 irqreturn_t (*irq_handler)(int, void *)) 1063 { 1064 vsi->irq_handler = irq_handler; 1065 } 1066 1067 /** 1068 * i40e_get_fd_cnt_all - get the total FD filter space available 1069 * @pf: pointer to the PF struct 1070 **/ 1071 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1072 { 1073 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1074 } 1075 1076 /** 1077 * i40e_read_fd_input_set - reads value of flow director input set register 1078 * @pf: pointer to the PF struct 1079 * @addr: register addr 1080 * 1081 * This function reads value of flow director input set register 1082 * specified by 'addr' (which is specific to flow-type) 1083 **/ 1084 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1085 { 1086 u64 val; 1087 1088 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1089 val <<= 32; 1090 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1091 1092 return val; 1093 } 1094 1095 /** 1096 * i40e_write_fd_input_set - writes value into flow director input set register 1097 * @pf: pointer to the PF struct 1098 * @addr: register addr 1099 * @val: value to be written 1100 * 1101 * This function writes specified value to the register specified by 'addr'. 1102 * This register is input set register based on flow-type. 1103 **/ 1104 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1105 u16 addr, u64 val) 1106 { 1107 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1108 (u32)(val >> 32)); 1109 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1110 (u32)(val & 0xFFFFFFFFULL)); 1111 } 1112 1113 /** 1114 * i40e_get_pf_count - get PCI PF count. 1115 * @hw: pointer to a hw. 1116 * 1117 * Reports the function number of the highest PCI physical 1118 * function plus 1 as it is loaded from the NVM. 1119 * 1120 * Return: PCI PF count. 1121 **/ 1122 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1123 { 1124 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1125 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1126 } 1127 1128 /* needed by i40e_ethtool.c */ 1129 int i40e_up(struct i40e_vsi *vsi); 1130 void i40e_down(struct i40e_vsi *vsi); 1131 extern const char i40e_driver_name[]; 1132 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1133 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1134 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1135 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1136 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1137 u16 rss_table_size, u16 rss_size); 1138 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1139 /** 1140 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1141 * @pf: PF to search for VSI 1142 * @type: Value indicating type of VSI we are looking for 1143 **/ 1144 static inline struct i40e_vsi * 1145 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1146 { 1147 int i; 1148 1149 for (i = 0; i < pf->num_alloc_vsi; i++) { 1150 struct i40e_vsi *vsi = pf->vsi[i]; 1151 1152 if (vsi && vsi->type == type) 1153 return vsi; 1154 } 1155 1156 return NULL; 1157 } 1158 void i40e_update_stats(struct i40e_vsi *vsi); 1159 void i40e_update_veb_stats(struct i40e_veb *veb); 1160 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1161 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1162 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1163 bool printconfig); 1164 1165 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1166 struct i40e_fdir_filter *input, bool add); 1167 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1168 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1169 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1170 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1171 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1172 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1173 void i40e_set_ethtool_ops(struct net_device *netdev); 1174 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1175 const u8 *macaddr, s16 vlan); 1176 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1177 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1178 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1179 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1180 u16 uplink, u32 param1); 1181 int i40e_vsi_release(struct i40e_vsi *vsi); 1182 void i40e_service_event_schedule(struct i40e_pf *pf); 1183 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1184 u8 *msg, u16 len); 1185 1186 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1187 bool enable); 1188 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1189 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1190 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1191 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1192 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1193 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1194 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1195 u16 downlink_seid, u8 enabled_tc); 1196 void i40e_veb_release(struct i40e_veb *veb); 1197 1198 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1199 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1200 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1201 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1202 void i40e_pf_reset_stats(struct i40e_pf *pf); 1203 #ifdef CONFIG_DEBUG_FS 1204 void i40e_dbg_pf_init(struct i40e_pf *pf); 1205 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1206 void i40e_dbg_init(void); 1207 void i40e_dbg_exit(void); 1208 #else 1209 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1210 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1211 static inline void i40e_dbg_init(void) {} 1212 static inline void i40e_dbg_exit(void) {} 1213 #endif /* CONFIG_DEBUG_FS*/ 1214 /* needed by client drivers */ 1215 int i40e_lan_add_device(struct i40e_pf *pf); 1216 int i40e_lan_del_device(struct i40e_pf *pf); 1217 void i40e_client_subtask(struct i40e_pf *pf); 1218 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1219 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1220 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1221 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1222 void i40e_client_update_msix_info(struct i40e_pf *pf); 1223 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1224 /** 1225 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1226 * @vsi: pointer to a vsi 1227 * @vector: enable a particular Hw Interrupt vector, without base_vector 1228 **/ 1229 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1230 { 1231 struct i40e_pf *pf = vsi->back; 1232 struct i40e_hw *hw = &pf->hw; 1233 u32 val; 1234 1235 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1236 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1237 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1238 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1239 /* skip the flush */ 1240 } 1241 1242 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1243 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1244 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1245 int i40e_open(struct net_device *netdev); 1246 int i40e_close(struct net_device *netdev); 1247 int i40e_vsi_open(struct i40e_vsi *vsi); 1248 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1249 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1250 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1251 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1252 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1253 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1254 const u8 *macaddr); 1255 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1256 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1257 int i40e_count_filters(struct i40e_vsi *vsi); 1258 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1259 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1260 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1261 { 1262 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP); 1263 } 1264 1265 #ifdef CONFIG_I40E_DCB 1266 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1267 struct i40e_dcbx_config *old_cfg, 1268 struct i40e_dcbx_config *new_cfg); 1269 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1270 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1271 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1272 struct i40e_dcbx_config *old_cfg, 1273 struct i40e_dcbx_config *new_cfg); 1274 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1275 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1276 #endif /* CONFIG_I40E_DCB */ 1277 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1278 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1279 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1280 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1281 void i40e_ptp_set_increment(struct i40e_pf *pf); 1282 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1283 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1284 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1285 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1286 void i40e_ptp_init(struct i40e_pf *pf); 1287 void i40e_ptp_stop(struct i40e_pf *pf); 1288 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1289 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1290 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1291 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1292 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1293 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1294 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1295 1296 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1297 1298 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1299 { 1300 return !!READ_ONCE(vsi->xdp_prog); 1301 } 1302 1303 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1304 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1305 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1306 struct i40e_cloud_filter *filter, 1307 bool add); 1308 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1309 struct i40e_cloud_filter *filter, 1310 bool add); 1311 1312 /** 1313 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1314 * @pf: pointer to a pf. 1315 * 1316 * Check and return value of flag I40E_FLAG_TC_MQPRIO. 1317 * 1318 * Return: I40E_FLAG_TC_MQPRIO set state. 1319 **/ 1320 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1321 { 1322 return pf->flags & I40E_FLAG_TC_MQPRIO; 1323 } 1324 1325 #endif /* _I40E_H_ */ 1326