xref: /linux/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml (revision 69bfec7548f4c1595bac0e3ddfc0458a5af31f4c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip PCIe v3 phy
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3568-pcie3-phy
16
17  reg:
18    maxItems: 1
19
20  clocks:
21    minItems: 3
22    maxItems: 3
23
24  clock-names:
25    items:
26      - const: refclk_m
27      - const: refclk_n
28      - const: pclk
29
30  data-lanes:
31    description: which lanes (by position) should be mapped to which
32      controller (value). 0 means lane disabled, higher value means used.
33      (controller-number +1 )
34    $ref: /schemas/types.yaml#/definitions/uint32-array
35    minItems: 2
36    maxItems: 16
37    items:
38      minimum: 0
39      maximum: 16
40
41  "#phy-cells":
42    const: 0
43
44  resets:
45    maxItems: 1
46
47  reset-names:
48    const: phy
49
50  rockchip,phy-grf:
51    $ref: /schemas/types.yaml#/definitions/phandle
52    description: phandle to the syscon managing the phy "general register files"
53
54  rockchip,pipe-grf:
55    $ref: /schemas/types.yaml#/definitions/phandle
56    description: phandle to the syscon managing the pipe "general register files"
57
58required:
59  - compatible
60  - reg
61  - rockchip,phy-grf
62  - "#phy-cells"
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/rk3568-cru.h>
69    pcie30phy: phy@fe8c0000 {
70      compatible = "rockchip,rk3568-pcie3-phy";
71      reg = <0xfe8c0000 0x20000>;
72      #phy-cells = <0>;
73      clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
74               <&pmucru CLK_PCIE30PHY_REF_N>,
75               <&cru PCLK_PCIE30PHY>;
76      clock-names = "refclk_m", "refclk_n", "pclk";
77      resets = <&cru SRST_PCIE30PHY>;
78      reset-names = "phy";
79      rockchip,phy-grf = <&pcie30_phy_grf>;
80    };
81