1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&L2_0>; 39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 40 operating-points-v2 = <&cpu_opp_table>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 50 operating-points-v2 = <&cpu_opp_table>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 CPU3: cpu@3 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x3>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 L2_0: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 }; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq5332", "qcom,scm"; 82 qcom,dload-mode = <&tcsr 0x6100>; 83 }; 84 }; 85 86 memory@40000000 { 87 device_type = "memory"; 88 /* We expect the bootloader to fill in the size */ 89 reg = <0x0 0x40000000 0x0 0x0>; 90 }; 91 92 cpu_opp_table: opp-table-cpu { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 96 opp-1488000000 { 97 opp-hz = /bits/ 64 <1488000000>; 98 clock-latency-ns = <200000>; 99 }; 100 }; 101 102 pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0"; 109 method = "smc"; 110 }; 111 112 reserved-memory { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 tz_mem: tz@4a600000 { 118 reg = <0x0 0x4a600000 0x0 0x200000>; 119 no-map; 120 }; 121 122 smem@4a800000 { 123 compatible = "qcom,smem"; 124 reg = <0x0 0x4a800000 0x0 0x00100000>; 125 no-map; 126 127 hwlocks = <&tcsr_mutex 0>; 128 }; 129 }; 130 131 soc@0 { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 ranges = <0 0 0 0xffffffff>; 136 137 rng: rng@e3000 { 138 compatible = "qcom,prng-ee"; 139 reg = <0x000e3000 0x1000>; 140 clocks = <&gcc GCC_PRNG_AHB_CLK>; 141 clock-names = "core"; 142 }; 143 144 tlmm: pinctrl@1000000 { 145 compatible = "qcom,ipq5332-tlmm"; 146 reg = <0x01000000 0x300000>; 147 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 148 gpio-controller; 149 #gpio-cells = <2>; 150 gpio-ranges = <&tlmm 0 0 53>; 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 154 serial_0_pins: serial0-state { 155 pins = "gpio18", "gpio19"; 156 function = "blsp0_uart0"; 157 drive-strength = <8>; 158 bias-pull-up; 159 }; 160 }; 161 162 gcc: clock-controller@1800000 { 163 compatible = "qcom,ipq5332-gcc"; 164 reg = <0x01800000 0x80000>; 165 #clock-cells = <1>; 166 #reset-cells = <1>; 167 #power-domain-cells = <1>; 168 clocks = <&xo_board>, 169 <&sleep_clk>, 170 <0>, 171 <0>, 172 <0>; 173 }; 174 175 tcsr_mutex: hwlock@1905000 { 176 compatible = "qcom,tcsr-mutex"; 177 reg = <0x01905000 0x20000>; 178 #hwlock-cells = <1>; 179 }; 180 181 tcsr: syscon@1937000 { 182 compatible = "qcom,tcsr-ipq5332", "syscon"; 183 reg = <0x01937000 0x21000>; 184 }; 185 186 sdhc: mmc@7804000 { 187 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 188 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 189 190 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-names = "hc_irq", "pwr_irq"; 193 194 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 195 <&gcc GCC_SDCC1_APPS_CLK>, 196 <&xo_board>; 197 clock-names = "iface", "core", "xo"; 198 status = "disabled"; 199 }; 200 201 blsp_dma: dma-controller@7884000 { 202 compatible = "qcom,bam-v1.7.0"; 203 reg = <0x07884000 0x1d000>; 204 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 206 clock-names = "bam_clk"; 207 #dma-cells = <1>; 208 qcom,ee = <0>; 209 }; 210 211 blsp1_uart0: serial@78af000 { 212 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 213 reg = <0x078af000 0x200>; 214 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 216 <&gcc GCC_BLSP1_AHB_CLK>; 217 clock-names = "core", "iface"; 218 status = "disabled"; 219 }; 220 221 blsp1_spi0: spi@78b5000 { 222 compatible = "qcom,spi-qup-v2.2.1"; 223 reg = <0x078b5000 0x600>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 228 <&gcc GCC_BLSP1_AHB_CLK>; 229 clock-names = "core", "iface"; 230 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 231 dma-names = "tx", "rx"; 232 status = "disabled"; 233 }; 234 235 blsp1_i2c1: i2c@78b6000 { 236 compatible = "qcom,i2c-qup-v2.2.1"; 237 reg = <0x078b6000 0x600>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 242 <&gcc GCC_BLSP1_AHB_CLK>; 243 clock-names = "core", "iface"; 244 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 245 dma-names = "tx", "rx"; 246 status = "disabled"; 247 }; 248 249 blsp1_spi2: spi@78b7000 { 250 compatible = "qcom,spi-qup-v2.2.1"; 251 reg = <0x078b7000 0x600>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 256 <&gcc GCC_BLSP1_AHB_CLK>; 257 clock-names = "core", "iface"; 258 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 259 dma-names = "tx", "rx"; 260 status = "disabled"; 261 }; 262 263 intc: interrupt-controller@b000000 { 264 compatible = "qcom,msm-qgic2"; 265 reg = <0x0b000000 0x1000>, /* GICD */ 266 <0x0b002000 0x1000>, /* GICC */ 267 <0x0b001000 0x1000>, /* GICH */ 268 <0x0b004000 0x1000>; /* GICV */ 269 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0 0x0b00c000 0x3000>; 275 276 v2m0: v2m@0 { 277 compatible = "arm,gic-v2m-frame"; 278 reg = <0x00000000 0xffd>; 279 msi-controller; 280 }; 281 282 v2m1: v2m@1000 { 283 compatible = "arm,gic-v2m-frame"; 284 reg = <0x00001000 0xffd>; 285 msi-controller; 286 }; 287 288 v2m2: v2m@2000 { 289 compatible = "arm,gic-v2m-frame"; 290 reg = <0x00002000 0xffd>; 291 msi-controller; 292 }; 293 }; 294 295 watchdog: watchdog@b017000 { 296 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 297 reg = <0x0b017000 0x1000>; 298 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 299 clocks = <&sleep_clk>; 300 timeout-sec = <30>; 301 }; 302 303 apcs_glb: mailbox@b111000 { 304 compatible = "qcom,ipq5332-apcs-apps-global", 305 "qcom,ipq6018-apcs-apps-global"; 306 reg = <0x0b111000 0x1000>; 307 #clock-cells = <1>; 308 clocks = <&a53pll>, <&xo_board>; 309 clock-names = "pll", "xo"; 310 #mbox-cells = <1>; 311 }; 312 313 a53pll: clock@b116000 { 314 compatible = "qcom,ipq5332-a53pll"; 315 reg = <0x0b116000 0x40>; 316 #clock-cells = <0>; 317 clocks = <&xo_board>; 318 clock-names = "xo"; 319 }; 320 321 timer@b120000 { 322 compatible = "arm,armv7-timer-mem"; 323 reg = <0x0b120000 0x1000>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges; 327 328 frame@b120000 { 329 reg = <0x0b121000 0x1000>, 330 <0x0b122000 0x1000>; 331 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 333 frame-number = <0>; 334 }; 335 336 frame@b123000 { 337 reg = <0x0b123000 0x1000>; 338 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 339 frame-number = <1>; 340 status = "disabled"; 341 }; 342 343 frame@b124000 { 344 reg = <0x0b124000 0x1000>; 345 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 346 frame-number = <2>; 347 status = "disabled"; 348 }; 349 350 frame@b125000 { 351 reg = <0x0b125000 0x1000>; 352 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 353 frame-number = <3>; 354 status = "disabled"; 355 }; 356 357 frame@b126000 { 358 reg = <0x0b126000 0x1000>; 359 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 360 frame-number = <4>; 361 status = "disabled"; 362 }; 363 364 frame@b127000 { 365 reg = <0x0b127000 0x1000>; 366 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 367 frame-number = <5>; 368 status = "disabled"; 369 }; 370 371 frame@b128000 { 372 reg = <0x0b128000 0x1000>; 373 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 374 frame-number = <6>; 375 status = "disabled"; 376 }; 377 }; 378 }; 379 380 timer { 381 compatible = "arm,armv8-timer"; 382 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 383 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 384 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 385 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 386 }; 387}; 388