1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/of_clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/sizes.h> 10 #include <asm/time.h> 11 12 #include <loongson1.h> 13 #include <platform.h> 14 15 #ifdef CONFIG_CEVT_CSRC_LS1X 16 17 #if defined(CONFIG_TIMER_USE_PWM1) 18 #define LS1X_TIMER_BASE LS1X_PWM1_BASE 19 #define LS1X_TIMER_IRQ LS1X_PWM1_IRQ 20 21 #elif defined(CONFIG_TIMER_USE_PWM2) 22 #define LS1X_TIMER_BASE LS1X_PWM2_BASE 23 #define LS1X_TIMER_IRQ LS1X_PWM2_IRQ 24 25 #elif defined(CONFIG_TIMER_USE_PWM3) 26 #define LS1X_TIMER_BASE LS1X_PWM3_BASE 27 #define LS1X_TIMER_IRQ LS1X_PWM3_IRQ 28 29 #else 30 #define LS1X_TIMER_BASE LS1X_PWM0_BASE 31 #define LS1X_TIMER_IRQ LS1X_PWM0_IRQ 32 #endif 33 34 DEFINE_RAW_SPINLOCK(ls1x_timer_lock); 35 36 static void __iomem *timer_reg_base; 37 static uint32_t ls1x_jiffies_per_tick; 38 39 static inline void ls1x_pwmtimer_set_period(uint32_t period) 40 { 41 __raw_writel(period, timer_reg_base + PWM_HRC); 42 __raw_writel(period, timer_reg_base + PWM_LRC); 43 } 44 45 static inline void ls1x_pwmtimer_restart(void) 46 { 47 __raw_writel(0x0, timer_reg_base + PWM_CNT); 48 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); 49 } 50 51 void __init ls1x_pwmtimer_init(void) 52 { 53 timer_reg_base = ioremap(LS1X_TIMER_BASE, SZ_16); 54 if (!timer_reg_base) 55 panic("Failed to remap timer registers"); 56 57 ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ); 58 59 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick); 60 ls1x_pwmtimer_restart(); 61 } 62 63 static u64 ls1x_clocksource_read(struct clocksource *cs) 64 { 65 unsigned long flags; 66 int count; 67 u32 jifs; 68 static int old_count; 69 static u32 old_jifs; 70 71 raw_spin_lock_irqsave(&ls1x_timer_lock, flags); 72 /* 73 * Although our caller may have the read side of xtime_lock, 74 * this is now a seqlock, and we are cheating in this routine 75 * by having side effects on state that we cannot undo if 76 * there is a collision on the seqlock and our caller has to 77 * retry. (Namely, old_jifs and old_count.) So we must treat 78 * jiffies as volatile despite the lock. We read jiffies 79 * before latching the timer count to guarantee that although 80 * the jiffies value might be older than the count (that is, 81 * the counter may underflow between the last point where 82 * jiffies was incremented and the point where we latch the 83 * count), it cannot be newer. 84 */ 85 jifs = jiffies; 86 /* read the count */ 87 count = __raw_readl(timer_reg_base + PWM_CNT); 88 89 /* 90 * It's possible for count to appear to go the wrong way for this 91 * reason: 92 * 93 * The timer counter underflows, but we haven't handled the resulting 94 * interrupt and incremented jiffies yet. 95 * 96 * Previous attempts to handle these cases intelligently were buggy, so 97 * we just do the simple thing now. 98 */ 99 if (count < old_count && jifs == old_jifs) 100 count = old_count; 101 102 old_count = count; 103 old_jifs = jifs; 104 105 raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags); 106 107 return (u64) (jifs * ls1x_jiffies_per_tick) + count; 108 } 109 110 static struct clocksource ls1x_clocksource = { 111 .name = "ls1x-pwmtimer", 112 .read = ls1x_clocksource_read, 113 .mask = CLOCKSOURCE_MASK(24), 114 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 115 }; 116 117 static irqreturn_t ls1x_clockevent_isr(int irq, void *devid) 118 { 119 struct clock_event_device *cd = devid; 120 121 ls1x_pwmtimer_restart(); 122 cd->event_handler(cd); 123 124 return IRQ_HANDLED; 125 } 126 127 static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd) 128 { 129 raw_spin_lock(&ls1x_timer_lock); 130 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick); 131 ls1x_pwmtimer_restart(); 132 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); 133 raw_spin_unlock(&ls1x_timer_lock); 134 135 return 0; 136 } 137 138 static int ls1x_clockevent_tick_resume(struct clock_event_device *cd) 139 { 140 raw_spin_lock(&ls1x_timer_lock); 141 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); 142 raw_spin_unlock(&ls1x_timer_lock); 143 144 return 0; 145 } 146 147 static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd) 148 { 149 raw_spin_lock(&ls1x_timer_lock); 150 __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN, 151 timer_reg_base + PWM_CTRL); 152 raw_spin_unlock(&ls1x_timer_lock); 153 154 return 0; 155 } 156 157 static int ls1x_clockevent_set_next(unsigned long evt, 158 struct clock_event_device *cd) 159 { 160 raw_spin_lock(&ls1x_timer_lock); 161 ls1x_pwmtimer_set_period(evt); 162 ls1x_pwmtimer_restart(); 163 raw_spin_unlock(&ls1x_timer_lock); 164 165 return 0; 166 } 167 168 static struct clock_event_device ls1x_clockevent = { 169 .name = "ls1x-pwmtimer", 170 .features = CLOCK_EVT_FEAT_PERIODIC, 171 .rating = 300, 172 .irq = LS1X_TIMER_IRQ, 173 .set_next_event = ls1x_clockevent_set_next, 174 .set_state_shutdown = ls1x_clockevent_set_state_shutdown, 175 .set_state_periodic = ls1x_clockevent_set_state_periodic, 176 .set_state_oneshot = ls1x_clockevent_set_state_shutdown, 177 .tick_resume = ls1x_clockevent_tick_resume, 178 }; 179 180 static void __init ls1x_time_init(void) 181 { 182 struct clock_event_device *cd = &ls1x_clockevent; 183 int ret; 184 185 if (!mips_hpt_frequency) 186 panic("Invalid timer clock rate"); 187 188 ls1x_pwmtimer_init(); 189 190 clockevent_set_clock(cd, mips_hpt_frequency); 191 cd->max_delta_ns = clockevent_delta2ns(0xffffff, cd); 192 cd->max_delta_ticks = 0xffffff; 193 cd->min_delta_ns = clockevent_delta2ns(0x000300, cd); 194 cd->min_delta_ticks = 0x000300; 195 cd->cpumask = cpumask_of(smp_processor_id()); 196 clockevents_register_device(cd); 197 198 ls1x_clocksource.rating = 200 + mips_hpt_frequency / 10000000; 199 ret = clocksource_register_hz(&ls1x_clocksource, mips_hpt_frequency); 200 if (ret) 201 panic(KERN_ERR "Failed to register clocksource: %d\n", ret); 202 203 if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr, 204 IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer", 205 &ls1x_clockevent)) 206 pr_err("Failed to register ls1x-pwmtimer interrupt\n"); 207 } 208 #endif /* CONFIG_CEVT_CSRC_LS1X */ 209 210 void __init plat_time_init(void) 211 { 212 struct clk *clk = NULL; 213 214 /* initialize LS1X clocks */ 215 of_clk_init(NULL); 216 217 #ifdef CONFIG_CEVT_CSRC_LS1X 218 /* setup LS1X PWM timer */ 219 clk = clk_get(NULL, "ls1x-pwmtimer"); 220 if (IS_ERR(clk)) 221 panic("unable to get timer clock, err=%ld", PTR_ERR(clk)); 222 223 mips_hpt_frequency = clk_get_rate(clk); 224 ls1x_time_init(); 225 #else 226 /* setup mips r4k timer */ 227 clk = clk_get(NULL, "cpu_clk"); 228 if (IS_ERR(clk)) 229 panic("unable to get cpu clock, err=%ld", PTR_ERR(clk)); 230 231 mips_hpt_frequency = clk_get_rate(clk) / 2; 232 #endif /* CONFIG_CEVT_CSRC_LS1X */ 233 } 234