1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/etherdevice.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "umr.h" 44 #include "qp.h" 45 #include "wr.h" 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum raw_qp_set_mask_map { 59 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 60 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 61 }; 62 63 struct mlx5_modify_raw_qp_param { 64 u16 operation; 65 66 u32 set_mask; /* raw_qp_set_mask_map */ 67 68 struct mlx5_rate_limit rl; 69 70 u8 rq_q_ctr_id; 71 u32 port; 72 }; 73 74 struct mlx5_ib_qp_event_work { 75 struct work_struct work; 76 struct mlx5_core_qp *qp; 77 int type; 78 }; 79 80 static struct workqueue_struct *mlx5_ib_qp_event_wq; 81 82 static void get_cqs(enum ib_qp_type qp_type, 83 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 84 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 85 86 static int is_qp0(enum ib_qp_type qp_type) 87 { 88 return qp_type == IB_QPT_SMI; 89 } 90 91 static int is_sqp(enum ib_qp_type qp_type) 92 { 93 return is_qp0(qp_type) || is_qp1(qp_type); 94 } 95 96 /** 97 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 98 * to kernel buffer 99 * 100 * @umem: User space memory where the WQ is 101 * @buffer: buffer to copy to 102 * @buflen: buffer length 103 * @wqe_index: index of WQE to copy from 104 * @wq_offset: offset to start of WQ 105 * @wq_wqe_cnt: number of WQEs in WQ 106 * @wq_wqe_shift: log2 of WQE size 107 * @bcnt: number of bytes to copy 108 * @bytes_copied: number of bytes to copy (return value) 109 * 110 * Copies from start of WQE bcnt or less bytes. 111 * Does not gurantee to copy the entire WQE. 112 * 113 * Return: zero on success, or an error code. 114 */ 115 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 116 size_t buflen, int wqe_index, 117 int wq_offset, int wq_wqe_cnt, 118 int wq_wqe_shift, int bcnt, 119 size_t *bytes_copied) 120 { 121 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 122 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 123 size_t copy_length; 124 int ret; 125 126 /* don't copy more than requested, more than buffer length or 127 * beyond WQ end 128 */ 129 copy_length = min_t(u32, buflen, wq_end - offset); 130 copy_length = min_t(u32, copy_length, bcnt); 131 132 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 133 if (ret) 134 return ret; 135 136 if (!ret && bytes_copied) 137 *bytes_copied = copy_length; 138 139 return 0; 140 } 141 142 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 143 void *buffer, size_t buflen, size_t *bc) 144 { 145 struct mlx5_wqe_ctrl_seg *ctrl; 146 size_t bytes_copied = 0; 147 size_t wqe_length; 148 void *p; 149 int ds; 150 151 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 152 153 /* read the control segment first */ 154 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 155 ctrl = p; 156 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 157 wqe_length = ds * MLX5_WQE_DS_UNITS; 158 159 /* read rest of WQE if it spreads over more than one stride */ 160 while (bytes_copied < wqe_length) { 161 size_t copy_length = 162 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 163 164 if (!copy_length) 165 break; 166 167 memcpy(buffer + bytes_copied, p, copy_length); 168 bytes_copied += copy_length; 169 170 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 171 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 172 } 173 *bc = bytes_copied; 174 return 0; 175 } 176 177 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 178 void *buffer, size_t buflen, size_t *bc) 179 { 180 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 181 struct ib_umem *umem = base->ubuffer.umem; 182 struct mlx5_ib_wq *wq = &qp->sq; 183 struct mlx5_wqe_ctrl_seg *ctrl; 184 size_t bytes_copied; 185 size_t bytes_copied2; 186 size_t wqe_length; 187 int ret; 188 int ds; 189 190 /* at first read as much as possible */ 191 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 192 wq->offset, wq->wqe_cnt, 193 wq->wqe_shift, buflen, 194 &bytes_copied); 195 if (ret) 196 return ret; 197 198 /* we need at least control segment size to proceed */ 199 if (bytes_copied < sizeof(*ctrl)) 200 return -EINVAL; 201 202 ctrl = buffer; 203 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 204 wqe_length = ds * MLX5_WQE_DS_UNITS; 205 206 /* if we copied enough then we are done */ 207 if (bytes_copied >= wqe_length) { 208 *bc = bytes_copied; 209 return 0; 210 } 211 212 /* otherwise this a wrapped around wqe 213 * so read the remaining bytes starting 214 * from wqe_index 0 215 */ 216 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 217 buflen - bytes_copied, 0, wq->offset, 218 wq->wqe_cnt, wq->wqe_shift, 219 wqe_length - bytes_copied, 220 &bytes_copied2); 221 222 if (ret) 223 return ret; 224 *bc = bytes_copied + bytes_copied2; 225 return 0; 226 } 227 228 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 229 size_t buflen, size_t *bc) 230 { 231 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 232 struct ib_umem *umem = base->ubuffer.umem; 233 234 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 235 return -EINVAL; 236 237 if (!umem) 238 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 239 buflen, bc); 240 241 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 242 } 243 244 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 245 void *buffer, size_t buflen, size_t *bc) 246 { 247 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 248 struct ib_umem *umem = base->ubuffer.umem; 249 struct mlx5_ib_wq *wq = &qp->rq; 250 size_t bytes_copied; 251 int ret; 252 253 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 254 wq->offset, wq->wqe_cnt, 255 wq->wqe_shift, buflen, 256 &bytes_copied); 257 258 if (ret) 259 return ret; 260 *bc = bytes_copied; 261 return 0; 262 } 263 264 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 265 size_t buflen, size_t *bc) 266 { 267 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 268 struct ib_umem *umem = base->ubuffer.umem; 269 struct mlx5_ib_wq *wq = &qp->rq; 270 size_t wqe_size = 1 << wq->wqe_shift; 271 272 if (buflen < wqe_size) 273 return -EINVAL; 274 275 if (!umem) 276 return -EOPNOTSUPP; 277 278 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 279 } 280 281 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 282 void *buffer, size_t buflen, size_t *bc) 283 { 284 struct ib_umem *umem = srq->umem; 285 size_t bytes_copied; 286 int ret; 287 288 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 289 srq->msrq.max, srq->msrq.wqe_shift, 290 buflen, &bytes_copied); 291 292 if (ret) 293 return ret; 294 *bc = bytes_copied; 295 return 0; 296 } 297 298 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 299 size_t buflen, size_t *bc) 300 { 301 struct ib_umem *umem = srq->umem; 302 size_t wqe_size = 1 << srq->msrq.wqe_shift; 303 304 if (buflen < wqe_size) 305 return -EINVAL; 306 307 if (!umem) 308 return -EOPNOTSUPP; 309 310 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 311 } 312 313 static void mlx5_ib_qp_err_syndrome(struct ib_qp *ibqp) 314 { 315 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 316 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 317 struct mlx5_ib_qp *qp = to_mqp(ibqp); 318 void *pas_ext_union, *err_syn; 319 u32 *outb; 320 int err; 321 322 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || 323 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) 324 return; 325 326 outb = kzalloc(outlen, GFP_KERNEL); 327 if (!outb) 328 return; 329 330 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 331 true); 332 if (err) 333 goto out; 334 335 pas_ext_union = 336 MLX5_ADDR_OF(query_qp_out, outb, qp_pas_or_qpc_ext_and_pas); 337 err_syn = MLX5_ADDR_OF(qpc_extension_and_pas_list_in, pas_ext_union, 338 qpc_data_extension.error_syndrome); 339 340 pr_err("%s/%d: QP %d error: %s (0x%x 0x%x 0x%x)\n", 341 ibqp->device->name, ibqp->port, ibqp->qp_num, 342 ib_wc_status_msg( 343 MLX5_GET(cqe_error_syndrome, err_syn, syndrome)), 344 MLX5_GET(cqe_error_syndrome, err_syn, vendor_error_syndrome), 345 MLX5_GET(cqe_error_syndrome, err_syn, hw_syndrome_type), 346 MLX5_GET(cqe_error_syndrome, err_syn, hw_error_syndrome)); 347 out: 348 kfree(outb); 349 } 350 351 static void mlx5_ib_handle_qp_event(struct work_struct *_work) 352 { 353 struct mlx5_ib_qp_event_work *qpe_work = 354 container_of(_work, struct mlx5_ib_qp_event_work, work); 355 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 356 struct ib_event event = {}; 357 358 event.device = ibqp->device; 359 event.element.qp = ibqp; 360 switch (qpe_work->type) { 361 case MLX5_EVENT_TYPE_PATH_MIG: 362 event.event = IB_EVENT_PATH_MIG; 363 break; 364 case MLX5_EVENT_TYPE_COMM_EST: 365 event.event = IB_EVENT_COMM_EST; 366 break; 367 case MLX5_EVENT_TYPE_SQ_DRAINED: 368 event.event = IB_EVENT_SQ_DRAINED; 369 break; 370 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 371 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 372 break; 373 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 374 event.event = IB_EVENT_QP_FATAL; 375 break; 376 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 377 event.event = IB_EVENT_PATH_MIG_ERR; 378 break; 379 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 380 event.event = IB_EVENT_QP_REQ_ERR; 381 break; 382 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 383 event.event = IB_EVENT_QP_ACCESS_ERR; 384 break; 385 default: 386 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", 387 qpe_work->type, qpe_work->qp->qpn); 388 goto out; 389 } 390 391 if ((event.event == IB_EVENT_QP_FATAL) || 392 (event.event == IB_EVENT_QP_ACCESS_ERR)) 393 mlx5_ib_qp_err_syndrome(ibqp); 394 395 ibqp->event_handler(&event, ibqp->qp_context); 396 397 out: 398 mlx5_core_res_put(&qpe_work->qp->common); 399 kfree(qpe_work); 400 } 401 402 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 403 { 404 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 405 struct mlx5_ib_qp_event_work *qpe_work; 406 407 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 408 /* This event is only valid for trans_qps */ 409 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 410 } 411 412 if (!ibqp->event_handler) 413 goto out_no_handler; 414 415 qpe_work = kzalloc(sizeof(*qpe_work), GFP_ATOMIC); 416 if (!qpe_work) 417 goto out_no_handler; 418 419 qpe_work->qp = qp; 420 qpe_work->type = type; 421 INIT_WORK(&qpe_work->work, mlx5_ib_handle_qp_event); 422 queue_work(mlx5_ib_qp_event_wq, &qpe_work->work); 423 return; 424 425 out_no_handler: 426 mlx5_core_res_put(&qp->common); 427 } 428 429 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 430 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 431 { 432 int wqe_size; 433 int wq_size; 434 435 /* Sanity check RQ size before proceeding */ 436 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 437 return -EINVAL; 438 439 if (!has_rq) { 440 qp->rq.max_gs = 0; 441 qp->rq.wqe_cnt = 0; 442 qp->rq.wqe_shift = 0; 443 cap->max_recv_wr = 0; 444 cap->max_recv_sge = 0; 445 } else { 446 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 447 448 if (ucmd) { 449 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 450 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 451 return -EINVAL; 452 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 453 if ((1 << qp->rq.wqe_shift) / 454 sizeof(struct mlx5_wqe_data_seg) < 455 wq_sig) 456 return -EINVAL; 457 qp->rq.max_gs = 458 (1 << qp->rq.wqe_shift) / 459 sizeof(struct mlx5_wqe_data_seg) - 460 wq_sig; 461 qp->rq.max_post = qp->rq.wqe_cnt; 462 } else { 463 wqe_size = 464 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 465 0; 466 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 467 wqe_size = roundup_pow_of_two(wqe_size); 468 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 469 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 470 qp->rq.wqe_cnt = wq_size / wqe_size; 471 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 472 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 473 wqe_size, 474 MLX5_CAP_GEN(dev->mdev, 475 max_wqe_sz_rq)); 476 return -EINVAL; 477 } 478 qp->rq.wqe_shift = ilog2(wqe_size); 479 qp->rq.max_gs = 480 (1 << qp->rq.wqe_shift) / 481 sizeof(struct mlx5_wqe_data_seg) - 482 wq_sig; 483 qp->rq.max_post = qp->rq.wqe_cnt; 484 } 485 } 486 487 return 0; 488 } 489 490 static int sq_overhead(struct ib_qp_init_attr *attr) 491 { 492 int size = 0; 493 494 switch (attr->qp_type) { 495 case IB_QPT_XRC_INI: 496 size += sizeof(struct mlx5_wqe_xrc_seg); 497 fallthrough; 498 case IB_QPT_RC: 499 size += sizeof(struct mlx5_wqe_ctrl_seg) + 500 max(sizeof(struct mlx5_wqe_atomic_seg) + 501 sizeof(struct mlx5_wqe_raddr_seg), 502 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 503 sizeof(struct mlx5_mkey_seg) + 504 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 505 MLX5_IB_UMR_OCTOWORD); 506 break; 507 508 case IB_QPT_XRC_TGT: 509 return 0; 510 511 case IB_QPT_UC: 512 size += sizeof(struct mlx5_wqe_ctrl_seg) + 513 max(sizeof(struct mlx5_wqe_raddr_seg), 514 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 515 sizeof(struct mlx5_mkey_seg)); 516 break; 517 518 case IB_QPT_UD: 519 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 520 size += sizeof(struct mlx5_wqe_eth_pad) + 521 sizeof(struct mlx5_wqe_eth_seg); 522 fallthrough; 523 case IB_QPT_SMI: 524 case MLX5_IB_QPT_HW_GSI: 525 size += sizeof(struct mlx5_wqe_ctrl_seg) + 526 sizeof(struct mlx5_wqe_datagram_seg); 527 break; 528 529 case MLX5_IB_QPT_REG_UMR: 530 size += sizeof(struct mlx5_wqe_ctrl_seg) + 531 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 532 sizeof(struct mlx5_mkey_seg); 533 break; 534 535 default: 536 return -EINVAL; 537 } 538 539 return size; 540 } 541 542 static int calc_send_wqe(struct ib_qp_init_attr *attr) 543 { 544 int inl_size = 0; 545 int size; 546 547 size = sq_overhead(attr); 548 if (size < 0) 549 return size; 550 551 if (attr->cap.max_inline_data) { 552 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 553 attr->cap.max_inline_data; 554 } 555 556 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 557 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 558 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 559 return MLX5_SIG_WQE_SIZE; 560 else 561 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 562 } 563 564 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 565 { 566 int max_sge; 567 568 if (attr->qp_type == IB_QPT_RC) 569 max_sge = (min_t(int, wqe_size, 512) - 570 sizeof(struct mlx5_wqe_ctrl_seg) - 571 sizeof(struct mlx5_wqe_raddr_seg)) / 572 sizeof(struct mlx5_wqe_data_seg); 573 else if (attr->qp_type == IB_QPT_XRC_INI) 574 max_sge = (min_t(int, wqe_size, 512) - 575 sizeof(struct mlx5_wqe_ctrl_seg) - 576 sizeof(struct mlx5_wqe_xrc_seg) - 577 sizeof(struct mlx5_wqe_raddr_seg)) / 578 sizeof(struct mlx5_wqe_data_seg); 579 else 580 max_sge = (wqe_size - sq_overhead(attr)) / 581 sizeof(struct mlx5_wqe_data_seg); 582 583 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 584 sizeof(struct mlx5_wqe_data_seg)); 585 } 586 587 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 588 struct mlx5_ib_qp *qp) 589 { 590 int wqe_size; 591 int wq_size; 592 593 if (!attr->cap.max_send_wr) 594 return 0; 595 596 wqe_size = calc_send_wqe(attr); 597 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 598 if (wqe_size < 0) 599 return wqe_size; 600 601 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 602 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 603 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 604 return -EINVAL; 605 } 606 607 qp->max_inline_data = wqe_size - sq_overhead(attr) - 608 sizeof(struct mlx5_wqe_inline_seg); 609 attr->cap.max_inline_data = qp->max_inline_data; 610 611 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 612 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 613 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 614 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 615 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 616 qp->sq.wqe_cnt, 617 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 618 return -ENOMEM; 619 } 620 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 621 qp->sq.max_gs = get_send_sge(attr, wqe_size); 622 if (qp->sq.max_gs < attr->cap.max_send_sge) 623 return -ENOMEM; 624 625 attr->cap.max_send_sge = qp->sq.max_gs; 626 qp->sq.max_post = wq_size / wqe_size; 627 attr->cap.max_send_wr = qp->sq.max_post; 628 629 return wq_size; 630 } 631 632 static int set_user_buf_size(struct mlx5_ib_dev *dev, 633 struct mlx5_ib_qp *qp, 634 struct mlx5_ib_create_qp *ucmd, 635 struct mlx5_ib_qp_base *base, 636 struct ib_qp_init_attr *attr) 637 { 638 int desc_sz = 1 << qp->sq.wqe_shift; 639 640 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 641 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 642 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 643 return -EINVAL; 644 } 645 646 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 647 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 648 ucmd->sq_wqe_count); 649 return -EINVAL; 650 } 651 652 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 653 654 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 655 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 656 qp->sq.wqe_cnt, 657 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 658 return -EINVAL; 659 } 660 661 if (attr->qp_type == IB_QPT_RAW_PACKET || 662 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 663 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 664 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 665 } else { 666 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 667 (qp->sq.wqe_cnt << 6); 668 } 669 670 return 0; 671 } 672 673 static int qp_has_rq(struct ib_qp_init_attr *attr) 674 { 675 if (attr->qp_type == IB_QPT_XRC_INI || 676 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 677 attr->qp_type == MLX5_IB_QPT_REG_UMR || 678 !attr->cap.max_recv_wr) 679 return 0; 680 681 return 1; 682 } 683 684 enum { 685 /* this is the first blue flame register in the array of bfregs assigned 686 * to a processes. Since we do not use it for blue flame but rather 687 * regular 64 bit doorbells, we do not need a lock for maintaiing 688 * "odd/even" order 689 */ 690 NUM_NON_BLUE_FLAME_BFREGS = 1, 691 }; 692 693 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 694 { 695 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 696 bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR; 697 } 698 699 static int num_med_bfreg(struct mlx5_ib_dev *dev, 700 struct mlx5_bfreg_info *bfregi) 701 { 702 int n; 703 704 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 705 NUM_NON_BLUE_FLAME_BFREGS; 706 707 return n >= 0 ? n : 0; 708 } 709 710 static int first_med_bfreg(struct mlx5_ib_dev *dev, 711 struct mlx5_bfreg_info *bfregi) 712 { 713 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 714 } 715 716 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 717 struct mlx5_bfreg_info *bfregi) 718 { 719 int med; 720 721 med = num_med_bfreg(dev, bfregi); 722 return ++med; 723 } 724 725 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 726 struct mlx5_bfreg_info *bfregi) 727 { 728 int i; 729 730 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 731 if (!bfregi->count[i]) { 732 bfregi->count[i]++; 733 return i; 734 } 735 } 736 737 return -ENOMEM; 738 } 739 740 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 741 struct mlx5_bfreg_info *bfregi) 742 { 743 int minidx = first_med_bfreg(dev, bfregi); 744 int i; 745 746 if (minidx < 0) 747 return minidx; 748 749 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 750 if (bfregi->count[i] < bfregi->count[minidx]) 751 minidx = i; 752 if (!bfregi->count[minidx]) 753 break; 754 } 755 756 bfregi->count[minidx]++; 757 return minidx; 758 } 759 760 static int alloc_bfreg(struct mlx5_ib_dev *dev, 761 struct mlx5_bfreg_info *bfregi) 762 { 763 int bfregn = -ENOMEM; 764 765 if (bfregi->lib_uar_dyn) 766 return -EINVAL; 767 768 mutex_lock(&bfregi->lock); 769 if (bfregi->ver >= 2) { 770 bfregn = alloc_high_class_bfreg(dev, bfregi); 771 if (bfregn < 0) 772 bfregn = alloc_med_class_bfreg(dev, bfregi); 773 } 774 775 if (bfregn < 0) { 776 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 777 bfregn = 0; 778 bfregi->count[bfregn]++; 779 } 780 mutex_unlock(&bfregi->lock); 781 782 return bfregn; 783 } 784 785 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 786 { 787 mutex_lock(&bfregi->lock); 788 bfregi->count[bfregn]--; 789 mutex_unlock(&bfregi->lock); 790 } 791 792 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 793 { 794 switch (state) { 795 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 796 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 797 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 798 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 799 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 800 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 801 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 802 default: return -1; 803 } 804 } 805 806 static int to_mlx5_st(enum ib_qp_type type) 807 { 808 switch (type) { 809 case IB_QPT_RC: return MLX5_QP_ST_RC; 810 case IB_QPT_UC: return MLX5_QP_ST_UC; 811 case IB_QPT_UD: return MLX5_QP_ST_UD; 812 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 813 case IB_QPT_XRC_INI: 814 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 815 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 816 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 817 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 818 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 819 default: return -EINVAL; 820 } 821 } 822 823 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 824 struct mlx5_ib_cq *recv_cq); 825 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 826 struct mlx5_ib_cq *recv_cq); 827 828 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 829 struct mlx5_bfreg_info *bfregi, u32 bfregn, 830 bool dyn_bfreg) 831 { 832 unsigned int bfregs_per_sys_page; 833 u32 index_of_sys_page; 834 u32 offset; 835 836 if (bfregi->lib_uar_dyn) 837 return -EINVAL; 838 839 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 840 MLX5_NON_FP_BFREGS_PER_UAR; 841 index_of_sys_page = bfregn / bfregs_per_sys_page; 842 843 if (dyn_bfreg) { 844 index_of_sys_page += bfregi->num_static_sys_pages; 845 846 if (index_of_sys_page >= bfregi->num_sys_pages) 847 return -EINVAL; 848 849 if (bfregn > bfregi->num_dyn_bfregs || 850 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 851 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 852 return -EINVAL; 853 } 854 } 855 856 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 857 return bfregi->sys_pages[index_of_sys_page] + offset; 858 } 859 860 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 861 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 862 { 863 struct mlx5_ib_ucontext *context = 864 rdma_udata_to_drv_context( 865 udata, 866 struct mlx5_ib_ucontext, 867 ibucontext); 868 869 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 870 atomic_dec(&dev->delay_drop.rqs_cnt); 871 872 mlx5_ib_db_unmap_user(context, &rwq->db); 873 ib_umem_release(rwq->umem); 874 } 875 876 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 877 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 878 struct mlx5_ib_create_wq *ucmd) 879 { 880 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 881 udata, struct mlx5_ib_ucontext, ibucontext); 882 unsigned long page_size = 0; 883 u32 offset = 0; 884 int err; 885 886 if (!ucmd->buf_addr) 887 return -EINVAL; 888 889 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 890 if (IS_ERR(rwq->umem)) { 891 mlx5_ib_dbg(dev, "umem_get failed\n"); 892 err = PTR_ERR(rwq->umem); 893 return err; 894 } 895 896 page_size = mlx5_umem_find_best_quantized_pgoff( 897 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 898 page_offset, 64, &rwq->rq_page_offset); 899 if (!page_size) { 900 mlx5_ib_warn(dev, "bad offset\n"); 901 err = -EINVAL; 902 goto err_umem; 903 } 904 905 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 906 rwq->page_shift = order_base_2(page_size); 907 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 908 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 909 910 mlx5_ib_dbg( 911 dev, 912 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 913 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 914 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 915 offset); 916 917 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 918 if (err) { 919 mlx5_ib_dbg(dev, "map failed\n"); 920 goto err_umem; 921 } 922 923 return 0; 924 925 err_umem: 926 ib_umem_release(rwq->umem); 927 return err; 928 } 929 930 static int adjust_bfregn(struct mlx5_ib_dev *dev, 931 struct mlx5_bfreg_info *bfregi, int bfregn) 932 { 933 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 934 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 935 } 936 937 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 938 struct mlx5_ib_qp *qp, struct ib_udata *udata, 939 struct ib_qp_init_attr *attr, u32 **in, 940 struct mlx5_ib_create_qp_resp *resp, int *inlen, 941 struct mlx5_ib_qp_base *base, 942 struct mlx5_ib_create_qp *ucmd) 943 { 944 struct mlx5_ib_ucontext *context; 945 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 946 unsigned int page_offset_quantized = 0; 947 unsigned long page_size = 0; 948 int uar_index = 0; 949 int bfregn; 950 int ncont = 0; 951 __be64 *pas; 952 void *qpc; 953 int err; 954 u16 uid; 955 u32 uar_flags; 956 957 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 958 ibucontext); 959 uar_flags = qp->flags_en & 960 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 961 switch (uar_flags) { 962 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 963 uar_index = ucmd->bfreg_index; 964 bfregn = MLX5_IB_INVALID_BFREG; 965 break; 966 case MLX5_QP_FLAG_BFREG_INDEX: 967 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 968 ucmd->bfreg_index, true); 969 if (uar_index < 0) 970 return uar_index; 971 bfregn = MLX5_IB_INVALID_BFREG; 972 break; 973 case 0: 974 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 975 return -EINVAL; 976 bfregn = alloc_bfreg(dev, &context->bfregi); 977 if (bfregn < 0) 978 return bfregn; 979 break; 980 default: 981 return -EINVAL; 982 } 983 984 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 985 if (bfregn != MLX5_IB_INVALID_BFREG) 986 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 987 false); 988 989 qp->rq.offset = 0; 990 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 991 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 992 993 err = set_user_buf_size(dev, qp, ucmd, base, attr); 994 if (err) 995 goto err_bfreg; 996 997 if (ucmd->buf_addr && ubuffer->buf_size) { 998 ubuffer->buf_addr = ucmd->buf_addr; 999 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1000 ubuffer->buf_size, 0); 1001 if (IS_ERR(ubuffer->umem)) { 1002 err = PTR_ERR(ubuffer->umem); 1003 goto err_bfreg; 1004 } 1005 page_size = mlx5_umem_find_best_quantized_pgoff( 1006 ubuffer->umem, qpc, log_page_size, 1007 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1008 &page_offset_quantized); 1009 if (!page_size) { 1010 err = -EINVAL; 1011 goto err_umem; 1012 } 1013 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 1014 } else { 1015 ubuffer->umem = NULL; 1016 } 1017 1018 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1019 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 1020 *in = kvzalloc(*inlen, GFP_KERNEL); 1021 if (!*in) { 1022 err = -ENOMEM; 1023 goto err_umem; 1024 } 1025 1026 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 1027 MLX5_SET(create_qp_in, *in, uid, uid); 1028 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1029 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1030 if (ubuffer->umem) { 1031 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 1032 MLX5_SET(qpc, qpc, log_page_size, 1033 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1034 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 1035 } 1036 MLX5_SET(qpc, qpc, uar_page, uar_index); 1037 if (bfregn != MLX5_IB_INVALID_BFREG) 1038 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1039 else 1040 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1041 qp->bfregn = bfregn; 1042 1043 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 1044 if (err) { 1045 mlx5_ib_dbg(dev, "map failed\n"); 1046 goto err_free; 1047 } 1048 1049 return 0; 1050 1051 err_free: 1052 kvfree(*in); 1053 1054 err_umem: 1055 ib_umem_release(ubuffer->umem); 1056 1057 err_bfreg: 1058 if (bfregn != MLX5_IB_INVALID_BFREG) 1059 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1060 return err; 1061 } 1062 1063 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1064 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1065 { 1066 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1067 udata, struct mlx5_ib_ucontext, ibucontext); 1068 1069 if (udata) { 1070 /* User QP */ 1071 mlx5_ib_db_unmap_user(context, &qp->db); 1072 ib_umem_release(base->ubuffer.umem); 1073 1074 /* 1075 * Free only the BFREGs which are handled by the kernel. 1076 * BFREGs of UARs allocated dynamically are handled by user. 1077 */ 1078 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1079 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1080 return; 1081 } 1082 1083 /* Kernel QP */ 1084 kvfree(qp->sq.wqe_head); 1085 kvfree(qp->sq.w_list); 1086 kvfree(qp->sq.wrid); 1087 kvfree(qp->sq.wr_data); 1088 kvfree(qp->rq.wrid); 1089 if (qp->db.db) 1090 mlx5_db_free(dev->mdev, &qp->db); 1091 if (qp->buf.frags) 1092 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1093 } 1094 1095 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1096 struct ib_qp_init_attr *init_attr, 1097 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1098 struct mlx5_ib_qp_base *base) 1099 { 1100 int uar_index; 1101 void *qpc; 1102 int err; 1103 1104 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1105 qp->bf.bfreg = &dev->fp_bfreg; 1106 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1107 qp->bf.bfreg = &dev->wc_bfreg; 1108 else 1109 qp->bf.bfreg = &dev->bfreg; 1110 1111 /* We need to divide by two since each register is comprised of 1112 * two buffers of identical size, namely odd and even 1113 */ 1114 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1115 uar_index = qp->bf.bfreg->index; 1116 1117 err = calc_sq_size(dev, init_attr, qp); 1118 if (err < 0) { 1119 mlx5_ib_dbg(dev, "err %d\n", err); 1120 return err; 1121 } 1122 1123 qp->rq.offset = 0; 1124 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1125 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1126 1127 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1128 &qp->buf, dev->mdev->priv.numa_node); 1129 if (err) { 1130 mlx5_ib_dbg(dev, "err %d\n", err); 1131 return err; 1132 } 1133 1134 if (qp->rq.wqe_cnt) 1135 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1136 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1137 1138 if (qp->sq.wqe_cnt) { 1139 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1140 MLX5_SEND_WQE_BB; 1141 mlx5_init_fbc_offset(qp->buf.frags + 1142 (qp->sq.offset / PAGE_SIZE), 1143 ilog2(MLX5_SEND_WQE_BB), 1144 ilog2(qp->sq.wqe_cnt), 1145 sq_strides_offset, &qp->sq.fbc); 1146 1147 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1148 } 1149 1150 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1151 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1152 *in = kvzalloc(*inlen, GFP_KERNEL); 1153 if (!*in) { 1154 err = -ENOMEM; 1155 goto err_buf; 1156 } 1157 1158 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1159 MLX5_SET(qpc, qpc, uar_page, uar_index); 1160 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1161 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1162 1163 /* Set "fast registration enabled" for all kernel QPs */ 1164 MLX5_SET(qpc, qpc, fre, 1); 1165 MLX5_SET(qpc, qpc, rlky, 1); 1166 1167 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1168 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1169 1170 mlx5_fill_page_frag_array(&qp->buf, 1171 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1172 *in, pas)); 1173 1174 err = mlx5_db_alloc(dev->mdev, &qp->db); 1175 if (err) { 1176 mlx5_ib_dbg(dev, "err %d\n", err); 1177 goto err_free; 1178 } 1179 1180 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1181 sizeof(*qp->sq.wrid), GFP_KERNEL); 1182 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1183 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1184 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1185 sizeof(*qp->rq.wrid), GFP_KERNEL); 1186 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1187 sizeof(*qp->sq.w_list), GFP_KERNEL); 1188 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1189 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1190 1191 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1192 !qp->sq.w_list || !qp->sq.wqe_head) { 1193 err = -ENOMEM; 1194 goto err_wrid; 1195 } 1196 1197 return 0; 1198 1199 err_wrid: 1200 kvfree(qp->sq.wqe_head); 1201 kvfree(qp->sq.w_list); 1202 kvfree(qp->sq.wrid); 1203 kvfree(qp->sq.wr_data); 1204 kvfree(qp->rq.wrid); 1205 mlx5_db_free(dev->mdev, &qp->db); 1206 1207 err_free: 1208 kvfree(*in); 1209 1210 err_buf: 1211 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1212 return err; 1213 } 1214 1215 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1216 { 1217 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1218 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1219 return MLX5_SRQ_RQ; 1220 else if (!qp->has_rq) 1221 return MLX5_ZERO_LEN_RQ; 1222 1223 return MLX5_NON_ZERO_RQ; 1224 } 1225 1226 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1227 struct mlx5_ib_qp *qp, 1228 struct mlx5_ib_sq *sq, u32 tdn, 1229 struct ib_pd *pd) 1230 { 1231 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1232 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1233 1234 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1235 MLX5_SET(tisc, tisc, transport_domain, tdn); 1236 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1237 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1238 1239 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1240 } 1241 1242 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1243 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1244 { 1245 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1246 } 1247 1248 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1249 { 1250 if (sq->flow_rule) 1251 mlx5_del_flow_rules(sq->flow_rule); 1252 sq->flow_rule = NULL; 1253 } 1254 1255 static bool fr_supported(int ts_cap) 1256 { 1257 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1258 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1259 } 1260 1261 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1262 bool fr_sup, bool rt_sup) 1263 { 1264 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1265 if (!rt_sup) { 1266 mlx5_ib_dbg(dev, 1267 "Real time TS format is not supported\n"); 1268 return -EOPNOTSUPP; 1269 } 1270 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1271 } 1272 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1273 if (!fr_sup) { 1274 mlx5_ib_dbg(dev, 1275 "Free running TS format is not supported\n"); 1276 return -EOPNOTSUPP; 1277 } 1278 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1279 } 1280 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1281 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1282 } 1283 1284 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1285 { 1286 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1287 1288 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1289 rt_supported(ts_cap)); 1290 } 1291 1292 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1293 { 1294 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1295 1296 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1297 rt_supported(ts_cap)); 1298 } 1299 1300 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1301 struct mlx5_ib_cq *recv_cq) 1302 { 1303 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1304 bool fr_sup = fr_supported(ts_cap); 1305 bool rt_sup = rt_supported(ts_cap); 1306 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1307 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1308 int send_ts_format = 1309 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1310 default_ts; 1311 int recv_ts_format = 1312 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1313 default_ts; 1314 1315 if (send_ts_format < 0 || recv_ts_format < 0) 1316 return -EOPNOTSUPP; 1317 1318 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1319 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1320 send_ts_format != recv_ts_format) { 1321 mlx5_ib_dbg( 1322 dev, 1323 "The send ts_format does not match the receive ts_format\n"); 1324 return -EOPNOTSUPP; 1325 } 1326 1327 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1328 } 1329 1330 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1331 struct ib_udata *udata, 1332 struct mlx5_ib_sq *sq, void *qpin, 1333 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1334 { 1335 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1336 __be64 *pas; 1337 void *in; 1338 void *sqc; 1339 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1340 void *wq; 1341 int inlen; 1342 int err; 1343 unsigned int page_offset_quantized; 1344 unsigned long page_size; 1345 int ts_format; 1346 1347 ts_format = get_sq_ts_format(dev, cq); 1348 if (ts_format < 0) 1349 return ts_format; 1350 1351 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1352 ubuffer->buf_size, 0); 1353 if (IS_ERR(sq->ubuffer.umem)) 1354 return PTR_ERR(sq->ubuffer.umem); 1355 page_size = mlx5_umem_find_best_quantized_pgoff( 1356 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1357 page_offset, 64, &page_offset_quantized); 1358 if (!page_size) { 1359 err = -EINVAL; 1360 goto err_umem; 1361 } 1362 1363 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1364 sizeof(u64) * 1365 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1366 in = kvzalloc(inlen, GFP_KERNEL); 1367 if (!in) { 1368 err = -ENOMEM; 1369 goto err_umem; 1370 } 1371 1372 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1373 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1374 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1375 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1376 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1377 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1378 MLX5_SET(sqc, sqc, ts_format, ts_format); 1379 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1380 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1381 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1382 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1383 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1384 MLX5_CAP_ETH(dev->mdev, swp)) 1385 MLX5_SET(sqc, sqc, allow_swp, 1); 1386 1387 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1388 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1389 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1390 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1391 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1392 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1393 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1394 MLX5_SET(wq, wq, log_wq_pg_sz, 1395 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1396 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1397 1398 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1399 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1400 1401 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1402 1403 kvfree(in); 1404 1405 if (err) 1406 goto err_umem; 1407 1408 return 0; 1409 1410 err_umem: 1411 ib_umem_release(sq->ubuffer.umem); 1412 sq->ubuffer.umem = NULL; 1413 1414 return err; 1415 } 1416 1417 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1418 struct mlx5_ib_sq *sq) 1419 { 1420 destroy_flow_rule_vport_sq(sq); 1421 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1422 ib_umem_release(sq->ubuffer.umem); 1423 } 1424 1425 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1426 struct mlx5_ib_rq *rq, void *qpin, 1427 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1428 { 1429 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1430 __be64 *pas; 1431 void *in; 1432 void *rqc; 1433 void *wq; 1434 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1435 struct ib_umem *umem = rq->base.ubuffer.umem; 1436 unsigned int page_offset_quantized; 1437 unsigned long page_size = 0; 1438 int ts_format; 1439 size_t inlen; 1440 int err; 1441 1442 ts_format = get_rq_ts_format(dev, cq); 1443 if (ts_format < 0) 1444 return ts_format; 1445 1446 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1447 MLX5_ADAPTER_PAGE_SHIFT, 1448 page_offset, 64, 1449 &page_offset_quantized); 1450 if (!page_size) 1451 return -EINVAL; 1452 1453 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1454 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1455 in = kvzalloc(inlen, GFP_KERNEL); 1456 if (!in) 1457 return -ENOMEM; 1458 1459 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1460 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1461 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1462 MLX5_SET(rqc, rqc, vsd, 1); 1463 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1464 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1465 MLX5_SET(rqc, rqc, ts_format, ts_format); 1466 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1467 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1468 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1469 1470 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1471 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1472 1473 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1474 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1475 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1476 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1477 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1478 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1479 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1480 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1481 MLX5_SET(wq, wq, log_wq_pg_sz, 1482 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1483 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1484 1485 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1486 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1487 1488 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1489 1490 kvfree(in); 1491 1492 return err; 1493 } 1494 1495 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1496 struct mlx5_ib_rq *rq) 1497 { 1498 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1499 } 1500 1501 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1502 struct mlx5_ib_rq *rq, 1503 u32 qp_flags_en, 1504 struct ib_pd *pd) 1505 { 1506 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1507 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1508 mlx5_ib_disable_lb(dev, false, true); 1509 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1510 } 1511 1512 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1513 struct mlx5_ib_rq *rq, u32 tdn, 1514 u32 *qp_flags_en, struct ib_pd *pd, 1515 u32 *out) 1516 { 1517 u8 lb_flag = 0; 1518 u32 *in; 1519 void *tirc; 1520 int inlen; 1521 int err; 1522 1523 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1524 in = kvzalloc(inlen, GFP_KERNEL); 1525 if (!in) 1526 return -ENOMEM; 1527 1528 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1529 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1530 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1531 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1532 MLX5_SET(tirc, tirc, transport_domain, tdn); 1533 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1534 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1535 1536 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1537 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1538 1539 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1540 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1541 1542 if (dev->is_rep) { 1543 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1544 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1545 } 1546 1547 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1548 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1549 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1550 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1551 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1552 err = mlx5_ib_enable_lb(dev, false, true); 1553 1554 if (err) 1555 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1556 } 1557 kvfree(in); 1558 1559 return err; 1560 } 1561 1562 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1563 u32 *in, size_t inlen, struct ib_pd *pd, 1564 struct ib_udata *udata, 1565 struct mlx5_ib_create_qp_resp *resp, 1566 struct ib_qp_init_attr *init_attr) 1567 { 1568 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1569 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1570 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1571 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1572 udata, struct mlx5_ib_ucontext, ibucontext); 1573 int err; 1574 u32 tdn = mucontext->tdn; 1575 u16 uid = to_mpd(pd)->uid; 1576 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1577 1578 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1579 return -EINVAL; 1580 if (qp->sq.wqe_cnt) { 1581 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1582 if (err) 1583 return err; 1584 1585 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1586 to_mcq(init_attr->send_cq)); 1587 if (err) 1588 goto err_destroy_tis; 1589 1590 if (uid) { 1591 resp->tisn = sq->tisn; 1592 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1593 resp->sqn = sq->base.mqp.qpn; 1594 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1595 } 1596 1597 sq->base.container_mibqp = qp; 1598 sq->base.mqp.event = mlx5_ib_qp_event; 1599 } 1600 1601 if (qp->rq.wqe_cnt) { 1602 rq->base.container_mibqp = qp; 1603 1604 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1605 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1606 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1607 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1608 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1609 to_mcq(init_attr->recv_cq)); 1610 if (err) 1611 goto err_destroy_sq; 1612 1613 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1614 out); 1615 if (err) 1616 goto err_destroy_rq; 1617 1618 if (uid) { 1619 resp->rqn = rq->base.mqp.qpn; 1620 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1621 resp->tirn = rq->tirn; 1622 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1623 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1624 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1625 resp->tir_icm_addr = MLX5_GET( 1626 create_tir_out, out, icm_address_31_0); 1627 resp->tir_icm_addr |= 1628 (u64)MLX5_GET(create_tir_out, out, 1629 icm_address_39_32) 1630 << 32; 1631 resp->tir_icm_addr |= 1632 (u64)MLX5_GET(create_tir_out, out, 1633 icm_address_63_40) 1634 << 40; 1635 resp->comp_mask |= 1636 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1637 } 1638 } 1639 } 1640 1641 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1642 rq->base.mqp.qpn; 1643 return 0; 1644 1645 err_destroy_rq: 1646 destroy_raw_packet_qp_rq(dev, rq); 1647 err_destroy_sq: 1648 if (!qp->sq.wqe_cnt) 1649 return err; 1650 destroy_raw_packet_qp_sq(dev, sq); 1651 err_destroy_tis: 1652 destroy_raw_packet_qp_tis(dev, sq, pd); 1653 1654 return err; 1655 } 1656 1657 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1658 struct mlx5_ib_qp *qp) 1659 { 1660 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1661 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1662 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1663 1664 if (qp->rq.wqe_cnt) { 1665 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1666 destroy_raw_packet_qp_rq(dev, rq); 1667 } 1668 1669 if (qp->sq.wqe_cnt) { 1670 destroy_raw_packet_qp_sq(dev, sq); 1671 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1672 } 1673 } 1674 1675 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1676 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1677 { 1678 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1679 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1680 1681 sq->sq = &qp->sq; 1682 rq->rq = &qp->rq; 1683 sq->doorbell = &qp->db; 1684 rq->doorbell = &qp->db; 1685 } 1686 1687 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1688 { 1689 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1690 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1691 mlx5_ib_disable_lb(dev, false, true); 1692 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1693 to_mpd(qp->ibqp.pd)->uid); 1694 } 1695 1696 struct mlx5_create_qp_params { 1697 struct ib_udata *udata; 1698 size_t inlen; 1699 size_t outlen; 1700 size_t ucmd_size; 1701 void *ucmd; 1702 u8 is_rss_raw : 1; 1703 struct ib_qp_init_attr *attr; 1704 u32 uidx; 1705 struct mlx5_ib_create_qp_resp resp; 1706 }; 1707 1708 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1709 struct mlx5_ib_qp *qp, 1710 struct mlx5_create_qp_params *params) 1711 { 1712 struct ib_qp_init_attr *init_attr = params->attr; 1713 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1714 struct ib_udata *udata = params->udata; 1715 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1716 udata, struct mlx5_ib_ucontext, ibucontext); 1717 int inlen; 1718 int outlen; 1719 int err; 1720 u32 *in; 1721 u32 *out; 1722 void *tirc; 1723 void *hfso; 1724 u32 selected_fields = 0; 1725 u32 outer_l4; 1726 u32 tdn = mucontext->tdn; 1727 u8 lb_flag = 0; 1728 1729 if (ucmd->comp_mask) { 1730 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1731 return -EOPNOTSUPP; 1732 } 1733 1734 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1735 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1736 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1737 return -EOPNOTSUPP; 1738 } 1739 1740 if (dev->is_rep) 1741 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1742 1743 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1744 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1745 1746 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1747 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1748 1749 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1750 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1751 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1752 if (!in) 1753 return -ENOMEM; 1754 1755 out = in + MLX5_ST_SZ_DW(create_tir_in); 1756 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1757 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1758 MLX5_SET(tirc, tirc, disp_type, 1759 MLX5_TIRC_DISP_TYPE_INDIRECT); 1760 MLX5_SET(tirc, tirc, indirect_table, 1761 init_attr->rwq_ind_tbl->ind_tbl_num); 1762 MLX5_SET(tirc, tirc, transport_domain, tdn); 1763 1764 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1765 1766 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1767 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1768 1769 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1770 1771 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1772 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1773 else 1774 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1775 1776 switch (ucmd->rx_hash_function) { 1777 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1778 { 1779 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1780 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1781 1782 if (len != ucmd->rx_key_len) { 1783 err = -EINVAL; 1784 goto err; 1785 } 1786 1787 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1788 memcpy(rss_key, ucmd->rx_hash_key, len); 1789 break; 1790 } 1791 default: 1792 err = -EOPNOTSUPP; 1793 goto err; 1794 } 1795 1796 if (!ucmd->rx_hash_fields_mask) { 1797 /* special case when this TIR serves as steering entry without hashing */ 1798 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1799 goto create_tir; 1800 err = -EINVAL; 1801 goto err; 1802 } 1803 1804 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1805 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1806 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1807 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1808 err = -EINVAL; 1809 goto err; 1810 } 1811 1812 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1813 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1814 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1815 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1816 MLX5_L3_PROT_TYPE_IPV4); 1817 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1818 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1819 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1820 MLX5_L3_PROT_TYPE_IPV6); 1821 1822 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1823 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1824 << 0 | 1825 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1826 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1827 << 1 | 1828 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1829 1830 /* Check that only one l4 protocol is set */ 1831 if (outer_l4 & (outer_l4 - 1)) { 1832 err = -EINVAL; 1833 goto err; 1834 } 1835 1836 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1837 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1838 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1839 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1840 MLX5_L4_PROT_TYPE_TCP); 1841 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1842 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1843 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1844 MLX5_L4_PROT_TYPE_UDP); 1845 1846 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1847 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1848 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1849 1850 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1851 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1852 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1853 1854 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1855 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1856 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1857 1858 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1859 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1860 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1861 1862 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1863 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1864 1865 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1866 1867 create_tir: 1868 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1869 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1870 1871 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1872 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1873 err = mlx5_ib_enable_lb(dev, false, true); 1874 1875 if (err) 1876 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1877 to_mpd(pd)->uid); 1878 } 1879 1880 if (err) 1881 goto err; 1882 1883 if (mucontext->devx_uid) { 1884 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1885 params->resp.tirn = qp->rss_qp.tirn; 1886 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1887 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1888 params->resp.tir_icm_addr = 1889 MLX5_GET(create_tir_out, out, icm_address_31_0); 1890 params->resp.tir_icm_addr |= 1891 (u64)MLX5_GET(create_tir_out, out, 1892 icm_address_39_32) 1893 << 32; 1894 params->resp.tir_icm_addr |= 1895 (u64)MLX5_GET(create_tir_out, out, 1896 icm_address_63_40) 1897 << 40; 1898 params->resp.comp_mask |= 1899 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1900 } 1901 } 1902 1903 kvfree(in); 1904 /* qpn is reserved for that QP */ 1905 qp->trans_qp.base.mqp.qpn = 0; 1906 qp->is_rss = true; 1907 return 0; 1908 1909 err: 1910 kvfree(in); 1911 return err; 1912 } 1913 1914 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1915 struct mlx5_ib_qp *qp, 1916 struct ib_qp_init_attr *init_attr, 1917 void *qpc) 1918 { 1919 int scqe_sz; 1920 bool allow_scat_cqe = false; 1921 1922 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1923 1924 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1925 return; 1926 1927 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1928 if (scqe_sz == 128) { 1929 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1930 return; 1931 } 1932 1933 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1934 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1935 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1936 } 1937 1938 static int atomic_size_to_mode(int size_mask) 1939 { 1940 /* driver does not support atomic_size > 256B 1941 * and does not know how to translate bigger sizes 1942 */ 1943 int supported_size_mask = size_mask & 0x1ff; 1944 int log_max_size; 1945 1946 if (!supported_size_mask) 1947 return -EOPNOTSUPP; 1948 1949 log_max_size = __fls(supported_size_mask); 1950 1951 if (log_max_size > 3) 1952 return log_max_size; 1953 1954 return MLX5_ATOMIC_MODE_8B; 1955 } 1956 1957 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1958 enum ib_qp_type qp_type) 1959 { 1960 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1961 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1962 int atomic_mode = -EOPNOTSUPP; 1963 int atomic_size_mask; 1964 1965 if (!atomic) 1966 return -EOPNOTSUPP; 1967 1968 if (qp_type == MLX5_IB_QPT_DCT) 1969 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1970 else 1971 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1972 1973 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1974 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1975 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1976 1977 if (atomic_mode <= 0 && 1978 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1979 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1980 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1981 1982 return atomic_mode; 1983 } 1984 1985 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1986 struct mlx5_create_qp_params *params) 1987 { 1988 struct ib_qp_init_attr *attr = params->attr; 1989 u32 uidx = params->uidx; 1990 struct mlx5_ib_resources *devr = &dev->devr; 1991 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1992 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1993 struct mlx5_core_dev *mdev = dev->mdev; 1994 struct mlx5_ib_qp_base *base; 1995 unsigned long flags; 1996 void *qpc; 1997 u32 *in; 1998 int err; 1999 2000 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2001 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2002 2003 in = kvzalloc(inlen, GFP_KERNEL); 2004 if (!in) 2005 return -ENOMEM; 2006 2007 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2008 2009 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 2010 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2011 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 2012 2013 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2014 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2015 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2016 MLX5_SET(qpc, qpc, cd_master, 1); 2017 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2018 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2019 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2020 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2021 2022 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 2023 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 2024 MLX5_SET(qpc, qpc, no_sq, 1); 2025 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2026 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2027 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2028 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 2029 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2030 2031 /* 0xffffff means we ask to work with cqe version 0 */ 2032 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2033 MLX5_SET(qpc, qpc, user_index, uidx); 2034 2035 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2036 MLX5_SET(qpc, qpc, end_padding_mode, 2037 MLX5_WQ_END_PAD_MODE_ALIGN); 2038 /* Special case to clean flag */ 2039 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2040 } 2041 2042 base = &qp->trans_qp.base; 2043 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2044 kvfree(in); 2045 if (err) 2046 return err; 2047 2048 base->container_mibqp = qp; 2049 base->mqp.event = mlx5_ib_qp_event; 2050 if (MLX5_CAP_GEN(mdev, ece_support)) 2051 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2052 2053 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2054 list_add_tail(&qp->qps_list, &dev->qp_list); 2055 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2056 2057 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 2058 return 0; 2059 } 2060 2061 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2062 struct mlx5_ib_qp *qp, 2063 struct mlx5_create_qp_params *params) 2064 { 2065 struct ib_qp_init_attr *init_attr = params->attr; 2066 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2067 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2068 struct ib_udata *udata = params->udata; 2069 u32 uidx = params->uidx; 2070 struct mlx5_ib_resources *devr = &dev->devr; 2071 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2072 struct mlx5_core_dev *mdev = dev->mdev; 2073 struct mlx5_ib_cq *send_cq; 2074 struct mlx5_ib_cq *recv_cq; 2075 unsigned long flags; 2076 struct mlx5_ib_qp_base *base; 2077 int ts_format; 2078 int mlx5_st; 2079 void *qpc; 2080 u32 *in; 2081 int err; 2082 2083 spin_lock_init(&qp->sq.lock); 2084 spin_lock_init(&qp->rq.lock); 2085 2086 mlx5_st = to_mlx5_st(qp->type); 2087 if (mlx5_st < 0) 2088 return -EINVAL; 2089 2090 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2091 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2092 2093 base = &qp->trans_qp.base; 2094 2095 qp->has_rq = qp_has_rq(init_attr); 2096 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2097 if (err) { 2098 mlx5_ib_dbg(dev, "err %d\n", err); 2099 return err; 2100 } 2101 2102 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2103 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2104 return -EINVAL; 2105 2106 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2107 return -EINVAL; 2108 2109 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2110 to_mcq(init_attr->recv_cq)); 2111 2112 if (ts_format < 0) 2113 return ts_format; 2114 2115 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2116 &inlen, base, ucmd); 2117 if (err) 2118 return err; 2119 2120 if (MLX5_CAP_GEN(mdev, ece_support)) 2121 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2122 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2123 2124 MLX5_SET(qpc, qpc, st, mlx5_st); 2125 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2126 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2127 2128 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2129 MLX5_SET(qpc, qpc, wq_signature, 1); 2130 2131 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2132 MLX5_SET(qpc, qpc, cd_master, 1); 2133 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2134 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2135 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2136 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2137 2138 if (qp->rq.wqe_cnt) { 2139 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2140 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2141 } 2142 2143 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2144 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2145 ucmd->dci_streams.log_num_concurent); 2146 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2147 ucmd->dci_streams.log_num_errored); 2148 } 2149 2150 MLX5_SET(qpc, qpc, ts_format, ts_format); 2151 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2152 2153 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2154 2155 /* Set default resources */ 2156 if (init_attr->srq) { 2157 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2158 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2159 to_msrq(init_attr->srq)->msrq.srqn); 2160 } else { 2161 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2162 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2163 to_msrq(devr->s1)->msrq.srqn); 2164 } 2165 2166 if (init_attr->send_cq) 2167 MLX5_SET(qpc, qpc, cqn_snd, 2168 to_mcq(init_attr->send_cq)->mcq.cqn); 2169 2170 if (init_attr->recv_cq) 2171 MLX5_SET(qpc, qpc, cqn_rcv, 2172 to_mcq(init_attr->recv_cq)->mcq.cqn); 2173 2174 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2175 2176 /* 0xffffff means we ask to work with cqe version 0 */ 2177 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2178 MLX5_SET(qpc, qpc, user_index, uidx); 2179 2180 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2181 MLX5_SET(qpc, qpc, end_padding_mode, 2182 MLX5_WQ_END_PAD_MODE_ALIGN); 2183 /* Special case to clean flag */ 2184 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2185 } 2186 2187 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2188 2189 kvfree(in); 2190 if (err) 2191 goto err_create; 2192 2193 base->container_mibqp = qp; 2194 base->mqp.event = mlx5_ib_qp_event; 2195 if (MLX5_CAP_GEN(mdev, ece_support)) 2196 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2197 2198 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2199 &send_cq, &recv_cq); 2200 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2201 mlx5_ib_lock_cqs(send_cq, recv_cq); 2202 /* Maintain device to QPs access, needed for further handling via reset 2203 * flow 2204 */ 2205 list_add_tail(&qp->qps_list, &dev->qp_list); 2206 /* Maintain CQ to QPs access, needed for further handling via reset flow 2207 */ 2208 if (send_cq) 2209 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2210 if (recv_cq) 2211 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2212 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2213 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2214 2215 return 0; 2216 2217 err_create: 2218 destroy_qp(dev, qp, base, udata); 2219 return err; 2220 } 2221 2222 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2223 struct mlx5_ib_qp *qp, 2224 struct mlx5_create_qp_params *params) 2225 { 2226 struct ib_qp_init_attr *init_attr = params->attr; 2227 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2228 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2229 struct ib_udata *udata = params->udata; 2230 u32 uidx = params->uidx; 2231 struct mlx5_ib_resources *devr = &dev->devr; 2232 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2233 struct mlx5_core_dev *mdev = dev->mdev; 2234 struct mlx5_ib_cq *send_cq; 2235 struct mlx5_ib_cq *recv_cq; 2236 unsigned long flags; 2237 struct mlx5_ib_qp_base *base; 2238 int ts_format; 2239 int mlx5_st; 2240 void *qpc; 2241 u32 *in; 2242 int err; 2243 2244 spin_lock_init(&qp->sq.lock); 2245 spin_lock_init(&qp->rq.lock); 2246 2247 mlx5_st = to_mlx5_st(qp->type); 2248 if (mlx5_st < 0) 2249 return -EINVAL; 2250 2251 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2252 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2253 2254 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2255 qp->underlay_qpn = init_attr->source_qpn; 2256 2257 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2258 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2259 &qp->raw_packet_qp.rq.base : 2260 &qp->trans_qp.base; 2261 2262 qp->has_rq = qp_has_rq(init_attr); 2263 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2264 if (err) { 2265 mlx5_ib_dbg(dev, "err %d\n", err); 2266 return err; 2267 } 2268 2269 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2270 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2271 return -EINVAL; 2272 2273 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2274 return -EINVAL; 2275 2276 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2277 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2278 to_mcq(init_attr->recv_cq)); 2279 if (ts_format < 0) 2280 return ts_format; 2281 } 2282 2283 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2284 &inlen, base, ucmd); 2285 if (err) 2286 return err; 2287 2288 if (is_sqp(init_attr->qp_type)) 2289 qp->port = init_attr->port_num; 2290 2291 if (MLX5_CAP_GEN(mdev, ece_support)) 2292 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2293 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2294 2295 MLX5_SET(qpc, qpc, st, mlx5_st); 2296 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2297 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2298 2299 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2300 MLX5_SET(qpc, qpc, wq_signature, 1); 2301 2302 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2303 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2304 2305 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2306 MLX5_SET(qpc, qpc, cd_master, 1); 2307 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2308 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2309 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2310 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2311 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2312 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2313 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2314 (init_attr->qp_type == IB_QPT_RC || 2315 init_attr->qp_type == IB_QPT_UC)) { 2316 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2317 2318 MLX5_SET(qpc, qpc, cs_res, 2319 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2320 MLX5_RES_SCAT_DATA32_CQE); 2321 } 2322 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2323 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2324 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2325 2326 if (qp->rq.wqe_cnt) { 2327 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2328 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2329 } 2330 2331 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2332 MLX5_SET(qpc, qpc, ts_format, ts_format); 2333 2334 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2335 2336 if (qp->sq.wqe_cnt) { 2337 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2338 } else { 2339 MLX5_SET(qpc, qpc, no_sq, 1); 2340 if (init_attr->srq && 2341 init_attr->srq->srq_type == IB_SRQT_TM) 2342 MLX5_SET(qpc, qpc, offload_type, 2343 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2344 } 2345 2346 /* Set default resources */ 2347 switch (init_attr->qp_type) { 2348 case IB_QPT_XRC_INI: 2349 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2350 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2351 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2352 break; 2353 default: 2354 if (init_attr->srq) { 2355 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2356 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2357 } else { 2358 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2359 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2360 } 2361 } 2362 2363 if (init_attr->send_cq) 2364 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2365 2366 if (init_attr->recv_cq) 2367 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2368 2369 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2370 2371 /* 0xffffff means we ask to work with cqe version 0 */ 2372 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2373 MLX5_SET(qpc, qpc, user_index, uidx); 2374 2375 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2376 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2377 MLX5_SET(qpc, qpc, end_padding_mode, 2378 MLX5_WQ_END_PAD_MODE_ALIGN); 2379 /* Special case to clean flag */ 2380 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2381 } 2382 2383 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2384 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2385 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2386 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2387 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2388 ¶ms->resp, init_attr); 2389 } else 2390 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2391 2392 kvfree(in); 2393 if (err) 2394 goto err_create; 2395 2396 base->container_mibqp = qp; 2397 base->mqp.event = mlx5_ib_qp_event; 2398 if (MLX5_CAP_GEN(mdev, ece_support)) 2399 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2400 2401 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2402 &send_cq, &recv_cq); 2403 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2404 mlx5_ib_lock_cqs(send_cq, recv_cq); 2405 /* Maintain device to QPs access, needed for further handling via reset 2406 * flow 2407 */ 2408 list_add_tail(&qp->qps_list, &dev->qp_list); 2409 /* Maintain CQ to QPs access, needed for further handling via reset flow 2410 */ 2411 if (send_cq) 2412 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2413 if (recv_cq) 2414 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2415 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2416 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2417 2418 return 0; 2419 2420 err_create: 2421 destroy_qp(dev, qp, base, udata); 2422 return err; 2423 } 2424 2425 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2426 struct mlx5_ib_qp *qp, 2427 struct mlx5_create_qp_params *params) 2428 { 2429 struct ib_qp_init_attr *attr = params->attr; 2430 u32 uidx = params->uidx; 2431 struct mlx5_ib_resources *devr = &dev->devr; 2432 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2433 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2434 struct mlx5_core_dev *mdev = dev->mdev; 2435 struct mlx5_ib_cq *send_cq; 2436 struct mlx5_ib_cq *recv_cq; 2437 unsigned long flags; 2438 struct mlx5_ib_qp_base *base; 2439 int mlx5_st; 2440 void *qpc; 2441 u32 *in; 2442 int err; 2443 2444 spin_lock_init(&qp->sq.lock); 2445 spin_lock_init(&qp->rq.lock); 2446 2447 mlx5_st = to_mlx5_st(qp->type); 2448 if (mlx5_st < 0) 2449 return -EINVAL; 2450 2451 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2452 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2453 2454 base = &qp->trans_qp.base; 2455 2456 qp->has_rq = qp_has_rq(attr); 2457 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2458 if (err) { 2459 mlx5_ib_dbg(dev, "err %d\n", err); 2460 return err; 2461 } 2462 2463 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2464 if (err) 2465 return err; 2466 2467 if (is_sqp(attr->qp_type)) 2468 qp->port = attr->port_num; 2469 2470 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2471 2472 MLX5_SET(qpc, qpc, st, mlx5_st); 2473 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2474 2475 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2476 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2477 else 2478 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2479 2480 2481 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2482 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2483 2484 if (qp->rq.wqe_cnt) { 2485 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2486 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2487 } 2488 2489 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2490 2491 if (qp->sq.wqe_cnt) 2492 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2493 else 2494 MLX5_SET(qpc, qpc, no_sq, 1); 2495 2496 if (attr->srq) { 2497 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2498 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2499 to_msrq(attr->srq)->msrq.srqn); 2500 } else { 2501 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2502 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2503 to_msrq(devr->s1)->msrq.srqn); 2504 } 2505 2506 if (attr->send_cq) 2507 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2508 2509 if (attr->recv_cq) 2510 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2511 2512 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2513 2514 /* 0xffffff means we ask to work with cqe version 0 */ 2515 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2516 MLX5_SET(qpc, qpc, user_index, uidx); 2517 2518 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2519 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2520 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2521 2522 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2523 kvfree(in); 2524 if (err) 2525 goto err_create; 2526 2527 base->container_mibqp = qp; 2528 base->mqp.event = mlx5_ib_qp_event; 2529 2530 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2531 &send_cq, &recv_cq); 2532 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2533 mlx5_ib_lock_cqs(send_cq, recv_cq); 2534 /* Maintain device to QPs access, needed for further handling via reset 2535 * flow 2536 */ 2537 list_add_tail(&qp->qps_list, &dev->qp_list); 2538 /* Maintain CQ to QPs access, needed for further handling via reset flow 2539 */ 2540 if (send_cq) 2541 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2542 if (recv_cq) 2543 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2544 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2545 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2546 2547 return 0; 2548 2549 err_create: 2550 destroy_qp(dev, qp, base, NULL); 2551 return err; 2552 } 2553 2554 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2555 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2556 { 2557 if (send_cq) { 2558 if (recv_cq) { 2559 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2560 spin_lock(&send_cq->lock); 2561 spin_lock_nested(&recv_cq->lock, 2562 SINGLE_DEPTH_NESTING); 2563 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2564 spin_lock(&send_cq->lock); 2565 __acquire(&recv_cq->lock); 2566 } else { 2567 spin_lock(&recv_cq->lock); 2568 spin_lock_nested(&send_cq->lock, 2569 SINGLE_DEPTH_NESTING); 2570 } 2571 } else { 2572 spin_lock(&send_cq->lock); 2573 __acquire(&recv_cq->lock); 2574 } 2575 } else if (recv_cq) { 2576 spin_lock(&recv_cq->lock); 2577 __acquire(&send_cq->lock); 2578 } else { 2579 __acquire(&send_cq->lock); 2580 __acquire(&recv_cq->lock); 2581 } 2582 } 2583 2584 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2585 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2586 { 2587 if (send_cq) { 2588 if (recv_cq) { 2589 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2590 spin_unlock(&recv_cq->lock); 2591 spin_unlock(&send_cq->lock); 2592 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2593 __release(&recv_cq->lock); 2594 spin_unlock(&send_cq->lock); 2595 } else { 2596 spin_unlock(&send_cq->lock); 2597 spin_unlock(&recv_cq->lock); 2598 } 2599 } else { 2600 __release(&recv_cq->lock); 2601 spin_unlock(&send_cq->lock); 2602 } 2603 } else if (recv_cq) { 2604 __release(&send_cq->lock); 2605 spin_unlock(&recv_cq->lock); 2606 } else { 2607 __release(&recv_cq->lock); 2608 __release(&send_cq->lock); 2609 } 2610 } 2611 2612 static void get_cqs(enum ib_qp_type qp_type, 2613 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2614 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2615 { 2616 switch (qp_type) { 2617 case IB_QPT_XRC_TGT: 2618 *send_cq = NULL; 2619 *recv_cq = NULL; 2620 break; 2621 case MLX5_IB_QPT_REG_UMR: 2622 case IB_QPT_XRC_INI: 2623 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2624 *recv_cq = NULL; 2625 break; 2626 2627 case IB_QPT_SMI: 2628 case MLX5_IB_QPT_HW_GSI: 2629 case IB_QPT_RC: 2630 case IB_QPT_UC: 2631 case IB_QPT_UD: 2632 case IB_QPT_RAW_PACKET: 2633 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2634 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2635 break; 2636 default: 2637 *send_cq = NULL; 2638 *recv_cq = NULL; 2639 break; 2640 } 2641 } 2642 2643 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2644 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2645 u8 lag_tx_affinity); 2646 2647 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2648 struct ib_udata *udata) 2649 { 2650 struct mlx5_ib_cq *send_cq, *recv_cq; 2651 struct mlx5_ib_qp_base *base; 2652 unsigned long flags; 2653 int err; 2654 2655 if (qp->is_rss) { 2656 destroy_rss_raw_qp_tir(dev, qp); 2657 return; 2658 } 2659 2660 base = (qp->type == IB_QPT_RAW_PACKET || 2661 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2662 &qp->raw_packet_qp.rq.base : 2663 &qp->trans_qp.base; 2664 2665 if (qp->state != IB_QPS_RESET) { 2666 if (qp->type != IB_QPT_RAW_PACKET && 2667 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2668 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2669 NULL, &base->mqp, NULL); 2670 } else { 2671 struct mlx5_modify_raw_qp_param raw_qp_param = { 2672 .operation = MLX5_CMD_OP_2RST_QP 2673 }; 2674 2675 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2676 } 2677 if (err) 2678 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2679 base->mqp.qpn); 2680 } 2681 2682 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2683 &recv_cq); 2684 2685 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2686 mlx5_ib_lock_cqs(send_cq, recv_cq); 2687 /* del from lists under both locks above to protect reset flow paths */ 2688 list_del(&qp->qps_list); 2689 if (send_cq) 2690 list_del(&qp->cq_send_list); 2691 2692 if (recv_cq) 2693 list_del(&qp->cq_recv_list); 2694 2695 if (!udata) { 2696 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2697 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2698 if (send_cq != recv_cq) 2699 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2700 NULL); 2701 } 2702 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2703 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2704 2705 if (qp->type == IB_QPT_RAW_PACKET || 2706 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2707 destroy_raw_packet_qp(dev, qp); 2708 } else { 2709 err = mlx5_core_destroy_qp(dev, &base->mqp); 2710 if (err) 2711 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2712 base->mqp.qpn); 2713 } 2714 2715 destroy_qp(dev, qp, base, udata); 2716 } 2717 2718 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2719 struct mlx5_ib_qp *qp, 2720 struct mlx5_create_qp_params *params) 2721 { 2722 struct ib_qp_init_attr *attr = params->attr; 2723 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2724 u32 uidx = params->uidx; 2725 void *dctc; 2726 2727 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2728 return -EOPNOTSUPP; 2729 2730 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2731 if (!qp->dct.in) 2732 return -ENOMEM; 2733 2734 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2735 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2736 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2737 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2738 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2739 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2740 MLX5_SET(dctc, dctc, user_index, uidx); 2741 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2742 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2743 2744 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2745 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2746 2747 if (rcqe_sz == 128) 2748 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2749 } 2750 2751 qp->state = IB_QPS_RESET; 2752 return 0; 2753 } 2754 2755 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2756 enum ib_qp_type *type) 2757 { 2758 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2759 goto out; 2760 2761 switch (attr->qp_type) { 2762 case IB_QPT_XRC_TGT: 2763 case IB_QPT_XRC_INI: 2764 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2765 goto out; 2766 fallthrough; 2767 case IB_QPT_RC: 2768 case IB_QPT_UC: 2769 case IB_QPT_SMI: 2770 case MLX5_IB_QPT_HW_GSI: 2771 case IB_QPT_DRIVER: 2772 case IB_QPT_GSI: 2773 case IB_QPT_RAW_PACKET: 2774 case IB_QPT_UD: 2775 case MLX5_IB_QPT_REG_UMR: 2776 break; 2777 default: 2778 goto out; 2779 } 2780 2781 *type = attr->qp_type; 2782 return 0; 2783 2784 out: 2785 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2786 return -EOPNOTSUPP; 2787 } 2788 2789 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2790 struct ib_qp_init_attr *attr, 2791 struct ib_udata *udata) 2792 { 2793 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2794 udata, struct mlx5_ib_ucontext, ibucontext); 2795 2796 if (!udata) { 2797 /* Kernel create_qp callers */ 2798 if (attr->rwq_ind_tbl) 2799 return -EOPNOTSUPP; 2800 2801 switch (attr->qp_type) { 2802 case IB_QPT_RAW_PACKET: 2803 case IB_QPT_DRIVER: 2804 return -EOPNOTSUPP; 2805 default: 2806 return 0; 2807 } 2808 } 2809 2810 /* Userspace create_qp callers */ 2811 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2812 mlx5_ib_dbg(dev, 2813 "Raw Packet QP is only supported for CQE version > 0\n"); 2814 return -EINVAL; 2815 } 2816 2817 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2818 mlx5_ib_dbg(dev, 2819 "Wrong QP type %d for the RWQ indirect table\n", 2820 attr->qp_type); 2821 return -EINVAL; 2822 } 2823 2824 /* 2825 * We don't need to see this warning, it means that kernel code 2826 * missing ib_pd. Placed here to catch developer's mistakes. 2827 */ 2828 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2829 "There is a missing PD pointer assignment\n"); 2830 return 0; 2831 } 2832 2833 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2834 bool cond, struct mlx5_ib_qp *qp) 2835 { 2836 if (!(*flags & flag)) 2837 return; 2838 2839 if (cond) { 2840 qp->flags_en |= flag; 2841 *flags &= ~flag; 2842 return; 2843 } 2844 2845 switch (flag) { 2846 case MLX5_QP_FLAG_SCATTER_CQE: 2847 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2848 /* 2849 * We don't return error if these flags were provided, 2850 * and mlx5 doesn't have right capability. 2851 */ 2852 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2853 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2854 return; 2855 default: 2856 break; 2857 } 2858 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2859 } 2860 2861 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2862 void *ucmd, struct ib_qp_init_attr *attr) 2863 { 2864 struct mlx5_core_dev *mdev = dev->mdev; 2865 bool cond; 2866 int flags; 2867 2868 if (attr->rwq_ind_tbl) 2869 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2870 else 2871 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2872 2873 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2874 case MLX5_QP_FLAG_TYPE_DCI: 2875 qp->type = MLX5_IB_QPT_DCI; 2876 break; 2877 case MLX5_QP_FLAG_TYPE_DCT: 2878 qp->type = MLX5_IB_QPT_DCT; 2879 break; 2880 default: 2881 if (qp->type != IB_QPT_DRIVER) 2882 break; 2883 /* 2884 * It is IB_QPT_DRIVER and or no subtype or 2885 * wrong subtype were provided. 2886 */ 2887 return -EINVAL; 2888 } 2889 2890 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2891 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2892 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2893 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2894 qp); 2895 2896 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2897 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2898 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2899 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2900 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2901 2902 if (qp->type == IB_QPT_RAW_PACKET) { 2903 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2904 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2905 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2906 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2907 cond, qp); 2908 process_vendor_flag(dev, &flags, 2909 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2910 qp); 2911 process_vendor_flag(dev, &flags, 2912 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2913 qp); 2914 } 2915 2916 if (qp->type == IB_QPT_RC) 2917 process_vendor_flag(dev, &flags, 2918 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2919 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2920 2921 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2922 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2923 2924 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2925 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2926 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2927 if (attr->rwq_ind_tbl && cond) { 2928 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2929 cond); 2930 return -EINVAL; 2931 } 2932 2933 if (flags) 2934 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2935 2936 return (flags) ? -EINVAL : 0; 2937 } 2938 2939 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2940 bool cond, struct mlx5_ib_qp *qp) 2941 { 2942 if (!(*flags & flag)) 2943 return; 2944 2945 if (cond) { 2946 qp->flags |= flag; 2947 *flags &= ~flag; 2948 return; 2949 } 2950 2951 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2952 /* 2953 * Special case, if condition didn't meet, it won't be error, 2954 * just different in-kernel flow. 2955 */ 2956 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2957 return; 2958 } 2959 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2960 } 2961 2962 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2963 struct ib_qp_init_attr *attr) 2964 { 2965 enum ib_qp_type qp_type = qp->type; 2966 struct mlx5_core_dev *mdev = dev->mdev; 2967 int create_flags = attr->create_flags; 2968 bool cond; 2969 2970 if (qp_type == MLX5_IB_QPT_DCT) 2971 return (create_flags) ? -EINVAL : 0; 2972 2973 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2974 return (create_flags) ? -EINVAL : 0; 2975 2976 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2977 mlx5_get_flow_namespace(dev->mdev, 2978 MLX5_FLOW_NAMESPACE_BYPASS), 2979 qp); 2980 process_create_flag(dev, &create_flags, 2981 IB_QP_CREATE_INTEGRITY_EN, 2982 MLX5_CAP_GEN(mdev, sho), qp); 2983 process_create_flag(dev, &create_flags, 2984 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2985 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2986 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2987 MLX5_CAP_GEN(mdev, cd), qp); 2988 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2989 MLX5_CAP_GEN(mdev, cd), qp); 2990 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2991 MLX5_CAP_GEN(mdev, cd), qp); 2992 2993 if (qp_type == IB_QPT_UD) { 2994 process_create_flag(dev, &create_flags, 2995 IB_QP_CREATE_IPOIB_UD_LSO, 2996 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2997 qp); 2998 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2999 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 3000 cond, qp); 3001 } 3002 3003 if (qp_type == IB_QPT_RAW_PACKET) { 3004 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3005 MLX5_CAP_ETH(mdev, scatter_fcs); 3006 process_create_flag(dev, &create_flags, 3007 IB_QP_CREATE_SCATTER_FCS, cond, qp); 3008 3009 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3010 MLX5_CAP_ETH(mdev, vlan_cap); 3011 process_create_flag(dev, &create_flags, 3012 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 3013 } 3014 3015 process_create_flag(dev, &create_flags, 3016 IB_QP_CREATE_PCI_WRITE_END_PADDING, 3017 MLX5_CAP_GEN(mdev, end_pad), qp); 3018 3019 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 3020 qp_type != MLX5_IB_QPT_REG_UMR, qp); 3021 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 3022 true, qp); 3023 3024 if (create_flags) { 3025 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 3026 create_flags); 3027 return -EOPNOTSUPP; 3028 } 3029 return 0; 3030 } 3031 3032 static int process_udata_size(struct mlx5_ib_dev *dev, 3033 struct mlx5_create_qp_params *params) 3034 { 3035 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 3036 struct ib_udata *udata = params->udata; 3037 size_t outlen = udata->outlen; 3038 size_t inlen = udata->inlen; 3039 3040 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 3041 params->ucmd_size = ucmd; 3042 if (!params->is_rss_raw) { 3043 /* User has old rdma-core, which doesn't support ECE */ 3044 size_t min_inlen = 3045 offsetof(struct mlx5_ib_create_qp, ece_options); 3046 3047 /* 3048 * We will check in check_ucmd_data() that user 3049 * cleared everything after inlen. 3050 */ 3051 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 3052 goto out; 3053 } 3054 3055 /* RSS RAW QP */ 3056 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 3057 return -EINVAL; 3058 3059 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 3060 return -EINVAL; 3061 3062 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 3063 params->ucmd_size = ucmd; 3064 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 3065 return -EINVAL; 3066 3067 params->inlen = min(ucmd, inlen); 3068 out: 3069 if (!params->inlen) 3070 mlx5_ib_dbg(dev, "udata is too small\n"); 3071 3072 return (params->inlen) ? 0 : -EINVAL; 3073 } 3074 3075 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 3076 struct mlx5_ib_qp *qp, 3077 struct mlx5_create_qp_params *params) 3078 { 3079 int err; 3080 3081 if (params->is_rss_raw) { 3082 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3083 goto out; 3084 } 3085 3086 switch (qp->type) { 3087 case MLX5_IB_QPT_DCT: 3088 err = create_dct(dev, pd, qp, params); 3089 rdma_restrack_no_track(&qp->ibqp.res); 3090 break; 3091 case MLX5_IB_QPT_DCI: 3092 err = create_dci(dev, pd, qp, params); 3093 break; 3094 case IB_QPT_XRC_TGT: 3095 err = create_xrc_tgt_qp(dev, qp, params); 3096 break; 3097 case IB_QPT_GSI: 3098 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3099 break; 3100 case MLX5_IB_QPT_HW_GSI: 3101 case MLX5_IB_QPT_REG_UMR: 3102 rdma_restrack_no_track(&qp->ibqp.res); 3103 fallthrough; 3104 default: 3105 if (params->udata) 3106 err = create_user_qp(dev, pd, qp, params); 3107 else 3108 err = create_kernel_qp(dev, pd, qp, params); 3109 } 3110 3111 out: 3112 if (err) { 3113 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3114 return err; 3115 } 3116 3117 if (is_qp0(qp->type)) 3118 qp->ibqp.qp_num = 0; 3119 else if (is_qp1(qp->type)) 3120 qp->ibqp.qp_num = 1; 3121 else 3122 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3123 3124 mlx5_ib_dbg(dev, 3125 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3126 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3127 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3128 -1, 3129 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3130 -1, 3131 params->resp.ece_options); 3132 3133 return 0; 3134 } 3135 3136 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3137 struct ib_qp_init_attr *attr) 3138 { 3139 int ret = 0; 3140 3141 switch (qp->type) { 3142 case MLX5_IB_QPT_DCT: 3143 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3144 break; 3145 case MLX5_IB_QPT_DCI: 3146 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3147 -EINVAL : 3148 0; 3149 break; 3150 case IB_QPT_RAW_PACKET: 3151 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3152 break; 3153 default: 3154 break; 3155 } 3156 3157 if (ret) 3158 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3159 3160 return ret; 3161 } 3162 3163 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3164 struct mlx5_create_qp_params *params) 3165 { 3166 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3167 struct ib_udata *udata = params->udata; 3168 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3169 udata, struct mlx5_ib_ucontext, ibucontext); 3170 3171 if (params->is_rss_raw) 3172 return 0; 3173 3174 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3175 } 3176 3177 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3178 { 3179 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3180 3181 if (mqp->state == IB_QPS_RTR) { 3182 int err; 3183 3184 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3185 if (err) { 3186 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3187 return err; 3188 } 3189 } 3190 3191 kfree(mqp->dct.in); 3192 return 0; 3193 } 3194 3195 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3196 struct mlx5_create_qp_params *params) 3197 { 3198 struct ib_udata *udata = params->udata; 3199 size_t size, last; 3200 int ret; 3201 3202 if (params->is_rss_raw) 3203 /* 3204 * These QPs don't have "reserved" field in their 3205 * create_qp input struct, so their data is always valid. 3206 */ 3207 last = sizeof(struct mlx5_ib_create_qp_rss); 3208 else 3209 last = offsetof(struct mlx5_ib_create_qp, reserved); 3210 3211 if (udata->inlen <= last) 3212 return 0; 3213 3214 /* 3215 * User provides different create_qp structures based on the 3216 * flow and we need to know if he cleared memory after our 3217 * struct create_qp ends. 3218 */ 3219 size = udata->inlen - last; 3220 ret = ib_is_udata_cleared(params->udata, last, size); 3221 if (!ret) 3222 mlx5_ib_dbg( 3223 dev, 3224 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3225 udata->inlen, params->ucmd_size, last, size); 3226 return ret ? 0 : -EINVAL; 3227 } 3228 3229 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3230 struct ib_udata *udata) 3231 { 3232 struct mlx5_create_qp_params params = {}; 3233 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3234 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3235 struct ib_pd *pd = ibqp->pd; 3236 enum ib_qp_type type; 3237 int err; 3238 3239 err = check_qp_type(dev, attr, &type); 3240 if (err) 3241 return err; 3242 3243 err = check_valid_flow(dev, pd, attr, udata); 3244 if (err) 3245 return err; 3246 3247 params.udata = udata; 3248 params.uidx = MLX5_IB_DEFAULT_UIDX; 3249 params.attr = attr; 3250 params.is_rss_raw = !!attr->rwq_ind_tbl; 3251 3252 if (udata) { 3253 err = process_udata_size(dev, ¶ms); 3254 if (err) 3255 return err; 3256 3257 err = check_ucmd_data(dev, ¶ms); 3258 if (err) 3259 return err; 3260 3261 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3262 if (!params.ucmd) 3263 return -ENOMEM; 3264 3265 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3266 if (err) 3267 goto free_ucmd; 3268 } 3269 3270 mutex_init(&qp->mutex); 3271 qp->type = type; 3272 if (udata) { 3273 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3274 if (err) 3275 goto free_ucmd; 3276 3277 err = get_qp_uidx(qp, ¶ms); 3278 if (err) 3279 goto free_ucmd; 3280 } 3281 err = process_create_flags(dev, qp, attr); 3282 if (err) 3283 goto free_ucmd; 3284 3285 err = check_qp_attr(dev, qp, attr); 3286 if (err) 3287 goto free_ucmd; 3288 3289 err = create_qp(dev, pd, qp, ¶ms); 3290 if (err) 3291 goto free_ucmd; 3292 3293 kfree(params.ucmd); 3294 params.ucmd = NULL; 3295 3296 if (udata) 3297 /* 3298 * It is safe to copy response for all user create QP flows, 3299 * including MLX5_IB_QPT_DCT, which doesn't need it. 3300 * In that case, resp will be filled with zeros. 3301 */ 3302 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3303 if (err) 3304 goto destroy_qp; 3305 3306 return 0; 3307 3308 destroy_qp: 3309 switch (qp->type) { 3310 case MLX5_IB_QPT_DCT: 3311 mlx5_ib_destroy_dct(qp); 3312 break; 3313 case IB_QPT_GSI: 3314 mlx5_ib_destroy_gsi(qp); 3315 break; 3316 default: 3317 destroy_qp_common(dev, qp, udata); 3318 } 3319 3320 free_ucmd: 3321 kfree(params.ucmd); 3322 return err; 3323 } 3324 3325 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3326 { 3327 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3328 struct mlx5_ib_qp *mqp = to_mqp(qp); 3329 3330 if (mqp->type == IB_QPT_GSI) 3331 return mlx5_ib_destroy_gsi(mqp); 3332 3333 if (mqp->type == MLX5_IB_QPT_DCT) 3334 return mlx5_ib_destroy_dct(mqp); 3335 3336 destroy_qp_common(dev, mqp, udata); 3337 return 0; 3338 } 3339 3340 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3341 const struct ib_qp_attr *attr, int attr_mask, 3342 void *qpc) 3343 { 3344 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3345 u8 dest_rd_atomic; 3346 u32 access_flags; 3347 3348 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3349 dest_rd_atomic = attr->max_dest_rd_atomic; 3350 else 3351 dest_rd_atomic = qp->trans_qp.resp_depth; 3352 3353 if (attr_mask & IB_QP_ACCESS_FLAGS) 3354 access_flags = attr->qp_access_flags; 3355 else 3356 access_flags = qp->trans_qp.atomic_rd_en; 3357 3358 if (!dest_rd_atomic) 3359 access_flags &= IB_ACCESS_REMOTE_WRITE; 3360 3361 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3362 3363 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3364 int atomic_mode; 3365 3366 atomic_mode = get_atomic_mode(dev, qp->type); 3367 if (atomic_mode < 0) 3368 return -EOPNOTSUPP; 3369 3370 MLX5_SET(qpc, qpc, rae, 1); 3371 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3372 } 3373 3374 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3375 return 0; 3376 } 3377 3378 enum { 3379 MLX5_PATH_FLAG_FL = 1 << 0, 3380 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3381 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3382 }; 3383 3384 static int mlx5_to_ib_rate_map(u8 rate) 3385 { 3386 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3387 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3388 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3389 IB_RATE_400_GBPS }; 3390 3391 if (rate < ARRAY_SIZE(rates)) 3392 return rates[rate]; 3393 3394 return rate - MLX5_STAT_RATE_OFFSET; 3395 } 3396 3397 static int ib_to_mlx5_rate_map(u8 rate) 3398 { 3399 switch (rate) { 3400 case IB_RATE_PORT_CURRENT: 3401 return 0; 3402 case IB_RATE_56_GBPS: 3403 return 1; 3404 case IB_RATE_25_GBPS: 3405 return 2; 3406 case IB_RATE_100_GBPS: 3407 return 3; 3408 case IB_RATE_200_GBPS: 3409 return 4; 3410 case IB_RATE_50_GBPS: 3411 return 5; 3412 case IB_RATE_400_GBPS: 3413 return 6; 3414 default: 3415 return rate + MLX5_STAT_RATE_OFFSET; 3416 } 3417 3418 return 0; 3419 } 3420 3421 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3422 { 3423 u32 stat_rate_support; 3424 3425 if (rate == IB_RATE_PORT_CURRENT) 3426 return 0; 3427 3428 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3429 return -EINVAL; 3430 3431 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3432 while (rate != IB_RATE_PORT_CURRENT && 3433 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3434 --rate; 3435 3436 return ib_to_mlx5_rate_map(rate); 3437 } 3438 3439 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3440 struct mlx5_ib_sq *sq, u8 sl, 3441 struct ib_pd *pd) 3442 { 3443 void *in; 3444 void *tisc; 3445 int inlen; 3446 int err; 3447 3448 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3449 in = kvzalloc(inlen, GFP_KERNEL); 3450 if (!in) 3451 return -ENOMEM; 3452 3453 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3454 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3455 3456 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3457 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3458 3459 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3460 3461 kvfree(in); 3462 3463 return err; 3464 } 3465 3466 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3467 struct mlx5_ib_sq *sq, u8 tx_affinity, 3468 struct ib_pd *pd) 3469 { 3470 void *in; 3471 void *tisc; 3472 int inlen; 3473 int err; 3474 3475 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3476 in = kvzalloc(inlen, GFP_KERNEL); 3477 if (!in) 3478 return -ENOMEM; 3479 3480 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3481 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3482 3483 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3484 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3485 3486 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3487 3488 kvfree(in); 3489 3490 return err; 3491 } 3492 3493 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3494 u32 lqpn, u32 rqpn) 3495 3496 { 3497 u32 fl = ah->grh.flow_label; 3498 3499 if (!fl) 3500 fl = rdma_calc_flow_label(lqpn, rqpn); 3501 3502 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3503 } 3504 3505 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3506 const struct rdma_ah_attr *ah, void *path, u8 port, 3507 int attr_mask, u32 path_flags, 3508 const struct ib_qp_attr *attr, bool alt) 3509 { 3510 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3511 int err; 3512 enum ib_gid_type gid_type; 3513 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3514 u8 sl = rdma_ah_get_sl(ah); 3515 3516 if (attr_mask & IB_QP_PKEY_INDEX) 3517 MLX5_SET(ads, path, pkey_index, 3518 alt ? attr->alt_pkey_index : attr->pkey_index); 3519 3520 if (ah_flags & IB_AH_GRH) { 3521 const struct ib_port_immutable *immutable; 3522 3523 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3524 if (grh->sgid_index >= immutable->gid_tbl_len) { 3525 pr_err("sgid_index (%u) too large. max is %d\n", 3526 grh->sgid_index, 3527 immutable->gid_tbl_len); 3528 return -EINVAL; 3529 } 3530 } 3531 3532 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3533 if (!(ah_flags & IB_AH_GRH)) 3534 return -EINVAL; 3535 3536 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3537 ah->roce.dmac); 3538 if ((qp->type == IB_QPT_RC || 3539 qp->type == IB_QPT_UC || 3540 qp->type == IB_QPT_XRC_INI || 3541 qp->type == IB_QPT_XRC_TGT) && 3542 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3543 (attr_mask & IB_QP_DEST_QPN)) 3544 mlx5_set_path_udp_sport(path, ah, 3545 qp->ibqp.qp_num, 3546 attr->dest_qp_num); 3547 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3548 gid_type = ah->grh.sgid_attr->gid_type; 3549 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3550 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3551 } else { 3552 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3553 MLX5_SET(ads, path, free_ar, 3554 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3555 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3556 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3557 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3558 MLX5_SET(ads, path, sl, sl); 3559 } 3560 3561 if (ah_flags & IB_AH_GRH) { 3562 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3563 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3564 MLX5_SET(ads, path, tclass, grh->traffic_class); 3565 MLX5_SET(ads, path, flow_label, grh->flow_label); 3566 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3567 sizeof(grh->dgid.raw)); 3568 } 3569 3570 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3571 if (err < 0) 3572 return err; 3573 MLX5_SET(ads, path, stat_rate, err); 3574 MLX5_SET(ads, path, vhca_port_num, port); 3575 3576 if (attr_mask & IB_QP_TIMEOUT) 3577 MLX5_SET(ads, path, ack_timeout, 3578 alt ? attr->alt_timeout : attr->timeout); 3579 3580 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3581 return modify_raw_packet_eth_prio(dev->mdev, 3582 &qp->raw_packet_qp.sq, 3583 sl & 0xf, qp->ibqp.pd); 3584 3585 return 0; 3586 } 3587 3588 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3589 [MLX5_QP_STATE_INIT] = { 3590 [MLX5_QP_STATE_INIT] = { 3591 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3592 MLX5_QP_OPTPAR_RAE | 3593 MLX5_QP_OPTPAR_RWE | 3594 MLX5_QP_OPTPAR_PKEY_INDEX | 3595 MLX5_QP_OPTPAR_PRI_PORT | 3596 MLX5_QP_OPTPAR_LAG_TX_AFF, 3597 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3598 MLX5_QP_OPTPAR_PKEY_INDEX | 3599 MLX5_QP_OPTPAR_PRI_PORT | 3600 MLX5_QP_OPTPAR_LAG_TX_AFF, 3601 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3602 MLX5_QP_OPTPAR_Q_KEY | 3603 MLX5_QP_OPTPAR_PRI_PORT, 3604 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3605 MLX5_QP_OPTPAR_RAE | 3606 MLX5_QP_OPTPAR_RWE | 3607 MLX5_QP_OPTPAR_PKEY_INDEX | 3608 MLX5_QP_OPTPAR_PRI_PORT | 3609 MLX5_QP_OPTPAR_LAG_TX_AFF, 3610 }, 3611 [MLX5_QP_STATE_RTR] = { 3612 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3613 MLX5_QP_OPTPAR_RRE | 3614 MLX5_QP_OPTPAR_RAE | 3615 MLX5_QP_OPTPAR_RWE | 3616 MLX5_QP_OPTPAR_PKEY_INDEX | 3617 MLX5_QP_OPTPAR_LAG_TX_AFF, 3618 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3619 MLX5_QP_OPTPAR_RWE | 3620 MLX5_QP_OPTPAR_PKEY_INDEX | 3621 MLX5_QP_OPTPAR_LAG_TX_AFF, 3622 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3623 MLX5_QP_OPTPAR_Q_KEY, 3624 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3625 MLX5_QP_OPTPAR_Q_KEY, 3626 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3627 MLX5_QP_OPTPAR_RRE | 3628 MLX5_QP_OPTPAR_RAE | 3629 MLX5_QP_OPTPAR_RWE | 3630 MLX5_QP_OPTPAR_PKEY_INDEX | 3631 MLX5_QP_OPTPAR_LAG_TX_AFF, 3632 }, 3633 }, 3634 [MLX5_QP_STATE_RTR] = { 3635 [MLX5_QP_STATE_RTS] = { 3636 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3637 MLX5_QP_OPTPAR_RRE | 3638 MLX5_QP_OPTPAR_RAE | 3639 MLX5_QP_OPTPAR_RWE | 3640 MLX5_QP_OPTPAR_PM_STATE | 3641 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3642 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3643 MLX5_QP_OPTPAR_RWE | 3644 MLX5_QP_OPTPAR_PM_STATE, 3645 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3646 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3647 MLX5_QP_OPTPAR_RRE | 3648 MLX5_QP_OPTPAR_RAE | 3649 MLX5_QP_OPTPAR_RWE | 3650 MLX5_QP_OPTPAR_PM_STATE | 3651 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3652 }, 3653 }, 3654 [MLX5_QP_STATE_RTS] = { 3655 [MLX5_QP_STATE_RTS] = { 3656 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3657 MLX5_QP_OPTPAR_RAE | 3658 MLX5_QP_OPTPAR_RWE | 3659 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3660 MLX5_QP_OPTPAR_PM_STATE | 3661 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3662 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3663 MLX5_QP_OPTPAR_PM_STATE | 3664 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3665 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3666 MLX5_QP_OPTPAR_SRQN | 3667 MLX5_QP_OPTPAR_CQN_RCV, 3668 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3669 MLX5_QP_OPTPAR_RAE | 3670 MLX5_QP_OPTPAR_RWE | 3671 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3672 MLX5_QP_OPTPAR_PM_STATE | 3673 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3674 }, 3675 }, 3676 [MLX5_QP_STATE_SQER] = { 3677 [MLX5_QP_STATE_RTS] = { 3678 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3679 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3680 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3681 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3682 MLX5_QP_OPTPAR_RWE | 3683 MLX5_QP_OPTPAR_RAE | 3684 MLX5_QP_OPTPAR_RRE, 3685 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3686 MLX5_QP_OPTPAR_RWE | 3687 MLX5_QP_OPTPAR_RAE | 3688 MLX5_QP_OPTPAR_RRE, 3689 }, 3690 }, 3691 [MLX5_QP_STATE_SQD] = { 3692 [MLX5_QP_STATE_RTS] = { 3693 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3694 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3695 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3696 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3697 MLX5_QP_OPTPAR_RWE | 3698 MLX5_QP_OPTPAR_RAE | 3699 MLX5_QP_OPTPAR_RRE, 3700 }, 3701 }, 3702 }; 3703 3704 static int ib_nr_to_mlx5_nr(int ib_mask) 3705 { 3706 switch (ib_mask) { 3707 case IB_QP_STATE: 3708 return 0; 3709 case IB_QP_CUR_STATE: 3710 return 0; 3711 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3712 return 0; 3713 case IB_QP_ACCESS_FLAGS: 3714 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3715 MLX5_QP_OPTPAR_RAE; 3716 case IB_QP_PKEY_INDEX: 3717 return MLX5_QP_OPTPAR_PKEY_INDEX; 3718 case IB_QP_PORT: 3719 return MLX5_QP_OPTPAR_PRI_PORT; 3720 case IB_QP_QKEY: 3721 return MLX5_QP_OPTPAR_Q_KEY; 3722 case IB_QP_AV: 3723 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3724 MLX5_QP_OPTPAR_PRI_PORT; 3725 case IB_QP_PATH_MTU: 3726 return 0; 3727 case IB_QP_TIMEOUT: 3728 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3729 case IB_QP_RETRY_CNT: 3730 return MLX5_QP_OPTPAR_RETRY_COUNT; 3731 case IB_QP_RNR_RETRY: 3732 return MLX5_QP_OPTPAR_RNR_RETRY; 3733 case IB_QP_RQ_PSN: 3734 return 0; 3735 case IB_QP_MAX_QP_RD_ATOMIC: 3736 return MLX5_QP_OPTPAR_SRA_MAX; 3737 case IB_QP_ALT_PATH: 3738 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3739 case IB_QP_MIN_RNR_TIMER: 3740 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3741 case IB_QP_SQ_PSN: 3742 return 0; 3743 case IB_QP_MAX_DEST_RD_ATOMIC: 3744 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3745 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3746 case IB_QP_PATH_MIG_STATE: 3747 return MLX5_QP_OPTPAR_PM_STATE; 3748 case IB_QP_CAP: 3749 return 0; 3750 case IB_QP_DEST_QPN: 3751 return 0; 3752 } 3753 return 0; 3754 } 3755 3756 static int ib_mask_to_mlx5_opt(int ib_mask) 3757 { 3758 int result = 0; 3759 int i; 3760 3761 for (i = 0; i < 8 * sizeof(int); i++) { 3762 if ((1 << i) & ib_mask) 3763 result |= ib_nr_to_mlx5_nr(1 << i); 3764 } 3765 3766 return result; 3767 } 3768 3769 static int modify_raw_packet_qp_rq( 3770 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3771 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3772 { 3773 void *in; 3774 void *rqc; 3775 int inlen; 3776 int err; 3777 3778 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3779 in = kvzalloc(inlen, GFP_KERNEL); 3780 if (!in) 3781 return -ENOMEM; 3782 3783 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3784 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3785 3786 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3787 MLX5_SET(rqc, rqc, state, new_state); 3788 3789 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3790 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3791 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3792 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3793 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3794 } else 3795 dev_info_once( 3796 &dev->ib_dev.dev, 3797 "RAW PACKET QP counters are not supported on current FW\n"); 3798 } 3799 3800 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3801 if (err) 3802 goto out; 3803 3804 rq->state = new_state; 3805 3806 out: 3807 kvfree(in); 3808 return err; 3809 } 3810 3811 static int modify_raw_packet_qp_sq( 3812 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3813 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3814 { 3815 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3816 struct mlx5_rate_limit old_rl = ibqp->rl; 3817 struct mlx5_rate_limit new_rl = old_rl; 3818 bool new_rate_added = false; 3819 u16 rl_index = 0; 3820 void *in; 3821 void *sqc; 3822 int inlen; 3823 int err; 3824 3825 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3826 in = kvzalloc(inlen, GFP_KERNEL); 3827 if (!in) 3828 return -ENOMEM; 3829 3830 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3831 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3832 3833 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3834 MLX5_SET(sqc, sqc, state, new_state); 3835 3836 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3837 if (new_state != MLX5_SQC_STATE_RDY) 3838 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3839 __func__); 3840 else 3841 new_rl = raw_qp_param->rl; 3842 } 3843 3844 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3845 if (new_rl.rate) { 3846 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3847 if (err) { 3848 pr_err("Failed configuring rate limit(err %d): \ 3849 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3850 err, new_rl.rate, new_rl.max_burst_sz, 3851 new_rl.typical_pkt_sz); 3852 3853 goto out; 3854 } 3855 new_rate_added = true; 3856 } 3857 3858 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3859 /* index 0 means no limit */ 3860 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3861 } 3862 3863 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3864 if (err) { 3865 /* Remove new rate from table if failed */ 3866 if (new_rate_added) 3867 mlx5_rl_remove_rate(dev, &new_rl); 3868 goto out; 3869 } 3870 3871 /* Only remove the old rate after new rate was set */ 3872 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3873 (new_state != MLX5_SQC_STATE_RDY)) { 3874 mlx5_rl_remove_rate(dev, &old_rl); 3875 if (new_state != MLX5_SQC_STATE_RDY) 3876 memset(&new_rl, 0, sizeof(new_rl)); 3877 } 3878 3879 ibqp->rl = new_rl; 3880 sq->state = new_state; 3881 3882 out: 3883 kvfree(in); 3884 return err; 3885 } 3886 3887 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3888 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3889 u8 tx_affinity) 3890 { 3891 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3892 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3893 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3894 int modify_rq = !!qp->rq.wqe_cnt; 3895 int modify_sq = !!qp->sq.wqe_cnt; 3896 int rq_state; 3897 int sq_state; 3898 int err; 3899 3900 switch (raw_qp_param->operation) { 3901 case MLX5_CMD_OP_RST2INIT_QP: 3902 rq_state = MLX5_RQC_STATE_RDY; 3903 sq_state = MLX5_SQC_STATE_RST; 3904 break; 3905 case MLX5_CMD_OP_2ERR_QP: 3906 rq_state = MLX5_RQC_STATE_ERR; 3907 sq_state = MLX5_SQC_STATE_ERR; 3908 break; 3909 case MLX5_CMD_OP_2RST_QP: 3910 rq_state = MLX5_RQC_STATE_RST; 3911 sq_state = MLX5_SQC_STATE_RST; 3912 break; 3913 case MLX5_CMD_OP_RTR2RTS_QP: 3914 case MLX5_CMD_OP_RTS2RTS_QP: 3915 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3916 return -EINVAL; 3917 3918 modify_rq = 0; 3919 sq_state = MLX5_SQC_STATE_RDY; 3920 break; 3921 case MLX5_CMD_OP_INIT2INIT_QP: 3922 case MLX5_CMD_OP_INIT2RTR_QP: 3923 if (raw_qp_param->set_mask) 3924 return -EINVAL; 3925 else 3926 return 0; 3927 default: 3928 WARN_ON(1); 3929 return -EINVAL; 3930 } 3931 3932 if (modify_rq) { 3933 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3934 qp->ibqp.pd); 3935 if (err) 3936 return err; 3937 } 3938 3939 if (modify_sq) { 3940 struct mlx5_flow_handle *flow_rule; 3941 3942 if (tx_affinity) { 3943 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3944 tx_affinity, 3945 qp->ibqp.pd); 3946 if (err) 3947 return err; 3948 } 3949 3950 flow_rule = create_flow_rule_vport_sq(dev, sq, 3951 raw_qp_param->port); 3952 if (IS_ERR(flow_rule)) 3953 return PTR_ERR(flow_rule); 3954 3955 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3956 raw_qp_param, qp->ibqp.pd); 3957 if (err) { 3958 if (flow_rule) 3959 mlx5_del_flow_rules(flow_rule); 3960 return err; 3961 } 3962 3963 if (flow_rule) { 3964 destroy_flow_rule_vport_sq(sq); 3965 sq->flow_rule = flow_rule; 3966 } 3967 3968 return err; 3969 } 3970 3971 return 0; 3972 } 3973 3974 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3975 struct ib_udata *udata) 3976 { 3977 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3978 udata, struct mlx5_ib_ucontext, ibucontext); 3979 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3980 atomic_t *tx_port_affinity; 3981 3982 if (ucontext) 3983 tx_port_affinity = &ucontext->tx_port_affinity; 3984 else 3985 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3986 3987 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3988 (dev->lag_active ? dev->lag_ports : MLX5_CAP_GEN(dev->mdev, num_lag_ports)) + 1; 3989 } 3990 3991 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3992 { 3993 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3994 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3995 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3996 (qp->type == MLX5_IB_QPT_DCI)) 3997 return true; 3998 return false; 3999 } 4000 4001 static unsigned int get_tx_affinity(struct ib_qp *qp, 4002 const struct ib_qp_attr *attr, 4003 int attr_mask, u8 init, 4004 struct ib_udata *udata) 4005 { 4006 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4007 udata, struct mlx5_ib_ucontext, ibucontext); 4008 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4009 struct mlx5_ib_qp *mqp = to_mqp(qp); 4010 struct mlx5_ib_qp_base *qp_base; 4011 unsigned int tx_affinity; 4012 4013 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 4014 qp_supports_affinity(mqp))) 4015 return 0; 4016 4017 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4018 tx_affinity = mqp->gsi_lag_port; 4019 else if (init) 4020 tx_affinity = get_tx_affinity_rr(dev, udata); 4021 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 4022 tx_affinity = 4023 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 4024 else 4025 return 0; 4026 4027 qp_base = &mqp->trans_qp.base; 4028 if (ucontext) 4029 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 4030 tx_affinity, qp_base->mqp.qpn, ucontext); 4031 else 4032 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 4033 tx_affinity, qp_base->mqp.qpn); 4034 return tx_affinity; 4035 } 4036 4037 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4038 struct rdma_counter *counter) 4039 { 4040 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4041 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 4042 struct mlx5_ib_qp *mqp = to_mqp(qp); 4043 struct mlx5_ib_qp_base *base; 4044 u32 set_id; 4045 u32 *qpc; 4046 4047 if (counter) 4048 set_id = counter->id; 4049 else 4050 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4051 4052 base = &mqp->trans_qp.base; 4053 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 4054 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 4055 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 4056 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 4057 MLX5_QP_OPTPAR_COUNTER_SET_ID); 4058 4059 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 4060 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4061 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 4062 } 4063 4064 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 4065 const struct ib_qp_attr *attr, int attr_mask, 4066 enum ib_qp_state cur_state, 4067 enum ib_qp_state new_state, 4068 const struct mlx5_ib_modify_qp *ucmd, 4069 struct mlx5_ib_modify_qp_resp *resp, 4070 struct ib_udata *udata) 4071 { 4072 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 4073 [MLX5_QP_STATE_RST] = { 4074 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4075 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4076 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 4077 }, 4078 [MLX5_QP_STATE_INIT] = { 4079 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4080 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4081 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4082 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4083 }, 4084 [MLX5_QP_STATE_RTR] = { 4085 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4086 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4087 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4088 }, 4089 [MLX5_QP_STATE_RTS] = { 4090 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4091 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4092 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4093 }, 4094 [MLX5_QP_STATE_SQD] = { 4095 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4096 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4097 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4098 }, 4099 [MLX5_QP_STATE_SQER] = { 4100 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4101 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4102 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4103 }, 4104 [MLX5_QP_STATE_ERR] = { 4105 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4106 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4107 } 4108 }; 4109 4110 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4111 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4112 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4113 struct mlx5_ib_cq *send_cq, *recv_cq; 4114 struct mlx5_ib_pd *pd; 4115 enum mlx5_qp_state mlx5_cur, mlx5_new; 4116 void *qpc, *pri_path, *alt_path; 4117 enum mlx5_qp_optpar optpar = 0; 4118 u32 set_id = 0; 4119 int mlx5_st; 4120 int err; 4121 u16 op; 4122 u8 tx_affinity = 0; 4123 4124 mlx5_st = to_mlx5_st(qp->type); 4125 if (mlx5_st < 0) 4126 return -EINVAL; 4127 4128 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4129 if (!qpc) 4130 return -ENOMEM; 4131 4132 pd = to_mpd(qp->ibqp.pd); 4133 MLX5_SET(qpc, qpc, st, mlx5_st); 4134 4135 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4136 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4137 } else { 4138 switch (attr->path_mig_state) { 4139 case IB_MIG_MIGRATED: 4140 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4141 break; 4142 case IB_MIG_REARM: 4143 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4144 break; 4145 case IB_MIG_ARMED: 4146 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4147 break; 4148 } 4149 } 4150 4151 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4152 cur_state == IB_QPS_RESET && 4153 new_state == IB_QPS_INIT, udata); 4154 4155 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4156 if (tx_affinity && new_state == IB_QPS_RTR && 4157 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4158 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4159 4160 if (is_sqp(qp->type)) { 4161 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4162 MLX5_SET(qpc, qpc, log_msg_max, 8); 4163 } else if ((qp->type == IB_QPT_UD && 4164 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4165 qp->type == MLX5_IB_QPT_REG_UMR) { 4166 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4167 MLX5_SET(qpc, qpc, log_msg_max, 12); 4168 } else if (attr_mask & IB_QP_PATH_MTU) { 4169 if (attr->path_mtu < IB_MTU_256 || 4170 attr->path_mtu > IB_MTU_4096) { 4171 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4172 err = -EINVAL; 4173 goto out; 4174 } 4175 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4176 MLX5_SET(qpc, qpc, log_msg_max, 4177 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4178 } 4179 4180 if (attr_mask & IB_QP_DEST_QPN) 4181 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4182 4183 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4184 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4185 4186 if (attr_mask & IB_QP_PKEY_INDEX) 4187 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4188 4189 /* todo implement counter_index functionality */ 4190 4191 if (is_sqp(qp->type)) 4192 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4193 4194 if (attr_mask & IB_QP_PORT) 4195 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4196 4197 if (attr_mask & IB_QP_AV) { 4198 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4199 attr_mask & IB_QP_PORT ? attr->port_num : 4200 qp->port, 4201 attr_mask, 0, attr, false); 4202 if (err) 4203 goto out; 4204 } 4205 4206 if (attr_mask & IB_QP_TIMEOUT) 4207 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4208 4209 if (attr_mask & IB_QP_ALT_PATH) { 4210 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4211 attr->alt_port_num, 4212 attr_mask | IB_QP_PKEY_INDEX | 4213 IB_QP_TIMEOUT, 4214 0, attr, true); 4215 if (err) 4216 goto out; 4217 } 4218 4219 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4220 &send_cq, &recv_cq); 4221 4222 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4223 if (send_cq) 4224 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4225 if (recv_cq) 4226 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4227 4228 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4229 4230 if (attr_mask & IB_QP_RNR_RETRY) 4231 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4232 4233 if (attr_mask & IB_QP_RETRY_CNT) 4234 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4235 4236 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4237 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 4238 4239 if (attr_mask & IB_QP_SQ_PSN) 4240 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4241 4242 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4243 MLX5_SET(qpc, qpc, log_rra_max, 4244 ilog2(attr->max_dest_rd_atomic)); 4245 4246 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4247 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4248 if (err) 4249 goto out; 4250 } 4251 4252 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4253 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4254 4255 if (attr_mask & IB_QP_RQ_PSN) 4256 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4257 4258 if (attr_mask & IB_QP_QKEY) 4259 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4260 4261 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4262 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4263 4264 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4265 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4266 qp->port) - 1; 4267 4268 /* Underlay port should be used - index 0 function per port */ 4269 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4270 port_num = 0; 4271 4272 if (ibqp->counter) 4273 set_id = ibqp->counter->id; 4274 else 4275 set_id = mlx5_ib_get_counters_id(dev, port_num); 4276 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4277 } 4278 4279 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4280 MLX5_SET(qpc, qpc, rlky, 1); 4281 4282 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4283 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4284 4285 mlx5_cur = to_mlx5_state(cur_state); 4286 mlx5_new = to_mlx5_state(new_state); 4287 4288 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4289 !optab[mlx5_cur][mlx5_new]) { 4290 err = -EINVAL; 4291 goto out; 4292 } 4293 4294 op = optab[mlx5_cur][mlx5_new]; 4295 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4296 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4297 4298 if (qp->type == IB_QPT_RAW_PACKET || 4299 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4300 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4301 4302 raw_qp_param.operation = op; 4303 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4304 raw_qp_param.rq_q_ctr_id = set_id; 4305 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4306 } 4307 4308 if (attr_mask & IB_QP_PORT) 4309 raw_qp_param.port = attr->port_num; 4310 4311 if (attr_mask & IB_QP_RATE_LIMIT) { 4312 raw_qp_param.rl.rate = attr->rate_limit; 4313 4314 if (ucmd->burst_info.max_burst_sz) { 4315 if (attr->rate_limit && 4316 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4317 raw_qp_param.rl.max_burst_sz = 4318 ucmd->burst_info.max_burst_sz; 4319 } else { 4320 err = -EINVAL; 4321 goto out; 4322 } 4323 } 4324 4325 if (ucmd->burst_info.typical_pkt_sz) { 4326 if (attr->rate_limit && 4327 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4328 raw_qp_param.rl.typical_pkt_sz = 4329 ucmd->burst_info.typical_pkt_sz; 4330 } else { 4331 err = -EINVAL; 4332 goto out; 4333 } 4334 } 4335 4336 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4337 } 4338 4339 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4340 } else { 4341 if (udata) { 4342 /* For the kernel flows, the resp will stay zero */ 4343 resp->ece_options = 4344 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4345 ucmd->ece_options : 0; 4346 resp->response_length = sizeof(*resp); 4347 } 4348 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4349 &resp->ece_options); 4350 } 4351 4352 if (err) 4353 goto out; 4354 4355 qp->state = new_state; 4356 4357 if (attr_mask & IB_QP_ACCESS_FLAGS) 4358 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4359 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4360 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4361 if (attr_mask & IB_QP_PORT) 4362 qp->port = attr->port_num; 4363 if (attr_mask & IB_QP_ALT_PATH) 4364 qp->trans_qp.alt_port = attr->alt_port_num; 4365 4366 /* 4367 * If we moved a kernel QP to RESET, clean up all old CQ 4368 * entries and reinitialize the QP. 4369 */ 4370 if (new_state == IB_QPS_RESET && 4371 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4372 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4373 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4374 if (send_cq != recv_cq) 4375 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4376 4377 qp->rq.head = 0; 4378 qp->rq.tail = 0; 4379 qp->sq.head = 0; 4380 qp->sq.tail = 0; 4381 qp->sq.cur_post = 0; 4382 if (qp->sq.wqe_cnt) 4383 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4384 qp->sq.last_poll = 0; 4385 qp->db.db[MLX5_RCV_DBR] = 0; 4386 qp->db.db[MLX5_SND_DBR] = 0; 4387 } 4388 4389 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4390 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4391 if (!err) 4392 qp->counter_pending = 0; 4393 } 4394 4395 out: 4396 kfree(qpc); 4397 return err; 4398 } 4399 4400 static inline bool is_valid_mask(int mask, int req, int opt) 4401 { 4402 if ((mask & req) != req) 4403 return false; 4404 4405 if (mask & ~(req | opt)) 4406 return false; 4407 4408 return true; 4409 } 4410 4411 /* check valid transition for driver QP types 4412 * for now the only QP type that this function supports is DCI 4413 */ 4414 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4415 enum ib_qp_attr_mask attr_mask) 4416 { 4417 int req = IB_QP_STATE; 4418 int opt = 0; 4419 4420 if (new_state == IB_QPS_RESET) { 4421 return is_valid_mask(attr_mask, req, opt); 4422 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4423 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4424 return is_valid_mask(attr_mask, req, opt); 4425 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4426 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4427 return is_valid_mask(attr_mask, req, opt); 4428 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4429 req |= IB_QP_PATH_MTU; 4430 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4431 return is_valid_mask(attr_mask, req, opt); 4432 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4433 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4434 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4435 opt = IB_QP_MIN_RNR_TIMER; 4436 return is_valid_mask(attr_mask, req, opt); 4437 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4438 opt = IB_QP_MIN_RNR_TIMER; 4439 return is_valid_mask(attr_mask, req, opt); 4440 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4441 return is_valid_mask(attr_mask, req, opt); 4442 } 4443 return false; 4444 } 4445 4446 /* mlx5_ib_modify_dct: modify a DCT QP 4447 * valid transitions are: 4448 * RESET to INIT: must set access_flags, pkey_index and port 4449 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4450 * mtu, gid_index and hop_limit 4451 * Other transitions and attributes are illegal 4452 */ 4453 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4454 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4455 struct ib_udata *udata) 4456 { 4457 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4458 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4459 enum ib_qp_state cur_state, new_state; 4460 int required = IB_QP_STATE; 4461 void *dctc; 4462 int err; 4463 4464 if (!(attr_mask & IB_QP_STATE)) 4465 return -EINVAL; 4466 4467 cur_state = qp->state; 4468 new_state = attr->qp_state; 4469 4470 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4471 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4472 /* 4473 * DCT doesn't initialize QP till modify command is executed, 4474 * so we need to overwrite previously set ECE field if user 4475 * provided any value except zero, which means not set/not 4476 * valid. 4477 */ 4478 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4479 4480 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4481 u16 set_id; 4482 4483 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4484 if (!is_valid_mask(attr_mask, required, 0)) 4485 return -EINVAL; 4486 4487 if (attr->port_num == 0 || 4488 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4489 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4490 attr->port_num, dev->num_ports); 4491 return -EINVAL; 4492 } 4493 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4494 MLX5_SET(dctc, dctc, rre, 1); 4495 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4496 MLX5_SET(dctc, dctc, rwe, 1); 4497 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4498 int atomic_mode; 4499 4500 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4501 if (atomic_mode < 0) 4502 return -EOPNOTSUPP; 4503 4504 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4505 MLX5_SET(dctc, dctc, rae, 1); 4506 } 4507 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4508 if (mlx5_lag_is_active(dev->mdev)) 4509 MLX5_SET(dctc, dctc, port, 4510 get_tx_affinity_rr(dev, udata)); 4511 else 4512 MLX5_SET(dctc, dctc, port, attr->port_num); 4513 4514 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4515 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4516 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4517 struct mlx5_ib_modify_qp_resp resp = {}; 4518 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4519 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4520 4521 if (udata->outlen < min_resp_len) 4522 return -EINVAL; 4523 /* 4524 * If we don't have enough space for the ECE options, 4525 * simply indicate it with resp.response_length. 4526 */ 4527 resp.response_length = (udata->outlen < sizeof(resp)) ? 4528 min_resp_len : 4529 sizeof(resp); 4530 4531 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4532 if (!is_valid_mask(attr_mask, required, 0)) 4533 return -EINVAL; 4534 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4535 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4536 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4537 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4538 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4539 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4540 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) 4541 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7); 4542 4543 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4544 MLX5_ST_SZ_BYTES(create_dct_in), out, 4545 sizeof(out)); 4546 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); 4547 if (err) 4548 return err; 4549 resp.dctn = qp->dct.mdct.mqp.qpn; 4550 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4551 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4552 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4553 if (err) { 4554 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4555 return err; 4556 } 4557 } else { 4558 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4559 return -EINVAL; 4560 } 4561 4562 qp->state = new_state; 4563 return 0; 4564 } 4565 4566 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4567 struct mlx5_ib_qp *qp) 4568 { 4569 if (dev->profile != &raw_eth_profile) 4570 return true; 4571 4572 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4573 return true; 4574 4575 /* Internal QP used for wc testing, with NOPs in wq */ 4576 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4577 return true; 4578 4579 return false; 4580 } 4581 4582 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr, 4583 int attr_mask, enum ib_qp_type qp_type) 4584 { 4585 int log_max_ra_res; 4586 int log_max_ra_req; 4587 4588 if (qp_type == MLX5_IB_QPT_DCI) { 4589 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4590 log_max_ra_res_dc); 4591 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4592 log_max_ra_req_dc); 4593 } else { 4594 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4595 log_max_ra_res_qp); 4596 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4597 log_max_ra_req_qp); 4598 } 4599 4600 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4601 attr->max_rd_atomic > log_max_ra_res) { 4602 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4603 attr->max_rd_atomic); 4604 return false; 4605 } 4606 4607 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4608 attr->max_dest_rd_atomic > log_max_ra_req) { 4609 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4610 attr->max_dest_rd_atomic); 4611 return false; 4612 } 4613 return true; 4614 } 4615 4616 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4617 int attr_mask, struct ib_udata *udata) 4618 { 4619 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4620 struct mlx5_ib_modify_qp_resp resp = {}; 4621 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4622 struct mlx5_ib_modify_qp ucmd = {}; 4623 enum ib_qp_type qp_type; 4624 enum ib_qp_state cur_state, new_state; 4625 int err = -EINVAL; 4626 4627 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4628 return -EOPNOTSUPP; 4629 4630 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4631 return -EOPNOTSUPP; 4632 4633 if (ibqp->rwq_ind_tbl) 4634 return -ENOSYS; 4635 4636 if (udata && udata->inlen) { 4637 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4638 return -EINVAL; 4639 4640 if (udata->inlen > sizeof(ucmd) && 4641 !ib_is_udata_cleared(udata, sizeof(ucmd), 4642 udata->inlen - sizeof(ucmd))) 4643 return -EOPNOTSUPP; 4644 4645 if (ib_copy_from_udata(&ucmd, udata, 4646 min(udata->inlen, sizeof(ucmd)))) 4647 return -EFAULT; 4648 4649 if (ucmd.comp_mask || 4650 memchr_inv(&ucmd.burst_info.reserved, 0, 4651 sizeof(ucmd.burst_info.reserved))) 4652 return -EOPNOTSUPP; 4653 4654 } 4655 4656 if (qp->type == IB_QPT_GSI) 4657 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4658 4659 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4660 4661 if (qp_type == MLX5_IB_QPT_DCT) 4662 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4663 4664 mutex_lock(&qp->mutex); 4665 4666 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4667 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4668 4669 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4670 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4671 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4672 attr_mask); 4673 goto out; 4674 } 4675 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4676 qp_type != MLX5_IB_QPT_DCI && 4677 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4678 attr_mask)) { 4679 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4680 cur_state, new_state, qp->type, attr_mask); 4681 goto out; 4682 } else if (qp_type == MLX5_IB_QPT_DCI && 4683 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4684 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4685 cur_state, new_state, qp_type, attr_mask); 4686 goto out; 4687 } 4688 4689 if ((attr_mask & IB_QP_PORT) && 4690 (attr->port_num == 0 || 4691 attr->port_num > dev->num_ports)) { 4692 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4693 attr->port_num, dev->num_ports); 4694 goto out; 4695 } 4696 4697 if ((attr_mask & IB_QP_PKEY_INDEX) && 4698 attr->pkey_index >= dev->pkey_table_len) { 4699 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4700 goto out; 4701 } 4702 4703 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type)) 4704 goto out; 4705 4706 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4707 err = 0; 4708 goto out; 4709 } 4710 4711 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4712 new_state, &ucmd, &resp, udata); 4713 4714 /* resp.response_length is set in ECE supported flows only */ 4715 if (!err && resp.response_length && 4716 udata->outlen >= resp.response_length) 4717 /* Return -EFAULT to the user and expect him to destroy QP. */ 4718 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4719 4720 out: 4721 mutex_unlock(&qp->mutex); 4722 return err; 4723 } 4724 4725 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4726 { 4727 switch (mlx5_state) { 4728 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4729 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4730 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4731 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4732 case MLX5_QP_STATE_SQ_DRAINING: 4733 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4734 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4735 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4736 default: return -1; 4737 } 4738 } 4739 4740 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4741 { 4742 switch (mlx5_mig_state) { 4743 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4744 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4745 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4746 default: return -1; 4747 } 4748 } 4749 4750 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4751 struct rdma_ah_attr *ah_attr, void *path) 4752 { 4753 int port = MLX5_GET(ads, path, vhca_port_num); 4754 int static_rate; 4755 4756 memset(ah_attr, 0, sizeof(*ah_attr)); 4757 4758 if (!port || port > ibdev->num_ports) 4759 return; 4760 4761 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4762 4763 rdma_ah_set_port_num(ah_attr, port); 4764 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4765 4766 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4767 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4768 4769 static_rate = MLX5_GET(ads, path, stat_rate); 4770 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4771 if (MLX5_GET(ads, path, grh) || 4772 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4773 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4774 MLX5_GET(ads, path, src_addr_index), 4775 MLX5_GET(ads, path, hop_limit), 4776 MLX5_GET(ads, path, tclass)); 4777 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4778 } 4779 } 4780 4781 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4782 struct mlx5_ib_sq *sq, 4783 u8 *sq_state) 4784 { 4785 int err; 4786 4787 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4788 if (err) 4789 goto out; 4790 sq->state = *sq_state; 4791 4792 out: 4793 return err; 4794 } 4795 4796 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4797 struct mlx5_ib_rq *rq, 4798 u8 *rq_state) 4799 { 4800 void *out; 4801 void *rqc; 4802 int inlen; 4803 int err; 4804 4805 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4806 out = kvzalloc(inlen, GFP_KERNEL); 4807 if (!out) 4808 return -ENOMEM; 4809 4810 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4811 if (err) 4812 goto out; 4813 4814 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4815 *rq_state = MLX5_GET(rqc, rqc, state); 4816 rq->state = *rq_state; 4817 4818 out: 4819 kvfree(out); 4820 return err; 4821 } 4822 4823 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4824 struct mlx5_ib_qp *qp, u8 *qp_state) 4825 { 4826 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4827 [MLX5_RQC_STATE_RST] = { 4828 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4829 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4830 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4831 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4832 }, 4833 [MLX5_RQC_STATE_RDY] = { 4834 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4835 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4836 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4837 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4838 }, 4839 [MLX5_RQC_STATE_ERR] = { 4840 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4841 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4842 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4843 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4844 }, 4845 [MLX5_RQ_STATE_NA] = { 4846 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4847 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4848 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4849 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4850 }, 4851 }; 4852 4853 *qp_state = sqrq_trans[rq_state][sq_state]; 4854 4855 if (*qp_state == MLX5_QP_STATE_BAD) { 4856 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4857 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4858 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4859 return -EINVAL; 4860 } 4861 4862 if (*qp_state == MLX5_QP_STATE) 4863 *qp_state = qp->state; 4864 4865 return 0; 4866 } 4867 4868 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4869 struct mlx5_ib_qp *qp, 4870 u8 *raw_packet_qp_state) 4871 { 4872 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4873 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4874 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4875 int err; 4876 u8 sq_state = MLX5_SQ_STATE_NA; 4877 u8 rq_state = MLX5_RQ_STATE_NA; 4878 4879 if (qp->sq.wqe_cnt) { 4880 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4881 if (err) 4882 return err; 4883 } 4884 4885 if (qp->rq.wqe_cnt) { 4886 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4887 if (err) 4888 return err; 4889 } 4890 4891 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4892 raw_packet_qp_state); 4893 } 4894 4895 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4896 struct ib_qp_attr *qp_attr) 4897 { 4898 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4899 void *qpc, *pri_path, *alt_path; 4900 u32 *outb; 4901 int err; 4902 4903 outb = kzalloc(outlen, GFP_KERNEL); 4904 if (!outb) 4905 return -ENOMEM; 4906 4907 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 4908 false); 4909 if (err) 4910 goto out; 4911 4912 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4913 4914 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4915 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4916 qp_attr->sq_draining = 1; 4917 4918 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4919 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4920 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4921 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4922 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4923 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4924 4925 if (MLX5_GET(qpc, qpc, rre)) 4926 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4927 if (MLX5_GET(qpc, qpc, rwe)) 4928 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4929 if (MLX5_GET(qpc, qpc, rae)) 4930 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4931 4932 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4933 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4934 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4935 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4936 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4937 4938 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4939 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4940 4941 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 4942 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 4943 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4944 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4945 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4946 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4947 } 4948 4949 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4950 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4951 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4952 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4953 4954 out: 4955 kfree(outb); 4956 return err; 4957 } 4958 4959 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4960 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4961 struct ib_qp_init_attr *qp_init_attr) 4962 { 4963 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4964 u32 *out; 4965 u32 access_flags = 0; 4966 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4967 void *dctc; 4968 int err; 4969 int supported_mask = IB_QP_STATE | 4970 IB_QP_ACCESS_FLAGS | 4971 IB_QP_PORT | 4972 IB_QP_MIN_RNR_TIMER | 4973 IB_QP_AV | 4974 IB_QP_PATH_MTU | 4975 IB_QP_PKEY_INDEX; 4976 4977 if (qp_attr_mask & ~supported_mask) 4978 return -EINVAL; 4979 if (mqp->state != IB_QPS_RTR) 4980 return -EINVAL; 4981 4982 out = kzalloc(outlen, GFP_KERNEL); 4983 if (!out) 4984 return -ENOMEM; 4985 4986 err = mlx5_core_dct_query(dev, dct, out, outlen); 4987 if (err) 4988 goto out; 4989 4990 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4991 4992 if (qp_attr_mask & IB_QP_STATE) 4993 qp_attr->qp_state = IB_QPS_RTR; 4994 4995 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4996 if (MLX5_GET(dctc, dctc, rre)) 4997 access_flags |= IB_ACCESS_REMOTE_READ; 4998 if (MLX5_GET(dctc, dctc, rwe)) 4999 access_flags |= IB_ACCESS_REMOTE_WRITE; 5000 if (MLX5_GET(dctc, dctc, rae)) 5001 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5002 qp_attr->qp_access_flags = access_flags; 5003 } 5004 5005 if (qp_attr_mask & IB_QP_PORT) 5006 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5007 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5008 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5009 if (qp_attr_mask & IB_QP_AV) { 5010 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5011 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5012 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5013 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5014 } 5015 if (qp_attr_mask & IB_QP_PATH_MTU) 5016 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5017 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5018 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5019 out: 5020 kfree(out); 5021 return err; 5022 } 5023 5024 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5025 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5026 { 5027 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5028 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5029 int err = 0; 5030 u8 raw_packet_qp_state; 5031 5032 if (ibqp->rwq_ind_tbl) 5033 return -ENOSYS; 5034 5035 if (qp->type == IB_QPT_GSI) 5036 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5037 qp_init_attr); 5038 5039 /* Not all of output fields are applicable, make sure to zero them */ 5040 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5041 memset(qp_attr, 0, sizeof(*qp_attr)); 5042 5043 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 5044 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5045 qp_attr_mask, qp_init_attr); 5046 5047 mutex_lock(&qp->mutex); 5048 5049 if (qp->type == IB_QPT_RAW_PACKET || 5050 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 5051 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5052 if (err) 5053 goto out; 5054 qp->state = raw_packet_qp_state; 5055 qp_attr->port_num = 1; 5056 } else { 5057 err = query_qp_attr(dev, qp, qp_attr); 5058 if (err) 5059 goto out; 5060 } 5061 5062 qp_attr->qp_state = qp->state; 5063 qp_attr->cur_qp_state = qp_attr->qp_state; 5064 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5065 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5066 5067 if (!ibqp->uobject) { 5068 qp_attr->cap.max_send_wr = qp->sq.max_post; 5069 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5070 qp_init_attr->qp_context = ibqp->qp_context; 5071 } else { 5072 qp_attr->cap.max_send_wr = 0; 5073 qp_attr->cap.max_send_sge = 0; 5074 } 5075 5076 qp_init_attr->qp_type = qp->type; 5077 qp_init_attr->recv_cq = ibqp->recv_cq; 5078 qp_init_attr->send_cq = ibqp->send_cq; 5079 qp_init_attr->srq = ibqp->srq; 5080 qp_attr->cap.max_inline_data = qp->max_inline_data; 5081 5082 qp_init_attr->cap = qp_attr->cap; 5083 5084 qp_init_attr->create_flags = qp->flags; 5085 5086 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5087 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5088 5089 out: 5090 mutex_unlock(&qp->mutex); 5091 return err; 5092 } 5093 5094 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 5095 { 5096 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 5097 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 5098 5099 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5100 return -EOPNOTSUPP; 5101 5102 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5103 } 5104 5105 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5106 { 5107 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5108 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5109 5110 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5111 } 5112 5113 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5114 { 5115 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5116 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5117 struct ib_event event; 5118 5119 if (rwq->ibwq.event_handler) { 5120 event.device = rwq->ibwq.device; 5121 event.element.wq = &rwq->ibwq; 5122 switch (type) { 5123 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5124 event.event = IB_EVENT_WQ_FATAL; 5125 break; 5126 default: 5127 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5128 return; 5129 } 5130 5131 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5132 } 5133 } 5134 5135 static int set_delay_drop(struct mlx5_ib_dev *dev) 5136 { 5137 int err = 0; 5138 5139 mutex_lock(&dev->delay_drop.lock); 5140 if (dev->delay_drop.activate) 5141 goto out; 5142 5143 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5144 if (err) 5145 goto out; 5146 5147 dev->delay_drop.activate = true; 5148 out: 5149 mutex_unlock(&dev->delay_drop.lock); 5150 5151 if (!err) 5152 atomic_inc(&dev->delay_drop.rqs_cnt); 5153 return err; 5154 } 5155 5156 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5157 struct ib_wq_init_attr *init_attr) 5158 { 5159 struct mlx5_ib_dev *dev; 5160 int has_net_offloads; 5161 __be64 *rq_pas0; 5162 int ts_format; 5163 void *in; 5164 void *rqc; 5165 void *wq; 5166 int inlen; 5167 int err; 5168 5169 dev = to_mdev(pd->device); 5170 5171 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5172 if (ts_format < 0) 5173 return ts_format; 5174 5175 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5176 in = kvzalloc(inlen, GFP_KERNEL); 5177 if (!in) 5178 return -ENOMEM; 5179 5180 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5181 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5182 MLX5_SET(rqc, rqc, mem_rq_type, 5183 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5184 MLX5_SET(rqc, rqc, ts_format, ts_format); 5185 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5186 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5187 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5188 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5189 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5190 MLX5_SET(wq, wq, wq_type, 5191 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5192 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5193 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5194 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5195 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5196 err = -EOPNOTSUPP; 5197 goto out; 5198 } else { 5199 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5200 } 5201 } 5202 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5203 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5204 /* 5205 * In Firmware number of strides in each WQE is: 5206 * "512 * 2^single_wqe_log_num_of_strides" 5207 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5208 * accepted as 0 to 9 5209 */ 5210 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5211 2, 3, 4, 5, 6, 7, 8, 9 }; 5212 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5213 MLX5_SET(wq, wq, log_wqe_stride_size, 5214 rwq->single_stride_log_num_of_bytes - 5215 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5216 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5217 fw_map[rwq->log_num_strides - 5218 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5219 } 5220 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5221 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5222 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5223 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5224 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5225 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5226 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5227 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5228 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5229 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5230 err = -EOPNOTSUPP; 5231 goto out; 5232 } 5233 } else { 5234 MLX5_SET(rqc, rqc, vsd, 1); 5235 } 5236 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5237 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5238 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5239 err = -EOPNOTSUPP; 5240 goto out; 5241 } 5242 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5243 } 5244 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5245 if (!(dev->ib_dev.attrs.raw_packet_caps & 5246 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5247 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5248 err = -EOPNOTSUPP; 5249 goto out; 5250 } 5251 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5252 } 5253 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5254 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5255 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5256 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5257 err = set_delay_drop(dev); 5258 if (err) { 5259 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5260 err); 5261 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5262 } else { 5263 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5264 } 5265 } 5266 out: 5267 kvfree(in); 5268 return err; 5269 } 5270 5271 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5272 struct ib_wq_init_attr *wq_init_attr, 5273 struct mlx5_ib_create_wq *ucmd, 5274 struct mlx5_ib_rwq *rwq) 5275 { 5276 /* Sanity check RQ size before proceeding */ 5277 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5278 return -EINVAL; 5279 5280 if (!ucmd->rq_wqe_count) 5281 return -EINVAL; 5282 5283 rwq->wqe_count = ucmd->rq_wqe_count; 5284 rwq->wqe_shift = ucmd->rq_wqe_shift; 5285 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5286 return -EINVAL; 5287 5288 rwq->log_rq_stride = rwq->wqe_shift; 5289 rwq->log_rq_size = ilog2(rwq->wqe_count); 5290 return 0; 5291 } 5292 5293 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5294 { 5295 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5296 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5297 return false; 5298 5299 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5300 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5301 return false; 5302 5303 return true; 5304 } 5305 5306 static int prepare_user_rq(struct ib_pd *pd, 5307 struct ib_wq_init_attr *init_attr, 5308 struct ib_udata *udata, 5309 struct mlx5_ib_rwq *rwq) 5310 { 5311 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5312 struct mlx5_ib_create_wq ucmd = {}; 5313 int err; 5314 size_t required_cmd_sz; 5315 5316 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5317 single_stride_log_num_of_bytes); 5318 if (udata->inlen < required_cmd_sz) { 5319 mlx5_ib_dbg(dev, "invalid inlen\n"); 5320 return -EINVAL; 5321 } 5322 5323 if (udata->inlen > sizeof(ucmd) && 5324 !ib_is_udata_cleared(udata, sizeof(ucmd), 5325 udata->inlen - sizeof(ucmd))) { 5326 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5327 return -EOPNOTSUPP; 5328 } 5329 5330 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5331 mlx5_ib_dbg(dev, "copy failed\n"); 5332 return -EFAULT; 5333 } 5334 5335 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5336 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5337 return -EOPNOTSUPP; 5338 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5339 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5340 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5341 return -EOPNOTSUPP; 5342 } 5343 if ((ucmd.single_stride_log_num_of_bytes < 5344 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5345 (ucmd.single_stride_log_num_of_bytes > 5346 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5347 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5348 ucmd.single_stride_log_num_of_bytes, 5349 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5350 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5351 return -EINVAL; 5352 } 5353 if (!log_of_strides_valid(dev, 5354 ucmd.single_wqe_log_num_of_strides)) { 5355 mlx5_ib_dbg( 5356 dev, 5357 "Invalid log num strides (%u. Range is %u - %u)\n", 5358 ucmd.single_wqe_log_num_of_strides, 5359 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5360 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5361 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5362 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5363 return -EINVAL; 5364 } 5365 rwq->single_stride_log_num_of_bytes = 5366 ucmd.single_stride_log_num_of_bytes; 5367 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5368 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5369 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5370 } 5371 5372 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5373 if (err) { 5374 mlx5_ib_dbg(dev, "err %d\n", err); 5375 return err; 5376 } 5377 5378 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5379 if (err) { 5380 mlx5_ib_dbg(dev, "err %d\n", err); 5381 return err; 5382 } 5383 5384 rwq->user_index = ucmd.user_index; 5385 return 0; 5386 } 5387 5388 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5389 struct ib_wq_init_attr *init_attr, 5390 struct ib_udata *udata) 5391 { 5392 struct mlx5_ib_dev *dev; 5393 struct mlx5_ib_rwq *rwq; 5394 struct mlx5_ib_create_wq_resp resp = {}; 5395 size_t min_resp_len; 5396 int err; 5397 5398 if (!udata) 5399 return ERR_PTR(-ENOSYS); 5400 5401 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5402 if (udata->outlen && udata->outlen < min_resp_len) 5403 return ERR_PTR(-EINVAL); 5404 5405 if (!capable(CAP_SYS_RAWIO) && 5406 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5407 return ERR_PTR(-EPERM); 5408 5409 dev = to_mdev(pd->device); 5410 switch (init_attr->wq_type) { 5411 case IB_WQT_RQ: 5412 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5413 if (!rwq) 5414 return ERR_PTR(-ENOMEM); 5415 err = prepare_user_rq(pd, init_attr, udata, rwq); 5416 if (err) 5417 goto err; 5418 err = create_rq(rwq, pd, init_attr); 5419 if (err) 5420 goto err_user_rq; 5421 break; 5422 default: 5423 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5424 init_attr->wq_type); 5425 return ERR_PTR(-EINVAL); 5426 } 5427 5428 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5429 rwq->ibwq.state = IB_WQS_RESET; 5430 if (udata->outlen) { 5431 resp.response_length = offsetofend( 5432 struct mlx5_ib_create_wq_resp, response_length); 5433 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5434 if (err) 5435 goto err_copy; 5436 } 5437 5438 rwq->core_qp.event = mlx5_ib_wq_event; 5439 rwq->ibwq.event_handler = init_attr->event_handler; 5440 return &rwq->ibwq; 5441 5442 err_copy: 5443 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5444 err_user_rq: 5445 destroy_user_rq(dev, pd, rwq, udata); 5446 err: 5447 kfree(rwq); 5448 return ERR_PTR(err); 5449 } 5450 5451 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5452 { 5453 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5454 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5455 int ret; 5456 5457 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5458 if (ret) 5459 return ret; 5460 destroy_user_rq(dev, wq->pd, rwq, udata); 5461 kfree(rwq); 5462 return 0; 5463 } 5464 5465 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5466 struct ib_rwq_ind_table_init_attr *init_attr, 5467 struct ib_udata *udata) 5468 { 5469 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5470 to_mrwq_ind_table(ib_rwq_ind_table); 5471 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5472 int sz = 1 << init_attr->log_ind_tbl_size; 5473 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5474 size_t min_resp_len; 5475 int inlen; 5476 int err; 5477 int i; 5478 u32 *in; 5479 void *rqtc; 5480 5481 if (udata->inlen > 0 && 5482 !ib_is_udata_cleared(udata, 0, 5483 udata->inlen)) 5484 return -EOPNOTSUPP; 5485 5486 if (init_attr->log_ind_tbl_size > 5487 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5488 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5489 init_attr->log_ind_tbl_size, 5490 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5491 return -EINVAL; 5492 } 5493 5494 min_resp_len = 5495 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5496 if (udata->outlen && udata->outlen < min_resp_len) 5497 return -EINVAL; 5498 5499 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5500 in = kvzalloc(inlen, GFP_KERNEL); 5501 if (!in) 5502 return -ENOMEM; 5503 5504 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5505 5506 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5507 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5508 5509 for (i = 0; i < sz; i++) 5510 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5511 5512 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5513 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5514 5515 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5516 kvfree(in); 5517 if (err) 5518 return err; 5519 5520 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5521 if (udata->outlen) { 5522 resp.response_length = 5523 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5524 response_length); 5525 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5526 if (err) 5527 goto err_copy; 5528 } 5529 5530 return 0; 5531 5532 err_copy: 5533 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5534 return err; 5535 } 5536 5537 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5538 { 5539 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5540 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5541 5542 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5543 } 5544 5545 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5546 u32 wq_attr_mask, struct ib_udata *udata) 5547 { 5548 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5549 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5550 struct mlx5_ib_modify_wq ucmd = {}; 5551 size_t required_cmd_sz; 5552 int curr_wq_state; 5553 int wq_state; 5554 int inlen; 5555 int err; 5556 void *rqc; 5557 void *in; 5558 5559 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5560 if (udata->inlen < required_cmd_sz) 5561 return -EINVAL; 5562 5563 if (udata->inlen > sizeof(ucmd) && 5564 !ib_is_udata_cleared(udata, sizeof(ucmd), 5565 udata->inlen - sizeof(ucmd))) 5566 return -EOPNOTSUPP; 5567 5568 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5569 return -EFAULT; 5570 5571 if (ucmd.comp_mask || ucmd.reserved) 5572 return -EOPNOTSUPP; 5573 5574 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5575 in = kvzalloc(inlen, GFP_KERNEL); 5576 if (!in) 5577 return -ENOMEM; 5578 5579 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5580 5581 curr_wq_state = wq_attr->curr_wq_state; 5582 wq_state = wq_attr->wq_state; 5583 if (curr_wq_state == IB_WQS_ERR) 5584 curr_wq_state = MLX5_RQC_STATE_ERR; 5585 if (wq_state == IB_WQS_ERR) 5586 wq_state = MLX5_RQC_STATE_ERR; 5587 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5588 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5589 MLX5_SET(rqc, rqc, state, wq_state); 5590 5591 if (wq_attr_mask & IB_WQ_FLAGS) { 5592 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5593 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5594 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5595 mlx5_ib_dbg(dev, "VLAN offloads are not " 5596 "supported\n"); 5597 err = -EOPNOTSUPP; 5598 goto out; 5599 } 5600 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5601 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5602 MLX5_SET(rqc, rqc, vsd, 5603 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5604 } 5605 5606 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5607 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5608 err = -EOPNOTSUPP; 5609 goto out; 5610 } 5611 } 5612 5613 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5614 u16 set_id; 5615 5616 set_id = mlx5_ib_get_counters_id(dev, 0); 5617 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5618 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5619 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5620 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5621 } else 5622 dev_info_once( 5623 &dev->ib_dev.dev, 5624 "Receive WQ counters are not supported on current FW\n"); 5625 } 5626 5627 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5628 if (!err) 5629 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5630 5631 out: 5632 kvfree(in); 5633 return err; 5634 } 5635 5636 struct mlx5_ib_drain_cqe { 5637 struct ib_cqe cqe; 5638 struct completion done; 5639 }; 5640 5641 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5642 { 5643 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5644 struct mlx5_ib_drain_cqe, 5645 cqe); 5646 5647 complete(&cqe->done); 5648 } 5649 5650 /* This function returns only once the drained WR was completed */ 5651 static void handle_drain_completion(struct ib_cq *cq, 5652 struct mlx5_ib_drain_cqe *sdrain, 5653 struct mlx5_ib_dev *dev) 5654 { 5655 struct mlx5_core_dev *mdev = dev->mdev; 5656 5657 if (cq->poll_ctx == IB_POLL_DIRECT) { 5658 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5659 ib_process_cq_direct(cq, -1); 5660 return; 5661 } 5662 5663 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5664 struct mlx5_ib_cq *mcq = to_mcq(cq); 5665 bool triggered = false; 5666 unsigned long flags; 5667 5668 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5669 /* Make sure that the CQ handler won't run if wasn't run yet */ 5670 if (!mcq->mcq.reset_notify_added) 5671 mcq->mcq.reset_notify_added = 1; 5672 else 5673 triggered = true; 5674 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5675 5676 if (triggered) { 5677 /* Wait for any scheduled/running task to be ended */ 5678 switch (cq->poll_ctx) { 5679 case IB_POLL_SOFTIRQ: 5680 irq_poll_disable(&cq->iop); 5681 irq_poll_enable(&cq->iop); 5682 break; 5683 case IB_POLL_WORKQUEUE: 5684 cancel_work_sync(&cq->work); 5685 break; 5686 default: 5687 WARN_ON_ONCE(1); 5688 } 5689 } 5690 5691 /* Run the CQ handler - this makes sure that the drain WR will 5692 * be processed if wasn't processed yet. 5693 */ 5694 mcq->mcq.comp(&mcq->mcq, NULL); 5695 } 5696 5697 wait_for_completion(&sdrain->done); 5698 } 5699 5700 void mlx5_ib_drain_sq(struct ib_qp *qp) 5701 { 5702 struct ib_cq *cq = qp->send_cq; 5703 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5704 struct mlx5_ib_drain_cqe sdrain; 5705 const struct ib_send_wr *bad_swr; 5706 struct ib_rdma_wr swr = { 5707 .wr = { 5708 .next = NULL, 5709 { .wr_cqe = &sdrain.cqe, }, 5710 .opcode = IB_WR_RDMA_WRITE, 5711 }, 5712 }; 5713 int ret; 5714 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5715 struct mlx5_core_dev *mdev = dev->mdev; 5716 5717 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5718 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5719 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5720 return; 5721 } 5722 5723 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5724 init_completion(&sdrain.done); 5725 5726 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5727 if (ret) { 5728 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5729 return; 5730 } 5731 5732 handle_drain_completion(cq, &sdrain, dev); 5733 } 5734 5735 void mlx5_ib_drain_rq(struct ib_qp *qp) 5736 { 5737 struct ib_cq *cq = qp->recv_cq; 5738 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5739 struct mlx5_ib_drain_cqe rdrain; 5740 struct ib_recv_wr rwr = {}; 5741 const struct ib_recv_wr *bad_rwr; 5742 int ret; 5743 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5744 struct mlx5_core_dev *mdev = dev->mdev; 5745 5746 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5747 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5748 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5749 return; 5750 } 5751 5752 rwr.wr_cqe = &rdrain.cqe; 5753 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5754 init_completion(&rdrain.done); 5755 5756 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5757 if (ret) { 5758 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5759 return; 5760 } 5761 5762 handle_drain_completion(cq, &rdrain, dev); 5763 } 5764 5765 /* 5766 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5767 * the default counter 5768 */ 5769 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5770 { 5771 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5772 struct mlx5_ib_qp *mqp = to_mqp(qp); 5773 int err = 0; 5774 5775 mutex_lock(&mqp->mutex); 5776 if (mqp->state == IB_QPS_RESET) { 5777 qp->counter = counter; 5778 goto out; 5779 } 5780 5781 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5782 err = -EOPNOTSUPP; 5783 goto out; 5784 } 5785 5786 if (mqp->state == IB_QPS_RTS) { 5787 err = __mlx5_ib_qp_set_counter(qp, counter); 5788 if (!err) 5789 qp->counter = counter; 5790 5791 goto out; 5792 } 5793 5794 mqp->counter_pending = 1; 5795 qp->counter = counter; 5796 5797 out: 5798 mutex_unlock(&mqp->mutex); 5799 return err; 5800 } 5801 5802 int mlx5_ib_qp_event_init(void) 5803 { 5804 mlx5_ib_qp_event_wq = alloc_ordered_workqueue("mlx5_ib_qp_event_wq", 0); 5805 if (!mlx5_ib_qp_event_wq) 5806 return -ENOMEM; 5807 5808 return 0; 5809 } 5810 5811 void mlx5_ib_qp_event_cleanup(void) 5812 { 5813 destroy_workqueue(mlx5_ib_qp_event_wq); 5814 } 5815