1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include "efx.h" 13 #include "nic_common.h" 14 #include "tx_common.h" 15 16 static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue) 17 { 18 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 19 PAGE_SIZE >> EFX_TX_CB_ORDER); 20 } 21 22 int efx_siena_probe_tx_queue(struct efx_tx_queue *tx_queue) 23 { 24 struct efx_nic *efx = tx_queue->efx; 25 unsigned int entries; 26 int rc; 27 28 /* Create the smallest power-of-two aligned ring */ 29 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); 30 EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); 31 tx_queue->ptr_mask = entries - 1; 32 33 netif_dbg(efx, probe, efx->net_dev, 34 "creating TX queue %d size %#x mask %#x\n", 35 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); 36 37 /* Allocate software ring */ 38 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer), 39 GFP_KERNEL); 40 if (!tx_queue->buffer) 41 return -ENOMEM; 42 43 tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue), 44 sizeof(tx_queue->cb_page[0]), GFP_KERNEL); 45 if (!tx_queue->cb_page) { 46 rc = -ENOMEM; 47 goto fail1; 48 } 49 50 /* Allocate hardware ring, determine TXQ type */ 51 rc = efx_nic_probe_tx(tx_queue); 52 if (rc) 53 goto fail2; 54 55 tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue; 56 return 0; 57 58 fail2: 59 kfree(tx_queue->cb_page); 60 tx_queue->cb_page = NULL; 61 fail1: 62 kfree(tx_queue->buffer); 63 tx_queue->buffer = NULL; 64 return rc; 65 } 66 67 void efx_siena_init_tx_queue(struct efx_tx_queue *tx_queue) 68 { 69 struct efx_nic *efx = tx_queue->efx; 70 71 netif_dbg(efx, drv, efx->net_dev, 72 "initialising TX queue %d\n", tx_queue->queue); 73 74 tx_queue->insert_count = 0; 75 tx_queue->notify_count = 0; 76 tx_queue->write_count = 0; 77 tx_queue->packet_write_count = 0; 78 tx_queue->old_write_count = 0; 79 tx_queue->read_count = 0; 80 tx_queue->old_read_count = 0; 81 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; 82 tx_queue->xmit_pending = false; 83 tx_queue->timestamping = (efx_siena_ptp_use_mac_tx_timestamps(efx) && 84 tx_queue->channel == efx_siena_ptp_channel(efx)); 85 tx_queue->completed_timestamp_major = 0; 86 tx_queue->completed_timestamp_minor = 0; 87 88 tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel); 89 tx_queue->tso_version = 0; 90 91 /* Set up TX descriptor ring */ 92 efx_nic_init_tx(tx_queue); 93 94 tx_queue->initialised = true; 95 } 96 97 void efx_siena_remove_tx_queue(struct efx_tx_queue *tx_queue) 98 { 99 int i; 100 101 if (!tx_queue->buffer) 102 return; 103 104 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 105 "destroying TX queue %d\n", tx_queue->queue); 106 efx_nic_remove_tx(tx_queue); 107 108 if (tx_queue->cb_page) { 109 for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++) 110 efx_siena_free_buffer(tx_queue->efx, 111 &tx_queue->cb_page[i]); 112 kfree(tx_queue->cb_page); 113 tx_queue->cb_page = NULL; 114 } 115 116 kfree(tx_queue->buffer); 117 tx_queue->buffer = NULL; 118 tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL; 119 } 120 121 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, 122 struct efx_tx_buffer *buffer, 123 unsigned int *pkts_compl, 124 unsigned int *bytes_compl) 125 { 126 if (buffer->unmap_len) { 127 struct device *dma_dev = &tx_queue->efx->pci_dev->dev; 128 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset; 129 130 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE) 131 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len, 132 DMA_TO_DEVICE); 133 else 134 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len, 135 DMA_TO_DEVICE); 136 buffer->unmap_len = 0; 137 } 138 139 if (buffer->flags & EFX_TX_BUF_SKB) { 140 struct sk_buff *skb = (struct sk_buff *)buffer->skb; 141 142 EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl); 143 (*pkts_compl)++; 144 (*bytes_compl) += skb->len; 145 if (tx_queue->timestamping && 146 (tx_queue->completed_timestamp_major || 147 tx_queue->completed_timestamp_minor)) { 148 struct skb_shared_hwtstamps hwtstamp; 149 150 hwtstamp.hwtstamp = 151 efx_siena_ptp_nic_to_kernel_time(tx_queue); 152 skb_tstamp_tx(skb, &hwtstamp); 153 154 tx_queue->completed_timestamp_major = 0; 155 tx_queue->completed_timestamp_minor = 0; 156 } 157 dev_consume_skb_any((struct sk_buff *)buffer->skb); 158 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, 159 "TX queue %d transmission id %x complete\n", 160 tx_queue->queue, tx_queue->read_count); 161 } else if (buffer->flags & EFX_TX_BUF_XDP) { 162 xdp_return_frame_rx_napi(buffer->xdpf); 163 } 164 165 buffer->len = 0; 166 buffer->flags = 0; 167 } 168 169 void efx_siena_fini_tx_queue(struct efx_tx_queue *tx_queue) 170 { 171 struct efx_tx_buffer *buffer; 172 173 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 174 "shutting down TX queue %d\n", tx_queue->queue); 175 176 if (!tx_queue->buffer) 177 return; 178 179 /* Free any buffers left in the ring */ 180 while (tx_queue->read_count != tx_queue->write_count) { 181 unsigned int pkts_compl = 0, bytes_compl = 0; 182 183 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; 184 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 185 186 ++tx_queue->read_count; 187 } 188 tx_queue->xmit_pending = false; 189 netdev_tx_reset_queue(tx_queue->core_txq); 190 } 191 192 /* Remove packets from the TX queue 193 * 194 * This removes packets from the TX queue, up to and including the 195 * specified index. 196 */ 197 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, 198 unsigned int index, 199 unsigned int *pkts_compl, 200 unsigned int *bytes_compl) 201 { 202 struct efx_nic *efx = tx_queue->efx; 203 unsigned int stop_index, read_ptr; 204 205 stop_index = (index + 1) & tx_queue->ptr_mask; 206 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 207 208 while (read_ptr != stop_index) { 209 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; 210 211 if (!efx_tx_buffer_in_use(buffer)) { 212 netif_err(efx, tx_err, efx->net_dev, 213 "TX queue %d spurious TX completion id %d\n", 214 tx_queue->queue, read_ptr); 215 efx_siena_schedule_reset(efx, RESET_TYPE_TX_SKIP); 216 return; 217 } 218 219 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); 220 221 ++tx_queue->read_count; 222 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 223 } 224 } 225 226 void efx_siena_xmit_done_check_empty(struct efx_tx_queue *tx_queue) 227 { 228 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { 229 tx_queue->old_write_count = READ_ONCE(tx_queue->write_count); 230 if (tx_queue->read_count == tx_queue->old_write_count) { 231 /* Ensure that read_count is flushed. */ 232 smp_mb(); 233 tx_queue->empty_read_count = 234 tx_queue->read_count | EFX_EMPTY_COUNT_VALID; 235 } 236 } 237 } 238 239 void efx_siena_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) 240 { 241 unsigned int fill_level, pkts_compl = 0, bytes_compl = 0; 242 struct efx_nic *efx = tx_queue->efx; 243 244 EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask); 245 246 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); 247 tx_queue->pkts_compl += pkts_compl; 248 tx_queue->bytes_compl += bytes_compl; 249 250 if (pkts_compl > 1) 251 ++tx_queue->merge_events; 252 253 /* See if we need to restart the netif queue. This memory 254 * barrier ensures that we write read_count (inside 255 * efx_dequeue_buffers()) before reading the queue status. 256 */ 257 smp_mb(); 258 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && 259 likely(efx->port_enabled) && 260 likely(netif_device_present(efx->net_dev))) { 261 fill_level = efx_channel_tx_fill_level(tx_queue->channel); 262 if (fill_level <= efx->txq_wake_thresh) 263 netif_tx_wake_queue(tx_queue->core_txq); 264 } 265 266 efx_siena_xmit_done_check_empty(tx_queue); 267 } 268 269 /* Remove buffers put into a tx_queue for the current packet. 270 * None of the buffers must have an skb attached. 271 */ 272 void efx_siena_enqueue_unwind(struct efx_tx_queue *tx_queue, 273 unsigned int insert_count) 274 { 275 struct efx_tx_buffer *buffer; 276 unsigned int bytes_compl = 0; 277 unsigned int pkts_compl = 0; 278 279 /* Work backwards until we hit the original insert pointer value */ 280 while (tx_queue->insert_count != insert_count) { 281 --tx_queue->insert_count; 282 buffer = __efx_tx_queue_get_insert_buffer(tx_queue); 283 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 284 } 285 } 286 287 struct efx_tx_buffer *efx_siena_tx_map_chunk(struct efx_tx_queue *tx_queue, 288 dma_addr_t dma_addr, size_t len) 289 { 290 const struct efx_nic_type *nic_type = tx_queue->efx->type; 291 struct efx_tx_buffer *buffer; 292 unsigned int dma_len; 293 294 /* Map the fragment taking account of NIC-dependent DMA limits. */ 295 do { 296 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 297 298 if (nic_type->tx_limit_len) 299 dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len); 300 else 301 dma_len = len; 302 303 buffer->len = dma_len; 304 buffer->dma_addr = dma_addr; 305 buffer->flags = EFX_TX_BUF_CONT; 306 len -= dma_len; 307 dma_addr += dma_len; 308 ++tx_queue->insert_count; 309 } while (len); 310 311 return buffer; 312 } 313 314 static int efx_tx_tso_header_length(struct sk_buff *skb) 315 { 316 size_t header_len; 317 318 if (skb->encapsulation) 319 header_len = skb_inner_transport_header(skb) - 320 skb->data + 321 (inner_tcp_hdr(skb)->doff << 2u); 322 else 323 header_len = skb_transport_header(skb) - skb->data + 324 (tcp_hdr(skb)->doff << 2u); 325 return header_len; 326 } 327 328 /* Map all data from an SKB for DMA and create descriptors on the queue. */ 329 int efx_siena_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 330 unsigned int segment_count) 331 { 332 struct efx_nic *efx = tx_queue->efx; 333 struct device *dma_dev = &efx->pci_dev->dev; 334 unsigned int frag_index, nr_frags; 335 dma_addr_t dma_addr, unmap_addr; 336 unsigned short dma_flags; 337 size_t len, unmap_len; 338 339 nr_frags = skb_shinfo(skb)->nr_frags; 340 frag_index = 0; 341 342 /* Map header data. */ 343 len = skb_headlen(skb); 344 dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE); 345 dma_flags = EFX_TX_BUF_MAP_SINGLE; 346 unmap_len = len; 347 unmap_addr = dma_addr; 348 349 if (unlikely(dma_mapping_error(dma_dev, dma_addr))) 350 return -EIO; 351 352 if (segment_count) { 353 /* For TSO we need to put the header in to a separate 354 * descriptor. Map this separately if necessary. 355 */ 356 size_t header_len = efx_tx_tso_header_length(skb); 357 358 if (header_len != len) { 359 tx_queue->tso_long_headers++; 360 efx_siena_tx_map_chunk(tx_queue, dma_addr, header_len); 361 len -= header_len; 362 dma_addr += header_len; 363 } 364 } 365 366 /* Add descriptors for each fragment. */ 367 do { 368 struct efx_tx_buffer *buffer; 369 skb_frag_t *fragment; 370 371 buffer = efx_siena_tx_map_chunk(tx_queue, dma_addr, len); 372 373 /* The final descriptor for a fragment is responsible for 374 * unmapping the whole fragment. 375 */ 376 buffer->flags = EFX_TX_BUF_CONT | dma_flags; 377 buffer->unmap_len = unmap_len; 378 buffer->dma_offset = buffer->dma_addr - unmap_addr; 379 380 if (frag_index >= nr_frags) { 381 /* Store SKB details with the final buffer for 382 * the completion. 383 */ 384 buffer->skb = skb; 385 buffer->flags = EFX_TX_BUF_SKB | dma_flags; 386 return 0; 387 } 388 389 /* Move on to the next fragment. */ 390 fragment = &skb_shinfo(skb)->frags[frag_index++]; 391 len = skb_frag_size(fragment); 392 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len, 393 DMA_TO_DEVICE); 394 dma_flags = 0; 395 unmap_len = len; 396 unmap_addr = dma_addr; 397 398 if (unlikely(dma_mapping_error(dma_dev, dma_addr))) 399 return -EIO; 400 } while (1); 401 } 402 403 unsigned int efx_siena_tx_max_skb_descs(struct efx_nic *efx) 404 { 405 /* Header and payload descriptor for each output segment, plus 406 * one for every input fragment boundary within a segment 407 */ 408 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS; 409 410 /* Possibly one more per segment for option descriptors */ 411 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 412 max_descs += EFX_TSO_MAX_SEGS; 413 414 /* Possibly more for PCIe page boundaries within input fragments */ 415 if (PAGE_SIZE > EFX_PAGE_SIZE) 416 max_descs += max_t(unsigned int, MAX_SKB_FRAGS, 417 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE)); 418 419 return max_descs; 420 } 421 422 /* 423 * Fallback to software TSO. 424 * 425 * This is used if we are unable to send a GSO packet through hardware TSO. 426 * This should only ever happen due to per-queue restrictions - unsupported 427 * packets should first be filtered by the feature flags. 428 * 429 * Returns 0 on success, error code otherwise. 430 */ 431 int efx_siena_tx_tso_fallback(struct efx_tx_queue *tx_queue, 432 struct sk_buff *skb) 433 { 434 struct sk_buff *segments, *next; 435 436 segments = skb_gso_segment(skb, 0); 437 if (IS_ERR(segments)) 438 return PTR_ERR(segments); 439 440 dev_consume_skb_any(skb); 441 442 skb_list_walk_safe(segments, skb, next) { 443 skb_mark_not_on_list(skb); 444 efx_enqueue_skb(tx_queue, skb); 445 } 446 447 return 0; 448 } 449