1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/console.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dmapool.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/serial_core.h> 26 #include <linux/slab.h> 27 #include <linux/tty_flip.h> 28 29 /* All registers are 8-bit width */ 30 #define UARTBDH 0x00 31 #define UARTBDL 0x01 32 #define UARTCR1 0x02 33 #define UARTCR2 0x03 34 #define UARTSR1 0x04 35 #define UARTCR3 0x06 36 #define UARTDR 0x07 37 #define UARTCR4 0x0a 38 #define UARTCR5 0x0b 39 #define UARTMODEM 0x0d 40 #define UARTPFIFO 0x10 41 #define UARTCFIFO 0x11 42 #define UARTSFIFO 0x12 43 #define UARTTWFIFO 0x13 44 #define UARTTCFIFO 0x14 45 #define UARTRWFIFO 0x15 46 47 #define UARTBDH_LBKDIE 0x80 48 #define UARTBDH_RXEDGIE 0x40 49 #define UARTBDH_SBR_MASK 0x1f 50 51 #define UARTCR1_LOOPS 0x80 52 #define UARTCR1_RSRC 0x20 53 #define UARTCR1_M 0x10 54 #define UARTCR1_WAKE 0x08 55 #define UARTCR1_ILT 0x04 56 #define UARTCR1_PE 0x02 57 #define UARTCR1_PT 0x01 58 59 #define UARTCR2_TIE 0x80 60 #define UARTCR2_TCIE 0x40 61 #define UARTCR2_RIE 0x20 62 #define UARTCR2_ILIE 0x10 63 #define UARTCR2_TE 0x08 64 #define UARTCR2_RE 0x04 65 #define UARTCR2_RWU 0x02 66 #define UARTCR2_SBK 0x01 67 68 #define UARTSR1_TDRE 0x80 69 #define UARTSR1_TC 0x40 70 #define UARTSR1_RDRF 0x20 71 #define UARTSR1_IDLE 0x10 72 #define UARTSR1_OR 0x08 73 #define UARTSR1_NF 0x04 74 #define UARTSR1_FE 0x02 75 #define UARTSR1_PE 0x01 76 77 #define UARTCR3_R8 0x80 78 #define UARTCR3_T8 0x40 79 #define UARTCR3_TXDIR 0x20 80 #define UARTCR3_TXINV 0x10 81 #define UARTCR3_ORIE 0x08 82 #define UARTCR3_NEIE 0x04 83 #define UARTCR3_FEIE 0x02 84 #define UARTCR3_PEIE 0x01 85 86 #define UARTCR4_MAEN1 0x80 87 #define UARTCR4_MAEN2 0x40 88 #define UARTCR4_M10 0x20 89 #define UARTCR4_BRFA_MASK 0x1f 90 #define UARTCR4_BRFA_OFF 0 91 92 #define UARTCR5_TDMAS 0x80 93 #define UARTCR5_RDMAS 0x20 94 95 #define UARTMODEM_RXRTSE 0x08 96 #define UARTMODEM_TXRTSPOL 0x04 97 #define UARTMODEM_TXRTSE 0x02 98 #define UARTMODEM_TXCTSE 0x01 99 100 #define UARTPFIFO_TXFE 0x80 101 #define UARTPFIFO_FIFOSIZE_MASK 0x7 102 #define UARTPFIFO_TXSIZE_OFF 4 103 #define UARTPFIFO_RXFE 0x08 104 #define UARTPFIFO_RXSIZE_OFF 0 105 106 #define UARTCFIFO_TXFLUSH 0x80 107 #define UARTCFIFO_RXFLUSH 0x40 108 #define UARTCFIFO_RXOFE 0x04 109 #define UARTCFIFO_TXOFE 0x02 110 #define UARTCFIFO_RXUFE 0x01 111 112 #define UARTSFIFO_TXEMPT 0x80 113 #define UARTSFIFO_RXEMPT 0x40 114 #define UARTSFIFO_RXOF 0x04 115 #define UARTSFIFO_TXOF 0x02 116 #define UARTSFIFO_RXUF 0x01 117 118 /* 32-bit global registers only for i.MX7ULP/i.MX8x 119 * Used to reset all internal logic and registers, except the Global Register. 120 */ 121 #define UART_GLOBAL 0x8 122 123 /* 32-bit register definition */ 124 #define UARTBAUD 0x00 125 #define UARTSTAT 0x04 126 #define UARTCTRL 0x08 127 #define UARTDATA 0x0C 128 #define UARTMATCH 0x10 129 #define UARTMODIR 0x14 130 #define UARTFIFO 0x18 131 #define UARTWATER 0x1c 132 133 #define UARTBAUD_MAEN1 0x80000000 134 #define UARTBAUD_MAEN2 0x40000000 135 #define UARTBAUD_M10 0x20000000 136 #define UARTBAUD_TDMAE 0x00800000 137 #define UARTBAUD_RDMAE 0x00200000 138 #define UARTBAUD_MATCFG 0x00400000 139 #define UARTBAUD_BOTHEDGE 0x00020000 140 #define UARTBAUD_RESYNCDIS 0x00010000 141 #define UARTBAUD_LBKDIE 0x00008000 142 #define UARTBAUD_RXEDGIE 0x00004000 143 #define UARTBAUD_SBNS 0x00002000 144 #define UARTBAUD_SBR 0x00000000 145 #define UARTBAUD_SBR_MASK 0x1fff 146 #define UARTBAUD_OSR_MASK 0x1f 147 #define UARTBAUD_OSR_SHIFT 24 148 149 #define UARTSTAT_LBKDIF 0x80000000 150 #define UARTSTAT_RXEDGIF 0x40000000 151 #define UARTSTAT_MSBF 0x20000000 152 #define UARTSTAT_RXINV 0x10000000 153 #define UARTSTAT_RWUID 0x08000000 154 #define UARTSTAT_BRK13 0x04000000 155 #define UARTSTAT_LBKDE 0x02000000 156 #define UARTSTAT_RAF 0x01000000 157 #define UARTSTAT_TDRE 0x00800000 158 #define UARTSTAT_TC 0x00400000 159 #define UARTSTAT_RDRF 0x00200000 160 #define UARTSTAT_IDLE 0x00100000 161 #define UARTSTAT_OR 0x00080000 162 #define UARTSTAT_NF 0x00040000 163 #define UARTSTAT_FE 0x00020000 164 #define UARTSTAT_PE 0x00010000 165 #define UARTSTAT_MA1F 0x00008000 166 #define UARTSTAT_M21F 0x00004000 167 168 #define UARTCTRL_R8T9 0x80000000 169 #define UARTCTRL_R9T8 0x40000000 170 #define UARTCTRL_TXDIR 0x20000000 171 #define UARTCTRL_TXINV 0x10000000 172 #define UARTCTRL_ORIE 0x08000000 173 #define UARTCTRL_NEIE 0x04000000 174 #define UARTCTRL_FEIE 0x02000000 175 #define UARTCTRL_PEIE 0x01000000 176 #define UARTCTRL_TIE 0x00800000 177 #define UARTCTRL_TCIE 0x00400000 178 #define UARTCTRL_RIE 0x00200000 179 #define UARTCTRL_ILIE 0x00100000 180 #define UARTCTRL_TE 0x00080000 181 #define UARTCTRL_RE 0x00040000 182 #define UARTCTRL_RWU 0x00020000 183 #define UARTCTRL_SBK 0x00010000 184 #define UARTCTRL_MA1IE 0x00008000 185 #define UARTCTRL_MA2IE 0x00004000 186 #define UARTCTRL_IDLECFG GENMASK(10, 8) 187 #define UARTCTRL_LOOPS 0x00000080 188 #define UARTCTRL_DOZEEN 0x00000040 189 #define UARTCTRL_RSRC 0x00000020 190 #define UARTCTRL_M 0x00000010 191 #define UARTCTRL_WAKE 0x00000008 192 #define UARTCTRL_ILT 0x00000004 193 #define UARTCTRL_PE 0x00000002 194 #define UARTCTRL_PT 0x00000001 195 196 #define UARTDATA_NOISY 0x00008000 197 #define UARTDATA_PARITYE 0x00004000 198 #define UARTDATA_FRETSC 0x00002000 199 #define UARTDATA_RXEMPT 0x00001000 200 #define UARTDATA_IDLINE 0x00000800 201 #define UARTDATA_MASK 0x3ff 202 203 #define UARTMODIR_IREN 0x00020000 204 #define UARTMODIR_RTSWATER GENMASK(10, 8) 205 #define UARTMODIR_TXCTSSRC 0x00000020 206 #define UARTMODIR_TXCTSC 0x00000010 207 #define UARTMODIR_RXRTSE 0x00000008 208 #define UARTMODIR_TXRTSPOL 0x00000004 209 #define UARTMODIR_TXRTSE 0x00000002 210 #define UARTMODIR_TXCTSE 0x00000001 211 212 #define UARTFIFO_TXEMPT 0x00800000 213 #define UARTFIFO_RXEMPT 0x00400000 214 #define UARTFIFO_TXOF 0x00020000 215 #define UARTFIFO_RXUF 0x00010000 216 #define UARTFIFO_TXFLUSH 0x00008000 217 #define UARTFIFO_RXFLUSH 0x00004000 218 #define UARTFIFO_RXIDEN GENMASK(12, 10) 219 #define UARTFIFO_TXOFE 0x00000200 220 #define UARTFIFO_RXUFE 0x00000100 221 #define UARTFIFO_TXFE 0x00000080 222 #define UARTFIFO_FIFOSIZE_MASK 0x7 223 #define UARTFIFO_TXSIZE_OFF 4 224 #define UARTFIFO_RXFE 0x00000008 225 #define UARTFIFO_RXSIZE_OFF 0 226 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 227 228 #define UARTWATER_COUNT_MASK 0xff 229 #define UARTWATER_TXCNT_OFF 8 230 #define UARTWATER_RXCNT_OFF 24 231 #define UARTWATER_WATER_MASK 0xff 232 #define UARTWATER_TXWATER_OFF 0 233 #define UARTWATER_RXWATER_OFF 16 234 235 #define UART_GLOBAL_RST 0x2 236 #define GLOBAL_RST_MIN_US 20 237 #define GLOBAL_RST_MAX_US 40 238 239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 240 #define DMA_RX_TIMEOUT (10) 241 #define UART_AUTOSUSPEND_TIMEOUT 3000 242 243 #define DRIVER_NAME "fsl-lpuart" 244 #define DEV_NAME "ttyLP" 245 #define UART_NR 8 246 247 /* IMX lpuart has four extra unused regs located at the beginning */ 248 #define IMX_REG_OFF 0x10 249 250 enum lpuart_type { 251 VF610_LPUART, 252 LS1021A_LPUART, 253 LS1028A_LPUART, 254 IMX7ULP_LPUART, 255 IMX8ULP_LPUART, 256 IMX8QXP_LPUART, 257 IMXRT1050_LPUART, 258 }; 259 260 struct lpuart_port { 261 struct uart_port port; 262 enum lpuart_type devtype; 263 struct clk *ipg_clk; 264 struct clk *baud_clk; 265 unsigned int txfifo_size; 266 unsigned int rxfifo_size; 267 268 u8 rx_watermark; 269 bool lpuart_dma_tx_use; 270 bool lpuart_dma_rx_use; 271 struct dma_chan *dma_tx_chan; 272 struct dma_chan *dma_rx_chan; 273 struct dma_async_tx_descriptor *dma_tx_desc; 274 struct dma_async_tx_descriptor *dma_rx_desc; 275 dma_cookie_t dma_tx_cookie; 276 dma_cookie_t dma_rx_cookie; 277 unsigned int dma_tx_bytes; 278 unsigned int dma_rx_bytes; 279 bool dma_tx_in_progress; 280 unsigned int dma_rx_timeout; 281 struct timer_list lpuart_timer; 282 struct scatterlist rx_sgl, tx_sgl[2]; 283 struct circ_buf rx_ring; 284 int rx_dma_rng_buf_len; 285 unsigned int dma_tx_nents; 286 wait_queue_head_t dma_wait; 287 bool is_cs7; /* Set to true when character size is 7 */ 288 /* and the parity is enabled */ 289 }; 290 291 struct lpuart_soc_data { 292 enum lpuart_type devtype; 293 char iotype; 294 u8 reg_off; 295 u8 rx_watermark; 296 }; 297 298 static const struct lpuart_soc_data vf_data = { 299 .devtype = VF610_LPUART, 300 .iotype = UPIO_MEM, 301 .rx_watermark = 1, 302 }; 303 304 static const struct lpuart_soc_data ls1021a_data = { 305 .devtype = LS1021A_LPUART, 306 .iotype = UPIO_MEM32BE, 307 .rx_watermark = 1, 308 }; 309 310 static const struct lpuart_soc_data ls1028a_data = { 311 .devtype = LS1028A_LPUART, 312 .iotype = UPIO_MEM32, 313 .rx_watermark = 1, 314 }; 315 316 static struct lpuart_soc_data imx7ulp_data = { 317 .devtype = IMX7ULP_LPUART, 318 .iotype = UPIO_MEM32, 319 .reg_off = IMX_REG_OFF, 320 .rx_watermark = 1, 321 }; 322 323 static struct lpuart_soc_data imx8ulp_data = { 324 .devtype = IMX8ULP_LPUART, 325 .iotype = UPIO_MEM32, 326 .reg_off = IMX_REG_OFF, 327 .rx_watermark = 3, 328 }; 329 330 static struct lpuart_soc_data imx8qxp_data = { 331 .devtype = IMX8QXP_LPUART, 332 .iotype = UPIO_MEM32, 333 .reg_off = IMX_REG_OFF, 334 .rx_watermark = 31, 335 }; 336 static struct lpuart_soc_data imxrt1050_data = { 337 .devtype = IMXRT1050_LPUART, 338 .iotype = UPIO_MEM32, 339 .reg_off = IMX_REG_OFF, 340 .rx_watermark = 1, 341 }; 342 343 static const struct of_device_id lpuart_dt_ids[] = { 344 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 345 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 346 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 347 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 348 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, 349 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 350 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 351 { /* sentinel */ } 352 }; 353 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 354 355 /* Forward declare this for the dma callbacks*/ 356 static void lpuart_dma_tx_complete(void *arg); 357 358 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 359 { 360 return (sport->devtype == LS1021A_LPUART || 361 sport->devtype == LS1028A_LPUART); 362 } 363 364 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 365 { 366 return sport->devtype == IMX7ULP_LPUART; 367 } 368 369 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) 370 { 371 return sport->devtype == IMX8ULP_LPUART; 372 } 373 374 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 375 { 376 return sport->devtype == IMX8QXP_LPUART; 377 } 378 379 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 380 { 381 switch (port->iotype) { 382 case UPIO_MEM32: 383 return readl(port->membase + off); 384 case UPIO_MEM32BE: 385 return ioread32be(port->membase + off); 386 default: 387 return 0; 388 } 389 } 390 391 static inline void lpuart32_write(struct uart_port *port, u32 val, 392 u32 off) 393 { 394 switch (port->iotype) { 395 case UPIO_MEM32: 396 writel(val, port->membase + off); 397 break; 398 case UPIO_MEM32BE: 399 iowrite32be(val, port->membase + off); 400 break; 401 } 402 } 403 404 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 405 { 406 int ret = 0; 407 408 if (is_en) { 409 ret = clk_prepare_enable(sport->ipg_clk); 410 if (ret) 411 return ret; 412 413 ret = clk_prepare_enable(sport->baud_clk); 414 if (ret) { 415 clk_disable_unprepare(sport->ipg_clk); 416 return ret; 417 } 418 } else { 419 clk_disable_unprepare(sport->baud_clk); 420 clk_disable_unprepare(sport->ipg_clk); 421 } 422 423 return 0; 424 } 425 426 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 427 { 428 if (is_imx8qxp_lpuart(sport)) 429 return clk_get_rate(sport->baud_clk); 430 431 return clk_get_rate(sport->ipg_clk); 432 } 433 434 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 435 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 436 437 static void lpuart_stop_tx(struct uart_port *port) 438 { 439 unsigned char temp; 440 441 temp = readb(port->membase + UARTCR2); 442 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 443 writeb(temp, port->membase + UARTCR2); 444 } 445 446 static void lpuart32_stop_tx(struct uart_port *port) 447 { 448 unsigned long temp; 449 450 temp = lpuart32_read(port, UARTCTRL); 451 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 452 lpuart32_write(port, temp, UARTCTRL); 453 } 454 455 static void lpuart_stop_rx(struct uart_port *port) 456 { 457 unsigned char temp; 458 459 temp = readb(port->membase + UARTCR2); 460 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 461 } 462 463 static void lpuart32_stop_rx(struct uart_port *port) 464 { 465 unsigned long temp; 466 467 temp = lpuart32_read(port, UARTCTRL); 468 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 469 } 470 471 static void lpuart_dma_tx(struct lpuart_port *sport) 472 { 473 struct circ_buf *xmit = &sport->port.state->xmit; 474 struct scatterlist *sgl = sport->tx_sgl; 475 struct device *dev = sport->port.dev; 476 struct dma_chan *chan = sport->dma_tx_chan; 477 int ret; 478 479 if (sport->dma_tx_in_progress) 480 return; 481 482 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 483 484 if (xmit->tail < xmit->head || xmit->head == 0) { 485 sport->dma_tx_nents = 1; 486 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 487 } else { 488 sport->dma_tx_nents = 2; 489 sg_init_table(sgl, 2); 490 sg_set_buf(sgl, xmit->buf + xmit->tail, 491 UART_XMIT_SIZE - xmit->tail); 492 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 493 } 494 495 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 496 DMA_TO_DEVICE); 497 if (!ret) { 498 dev_err(dev, "DMA mapping error for TX.\n"); 499 return; 500 } 501 502 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 503 ret, DMA_MEM_TO_DEV, 504 DMA_PREP_INTERRUPT); 505 if (!sport->dma_tx_desc) { 506 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 507 DMA_TO_DEVICE); 508 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 509 return; 510 } 511 512 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 513 sport->dma_tx_desc->callback_param = sport; 514 sport->dma_tx_in_progress = true; 515 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 516 dma_async_issue_pending(chan); 517 } 518 519 static bool lpuart_stopped_or_empty(struct uart_port *port) 520 { 521 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 522 } 523 524 static void lpuart_dma_tx_complete(void *arg) 525 { 526 struct lpuart_port *sport = arg; 527 struct scatterlist *sgl = &sport->tx_sgl[0]; 528 struct circ_buf *xmit = &sport->port.state->xmit; 529 struct dma_chan *chan = sport->dma_tx_chan; 530 unsigned long flags; 531 532 spin_lock_irqsave(&sport->port.lock, flags); 533 if (!sport->dma_tx_in_progress) { 534 spin_unlock_irqrestore(&sport->port.lock, flags); 535 return; 536 } 537 538 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 539 DMA_TO_DEVICE); 540 541 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 542 sport->dma_tx_in_progress = false; 543 spin_unlock_irqrestore(&sport->port.lock, flags); 544 545 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 546 uart_write_wakeup(&sport->port); 547 548 if (waitqueue_active(&sport->dma_wait)) { 549 wake_up(&sport->dma_wait); 550 return; 551 } 552 553 spin_lock_irqsave(&sport->port.lock, flags); 554 555 if (!lpuart_stopped_or_empty(&sport->port)) 556 lpuart_dma_tx(sport); 557 558 spin_unlock_irqrestore(&sport->port.lock, flags); 559 } 560 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 562 { 563 switch (sport->port.iotype) { 564 case UPIO_MEM32: 565 return sport->port.mapbase + UARTDATA; 566 case UPIO_MEM32BE: 567 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 568 } 569 return sport->port.mapbase + UARTDR; 570 } 571 572 static int lpuart_dma_tx_request(struct uart_port *port) 573 { 574 struct lpuart_port *sport = container_of(port, 575 struct lpuart_port, port); 576 struct dma_slave_config dma_tx_sconfig = {}; 577 int ret; 578 579 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 580 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 581 dma_tx_sconfig.dst_maxburst = 1; 582 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 583 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 584 585 if (ret) { 586 dev_err(sport->port.dev, 587 "DMA slave config failed, err = %d\n", ret); 588 return ret; 589 } 590 591 return 0; 592 } 593 594 static bool lpuart_is_32(struct lpuart_port *sport) 595 { 596 return sport->port.iotype == UPIO_MEM32 || 597 sport->port.iotype == UPIO_MEM32BE; 598 } 599 600 static void lpuart_flush_buffer(struct uart_port *port) 601 { 602 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 603 struct dma_chan *chan = sport->dma_tx_chan; 604 u32 val; 605 606 if (sport->lpuart_dma_tx_use) { 607 if (sport->dma_tx_in_progress) { 608 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 609 sport->dma_tx_nents, DMA_TO_DEVICE); 610 sport->dma_tx_in_progress = false; 611 } 612 dmaengine_terminate_async(chan); 613 } 614 615 if (lpuart_is_32(sport)) { 616 val = lpuart32_read(&sport->port, UARTFIFO); 617 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 618 lpuart32_write(&sport->port, val, UARTFIFO); 619 } else { 620 val = readb(sport->port.membase + UARTCFIFO); 621 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 622 writeb(val, sport->port.membase + UARTCFIFO); 623 } 624 } 625 626 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 627 u8 bit) 628 { 629 while (!(readb(port->membase + offset) & bit)) 630 cpu_relax(); 631 } 632 633 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 634 u32 bit) 635 { 636 while (!(lpuart32_read(port, offset) & bit)) 637 cpu_relax(); 638 } 639 640 #if defined(CONFIG_CONSOLE_POLL) 641 642 static int lpuart_poll_init(struct uart_port *port) 643 { 644 struct lpuart_port *sport = container_of(port, 645 struct lpuart_port, port); 646 unsigned long flags; 647 unsigned char temp; 648 649 sport->port.fifosize = 0; 650 651 spin_lock_irqsave(&sport->port.lock, flags); 652 /* Disable Rx & Tx */ 653 writeb(0, sport->port.membase + UARTCR2); 654 655 temp = readb(sport->port.membase + UARTPFIFO); 656 /* Enable Rx and Tx FIFO */ 657 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 658 sport->port.membase + UARTPFIFO); 659 660 /* flush Tx and Rx FIFO */ 661 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 662 sport->port.membase + UARTCFIFO); 663 664 /* explicitly clear RDRF */ 665 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 666 readb(sport->port.membase + UARTDR); 667 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 668 } 669 670 writeb(0, sport->port.membase + UARTTWFIFO); 671 writeb(1, sport->port.membase + UARTRWFIFO); 672 673 /* Enable Rx and Tx */ 674 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 675 spin_unlock_irqrestore(&sport->port.lock, flags); 676 677 return 0; 678 } 679 680 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 681 { 682 /* drain */ 683 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 684 writeb(c, port->membase + UARTDR); 685 } 686 687 static int lpuart_poll_get_char(struct uart_port *port) 688 { 689 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 690 return NO_POLL_CHAR; 691 692 return readb(port->membase + UARTDR); 693 } 694 695 static int lpuart32_poll_init(struct uart_port *port) 696 { 697 unsigned long flags; 698 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 699 u32 temp; 700 701 sport->port.fifosize = 0; 702 703 spin_lock_irqsave(&sport->port.lock, flags); 704 705 /* Disable Rx & Tx */ 706 lpuart32_write(&sport->port, 0, UARTCTRL); 707 708 temp = lpuart32_read(&sport->port, UARTFIFO); 709 710 /* Enable Rx and Tx FIFO */ 711 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 712 713 /* flush Tx and Rx FIFO */ 714 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 715 716 /* explicitly clear RDRF */ 717 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 718 lpuart32_read(&sport->port, UARTDATA); 719 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 720 } 721 722 /* Enable Rx and Tx */ 723 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 724 spin_unlock_irqrestore(&sport->port.lock, flags); 725 726 return 0; 727 } 728 729 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 730 { 731 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 732 lpuart32_write(port, c, UARTDATA); 733 } 734 735 static int lpuart32_poll_get_char(struct uart_port *port) 736 { 737 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 738 return NO_POLL_CHAR; 739 740 return lpuart32_read(port, UARTDATA); 741 } 742 #endif 743 744 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 745 { 746 struct uart_port *port = &sport->port; 747 u8 ch; 748 749 uart_port_tx(port, ch, 750 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, 751 writeb(ch, port->membase + UARTDR)); 752 } 753 754 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 755 { 756 struct circ_buf *xmit = &sport->port.state->xmit; 757 unsigned long txcnt; 758 759 if (sport->port.x_char) { 760 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 761 sport->port.icount.tx++; 762 sport->port.x_char = 0; 763 return; 764 } 765 766 if (lpuart_stopped_or_empty(&sport->port)) { 767 lpuart32_stop_tx(&sport->port); 768 return; 769 } 770 771 txcnt = lpuart32_read(&sport->port, UARTWATER); 772 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 773 txcnt &= UARTWATER_COUNT_MASK; 774 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 775 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 776 uart_xmit_advance(&sport->port, 1); 777 txcnt = lpuart32_read(&sport->port, UARTWATER); 778 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 779 txcnt &= UARTWATER_COUNT_MASK; 780 } 781 782 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 783 uart_write_wakeup(&sport->port); 784 785 if (uart_circ_empty(xmit)) 786 lpuart32_stop_tx(&sport->port); 787 } 788 789 static void lpuart_start_tx(struct uart_port *port) 790 { 791 struct lpuart_port *sport = container_of(port, 792 struct lpuart_port, port); 793 unsigned char temp; 794 795 temp = readb(port->membase + UARTCR2); 796 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 797 798 if (sport->lpuart_dma_tx_use) { 799 if (!lpuart_stopped_or_empty(port)) 800 lpuart_dma_tx(sport); 801 } else { 802 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 803 lpuart_transmit_buffer(sport); 804 } 805 } 806 807 static void lpuart32_start_tx(struct uart_port *port) 808 { 809 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 810 unsigned long temp; 811 812 if (sport->lpuart_dma_tx_use) { 813 if (!lpuart_stopped_or_empty(port)) 814 lpuart_dma_tx(sport); 815 } else { 816 temp = lpuart32_read(port, UARTCTRL); 817 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 818 819 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 820 lpuart32_transmit_buffer(sport); 821 } 822 } 823 824 static void 825 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 826 { 827 switch (state) { 828 case UART_PM_STATE_OFF: 829 pm_runtime_mark_last_busy(port->dev); 830 pm_runtime_put_autosuspend(port->dev); 831 break; 832 default: 833 pm_runtime_get_sync(port->dev); 834 break; 835 } 836 } 837 838 /* return TIOCSER_TEMT when transmitter is not busy */ 839 static unsigned int lpuart_tx_empty(struct uart_port *port) 840 { 841 struct lpuart_port *sport = container_of(port, 842 struct lpuart_port, port); 843 unsigned char sr1 = readb(port->membase + UARTSR1); 844 unsigned char sfifo = readb(port->membase + UARTSFIFO); 845 846 if (sport->dma_tx_in_progress) 847 return 0; 848 849 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 850 return TIOCSER_TEMT; 851 852 return 0; 853 } 854 855 static unsigned int lpuart32_tx_empty(struct uart_port *port) 856 { 857 struct lpuart_port *sport = container_of(port, 858 struct lpuart_port, port); 859 unsigned long stat = lpuart32_read(port, UARTSTAT); 860 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 861 862 if (sport->dma_tx_in_progress) 863 return 0; 864 865 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 866 return TIOCSER_TEMT; 867 868 return 0; 869 } 870 871 static void lpuart_txint(struct lpuart_port *sport) 872 { 873 spin_lock(&sport->port.lock); 874 lpuart_transmit_buffer(sport); 875 spin_unlock(&sport->port.lock); 876 } 877 878 static void lpuart_rxint(struct lpuart_port *sport) 879 { 880 unsigned int flg, ignored = 0, overrun = 0; 881 struct tty_port *port = &sport->port.state->port; 882 unsigned char rx, sr; 883 884 spin_lock(&sport->port.lock); 885 886 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 887 flg = TTY_NORMAL; 888 sport->port.icount.rx++; 889 /* 890 * to clear the FE, OR, NF, FE, PE flags, 891 * read SR1 then read DR 892 */ 893 sr = readb(sport->port.membase + UARTSR1); 894 rx = readb(sport->port.membase + UARTDR); 895 896 if (uart_prepare_sysrq_char(&sport->port, rx)) 897 continue; 898 899 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 900 if (sr & UARTSR1_PE) 901 sport->port.icount.parity++; 902 else if (sr & UARTSR1_FE) 903 sport->port.icount.frame++; 904 905 if (sr & UARTSR1_OR) 906 overrun++; 907 908 if (sr & sport->port.ignore_status_mask) { 909 if (++ignored > 100) 910 goto out; 911 continue; 912 } 913 914 sr &= sport->port.read_status_mask; 915 916 if (sr & UARTSR1_PE) 917 flg = TTY_PARITY; 918 else if (sr & UARTSR1_FE) 919 flg = TTY_FRAME; 920 921 if (sr & UARTSR1_OR) 922 flg = TTY_OVERRUN; 923 924 sport->port.sysrq = 0; 925 } 926 927 if (tty_insert_flip_char(port, rx, flg) == 0) 928 sport->port.icount.buf_overrun++; 929 } 930 931 out: 932 if (overrun) { 933 sport->port.icount.overrun += overrun; 934 935 /* 936 * Overruns cause FIFO pointers to become missaligned. 937 * Flushing the receive FIFO reinitializes the pointers. 938 */ 939 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 940 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 941 } 942 943 uart_unlock_and_check_sysrq(&sport->port); 944 945 tty_flip_buffer_push(port); 946 } 947 948 static void lpuart32_txint(struct lpuart_port *sport) 949 { 950 spin_lock(&sport->port.lock); 951 lpuart32_transmit_buffer(sport); 952 spin_unlock(&sport->port.lock); 953 } 954 955 static void lpuart32_rxint(struct lpuart_port *sport) 956 { 957 unsigned int flg, ignored = 0; 958 struct tty_port *port = &sport->port.state->port; 959 unsigned long rx, sr; 960 bool is_break; 961 962 spin_lock(&sport->port.lock); 963 964 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 965 flg = TTY_NORMAL; 966 sport->port.icount.rx++; 967 /* 968 * to clear the FE, OR, NF, FE, PE flags, 969 * read STAT then read DATA reg 970 */ 971 sr = lpuart32_read(&sport->port, UARTSTAT); 972 rx = lpuart32_read(&sport->port, UARTDATA); 973 rx &= UARTDATA_MASK; 974 975 /* 976 * The LPUART can't distinguish between a break and a framing error, 977 * thus we assume it is a break if the received data is zero. 978 */ 979 is_break = (sr & UARTSTAT_FE) && !rx; 980 981 if (is_break && uart_handle_break(&sport->port)) 982 continue; 983 984 if (uart_prepare_sysrq_char(&sport->port, rx)) 985 continue; 986 987 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 988 if (sr & UARTSTAT_PE) { 989 sport->port.icount.parity++; 990 } else if (sr & UARTSTAT_FE) { 991 if (is_break) 992 sport->port.icount.brk++; 993 else 994 sport->port.icount.frame++; 995 } 996 997 if (sr & UARTSTAT_OR) 998 sport->port.icount.overrun++; 999 1000 if (sr & sport->port.ignore_status_mask) { 1001 if (++ignored > 100) 1002 goto out; 1003 continue; 1004 } 1005 1006 sr &= sport->port.read_status_mask; 1007 1008 if (sr & UARTSTAT_PE) { 1009 flg = TTY_PARITY; 1010 } else if (sr & UARTSTAT_FE) { 1011 if (is_break) 1012 flg = TTY_BREAK; 1013 else 1014 flg = TTY_FRAME; 1015 } 1016 1017 if (sr & UARTSTAT_OR) 1018 flg = TTY_OVERRUN; 1019 } 1020 1021 if (sport->is_cs7) 1022 rx &= 0x7F; 1023 1024 if (tty_insert_flip_char(port, rx, flg) == 0) 1025 sport->port.icount.buf_overrun++; 1026 } 1027 1028 out: 1029 uart_unlock_and_check_sysrq(&sport->port); 1030 1031 tty_flip_buffer_push(port); 1032 } 1033 1034 static irqreturn_t lpuart_int(int irq, void *dev_id) 1035 { 1036 struct lpuart_port *sport = dev_id; 1037 unsigned char sts; 1038 1039 sts = readb(sport->port.membase + UARTSR1); 1040 1041 /* SysRq, using dma, check for linebreak by framing err. */ 1042 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1043 readb(sport->port.membase + UARTDR); 1044 uart_handle_break(&sport->port); 1045 /* linebreak produces some garbage, removing it */ 1046 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1047 return IRQ_HANDLED; 1048 } 1049 1050 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1051 lpuart_rxint(sport); 1052 1053 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1054 lpuart_txint(sport); 1055 1056 return IRQ_HANDLED; 1057 } 1058 1059 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1060 { 1061 struct lpuart_port *sport = dev_id; 1062 unsigned long sts, rxcount; 1063 1064 sts = lpuart32_read(&sport->port, UARTSTAT); 1065 rxcount = lpuart32_read(&sport->port, UARTWATER); 1066 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1067 1068 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1069 lpuart32_rxint(sport); 1070 1071 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1072 lpuart32_txint(sport); 1073 1074 lpuart32_write(&sport->port, sts, UARTSTAT); 1075 return IRQ_HANDLED; 1076 } 1077 1078 1079 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1080 unsigned char *p, int count) 1081 { 1082 while (count--) { 1083 if (*p && uart_handle_sysrq_char(port, *p)) 1084 return; 1085 p++; 1086 } 1087 } 1088 1089 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1090 { 1091 struct circ_buf *ring = &sport->rx_ring; 1092 int count; 1093 1094 if (ring->head < ring->tail) { 1095 count = sport->rx_sgl.length - ring->tail; 1096 lpuart_handle_sysrq_chars(&sport->port, 1097 ring->buf + ring->tail, count); 1098 ring->tail = 0; 1099 } 1100 1101 if (ring->head > ring->tail) { 1102 count = ring->head - ring->tail; 1103 lpuart_handle_sysrq_chars(&sport->port, 1104 ring->buf + ring->tail, count); 1105 ring->tail = ring->head; 1106 } 1107 } 1108 1109 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1110 unsigned char *chars, size_t size, bool is_cs7) 1111 { 1112 int i; 1113 1114 if (is_cs7) 1115 for (i = 0; i < size; i++) 1116 chars[i] &= 0x7F; 1117 return tty_insert_flip_string(port, chars, size); 1118 } 1119 1120 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1121 { 1122 struct tty_port *port = &sport->port.state->port; 1123 struct dma_tx_state state; 1124 enum dma_status dmastat; 1125 struct dma_chan *chan = sport->dma_rx_chan; 1126 struct circ_buf *ring = &sport->rx_ring; 1127 unsigned long flags; 1128 int count, copied; 1129 1130 if (lpuart_is_32(sport)) { 1131 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1132 1133 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1134 /* Read DR to clear the error flags */ 1135 lpuart32_read(&sport->port, UARTDATA); 1136 1137 if (sr & UARTSTAT_PE) 1138 sport->port.icount.parity++; 1139 else if (sr & UARTSTAT_FE) 1140 sport->port.icount.frame++; 1141 } 1142 } else { 1143 unsigned char sr = readb(sport->port.membase + UARTSR1); 1144 1145 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1146 unsigned char cr2; 1147 1148 /* Disable receiver during this operation... */ 1149 cr2 = readb(sport->port.membase + UARTCR2); 1150 cr2 &= ~UARTCR2_RE; 1151 writeb(cr2, sport->port.membase + UARTCR2); 1152 1153 /* Read DR to clear the error flags */ 1154 readb(sport->port.membase + UARTDR); 1155 1156 if (sr & UARTSR1_PE) 1157 sport->port.icount.parity++; 1158 else if (sr & UARTSR1_FE) 1159 sport->port.icount.frame++; 1160 /* 1161 * At this point parity/framing error is 1162 * cleared However, since the DMA already read 1163 * the data register and we had to read it 1164 * again after reading the status register to 1165 * properly clear the flags, the FIFO actually 1166 * underflowed... This requires a clearing of 1167 * the FIFO... 1168 */ 1169 if (readb(sport->port.membase + UARTSFIFO) & 1170 UARTSFIFO_RXUF) { 1171 writeb(UARTSFIFO_RXUF, 1172 sport->port.membase + UARTSFIFO); 1173 writeb(UARTCFIFO_RXFLUSH, 1174 sport->port.membase + UARTCFIFO); 1175 } 1176 1177 cr2 |= UARTCR2_RE; 1178 writeb(cr2, sport->port.membase + UARTCR2); 1179 } 1180 } 1181 1182 async_tx_ack(sport->dma_rx_desc); 1183 1184 spin_lock_irqsave(&sport->port.lock, flags); 1185 1186 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1187 if (dmastat == DMA_ERROR) { 1188 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1189 spin_unlock_irqrestore(&sport->port.lock, flags); 1190 return; 1191 } 1192 1193 /* CPU claims ownership of RX DMA buffer */ 1194 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1195 DMA_FROM_DEVICE); 1196 1197 /* 1198 * ring->head points to the end of data already written by the DMA. 1199 * ring->tail points to the beginning of data to be read by the 1200 * framework. 1201 * The current transfer size should not be larger than the dma buffer 1202 * length. 1203 */ 1204 ring->head = sport->rx_sgl.length - state.residue; 1205 BUG_ON(ring->head > sport->rx_sgl.length); 1206 1207 /* 1208 * Silent handling of keys pressed in the sysrq timeframe 1209 */ 1210 if (sport->port.sysrq) { 1211 lpuart_handle_sysrq(sport); 1212 goto exit; 1213 } 1214 1215 /* 1216 * At this point ring->head may point to the first byte right after the 1217 * last byte of the dma buffer: 1218 * 0 <= ring->head <= sport->rx_sgl.length 1219 * 1220 * However ring->tail must always points inside the dma buffer: 1221 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1222 * 1223 * Since we use a ring buffer, we have to handle the case 1224 * where head is lower than tail. In such a case, we first read from 1225 * tail to the end of the buffer then reset tail. 1226 */ 1227 if (ring->head < ring->tail) { 1228 count = sport->rx_sgl.length - ring->tail; 1229 1230 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1231 count, sport->is_cs7); 1232 if (copied != count) 1233 sport->port.icount.buf_overrun++; 1234 ring->tail = 0; 1235 sport->port.icount.rx += copied; 1236 } 1237 1238 /* Finally we read data from tail to head */ 1239 if (ring->tail < ring->head) { 1240 count = ring->head - ring->tail; 1241 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1242 count, sport->is_cs7); 1243 if (copied != count) 1244 sport->port.icount.buf_overrun++; 1245 /* Wrap ring->head if needed */ 1246 if (ring->head >= sport->rx_sgl.length) 1247 ring->head = 0; 1248 ring->tail = ring->head; 1249 sport->port.icount.rx += copied; 1250 } 1251 1252 exit: 1253 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1254 DMA_FROM_DEVICE); 1255 1256 spin_unlock_irqrestore(&sport->port.lock, flags); 1257 1258 tty_flip_buffer_push(port); 1259 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1260 } 1261 1262 static void lpuart_dma_rx_complete(void *arg) 1263 { 1264 struct lpuart_port *sport = arg; 1265 1266 lpuart_copy_rx_to_tty(sport); 1267 } 1268 1269 static void lpuart_timer_func(struct timer_list *t) 1270 { 1271 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1272 1273 lpuart_copy_rx_to_tty(sport); 1274 } 1275 1276 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1277 { 1278 struct dma_slave_config dma_rx_sconfig = {}; 1279 struct circ_buf *ring = &sport->rx_ring; 1280 int ret, nent; 1281 struct tty_port *port = &sport->port.state->port; 1282 struct tty_struct *tty = port->tty; 1283 struct ktermios *termios = &tty->termios; 1284 struct dma_chan *chan = sport->dma_rx_chan; 1285 unsigned int bits = tty_get_frame_size(termios->c_cflag); 1286 unsigned int baud = tty_get_baud_rate(tty); 1287 1288 /* 1289 * Calculate length of one DMA buffer size to keep latency below 1290 * 10ms at any baud rate. 1291 */ 1292 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1293 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1294 if (sport->rx_dma_rng_buf_len < 16) 1295 sport->rx_dma_rng_buf_len = 16; 1296 1297 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1298 if (!ring->buf) 1299 return -ENOMEM; 1300 1301 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1302 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1303 DMA_FROM_DEVICE); 1304 1305 if (!nent) { 1306 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1307 return -EINVAL; 1308 } 1309 1310 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1311 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1312 dma_rx_sconfig.src_maxburst = 1; 1313 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1314 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1315 1316 if (ret < 0) { 1317 dev_err(sport->port.dev, 1318 "DMA Rx slave config failed, err = %d\n", ret); 1319 return ret; 1320 } 1321 1322 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1323 sg_dma_address(&sport->rx_sgl), 1324 sport->rx_sgl.length, 1325 sport->rx_sgl.length / 2, 1326 DMA_DEV_TO_MEM, 1327 DMA_PREP_INTERRUPT); 1328 if (!sport->dma_rx_desc) { 1329 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1330 return -EFAULT; 1331 } 1332 1333 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1334 sport->dma_rx_desc->callback_param = sport; 1335 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1336 dma_async_issue_pending(chan); 1337 1338 if (lpuart_is_32(sport)) { 1339 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1340 1341 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1342 } else { 1343 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1344 sport->port.membase + UARTCR5); 1345 } 1346 1347 return 0; 1348 } 1349 1350 static void lpuart_dma_rx_free(struct uart_port *port) 1351 { 1352 struct lpuart_port *sport = container_of(port, 1353 struct lpuart_port, port); 1354 struct dma_chan *chan = sport->dma_rx_chan; 1355 1356 dmaengine_terminate_sync(chan); 1357 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1358 kfree(sport->rx_ring.buf); 1359 sport->rx_ring.tail = 0; 1360 sport->rx_ring.head = 0; 1361 sport->dma_rx_desc = NULL; 1362 sport->dma_rx_cookie = -EINVAL; 1363 } 1364 1365 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1366 struct serial_rs485 *rs485) 1367 { 1368 struct lpuart_port *sport = container_of(port, 1369 struct lpuart_port, port); 1370 1371 u8 modem = readb(sport->port.membase + UARTMODEM) & 1372 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1373 writeb(modem, sport->port.membase + UARTMODEM); 1374 1375 if (rs485->flags & SER_RS485_ENABLED) { 1376 /* Enable auto RS-485 RTS mode */ 1377 modem |= UARTMODEM_TXRTSE; 1378 1379 /* 1380 * The hardware defaults to RTS logic HIGH while transfer. 1381 * Switch polarity in case RTS shall be logic HIGH 1382 * after transfer. 1383 * Note: UART is assumed to be active high. 1384 */ 1385 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1386 modem |= UARTMODEM_TXRTSPOL; 1387 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1388 modem &= ~UARTMODEM_TXRTSPOL; 1389 } 1390 1391 writeb(modem, sport->port.membase + UARTMODEM); 1392 return 0; 1393 } 1394 1395 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1396 struct serial_rs485 *rs485) 1397 { 1398 struct lpuart_port *sport = container_of(port, 1399 struct lpuart_port, port); 1400 1401 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1402 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1403 lpuart32_write(&sport->port, modem, UARTMODIR); 1404 1405 if (rs485->flags & SER_RS485_ENABLED) { 1406 /* Enable auto RS-485 RTS mode */ 1407 modem |= UARTMODEM_TXRTSE; 1408 1409 /* 1410 * The hardware defaults to RTS logic HIGH while transfer. 1411 * Switch polarity in case RTS shall be logic HIGH 1412 * after transfer. 1413 * Note: UART is assumed to be active high. 1414 */ 1415 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1416 modem |= UARTMODEM_TXRTSPOL; 1417 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1418 modem &= ~UARTMODEM_TXRTSPOL; 1419 } 1420 1421 lpuart32_write(&sport->port, modem, UARTMODIR); 1422 return 0; 1423 } 1424 1425 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1426 { 1427 unsigned int mctrl = 0; 1428 u8 reg; 1429 1430 reg = readb(port->membase + UARTCR1); 1431 if (reg & UARTCR1_LOOPS) 1432 mctrl |= TIOCM_LOOP; 1433 1434 return mctrl; 1435 } 1436 1437 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1438 { 1439 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1440 u32 reg; 1441 1442 reg = lpuart32_read(port, UARTCTRL); 1443 if (reg & UARTCTRL_LOOPS) 1444 mctrl |= TIOCM_LOOP; 1445 1446 return mctrl; 1447 } 1448 1449 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1450 { 1451 u8 reg; 1452 1453 reg = readb(port->membase + UARTCR1); 1454 1455 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1456 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1457 if (mctrl & TIOCM_LOOP) 1458 reg |= UARTCR1_LOOPS; 1459 1460 writeb(reg, port->membase + UARTCR1); 1461 } 1462 1463 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1464 { 1465 u32 reg; 1466 1467 reg = lpuart32_read(port, UARTCTRL); 1468 1469 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1470 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1471 if (mctrl & TIOCM_LOOP) 1472 reg |= UARTCTRL_LOOPS; 1473 1474 lpuart32_write(port, reg, UARTCTRL); 1475 } 1476 1477 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1478 { 1479 unsigned char temp; 1480 1481 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1482 1483 if (break_state != 0) 1484 temp |= UARTCR2_SBK; 1485 1486 writeb(temp, port->membase + UARTCR2); 1487 } 1488 1489 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1490 { 1491 unsigned long temp, modem; 1492 struct tty_struct *tty; 1493 unsigned int cflag = 0; 1494 1495 tty = tty_port_tty_get(&port->state->port); 1496 if (tty) { 1497 cflag = tty->termios.c_cflag; 1498 tty_kref_put(tty); 1499 } 1500 1501 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1502 modem = lpuart32_read(port, UARTMODIR); 1503 1504 if (break_state != 0) { 1505 temp |= UARTCTRL_SBK; 1506 /* 1507 * LPUART CTS has higher priority than SBK, need to disable CTS before 1508 * asserting SBK to avoid any interference if flow control is enabled. 1509 */ 1510 if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE) 1511 lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); 1512 } else { 1513 /* Re-enable the CTS when break off. */ 1514 if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE)) 1515 lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR); 1516 } 1517 1518 lpuart32_write(port, temp, UARTCTRL); 1519 } 1520 1521 static void lpuart_setup_watermark(struct lpuart_port *sport) 1522 { 1523 unsigned char val, cr2; 1524 unsigned char cr2_saved; 1525 1526 cr2 = readb(sport->port.membase + UARTCR2); 1527 cr2_saved = cr2; 1528 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1529 UARTCR2_RIE | UARTCR2_RE); 1530 writeb(cr2, sport->port.membase + UARTCR2); 1531 1532 val = readb(sport->port.membase + UARTPFIFO); 1533 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1534 sport->port.membase + UARTPFIFO); 1535 1536 /* flush Tx and Rx FIFO */ 1537 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1538 sport->port.membase + UARTCFIFO); 1539 1540 /* explicitly clear RDRF */ 1541 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1542 readb(sport->port.membase + UARTDR); 1543 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1544 } 1545 1546 if (uart_console(&sport->port)) 1547 sport->rx_watermark = 1; 1548 writeb(0, sport->port.membase + UARTTWFIFO); 1549 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); 1550 1551 /* Restore cr2 */ 1552 writeb(cr2_saved, sport->port.membase + UARTCR2); 1553 } 1554 1555 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1556 { 1557 unsigned char cr2; 1558 1559 lpuart_setup_watermark(sport); 1560 1561 cr2 = readb(sport->port.membase + UARTCR2); 1562 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1563 writeb(cr2, sport->port.membase + UARTCR2); 1564 } 1565 1566 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1567 { 1568 unsigned long val, ctrl; 1569 unsigned long ctrl_saved; 1570 1571 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1572 ctrl_saved = ctrl; 1573 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1574 UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); 1575 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1576 1577 /* enable FIFO mode */ 1578 val = lpuart32_read(&sport->port, UARTFIFO); 1579 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1580 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1581 val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); 1582 lpuart32_write(&sport->port, val, UARTFIFO); 1583 1584 /* set the watermark */ 1585 if (uart_console(&sport->port)) 1586 sport->rx_watermark = 1; 1587 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | 1588 (0x0 << UARTWATER_TXWATER_OFF); 1589 lpuart32_write(&sport->port, val, UARTWATER); 1590 1591 /* set RTS watermark */ 1592 if (!uart_console(&sport->port)) { 1593 val = lpuart32_read(&sport->port, UARTMODIR); 1594 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); 1595 lpuart32_write(&sport->port, val, UARTMODIR); 1596 } 1597 1598 /* Restore cr2 */ 1599 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1600 } 1601 1602 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1603 { 1604 u32 temp; 1605 1606 lpuart32_setup_watermark(sport); 1607 1608 temp = lpuart32_read(&sport->port, UARTCTRL); 1609 temp |= UARTCTRL_RE | UARTCTRL_TE; 1610 temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); 1611 lpuart32_write(&sport->port, temp, UARTCTRL); 1612 } 1613 1614 static void rx_dma_timer_init(struct lpuart_port *sport) 1615 { 1616 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1617 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1618 add_timer(&sport->lpuart_timer); 1619 } 1620 1621 static void lpuart_request_dma(struct lpuart_port *sport) 1622 { 1623 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1624 if (IS_ERR(sport->dma_tx_chan)) { 1625 dev_dbg_once(sport->port.dev, 1626 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1627 PTR_ERR(sport->dma_tx_chan)); 1628 sport->dma_tx_chan = NULL; 1629 } 1630 1631 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1632 if (IS_ERR(sport->dma_rx_chan)) { 1633 dev_dbg_once(sport->port.dev, 1634 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1635 PTR_ERR(sport->dma_rx_chan)); 1636 sport->dma_rx_chan = NULL; 1637 } 1638 } 1639 1640 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1641 { 1642 u32 uartbaud; 1643 int ret; 1644 1645 if (uart_console(&sport->port)) 1646 goto err; 1647 1648 if (!sport->dma_tx_chan) 1649 goto err; 1650 1651 ret = lpuart_dma_tx_request(&sport->port); 1652 if (ret) 1653 goto err; 1654 1655 init_waitqueue_head(&sport->dma_wait); 1656 sport->lpuart_dma_tx_use = true; 1657 if (lpuart_is_32(sport)) { 1658 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1659 lpuart32_write(&sport->port, 1660 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1661 } else { 1662 writeb(readb(sport->port.membase + UARTCR5) | 1663 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1664 } 1665 1666 return; 1667 1668 err: 1669 sport->lpuart_dma_tx_use = false; 1670 } 1671 1672 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1673 { 1674 int ret; 1675 unsigned char cr3; 1676 1677 if (uart_console(&sport->port)) 1678 goto err; 1679 1680 if (!sport->dma_rx_chan) 1681 goto err; 1682 1683 ret = lpuart_start_rx_dma(sport); 1684 if (ret) 1685 goto err; 1686 1687 /* set Rx DMA timeout */ 1688 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1689 if (!sport->dma_rx_timeout) 1690 sport->dma_rx_timeout = 1; 1691 1692 sport->lpuart_dma_rx_use = true; 1693 rx_dma_timer_init(sport); 1694 1695 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1696 cr3 = readb(sport->port.membase + UARTCR3); 1697 cr3 |= UARTCR3_FEIE; 1698 writeb(cr3, sport->port.membase + UARTCR3); 1699 } 1700 1701 return; 1702 1703 err: 1704 sport->lpuart_dma_rx_use = false; 1705 } 1706 1707 static void lpuart_hw_setup(struct lpuart_port *sport) 1708 { 1709 unsigned long flags; 1710 1711 spin_lock_irqsave(&sport->port.lock, flags); 1712 1713 lpuart_setup_watermark_enable(sport); 1714 1715 lpuart_rx_dma_startup(sport); 1716 lpuart_tx_dma_startup(sport); 1717 1718 spin_unlock_irqrestore(&sport->port.lock, flags); 1719 } 1720 1721 static int lpuart_startup(struct uart_port *port) 1722 { 1723 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1724 unsigned char temp; 1725 1726 /* determine FIFO size and enable FIFO mode */ 1727 temp = readb(sport->port.membase + UARTPFIFO); 1728 1729 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1730 UARTPFIFO_FIFOSIZE_MASK); 1731 sport->port.fifosize = sport->txfifo_size; 1732 1733 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1734 UARTPFIFO_FIFOSIZE_MASK); 1735 1736 lpuart_request_dma(sport); 1737 lpuart_hw_setup(sport); 1738 1739 return 0; 1740 } 1741 1742 static void lpuart32_hw_disable(struct lpuart_port *sport) 1743 { 1744 unsigned long temp; 1745 1746 temp = lpuart32_read(&sport->port, UARTCTRL); 1747 temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | 1748 UARTCTRL_TIE | UARTCTRL_TE); 1749 lpuart32_write(&sport->port, temp, UARTCTRL); 1750 } 1751 1752 static void lpuart32_configure(struct lpuart_port *sport) 1753 { 1754 unsigned long temp; 1755 1756 temp = lpuart32_read(&sport->port, UARTCTRL); 1757 if (!sport->lpuart_dma_rx_use) 1758 temp |= UARTCTRL_RIE | UARTCTRL_ILIE; 1759 if (!sport->lpuart_dma_tx_use) 1760 temp |= UARTCTRL_TIE; 1761 lpuart32_write(&sport->port, temp, UARTCTRL); 1762 } 1763 1764 static void lpuart32_hw_setup(struct lpuart_port *sport) 1765 { 1766 unsigned long flags; 1767 1768 spin_lock_irqsave(&sport->port.lock, flags); 1769 1770 lpuart32_hw_disable(sport); 1771 1772 lpuart_rx_dma_startup(sport); 1773 lpuart_tx_dma_startup(sport); 1774 1775 lpuart32_setup_watermark_enable(sport); 1776 lpuart32_configure(sport); 1777 1778 spin_unlock_irqrestore(&sport->port.lock, flags); 1779 } 1780 1781 static int lpuart32_startup(struct uart_port *port) 1782 { 1783 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1784 unsigned long temp; 1785 1786 /* determine FIFO size */ 1787 temp = lpuart32_read(&sport->port, UARTFIFO); 1788 1789 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1790 UARTFIFO_FIFOSIZE_MASK); 1791 sport->port.fifosize = sport->txfifo_size; 1792 1793 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1794 UARTFIFO_FIFOSIZE_MASK); 1795 1796 /* 1797 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1798 * Although they support the RX/TXSIZE fields, their encoding is 1799 * different. Eg the reference manual states 0b101 is 16 words. 1800 */ 1801 if (is_layerscape_lpuart(sport)) { 1802 sport->rxfifo_size = 16; 1803 sport->txfifo_size = 16; 1804 sport->port.fifosize = sport->txfifo_size; 1805 } 1806 1807 lpuart_request_dma(sport); 1808 lpuart32_hw_setup(sport); 1809 1810 return 0; 1811 } 1812 1813 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1814 { 1815 if (sport->lpuart_dma_rx_use) { 1816 del_timer_sync(&sport->lpuart_timer); 1817 lpuart_dma_rx_free(&sport->port); 1818 sport->lpuart_dma_rx_use = false; 1819 } 1820 1821 if (sport->lpuart_dma_tx_use) { 1822 if (wait_event_interruptible_timeout(sport->dma_wait, 1823 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1824 sport->dma_tx_in_progress = false; 1825 dmaengine_terminate_sync(sport->dma_tx_chan); 1826 } 1827 sport->lpuart_dma_tx_use = false; 1828 } 1829 1830 if (sport->dma_tx_chan) 1831 dma_release_channel(sport->dma_tx_chan); 1832 if (sport->dma_rx_chan) 1833 dma_release_channel(sport->dma_rx_chan); 1834 } 1835 1836 static void lpuart_shutdown(struct uart_port *port) 1837 { 1838 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1839 unsigned char temp; 1840 unsigned long flags; 1841 1842 spin_lock_irqsave(&port->lock, flags); 1843 1844 /* disable Rx/Tx and interrupts */ 1845 temp = readb(port->membase + UARTCR2); 1846 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1847 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1848 writeb(temp, port->membase + UARTCR2); 1849 1850 spin_unlock_irqrestore(&port->lock, flags); 1851 1852 lpuart_dma_shutdown(sport); 1853 } 1854 1855 static void lpuart32_shutdown(struct uart_port *port) 1856 { 1857 struct lpuart_port *sport = 1858 container_of(port, struct lpuart_port, port); 1859 unsigned long temp; 1860 unsigned long flags; 1861 1862 spin_lock_irqsave(&port->lock, flags); 1863 1864 /* clear status */ 1865 temp = lpuart32_read(&sport->port, UARTSTAT); 1866 lpuart32_write(&sport->port, temp, UARTSTAT); 1867 1868 /* disable Rx/Tx DMA */ 1869 temp = lpuart32_read(port, UARTBAUD); 1870 temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1871 lpuart32_write(port, temp, UARTBAUD); 1872 1873 /* disable Rx/Tx and interrupts and break condition */ 1874 temp = lpuart32_read(port, UARTCTRL); 1875 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | 1876 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1877 lpuart32_write(port, temp, UARTCTRL); 1878 1879 spin_unlock_irqrestore(&port->lock, flags); 1880 1881 lpuart_dma_shutdown(sport); 1882 } 1883 1884 static void 1885 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1886 const struct ktermios *old) 1887 { 1888 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1889 unsigned long flags; 1890 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1891 unsigned int baud; 1892 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1893 unsigned int sbr, brfa; 1894 1895 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1896 old_cr2 = readb(sport->port.membase + UARTCR2); 1897 cr3 = readb(sport->port.membase + UARTCR3); 1898 cr4 = readb(sport->port.membase + UARTCR4); 1899 bdh = readb(sport->port.membase + UARTBDH); 1900 modem = readb(sport->port.membase + UARTMODEM); 1901 /* 1902 * only support CS8 and CS7, and for CS7 must enable PE. 1903 * supported mode: 1904 * - (7,e/o,1) 1905 * - (8,n,1) 1906 * - (8,m/s,1) 1907 * - (8,e/o,1) 1908 */ 1909 while ((termios->c_cflag & CSIZE) != CS8 && 1910 (termios->c_cflag & CSIZE) != CS7) { 1911 termios->c_cflag &= ~CSIZE; 1912 termios->c_cflag |= old_csize; 1913 old_csize = CS8; 1914 } 1915 1916 if ((termios->c_cflag & CSIZE) == CS8 || 1917 (termios->c_cflag & CSIZE) == CS7) 1918 cr1 = old_cr1 & ~UARTCR1_M; 1919 1920 if (termios->c_cflag & CMSPAR) { 1921 if ((termios->c_cflag & CSIZE) != CS8) { 1922 termios->c_cflag &= ~CSIZE; 1923 termios->c_cflag |= CS8; 1924 } 1925 cr1 |= UARTCR1_M; 1926 } 1927 1928 /* 1929 * When auto RS-485 RTS mode is enabled, 1930 * hardware flow control need to be disabled. 1931 */ 1932 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1933 termios->c_cflag &= ~CRTSCTS; 1934 1935 if (termios->c_cflag & CRTSCTS) 1936 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1937 else 1938 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1939 1940 termios->c_cflag &= ~CSTOPB; 1941 1942 /* parity must be enabled when CS7 to match 8-bits format */ 1943 if ((termios->c_cflag & CSIZE) == CS7) 1944 termios->c_cflag |= PARENB; 1945 1946 if (termios->c_cflag & PARENB) { 1947 if (termios->c_cflag & CMSPAR) { 1948 cr1 &= ~UARTCR1_PE; 1949 if (termios->c_cflag & PARODD) 1950 cr3 |= UARTCR3_T8; 1951 else 1952 cr3 &= ~UARTCR3_T8; 1953 } else { 1954 cr1 |= UARTCR1_PE; 1955 if ((termios->c_cflag & CSIZE) == CS8) 1956 cr1 |= UARTCR1_M; 1957 if (termios->c_cflag & PARODD) 1958 cr1 |= UARTCR1_PT; 1959 else 1960 cr1 &= ~UARTCR1_PT; 1961 } 1962 } else { 1963 cr1 &= ~UARTCR1_PE; 1964 } 1965 1966 /* ask the core to calculate the divisor */ 1967 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1968 1969 /* 1970 * Need to update the Ring buffer length according to the selected 1971 * baud rate and restart Rx DMA path. 1972 * 1973 * Since timer function acqures sport->port.lock, need to stop before 1974 * acquring same lock because otherwise del_timer_sync() can deadlock. 1975 */ 1976 if (old && sport->lpuart_dma_rx_use) { 1977 del_timer_sync(&sport->lpuart_timer); 1978 lpuart_dma_rx_free(&sport->port); 1979 } 1980 1981 spin_lock_irqsave(&sport->port.lock, flags); 1982 1983 sport->port.read_status_mask = 0; 1984 if (termios->c_iflag & INPCK) 1985 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1986 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1987 sport->port.read_status_mask |= UARTSR1_FE; 1988 1989 /* characters to ignore */ 1990 sport->port.ignore_status_mask = 0; 1991 if (termios->c_iflag & IGNPAR) 1992 sport->port.ignore_status_mask |= UARTSR1_PE; 1993 if (termios->c_iflag & IGNBRK) { 1994 sport->port.ignore_status_mask |= UARTSR1_FE; 1995 /* 1996 * if we're ignoring parity and break indicators, 1997 * ignore overruns too (for real raw support). 1998 */ 1999 if (termios->c_iflag & IGNPAR) 2000 sport->port.ignore_status_mask |= UARTSR1_OR; 2001 } 2002 2003 /* update the per-port timeout */ 2004 uart_update_timeout(port, termios->c_cflag, baud); 2005 2006 /* wait transmit engin complete */ 2007 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2008 2009 /* disable transmit and receive */ 2010 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 2011 sport->port.membase + UARTCR2); 2012 2013 sbr = sport->port.uartclk / (16 * baud); 2014 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 2015 bdh &= ~UARTBDH_SBR_MASK; 2016 bdh |= (sbr >> 8) & 0x1F; 2017 cr4 &= ~UARTCR4_BRFA_MASK; 2018 brfa &= UARTCR4_BRFA_MASK; 2019 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 2020 writeb(bdh, sport->port.membase + UARTBDH); 2021 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 2022 writeb(cr3, sport->port.membase + UARTCR3); 2023 writeb(cr1, sport->port.membase + UARTCR1); 2024 writeb(modem, sport->port.membase + UARTMODEM); 2025 2026 /* restore control register */ 2027 writeb(old_cr2, sport->port.membase + UARTCR2); 2028 2029 if (old && sport->lpuart_dma_rx_use) { 2030 if (!lpuart_start_rx_dma(sport)) 2031 rx_dma_timer_init(sport); 2032 else 2033 sport->lpuart_dma_rx_use = false; 2034 } 2035 2036 spin_unlock_irqrestore(&sport->port.lock, flags); 2037 } 2038 2039 static void __lpuart32_serial_setbrg(struct uart_port *port, 2040 unsigned int baudrate, bool use_rx_dma, 2041 bool use_tx_dma) 2042 { 2043 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 2044 u32 clk = port->uartclk; 2045 2046 /* 2047 * The idea is to use the best OSR (over-sampling rate) possible. 2048 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2049 * Loop to find the best OSR value possible, one that generates minimum 2050 * baud_diff iterate through the rest of the supported values of OSR. 2051 * 2052 * Calculation Formula: 2053 * Baud Rate = baud clock / ((OSR+1) × SBR) 2054 */ 2055 baud_diff = baudrate; 2056 osr = 0; 2057 sbr = 0; 2058 2059 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2060 /* calculate the temporary sbr value */ 2061 tmp_sbr = (clk / (baudrate * tmp_osr)); 2062 if (tmp_sbr == 0) 2063 tmp_sbr = 1; 2064 2065 /* 2066 * calculate the baud rate difference based on the temporary 2067 * osr and sbr values 2068 */ 2069 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2070 2071 /* select best values between sbr and sbr+1 */ 2072 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 2073 if (tmp_diff > (baudrate - tmp)) { 2074 tmp_diff = baudrate - tmp; 2075 tmp_sbr++; 2076 } 2077 2078 if (tmp_sbr > UARTBAUD_SBR_MASK) 2079 continue; 2080 2081 if (tmp_diff <= baud_diff) { 2082 baud_diff = tmp_diff; 2083 osr = tmp_osr; 2084 sbr = tmp_sbr; 2085 2086 if (!baud_diff) 2087 break; 2088 } 2089 } 2090 2091 /* handle buadrate outside acceptable rate */ 2092 if (baud_diff > ((baudrate / 100) * 3)) 2093 dev_warn(port->dev, 2094 "unacceptable baud rate difference of more than 3%%\n"); 2095 2096 tmp = lpuart32_read(port, UARTBAUD); 2097 2098 if ((osr > 3) && (osr < 8)) 2099 tmp |= UARTBAUD_BOTHEDGE; 2100 2101 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2102 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2103 2104 tmp &= ~UARTBAUD_SBR_MASK; 2105 tmp |= sbr & UARTBAUD_SBR_MASK; 2106 2107 if (!use_rx_dma) 2108 tmp &= ~UARTBAUD_RDMAE; 2109 if (!use_tx_dma) 2110 tmp &= ~UARTBAUD_TDMAE; 2111 2112 lpuart32_write(port, tmp, UARTBAUD); 2113 } 2114 2115 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2116 unsigned int baudrate) 2117 { 2118 __lpuart32_serial_setbrg(&sport->port, baudrate, 2119 sport->lpuart_dma_rx_use, 2120 sport->lpuart_dma_tx_use); 2121 } 2122 2123 2124 static void 2125 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2126 const struct ktermios *old) 2127 { 2128 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2129 unsigned long flags; 2130 unsigned long ctrl, old_ctrl, bd, modem; 2131 unsigned int baud; 2132 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2133 2134 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2135 bd = lpuart32_read(&sport->port, UARTBAUD); 2136 modem = lpuart32_read(&sport->port, UARTMODIR); 2137 sport->is_cs7 = false; 2138 /* 2139 * only support CS8 and CS7, and for CS7 must enable PE. 2140 * supported mode: 2141 * - (7,e/o,1) 2142 * - (8,n,1) 2143 * - (8,m/s,1) 2144 * - (8,e/o,1) 2145 */ 2146 while ((termios->c_cflag & CSIZE) != CS8 && 2147 (termios->c_cflag & CSIZE) != CS7) { 2148 termios->c_cflag &= ~CSIZE; 2149 termios->c_cflag |= old_csize; 2150 old_csize = CS8; 2151 } 2152 2153 if ((termios->c_cflag & CSIZE) == CS8 || 2154 (termios->c_cflag & CSIZE) == CS7) 2155 ctrl = old_ctrl & ~UARTCTRL_M; 2156 2157 if (termios->c_cflag & CMSPAR) { 2158 if ((termios->c_cflag & CSIZE) != CS8) { 2159 termios->c_cflag &= ~CSIZE; 2160 termios->c_cflag |= CS8; 2161 } 2162 ctrl |= UARTCTRL_M; 2163 } 2164 2165 /* 2166 * When auto RS-485 RTS mode is enabled, 2167 * hardware flow control need to be disabled. 2168 */ 2169 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2170 termios->c_cflag &= ~CRTSCTS; 2171 2172 if (termios->c_cflag & CRTSCTS) 2173 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2174 else 2175 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2176 2177 if (termios->c_cflag & CSTOPB) 2178 bd |= UARTBAUD_SBNS; 2179 else 2180 bd &= ~UARTBAUD_SBNS; 2181 2182 /* parity must be enabled when CS7 to match 8-bits format */ 2183 if ((termios->c_cflag & CSIZE) == CS7) 2184 termios->c_cflag |= PARENB; 2185 2186 if ((termios->c_cflag & PARENB)) { 2187 if (termios->c_cflag & CMSPAR) { 2188 ctrl &= ~UARTCTRL_PE; 2189 ctrl |= UARTCTRL_M; 2190 } else { 2191 ctrl |= UARTCTRL_PE; 2192 if ((termios->c_cflag & CSIZE) == CS8) 2193 ctrl |= UARTCTRL_M; 2194 if (termios->c_cflag & PARODD) 2195 ctrl |= UARTCTRL_PT; 2196 else 2197 ctrl &= ~UARTCTRL_PT; 2198 } 2199 } else { 2200 ctrl &= ~UARTCTRL_PE; 2201 } 2202 2203 /* ask the core to calculate the divisor */ 2204 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2205 2206 /* 2207 * Need to update the Ring buffer length according to the selected 2208 * baud rate and restart Rx DMA path. 2209 * 2210 * Since timer function acqures sport->port.lock, need to stop before 2211 * acquring same lock because otherwise del_timer_sync() can deadlock. 2212 */ 2213 if (old && sport->lpuart_dma_rx_use) { 2214 del_timer_sync(&sport->lpuart_timer); 2215 lpuart_dma_rx_free(&sport->port); 2216 } 2217 2218 spin_lock_irqsave(&sport->port.lock, flags); 2219 2220 sport->port.read_status_mask = 0; 2221 if (termios->c_iflag & INPCK) 2222 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2223 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2224 sport->port.read_status_mask |= UARTSTAT_FE; 2225 2226 /* characters to ignore */ 2227 sport->port.ignore_status_mask = 0; 2228 if (termios->c_iflag & IGNPAR) 2229 sport->port.ignore_status_mask |= UARTSTAT_PE; 2230 if (termios->c_iflag & IGNBRK) { 2231 sport->port.ignore_status_mask |= UARTSTAT_FE; 2232 /* 2233 * if we're ignoring parity and break indicators, 2234 * ignore overruns too (for real raw support). 2235 */ 2236 if (termios->c_iflag & IGNPAR) 2237 sport->port.ignore_status_mask |= UARTSTAT_OR; 2238 } 2239 2240 /* update the per-port timeout */ 2241 uart_update_timeout(port, termios->c_cflag, baud); 2242 2243 /* wait transmit engin complete */ 2244 lpuart32_write(&sport->port, 0, UARTMODIR); 2245 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2246 2247 /* disable transmit and receive */ 2248 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2249 UARTCTRL); 2250 2251 lpuart32_write(&sport->port, bd, UARTBAUD); 2252 lpuart32_serial_setbrg(sport, baud); 2253 lpuart32_write(&sport->port, modem, UARTMODIR); 2254 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2255 /* restore control register */ 2256 2257 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2258 sport->is_cs7 = true; 2259 2260 if (old && sport->lpuart_dma_rx_use) { 2261 if (!lpuart_start_rx_dma(sport)) 2262 rx_dma_timer_init(sport); 2263 else 2264 sport->lpuart_dma_rx_use = false; 2265 } 2266 2267 spin_unlock_irqrestore(&sport->port.lock, flags); 2268 } 2269 2270 static const char *lpuart_type(struct uart_port *port) 2271 { 2272 return "FSL_LPUART"; 2273 } 2274 2275 static void lpuart_release_port(struct uart_port *port) 2276 { 2277 /* nothing to do */ 2278 } 2279 2280 static int lpuart_request_port(struct uart_port *port) 2281 { 2282 return 0; 2283 } 2284 2285 /* configure/autoconfigure the port */ 2286 static void lpuart_config_port(struct uart_port *port, int flags) 2287 { 2288 if (flags & UART_CONFIG_TYPE) 2289 port->type = PORT_LPUART; 2290 } 2291 2292 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2293 { 2294 int ret = 0; 2295 2296 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2297 ret = -EINVAL; 2298 if (port->irq != ser->irq) 2299 ret = -EINVAL; 2300 if (ser->io_type != UPIO_MEM) 2301 ret = -EINVAL; 2302 if (port->uartclk / 16 != ser->baud_base) 2303 ret = -EINVAL; 2304 if (port->iobase != ser->port) 2305 ret = -EINVAL; 2306 if (ser->hub6 != 0) 2307 ret = -EINVAL; 2308 return ret; 2309 } 2310 2311 static const struct uart_ops lpuart_pops = { 2312 .tx_empty = lpuart_tx_empty, 2313 .set_mctrl = lpuart_set_mctrl, 2314 .get_mctrl = lpuart_get_mctrl, 2315 .stop_tx = lpuart_stop_tx, 2316 .start_tx = lpuart_start_tx, 2317 .stop_rx = lpuart_stop_rx, 2318 .break_ctl = lpuart_break_ctl, 2319 .startup = lpuart_startup, 2320 .shutdown = lpuart_shutdown, 2321 .set_termios = lpuart_set_termios, 2322 .pm = lpuart_uart_pm, 2323 .type = lpuart_type, 2324 .request_port = lpuart_request_port, 2325 .release_port = lpuart_release_port, 2326 .config_port = lpuart_config_port, 2327 .verify_port = lpuart_verify_port, 2328 .flush_buffer = lpuart_flush_buffer, 2329 #if defined(CONFIG_CONSOLE_POLL) 2330 .poll_init = lpuart_poll_init, 2331 .poll_get_char = lpuart_poll_get_char, 2332 .poll_put_char = lpuart_poll_put_char, 2333 #endif 2334 }; 2335 2336 static const struct uart_ops lpuart32_pops = { 2337 .tx_empty = lpuart32_tx_empty, 2338 .set_mctrl = lpuart32_set_mctrl, 2339 .get_mctrl = lpuart32_get_mctrl, 2340 .stop_tx = lpuart32_stop_tx, 2341 .start_tx = lpuart32_start_tx, 2342 .stop_rx = lpuart32_stop_rx, 2343 .break_ctl = lpuart32_break_ctl, 2344 .startup = lpuart32_startup, 2345 .shutdown = lpuart32_shutdown, 2346 .set_termios = lpuart32_set_termios, 2347 .pm = lpuart_uart_pm, 2348 .type = lpuart_type, 2349 .request_port = lpuart_request_port, 2350 .release_port = lpuart_release_port, 2351 .config_port = lpuart_config_port, 2352 .verify_port = lpuart_verify_port, 2353 .flush_buffer = lpuart_flush_buffer, 2354 #if defined(CONFIG_CONSOLE_POLL) 2355 .poll_init = lpuart32_poll_init, 2356 .poll_get_char = lpuart32_poll_get_char, 2357 .poll_put_char = lpuart32_poll_put_char, 2358 #endif 2359 }; 2360 2361 static struct lpuart_port *lpuart_ports[UART_NR]; 2362 2363 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2364 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2365 { 2366 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2367 writeb(ch, port->membase + UARTDR); 2368 } 2369 2370 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2371 { 2372 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2373 lpuart32_write(port, ch, UARTDATA); 2374 } 2375 2376 static void 2377 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2378 { 2379 struct lpuart_port *sport = lpuart_ports[co->index]; 2380 unsigned char old_cr2, cr2; 2381 unsigned long flags; 2382 int locked = 1; 2383 2384 if (oops_in_progress) 2385 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2386 else 2387 spin_lock_irqsave(&sport->port.lock, flags); 2388 2389 /* first save CR2 and then disable interrupts */ 2390 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2391 cr2 |= UARTCR2_TE | UARTCR2_RE; 2392 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2393 writeb(cr2, sport->port.membase + UARTCR2); 2394 2395 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2396 2397 /* wait for transmitter finish complete and restore CR2 */ 2398 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2399 2400 writeb(old_cr2, sport->port.membase + UARTCR2); 2401 2402 if (locked) 2403 spin_unlock_irqrestore(&sport->port.lock, flags); 2404 } 2405 2406 static void 2407 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2408 { 2409 struct lpuart_port *sport = lpuart_ports[co->index]; 2410 unsigned long old_cr, cr; 2411 unsigned long flags; 2412 int locked = 1; 2413 2414 if (oops_in_progress) 2415 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2416 else 2417 spin_lock_irqsave(&sport->port.lock, flags); 2418 2419 /* first save CR2 and then disable interrupts */ 2420 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2421 cr |= UARTCTRL_TE | UARTCTRL_RE; 2422 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2423 lpuart32_write(&sport->port, cr, UARTCTRL); 2424 2425 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2426 2427 /* wait for transmitter finish complete and restore CR2 */ 2428 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2429 2430 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2431 2432 if (locked) 2433 spin_unlock_irqrestore(&sport->port.lock, flags); 2434 } 2435 2436 /* 2437 * if the port was already initialised (eg, by a boot loader), 2438 * try to determine the current setup. 2439 */ 2440 static void __init 2441 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2442 int *parity, int *bits) 2443 { 2444 unsigned char cr, bdh, bdl, brfa; 2445 unsigned int sbr, uartclk, baud_raw; 2446 2447 cr = readb(sport->port.membase + UARTCR2); 2448 cr &= UARTCR2_TE | UARTCR2_RE; 2449 if (!cr) 2450 return; 2451 2452 /* ok, the port was enabled */ 2453 2454 cr = readb(sport->port.membase + UARTCR1); 2455 2456 *parity = 'n'; 2457 if (cr & UARTCR1_PE) { 2458 if (cr & UARTCR1_PT) 2459 *parity = 'o'; 2460 else 2461 *parity = 'e'; 2462 } 2463 2464 if (cr & UARTCR1_M) 2465 *bits = 9; 2466 else 2467 *bits = 8; 2468 2469 bdh = readb(sport->port.membase + UARTBDH); 2470 bdh &= UARTBDH_SBR_MASK; 2471 bdl = readb(sport->port.membase + UARTBDL); 2472 sbr = bdh; 2473 sbr <<= 8; 2474 sbr |= bdl; 2475 brfa = readb(sport->port.membase + UARTCR4); 2476 brfa &= UARTCR4_BRFA_MASK; 2477 2478 uartclk = lpuart_get_baud_clk_rate(sport); 2479 /* 2480 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2481 */ 2482 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2483 2484 if (*baud != baud_raw) 2485 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2486 "from %d to %d\n", baud_raw, *baud); 2487 } 2488 2489 static void __init 2490 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2491 int *parity, int *bits) 2492 { 2493 unsigned long cr, bd; 2494 unsigned int sbr, uartclk, baud_raw; 2495 2496 cr = lpuart32_read(&sport->port, UARTCTRL); 2497 cr &= UARTCTRL_TE | UARTCTRL_RE; 2498 if (!cr) 2499 return; 2500 2501 /* ok, the port was enabled */ 2502 2503 cr = lpuart32_read(&sport->port, UARTCTRL); 2504 2505 *parity = 'n'; 2506 if (cr & UARTCTRL_PE) { 2507 if (cr & UARTCTRL_PT) 2508 *parity = 'o'; 2509 else 2510 *parity = 'e'; 2511 } 2512 2513 if (cr & UARTCTRL_M) 2514 *bits = 9; 2515 else 2516 *bits = 8; 2517 2518 bd = lpuart32_read(&sport->port, UARTBAUD); 2519 bd &= UARTBAUD_SBR_MASK; 2520 if (!bd) 2521 return; 2522 2523 sbr = bd; 2524 uartclk = lpuart_get_baud_clk_rate(sport); 2525 /* 2526 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2527 */ 2528 baud_raw = uartclk / (16 * sbr); 2529 2530 if (*baud != baud_raw) 2531 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2532 "from %d to %d\n", baud_raw, *baud); 2533 } 2534 2535 static int __init lpuart_console_setup(struct console *co, char *options) 2536 { 2537 struct lpuart_port *sport; 2538 int baud = 115200; 2539 int bits = 8; 2540 int parity = 'n'; 2541 int flow = 'n'; 2542 2543 /* 2544 * check whether an invalid uart number has been specified, and 2545 * if so, search for the first available port that does have 2546 * console support. 2547 */ 2548 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2549 co->index = 0; 2550 2551 sport = lpuart_ports[co->index]; 2552 if (sport == NULL) 2553 return -ENODEV; 2554 2555 if (options) 2556 uart_parse_options(options, &baud, &parity, &bits, &flow); 2557 else 2558 if (lpuart_is_32(sport)) 2559 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2560 else 2561 lpuart_console_get_options(sport, &baud, &parity, &bits); 2562 2563 if (lpuart_is_32(sport)) 2564 lpuart32_setup_watermark(sport); 2565 else 2566 lpuart_setup_watermark(sport); 2567 2568 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2569 } 2570 2571 static struct uart_driver lpuart_reg; 2572 static struct console lpuart_console = { 2573 .name = DEV_NAME, 2574 .write = lpuart_console_write, 2575 .device = uart_console_device, 2576 .setup = lpuart_console_setup, 2577 .flags = CON_PRINTBUFFER, 2578 .index = -1, 2579 .data = &lpuart_reg, 2580 }; 2581 2582 static struct console lpuart32_console = { 2583 .name = DEV_NAME, 2584 .write = lpuart32_console_write, 2585 .device = uart_console_device, 2586 .setup = lpuart_console_setup, 2587 .flags = CON_PRINTBUFFER, 2588 .index = -1, 2589 .data = &lpuart_reg, 2590 }; 2591 2592 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2593 { 2594 struct earlycon_device *dev = con->data; 2595 2596 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2597 } 2598 2599 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2600 { 2601 struct earlycon_device *dev = con->data; 2602 2603 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2604 } 2605 2606 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2607 const char *opt) 2608 { 2609 if (!device->port.membase) 2610 return -ENODEV; 2611 2612 device->con->write = lpuart_early_write; 2613 return 0; 2614 } 2615 2616 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2617 const char *opt) 2618 { 2619 if (!device->port.membase) 2620 return -ENODEV; 2621 2622 if (device->port.iotype != UPIO_MEM32) 2623 device->port.iotype = UPIO_MEM32BE; 2624 2625 device->con->write = lpuart32_early_write; 2626 return 0; 2627 } 2628 2629 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2630 const char *opt) 2631 { 2632 u32 cr; 2633 2634 if (!device->port.membase) 2635 return -ENODEV; 2636 2637 device->port.iotype = UPIO_MEM32; 2638 device->con->write = lpuart32_early_write; 2639 2640 /* set the baudrate */ 2641 if (device->port.uartclk && device->baud) 2642 __lpuart32_serial_setbrg(&device->port, device->baud, 2643 false, false); 2644 2645 /* enable transmitter */ 2646 cr = lpuart32_read(&device->port, UARTCTRL); 2647 cr |= UARTCTRL_TE; 2648 lpuart32_write(&device->port, cr, UARTCTRL); 2649 2650 return 0; 2651 } 2652 2653 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2654 const char *opt) 2655 { 2656 if (!device->port.membase) 2657 return -ENODEV; 2658 2659 device->port.iotype = UPIO_MEM32; 2660 device->port.membase += IMX_REG_OFF; 2661 device->con->write = lpuart32_early_write; 2662 2663 return 0; 2664 } 2665 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2666 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2667 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2668 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2669 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2670 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2671 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2672 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2673 2674 #define LPUART_CONSOLE (&lpuart_console) 2675 #define LPUART32_CONSOLE (&lpuart32_console) 2676 #else 2677 #define LPUART_CONSOLE NULL 2678 #define LPUART32_CONSOLE NULL 2679 #endif 2680 2681 static struct uart_driver lpuart_reg = { 2682 .owner = THIS_MODULE, 2683 .driver_name = DRIVER_NAME, 2684 .dev_name = DEV_NAME, 2685 .nr = ARRAY_SIZE(lpuart_ports), 2686 .cons = LPUART_CONSOLE, 2687 }; 2688 2689 static const struct serial_rs485 lpuart_rs485_supported = { 2690 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2691 /* delay_rts_* and RX_DURING_TX are not supported */ 2692 }; 2693 2694 static int lpuart_global_reset(struct lpuart_port *sport) 2695 { 2696 struct uart_port *port = &sport->port; 2697 void __iomem *global_addr; 2698 unsigned long ctrl, bd; 2699 unsigned int val = 0; 2700 int ret; 2701 2702 ret = clk_prepare_enable(sport->ipg_clk); 2703 if (ret) { 2704 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 2705 return ret; 2706 } 2707 2708 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 2709 /* 2710 * If the transmitter is used by earlycon, wait for transmit engine to 2711 * complete and then reset. 2712 */ 2713 ctrl = lpuart32_read(port, UARTCTRL); 2714 if (ctrl & UARTCTRL_TE) { 2715 bd = lpuart32_read(&sport->port, UARTBAUD); 2716 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, 2717 port)) { 2718 dev_warn(sport->port.dev, 2719 "timeout waiting for transmit engine to complete\n"); 2720 clk_disable_unprepare(sport->ipg_clk); 2721 return 0; 2722 } 2723 } 2724 2725 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 2726 writel(UART_GLOBAL_RST, global_addr); 2727 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2728 writel(0, global_addr); 2729 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2730 2731 /* Recover the transmitter for earlycon. */ 2732 if (ctrl & UARTCTRL_TE) { 2733 lpuart32_write(port, bd, UARTBAUD); 2734 lpuart32_write(port, ctrl, UARTCTRL); 2735 } 2736 } 2737 2738 clk_disable_unprepare(sport->ipg_clk); 2739 return 0; 2740 } 2741 2742 static int lpuart_probe(struct platform_device *pdev) 2743 { 2744 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2745 struct device_node *np = pdev->dev.of_node; 2746 struct lpuart_port *sport; 2747 struct resource *res; 2748 irq_handler_t handler; 2749 int ret; 2750 2751 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2752 if (!sport) 2753 return -ENOMEM; 2754 2755 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2756 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2757 if (IS_ERR(sport->port.membase)) 2758 return PTR_ERR(sport->port.membase); 2759 2760 sport->port.membase += sdata->reg_off; 2761 sport->port.mapbase = res->start + sdata->reg_off; 2762 sport->port.dev = &pdev->dev; 2763 sport->port.type = PORT_LPUART; 2764 sport->devtype = sdata->devtype; 2765 sport->rx_watermark = sdata->rx_watermark; 2766 ret = platform_get_irq(pdev, 0); 2767 if (ret < 0) 2768 return ret; 2769 sport->port.irq = ret; 2770 sport->port.iotype = sdata->iotype; 2771 if (lpuart_is_32(sport)) 2772 sport->port.ops = &lpuart32_pops; 2773 else 2774 sport->port.ops = &lpuart_pops; 2775 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2776 sport->port.flags = UPF_BOOT_AUTOCONF; 2777 2778 if (lpuart_is_32(sport)) 2779 sport->port.rs485_config = lpuart32_config_rs485; 2780 else 2781 sport->port.rs485_config = lpuart_config_rs485; 2782 sport->port.rs485_supported = lpuart_rs485_supported; 2783 2784 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2785 if (IS_ERR(sport->ipg_clk)) { 2786 ret = PTR_ERR(sport->ipg_clk); 2787 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2788 return ret; 2789 } 2790 2791 sport->baud_clk = NULL; 2792 if (is_imx8qxp_lpuart(sport)) { 2793 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2794 if (IS_ERR(sport->baud_clk)) { 2795 ret = PTR_ERR(sport->baud_clk); 2796 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2797 return ret; 2798 } 2799 } 2800 2801 ret = of_alias_get_id(np, "serial"); 2802 if (ret < 0) { 2803 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2804 return ret; 2805 } 2806 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2807 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2808 return -EINVAL; 2809 } 2810 sport->port.line = ret; 2811 2812 ret = lpuart_enable_clks(sport); 2813 if (ret) 2814 return ret; 2815 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2816 2817 lpuart_ports[sport->port.line] = sport; 2818 2819 platform_set_drvdata(pdev, &sport->port); 2820 2821 if (lpuart_is_32(sport)) { 2822 lpuart_reg.cons = LPUART32_CONSOLE; 2823 handler = lpuart32_int; 2824 } else { 2825 lpuart_reg.cons = LPUART_CONSOLE; 2826 handler = lpuart_int; 2827 } 2828 2829 pm_runtime_use_autosuspend(&pdev->dev); 2830 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 2831 pm_runtime_set_active(&pdev->dev); 2832 pm_runtime_enable(&pdev->dev); 2833 2834 ret = lpuart_global_reset(sport); 2835 if (ret) 2836 goto failed_reset; 2837 2838 ret = uart_get_rs485_mode(&sport->port); 2839 if (ret) 2840 goto failed_get_rs485; 2841 2842 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2843 if (ret) 2844 goto failed_attach_port; 2845 2846 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2847 DRIVER_NAME, sport); 2848 if (ret) 2849 goto failed_irq_request; 2850 2851 return 0; 2852 2853 failed_irq_request: 2854 uart_remove_one_port(&lpuart_reg, &sport->port); 2855 failed_attach_port: 2856 failed_get_rs485: 2857 failed_reset: 2858 pm_runtime_disable(&pdev->dev); 2859 pm_runtime_set_suspended(&pdev->dev); 2860 pm_runtime_dont_use_autosuspend(&pdev->dev); 2861 lpuart_disable_clks(sport); 2862 return ret; 2863 } 2864 2865 static int lpuart_remove(struct platform_device *pdev) 2866 { 2867 struct lpuart_port *sport = platform_get_drvdata(pdev); 2868 2869 uart_remove_one_port(&lpuart_reg, &sport->port); 2870 2871 lpuart_disable_clks(sport); 2872 2873 if (sport->dma_tx_chan) 2874 dma_release_channel(sport->dma_tx_chan); 2875 2876 if (sport->dma_rx_chan) 2877 dma_release_channel(sport->dma_rx_chan); 2878 2879 pm_runtime_disable(&pdev->dev); 2880 pm_runtime_set_suspended(&pdev->dev); 2881 pm_runtime_dont_use_autosuspend(&pdev->dev); 2882 return 0; 2883 } 2884 2885 static int lpuart_runtime_suspend(struct device *dev) 2886 { 2887 struct platform_device *pdev = to_platform_device(dev); 2888 struct lpuart_port *sport = platform_get_drvdata(pdev); 2889 2890 lpuart_disable_clks(sport); 2891 2892 return 0; 2893 }; 2894 2895 static int lpuart_runtime_resume(struct device *dev) 2896 { 2897 struct platform_device *pdev = to_platform_device(dev); 2898 struct lpuart_port *sport = platform_get_drvdata(pdev); 2899 2900 return lpuart_enable_clks(sport); 2901 }; 2902 2903 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) 2904 { 2905 unsigned int val, baud; 2906 2907 if (lpuart_is_32(sport)) { 2908 val = lpuart32_read(&sport->port, UARTCTRL); 2909 baud = lpuart32_read(&sport->port, UARTBAUD); 2910 if (on) { 2911 /* set rx_watermark to 0 in wakeup source mode */ 2912 lpuart32_write(&sport->port, 0, UARTWATER); 2913 val |= UARTCTRL_RIE; 2914 /* clear RXEDGIF flag before enable RXEDGIE interrupt */ 2915 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); 2916 baud |= UARTBAUD_RXEDGIE; 2917 } else { 2918 val &= ~UARTCTRL_RIE; 2919 baud &= ~UARTBAUD_RXEDGIE; 2920 } 2921 lpuart32_write(&sport->port, val, UARTCTRL); 2922 lpuart32_write(&sport->port, baud, UARTBAUD); 2923 } else { 2924 val = readb(sport->port.membase + UARTCR2); 2925 if (on) 2926 val |= UARTCR2_RIE; 2927 else 2928 val &= ~UARTCR2_RIE; 2929 writeb(val, sport->port.membase + UARTCR2); 2930 } 2931 } 2932 2933 static bool lpuart_uport_is_active(struct lpuart_port *sport) 2934 { 2935 struct tty_port *port = &sport->port.state->port; 2936 struct tty_struct *tty; 2937 struct device *tty_dev; 2938 int may_wake = 0; 2939 2940 tty = tty_port_tty_get(port); 2941 if (tty) { 2942 tty_dev = tty->dev; 2943 may_wake = device_may_wakeup(tty_dev); 2944 tty_kref_put(tty); 2945 } 2946 2947 if ((tty_port_initialized(port) && may_wake) || 2948 (!console_suspend_enabled && uart_console(&sport->port))) 2949 return true; 2950 2951 return false; 2952 } 2953 2954 static int lpuart_suspend_noirq(struct device *dev) 2955 { 2956 struct lpuart_port *sport = dev_get_drvdata(dev); 2957 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2958 2959 if (lpuart_uport_is_active(sport)) 2960 serial_lpuart_enable_wakeup(sport, !!irq_wake); 2961 2962 pinctrl_pm_select_sleep_state(dev); 2963 2964 return 0; 2965 } 2966 2967 static int lpuart_resume_noirq(struct device *dev) 2968 { 2969 struct lpuart_port *sport = dev_get_drvdata(dev); 2970 unsigned int val; 2971 2972 pinctrl_pm_select_default_state(dev); 2973 2974 if (lpuart_uport_is_active(sport)) { 2975 serial_lpuart_enable_wakeup(sport, false); 2976 2977 /* clear the wakeup flags */ 2978 if (lpuart_is_32(sport)) { 2979 val = lpuart32_read(&sport->port, UARTSTAT); 2980 lpuart32_write(&sport->port, val, UARTSTAT); 2981 } 2982 } 2983 2984 return 0; 2985 } 2986 2987 static int lpuart_suspend(struct device *dev) 2988 { 2989 struct lpuart_port *sport = dev_get_drvdata(dev); 2990 unsigned long temp, flags; 2991 2992 uart_suspend_port(&lpuart_reg, &sport->port); 2993 2994 if (lpuart_uport_is_active(sport)) { 2995 spin_lock_irqsave(&sport->port.lock, flags); 2996 if (lpuart_is_32(sport)) { 2997 /* disable Rx/Tx and interrupts */ 2998 temp = lpuart32_read(&sport->port, UARTCTRL); 2999 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 3000 lpuart32_write(&sport->port, temp, UARTCTRL); 3001 } else { 3002 /* disable Rx/Tx and interrupts */ 3003 temp = readb(sport->port.membase + UARTCR2); 3004 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 3005 writeb(temp, sport->port.membase + UARTCR2); 3006 } 3007 spin_unlock_irqrestore(&sport->port.lock, flags); 3008 3009 if (sport->lpuart_dma_rx_use) { 3010 /* 3011 * EDMA driver during suspend will forcefully release any 3012 * non-idle DMA channels. If port wakeup is enabled or if port 3013 * is console port or 'no_console_suspend' is set the Rx DMA 3014 * cannot resume as expected, hence gracefully release the 3015 * Rx DMA path before suspend and start Rx DMA path on resume. 3016 */ 3017 del_timer_sync(&sport->lpuart_timer); 3018 lpuart_dma_rx_free(&sport->port); 3019 3020 /* Disable Rx DMA to use UART port as wakeup source */ 3021 spin_lock_irqsave(&sport->port.lock, flags); 3022 if (lpuart_is_32(sport)) { 3023 temp = lpuart32_read(&sport->port, UARTBAUD); 3024 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 3025 UARTBAUD); 3026 } else { 3027 writeb(readb(sport->port.membase + UARTCR5) & 3028 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 3029 } 3030 spin_unlock_irqrestore(&sport->port.lock, flags); 3031 } 3032 3033 if (sport->lpuart_dma_tx_use) { 3034 spin_lock_irqsave(&sport->port.lock, flags); 3035 if (lpuart_is_32(sport)) { 3036 temp = lpuart32_read(&sport->port, UARTBAUD); 3037 temp &= ~UARTBAUD_TDMAE; 3038 lpuart32_write(&sport->port, temp, UARTBAUD); 3039 } else { 3040 temp = readb(sport->port.membase + UARTCR5); 3041 temp &= ~UARTCR5_TDMAS; 3042 writeb(temp, sport->port.membase + UARTCR5); 3043 } 3044 spin_unlock_irqrestore(&sport->port.lock, flags); 3045 sport->dma_tx_in_progress = false; 3046 dmaengine_terminate_sync(sport->dma_tx_chan); 3047 } 3048 } else if (pm_runtime_active(sport->port.dev)) { 3049 lpuart_disable_clks(sport); 3050 pm_runtime_disable(sport->port.dev); 3051 pm_runtime_set_suspended(sport->port.dev); 3052 } 3053 3054 return 0; 3055 } 3056 3057 static void lpuart_console_fixup(struct lpuart_port *sport) 3058 { 3059 struct tty_port *port = &sport->port.state->port; 3060 struct uart_port *uport = &sport->port; 3061 struct ktermios termios; 3062 3063 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers 3064 * all lost no matter the port is wakeup source. 3065 * For console port, console baud rate setting lost and print messy 3066 * log when enable the console port as wakeup source. To avoid the 3067 * issue happen, user should not enable uart port as wakeup source 3068 * in VLLS mode, or restore console setting here. 3069 */ 3070 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && 3071 console_suspend_enabled && uart_console(&sport->port)) { 3072 3073 mutex_lock(&port->mutex); 3074 memset(&termios, 0, sizeof(struct ktermios)); 3075 termios.c_cflag = uport->cons->cflag; 3076 if (port->tty && termios.c_cflag == 0) 3077 termios = port->tty->termios; 3078 uport->ops->set_termios(uport, &termios, NULL); 3079 mutex_unlock(&port->mutex); 3080 } 3081 } 3082 3083 static int lpuart_resume(struct device *dev) 3084 { 3085 struct lpuart_port *sport = dev_get_drvdata(dev); 3086 int ret; 3087 3088 if (lpuart_uport_is_active(sport)) { 3089 if (lpuart_is_32(sport)) 3090 lpuart32_hw_setup(sport); 3091 else 3092 lpuart_hw_setup(sport); 3093 } else if (pm_runtime_active(sport->port.dev)) { 3094 ret = lpuart_enable_clks(sport); 3095 if (ret) 3096 return ret; 3097 pm_runtime_set_active(sport->port.dev); 3098 pm_runtime_enable(sport->port.dev); 3099 } 3100 3101 lpuart_console_fixup(sport); 3102 uart_resume_port(&lpuart_reg, &sport->port); 3103 3104 return 0; 3105 } 3106 3107 static const struct dev_pm_ops lpuart_pm_ops = { 3108 RUNTIME_PM_OPS(lpuart_runtime_suspend, 3109 lpuart_runtime_resume, NULL) 3110 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, 3111 lpuart_resume_noirq) 3112 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) 3113 }; 3114 3115 static struct platform_driver lpuart_driver = { 3116 .probe = lpuart_probe, 3117 .remove = lpuart_remove, 3118 .driver = { 3119 .name = "fsl-lpuart", 3120 .of_match_table = lpuart_dt_ids, 3121 .pm = pm_ptr(&lpuart_pm_ops), 3122 }, 3123 }; 3124 3125 static int __init lpuart_serial_init(void) 3126 { 3127 int ret = uart_register_driver(&lpuart_reg); 3128 3129 if (ret) 3130 return ret; 3131 3132 ret = platform_driver_register(&lpuart_driver); 3133 if (ret) 3134 uart_unregister_driver(&lpuart_reg); 3135 3136 return ret; 3137 } 3138 3139 static void __exit lpuart_serial_exit(void) 3140 { 3141 platform_driver_unregister(&lpuart_driver); 3142 uart_unregister_driver(&lpuart_reg); 3143 } 3144 3145 module_init(lpuart_serial_init); 3146 module_exit(lpuart_serial_exit); 3147 3148 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 3149 MODULE_LICENSE("GPL v2"); 3150