1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include <drm/display/drm_dsc_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "intel_crtc.h" 15 #include "intel_de.h" 16 #include "intel_display_types.h" 17 #include "intel_dsi.h" 18 #include "intel_qp_tables.h" 19 #include "intel_vdsc.h" 20 #include "intel_vdsc_regs.h" 21 22 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 23 { 24 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 25 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 27 28 if (!HAS_DSC(i915)) 29 return false; 30 31 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A) 32 return false; 33 34 return true; 35 } 36 37 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 38 { 39 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 40 41 if (DISPLAY_VER(i915) >= 12) 42 return true; 43 44 if (cpu_transcoder == TRANSCODER_EDP || 45 cpu_transcoder == TRANSCODER_DSI_0 || 46 cpu_transcoder == TRANSCODER_DSI_1) 47 return false; 48 49 /* There's no pipe A DSC engine on ICL */ 50 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 51 52 return true; 53 } 54 55 static void 56 calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 57 { 58 int bpc = vdsc_cfg->bits_per_component; 59 int bpp = vdsc_cfg->bits_per_pixel >> 4; 60 static const s8 ofs_und6[] = { 61 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 62 }; 63 static const s8 ofs_und8[] = { 64 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 65 }; 66 static const s8 ofs_und12[] = { 67 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 68 }; 69 static const s8 ofs_und15[] = { 70 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 71 }; 72 int qp_bpc_modifier = (bpc - 8) * 2; 73 u32 res, buf_i, bpp_i; 74 75 if (vdsc_cfg->slice_height >= 8) 76 vdsc_cfg->first_line_bpg_offset = 77 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); 78 else 79 vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 80 81 /* Our hw supports only 444 modes as of today */ 82 if (bpp >= 12) 83 vdsc_cfg->initial_offset = 2048; 84 else if (bpp >= 10) 85 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 86 else if (bpp >= 8) 87 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 88 else 89 vdsc_cfg->initial_offset = 6144; 90 91 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 92 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 93 94 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier; 95 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier; 96 97 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 98 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 99 100 bpp_i = (2 * (bpp - 6)); 101 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 102 u8 range_bpg_offset; 103 104 /* Read range_minqp and range_max_qp from qp tables */ 105 vdsc_cfg->rc_range_params[buf_i].range_min_qp = 106 intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); 107 vdsc_cfg->rc_range_params[buf_i].range_max_qp = 108 intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); 109 110 /* Calculate range_bpg_offset */ 111 if (bpp <= 6) { 112 range_bpg_offset = ofs_und6[buf_i]; 113 } else if (bpp <= 8) { 114 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 115 range_bpg_offset = ofs_und6[buf_i] + res; 116 } else if (bpp <= 12) { 117 range_bpg_offset = ofs_und8[buf_i]; 118 } else if (bpp <= 15) { 119 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 120 range_bpg_offset = ofs_und12[buf_i] + res; 121 } else { 122 range_bpg_offset = ofs_und15[buf_i]; 123 } 124 125 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = 126 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; 127 } 128 } 129 130 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, 131 struct drm_dsc_config *vdsc_cfg) 132 { 133 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || 134 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 135 if (vdsc_cfg->slice_height > 4095) 136 return -EINVAL; 137 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) 138 return -EINVAL; 139 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 140 if (vdsc_cfg->slice_width % 2) 141 return -EINVAL; 142 if (vdsc_cfg->slice_height % 2) 143 return -EINVAL; 144 if (vdsc_cfg->slice_height > 4094) 145 return -EINVAL; 146 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) 147 return -EINVAL; 148 } 149 150 return 0; 151 } 152 153 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 154 { 155 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 156 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 157 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 158 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 159 int err; 160 int ret; 161 162 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 163 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 164 pipe_config->dsc.slice_count); 165 166 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); 167 168 if (err) { 169 drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n"); 170 return err; 171 } 172 173 /* 174 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 175 * else 1 176 */ 177 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 178 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; 179 180 if (DISPLAY_VER(dev_priv) >= 14 && 181 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 182 vdsc_cfg->native_420 = true; 183 /* We do not support YcBCr422 as of now */ 184 vdsc_cfg->native_422 = false; 185 vdsc_cfg->simple_422 = false; 186 /* Gen 11 does not support VBR */ 187 vdsc_cfg->vbr_enable = false; 188 189 /* Gen 11 only supports integral values of bpp */ 190 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 191 192 /* 193 * According to DSC 1.2 specs in Section 4.1 if native_420 is set: 194 * -We need to double the current bpp. 195 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice 196 * height < 8. 197 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma 198 * preservation in second line. 199 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded 200 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 201 * fractional bits. 202 */ 203 if (vdsc_cfg->native_420) { 204 vdsc_cfg->bits_per_pixel <<= 1; 205 206 if (vdsc_cfg->slice_height >= 8) 207 vdsc_cfg->second_line_bpg_offset = 12; 208 else 209 vdsc_cfg->second_line_bpg_offset = 210 2 * (vdsc_cfg->slice_height - 1); 211 212 vdsc_cfg->second_line_offset_adj = 512; 213 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, 214 vdsc_cfg->slice_height - 1); 215 } 216 217 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 218 219 drm_dsc_set_rc_buf_thresh(vdsc_cfg); 220 221 /* 222 * From XE_LPD onwards we supports compression bpps in steps of 1 223 * upto uncompressed bpp-1, hence add calculations for all the rc 224 * parameters 225 */ 226 if (DISPLAY_VER(dev_priv) >= 13) { 227 calculate_rc_params(vdsc_cfg); 228 } else { 229 if ((compressed_bpp == 8 || 230 compressed_bpp == 12) && 231 (vdsc_cfg->bits_per_component == 8 || 232 vdsc_cfg->bits_per_component == 10 || 233 vdsc_cfg->bits_per_component == 12)) 234 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR); 235 else 236 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444); 237 238 if (ret) 239 return ret; 240 241 /* 242 * FIXME: verify that the hardware actually needs these 243 * modifications rather than them being simple typos. 244 */ 245 if (compressed_bpp == 6 && 246 vdsc_cfg->bits_per_component == 8) 247 vdsc_cfg->rc_quant_incr_limit1 = 23; 248 249 if (compressed_bpp == 8 && 250 vdsc_cfg->bits_per_component == 14) 251 vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; 252 } 253 254 /* 255 * BitsPerComponent value determines mux_word_size: 256 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 257 * 48 bits otherwise 64 258 */ 259 if (vdsc_cfg->bits_per_component <= 10) 260 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 261 else 262 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 263 264 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 265 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 266 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 267 268 return 0; 269 } 270 271 enum intel_display_power_domain 272 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 273 { 274 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 275 enum pipe pipe = crtc->pipe; 276 277 /* 278 * VDSC/joining uses a separate power well, PW2, and requires 279 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 280 * 281 * - ICL eDP/DSI transcoder 282 * - Display version 12 (except RKL) pipe A 283 * 284 * For any other pipe, VDSC/joining uses the power well associated with 285 * the pipe in use. Hence another reference on the pipe power domain 286 * will suffice. (Except no VDSC/joining on ICL pipe A.) 287 */ 288 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 289 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 290 else if (is_pipe_dsc(crtc, cpu_transcoder)) 291 return POWER_DOMAIN_PIPE(pipe); 292 else 293 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 294 } 295 296 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 297 { 298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 300 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 301 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 302 enum pipe pipe = crtc->pipe; 303 u32 pps_val = 0; 304 u32 rc_buf_thresh_dword[4]; 305 u32 rc_range_params_dword[8]; 306 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 307 int i = 0; 308 309 if (crtc_state->bigjoiner_pipes) 310 num_vdsc_instances *= 2; 311 312 /* Populate PICTURE_PARAMETER_SET_0 registers */ 313 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 314 DSC_VER_MIN_SHIFT | 315 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 316 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 317 if (vdsc_cfg->dsc_version_minor == 2) { 318 pps_val |= DSC_ALT_ICH_SEL; 319 if (vdsc_cfg->native_420) 320 pps_val |= DSC_NATIVE_420_ENABLE; 321 if (vdsc_cfg->native_422) 322 pps_val |= DSC_NATIVE_422_ENABLE; 323 } 324 if (vdsc_cfg->block_pred_enable) 325 pps_val |= DSC_BLOCK_PREDICTION; 326 if (vdsc_cfg->convert_rgb) 327 pps_val |= DSC_COLOR_SPACE_CONVERSION; 328 if (vdsc_cfg->simple_422) 329 pps_val |= DSC_422_ENABLE; 330 if (vdsc_cfg->vbr_enable) 331 pps_val |= DSC_VBR_ENABLE; 332 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 333 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 334 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 335 pps_val); 336 /* 337 * If 2 VDSC instances are needed, configure PPS for second 338 * VDSC 339 */ 340 if (crtc_state->dsc.dsc_split) 341 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 342 pps_val); 343 } else { 344 intel_de_write(dev_priv, 345 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 346 pps_val); 347 if (crtc_state->dsc.dsc_split) 348 intel_de_write(dev_priv, 349 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 350 pps_val); 351 } 352 353 /* Populate PICTURE_PARAMETER_SET_1 registers */ 354 pps_val = 0; 355 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 356 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 357 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 358 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 359 pps_val); 360 /* 361 * If 2 VDSC instances are needed, configure PPS for second 362 * VDSC 363 */ 364 if (crtc_state->dsc.dsc_split) 365 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 366 pps_val); 367 } else { 368 intel_de_write(dev_priv, 369 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 370 pps_val); 371 if (crtc_state->dsc.dsc_split) 372 intel_de_write(dev_priv, 373 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 374 pps_val); 375 } 376 377 /* Populate PICTURE_PARAMETER_SET_2 registers */ 378 pps_val = 0; 379 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 380 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 381 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 382 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 383 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 384 pps_val); 385 /* 386 * If 2 VDSC instances are needed, configure PPS for second 387 * VDSC 388 */ 389 if (crtc_state->dsc.dsc_split) 390 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 391 pps_val); 392 } else { 393 intel_de_write(dev_priv, 394 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 395 pps_val); 396 if (crtc_state->dsc.dsc_split) 397 intel_de_write(dev_priv, 398 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 399 pps_val); 400 } 401 402 /* Populate PICTURE_PARAMETER_SET_3 registers */ 403 pps_val = 0; 404 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 405 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 406 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 407 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 408 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 409 pps_val); 410 /* 411 * If 2 VDSC instances are needed, configure PPS for second 412 * VDSC 413 */ 414 if (crtc_state->dsc.dsc_split) 415 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 416 pps_val); 417 } else { 418 intel_de_write(dev_priv, 419 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 420 pps_val); 421 if (crtc_state->dsc.dsc_split) 422 intel_de_write(dev_priv, 423 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 424 pps_val); 425 } 426 427 /* Populate PICTURE_PARAMETER_SET_4 registers */ 428 pps_val = 0; 429 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 430 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 431 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 432 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 433 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 434 pps_val); 435 /* 436 * If 2 VDSC instances are needed, configure PPS for second 437 * VDSC 438 */ 439 if (crtc_state->dsc.dsc_split) 440 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 441 pps_val); 442 } else { 443 intel_de_write(dev_priv, 444 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 445 pps_val); 446 if (crtc_state->dsc.dsc_split) 447 intel_de_write(dev_priv, 448 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 449 pps_val); 450 } 451 452 /* Populate PICTURE_PARAMETER_SET_5 registers */ 453 pps_val = 0; 454 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 455 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 456 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 457 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 458 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 459 pps_val); 460 /* 461 * If 2 VDSC instances are needed, configure PPS for second 462 * VDSC 463 */ 464 if (crtc_state->dsc.dsc_split) 465 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 466 pps_val); 467 } else { 468 intel_de_write(dev_priv, 469 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 470 pps_val); 471 if (crtc_state->dsc.dsc_split) 472 intel_de_write(dev_priv, 473 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 474 pps_val); 475 } 476 477 /* Populate PICTURE_PARAMETER_SET_6 registers */ 478 pps_val = 0; 479 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 480 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 481 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 482 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 483 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 484 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 485 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 486 pps_val); 487 /* 488 * If 2 VDSC instances are needed, configure PPS for second 489 * VDSC 490 */ 491 if (crtc_state->dsc.dsc_split) 492 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 493 pps_val); 494 } else { 495 intel_de_write(dev_priv, 496 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 497 pps_val); 498 if (crtc_state->dsc.dsc_split) 499 intel_de_write(dev_priv, 500 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 501 pps_val); 502 } 503 504 /* Populate PICTURE_PARAMETER_SET_7 registers */ 505 pps_val = 0; 506 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 507 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 508 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 509 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 510 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 511 pps_val); 512 /* 513 * If 2 VDSC instances are needed, configure PPS for second 514 * VDSC 515 */ 516 if (crtc_state->dsc.dsc_split) 517 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 518 pps_val); 519 } else { 520 intel_de_write(dev_priv, 521 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 522 pps_val); 523 if (crtc_state->dsc.dsc_split) 524 intel_de_write(dev_priv, 525 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 526 pps_val); 527 } 528 529 /* Populate PICTURE_PARAMETER_SET_8 registers */ 530 pps_val = 0; 531 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 532 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 533 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 534 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 535 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 536 pps_val); 537 /* 538 * If 2 VDSC instances are needed, configure PPS for second 539 * VDSC 540 */ 541 if (crtc_state->dsc.dsc_split) 542 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 543 pps_val); 544 } else { 545 intel_de_write(dev_priv, 546 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 547 pps_val); 548 if (crtc_state->dsc.dsc_split) 549 intel_de_write(dev_priv, 550 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 551 pps_val); 552 } 553 554 /* Populate PICTURE_PARAMETER_SET_9 registers */ 555 pps_val = 0; 556 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 557 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 558 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 559 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 560 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 561 pps_val); 562 /* 563 * If 2 VDSC instances are needed, configure PPS for second 564 * VDSC 565 */ 566 if (crtc_state->dsc.dsc_split) 567 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 568 pps_val); 569 } else { 570 intel_de_write(dev_priv, 571 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 572 pps_val); 573 if (crtc_state->dsc.dsc_split) 574 intel_de_write(dev_priv, 575 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 576 pps_val); 577 } 578 579 /* Populate PICTURE_PARAMETER_SET_10 registers */ 580 pps_val = 0; 581 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 582 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 583 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 584 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 585 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 586 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 587 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 588 pps_val); 589 /* 590 * If 2 VDSC instances are needed, configure PPS for second 591 * VDSC 592 */ 593 if (crtc_state->dsc.dsc_split) 594 intel_de_write(dev_priv, 595 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 596 } else { 597 intel_de_write(dev_priv, 598 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 599 pps_val); 600 if (crtc_state->dsc.dsc_split) 601 intel_de_write(dev_priv, 602 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 603 pps_val); 604 } 605 606 /* Populate Picture parameter set 16 */ 607 pps_val = 0; 608 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 609 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 610 vdsc_cfg->slice_width) | 611 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 612 vdsc_cfg->slice_height); 613 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 614 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 615 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 616 pps_val); 617 /* 618 * If 2 VDSC instances are needed, configure PPS for second 619 * VDSC 620 */ 621 if (crtc_state->dsc.dsc_split) 622 intel_de_write(dev_priv, 623 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 624 } else { 625 intel_de_write(dev_priv, 626 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 627 pps_val); 628 if (crtc_state->dsc.dsc_split) 629 intel_de_write(dev_priv, 630 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 631 pps_val); 632 } 633 634 if (DISPLAY_VER(dev_priv) >= 14) { 635 /* Populate PICTURE_PARAMETER_SET_17 registers */ 636 pps_val = 0; 637 pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); 638 drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); 639 intel_de_write(dev_priv, 640 MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe), 641 pps_val); 642 if (crtc_state->dsc.dsc_split) 643 intel_de_write(dev_priv, 644 MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe), 645 pps_val); 646 647 /* Populate PICTURE_PARAMETER_SET_18 registers */ 648 pps_val = 0; 649 pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | 650 DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); 651 drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); 652 intel_de_write(dev_priv, 653 MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe), 654 pps_val); 655 if (crtc_state->dsc.dsc_split) 656 intel_de_write(dev_priv, 657 MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe), 658 pps_val); 659 } 660 661 /* Populate the RC_BUF_THRESH registers */ 662 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 663 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 664 rc_buf_thresh_dword[i / 4] |= 665 (u32)(vdsc_cfg->rc_buf_thresh[i] << 666 BITS_PER_BYTE * (i % 4)); 667 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 668 rc_buf_thresh_dword[i / 4]); 669 } 670 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 671 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 672 rc_buf_thresh_dword[0]); 673 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 674 rc_buf_thresh_dword[1]); 675 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 676 rc_buf_thresh_dword[2]); 677 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 678 rc_buf_thresh_dword[3]); 679 if (crtc_state->dsc.dsc_split) { 680 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 681 rc_buf_thresh_dword[0]); 682 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 683 rc_buf_thresh_dword[1]); 684 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 685 rc_buf_thresh_dword[2]); 686 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 687 rc_buf_thresh_dword[3]); 688 } 689 } else { 690 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 691 rc_buf_thresh_dword[0]); 692 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 693 rc_buf_thresh_dword[1]); 694 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 695 rc_buf_thresh_dword[2]); 696 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 697 rc_buf_thresh_dword[3]); 698 if (crtc_state->dsc.dsc_split) { 699 intel_de_write(dev_priv, 700 ICL_DSC1_RC_BUF_THRESH_0(pipe), 701 rc_buf_thresh_dword[0]); 702 intel_de_write(dev_priv, 703 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 704 rc_buf_thresh_dword[1]); 705 intel_de_write(dev_priv, 706 ICL_DSC1_RC_BUF_THRESH_1(pipe), 707 rc_buf_thresh_dword[2]); 708 intel_de_write(dev_priv, 709 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 710 rc_buf_thresh_dword[3]); 711 } 712 } 713 714 /* Populate the RC_RANGE_PARAMETERS registers */ 715 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 716 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 717 rc_range_params_dword[i / 2] |= 718 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 719 RC_BPG_OFFSET_SHIFT) | 720 (vdsc_cfg->rc_range_params[i].range_max_qp << 721 RC_MAX_QP_SHIFT) | 722 (vdsc_cfg->rc_range_params[i].range_min_qp << 723 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 724 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 725 rc_range_params_dword[i / 2]); 726 } 727 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 728 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 729 rc_range_params_dword[0]); 730 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 731 rc_range_params_dword[1]); 732 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 733 rc_range_params_dword[2]); 734 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 735 rc_range_params_dword[3]); 736 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 737 rc_range_params_dword[4]); 738 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 739 rc_range_params_dword[5]); 740 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 741 rc_range_params_dword[6]); 742 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 743 rc_range_params_dword[7]); 744 if (crtc_state->dsc.dsc_split) { 745 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 746 rc_range_params_dword[0]); 747 intel_de_write(dev_priv, 748 DSCC_RC_RANGE_PARAMETERS_0_UDW, 749 rc_range_params_dword[1]); 750 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 751 rc_range_params_dword[2]); 752 intel_de_write(dev_priv, 753 DSCC_RC_RANGE_PARAMETERS_1_UDW, 754 rc_range_params_dword[3]); 755 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 756 rc_range_params_dword[4]); 757 intel_de_write(dev_priv, 758 DSCC_RC_RANGE_PARAMETERS_2_UDW, 759 rc_range_params_dword[5]); 760 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 761 rc_range_params_dword[6]); 762 intel_de_write(dev_priv, 763 DSCC_RC_RANGE_PARAMETERS_3_UDW, 764 rc_range_params_dword[7]); 765 } 766 } else { 767 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 768 rc_range_params_dword[0]); 769 intel_de_write(dev_priv, 770 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 771 rc_range_params_dword[1]); 772 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 773 rc_range_params_dword[2]); 774 intel_de_write(dev_priv, 775 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 776 rc_range_params_dword[3]); 777 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 778 rc_range_params_dword[4]); 779 intel_de_write(dev_priv, 780 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 781 rc_range_params_dword[5]); 782 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 783 rc_range_params_dword[6]); 784 intel_de_write(dev_priv, 785 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 786 rc_range_params_dword[7]); 787 if (crtc_state->dsc.dsc_split) { 788 intel_de_write(dev_priv, 789 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 790 rc_range_params_dword[0]); 791 intel_de_write(dev_priv, 792 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 793 rc_range_params_dword[1]); 794 intel_de_write(dev_priv, 795 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 796 rc_range_params_dword[2]); 797 intel_de_write(dev_priv, 798 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 799 rc_range_params_dword[3]); 800 intel_de_write(dev_priv, 801 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 802 rc_range_params_dword[4]); 803 intel_de_write(dev_priv, 804 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 805 rc_range_params_dword[5]); 806 intel_de_write(dev_priv, 807 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 808 rc_range_params_dword[6]); 809 intel_de_write(dev_priv, 810 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 811 rc_range_params_dword[7]); 812 } 813 } 814 } 815 816 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 817 const struct intel_crtc_state *crtc_state) 818 { 819 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 820 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 821 struct mipi_dsi_device *dsi; 822 struct drm_dsc_picture_parameter_set pps; 823 enum port port; 824 825 if (!crtc_state->dsc.compression_enable) 826 return; 827 828 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 829 830 for_each_dsi_port(port, intel_dsi->ports) { 831 dsi = intel_dsi->dsi_hosts[port]->device; 832 833 mipi_dsi_picture_parameter_set(dsi, &pps); 834 mipi_dsi_compression_mode(dsi, true); 835 } 836 } 837 838 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 839 const struct intel_crtc_state *crtc_state) 840 { 841 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 842 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 843 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 844 845 if (!crtc_state->dsc.compression_enable) 846 return; 847 848 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 849 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 850 851 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 852 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 853 854 dig_port->write_infoframe(encoder, crtc_state, 855 DP_SDP_PPS, &dp_dsc_pps_sdp, 856 sizeof(dp_dsc_pps_sdp)); 857 } 858 859 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 860 { 861 return is_pipe_dsc(crtc, cpu_transcoder) ? 862 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 863 } 864 865 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 866 { 867 return is_pipe_dsc(crtc, cpu_transcoder) ? 868 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 869 } 870 871 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 872 { 873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 875 u32 dss_ctl1_val = 0; 876 877 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { 878 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 879 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 880 else 881 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 882 883 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 884 } 885 } 886 887 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 888 { 889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 890 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 891 u32 dss_ctl1_val = 0; 892 u32 dss_ctl2_val = 0; 893 894 if (!crtc_state->dsc.compression_enable) 895 return; 896 897 intel_dsc_pps_configure(crtc_state); 898 899 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 900 if (crtc_state->dsc.dsc_split) { 901 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 902 dss_ctl1_val |= JOINER_ENABLE; 903 } 904 if (crtc_state->bigjoiner_pipes) { 905 dss_ctl1_val |= BIG_JOINER_ENABLE; 906 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 907 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 908 } 909 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 910 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 911 } 912 913 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 914 { 915 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 917 918 /* Disable only if either of them is enabled */ 919 if (old_crtc_state->dsc.compression_enable || 920 old_crtc_state->bigjoiner_pipes) { 921 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 922 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 923 } 924 } 925 926 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 927 { 928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 930 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 931 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 932 enum pipe pipe = crtc->pipe; 933 enum intel_display_power_domain power_domain; 934 intel_wakeref_t wakeref; 935 u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0; 936 937 if (!intel_dsc_source_support(crtc_state)) 938 return; 939 940 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 941 942 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 943 if (!wakeref) 944 return; 945 946 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 947 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 948 949 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 950 if (!crtc_state->dsc.compression_enable) 951 goto out; 952 953 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 954 (dss_ctl1 & JOINER_ENABLE); 955 956 /* FIXME: add more state readout as needed */ 957 958 /* PPS0 & PPS1 */ 959 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 960 pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 961 } else { 962 pps0 = intel_de_read(dev_priv, 963 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)); 964 pps1 = intel_de_read(dev_priv, 965 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 966 } 967 968 vdsc_cfg->bits_per_pixel = pps1; 969 970 if (pps0 & DSC_NATIVE_420_ENABLE) 971 vdsc_cfg->bits_per_pixel >>= 1; 972 973 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 974 out: 975 intel_display_power_put(dev_priv, power_domain, wakeref); 976 } 977