1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (C) 2012-2013 Broadcom Corporation 3 4#include <dt-bindings/clock/bcm281xx.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 model = "BCM11351 SoC"; 12 compatible = "brcm,bcm11351"; 13 interrupt-parent = <&gic>; 14 15 chosen { 16 bootargs = "console=ttyS0,115200n8"; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 reg = <0>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 enable-method = "brcm,bcm11351-cpu-method"; 33 secondary-boot-reg = <0x3500417c>; 34 reg = <1>; 35 }; 36 }; 37 38 gic: interrupt-controller@3ff00100 { 39 compatible = "arm,cortex-a9-gic"; 40 #interrupt-cells = <3>; 41 #address-cells = <0>; 42 interrupt-controller; 43 reg = <0x3ff01000 0x1000>, 44 <0x3ff00100 0x100>; 45 }; 46 47 smc@3404c000 { 48 compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; 49 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ 50 }; 51 52 uartb: serial@3e000000 { 53 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 54 reg = <0x3e000000 0x1000>; 55 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; 56 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 57 reg-shift = <2>; 58 reg-io-width = <4>; 59 status = "disabled"; 60 }; 61 62 uartb2: serial@3e001000 { 63 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 64 reg = <0x3e001000 0x1000>; 65 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; 66 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 67 reg-shift = <2>; 68 reg-io-width = <4>; 69 status = "disabled"; 70 }; 71 72 uartb3: serial@3e002000 { 73 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 74 reg = <0x3e002000 0x1000>; 75 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; 76 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 77 reg-shift = <2>; 78 reg-io-width = <4>; 79 status = "disabled"; 80 }; 81 82 uartb4: serial@3e003000 { 83 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 84 reg = <0x3e003000 0x1000>; 85 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; 86 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 status = "disabled"; 90 }; 91 92 L2: l2-cache@3ff20000 { 93 compatible = "brcm,bcm11351-a2-pl310-cache"; 94 reg = <0x3ff20000 0x1000>; 95 cache-unified; 96 cache-level = <2>; 97 }; 98 99 watchdog@35002f40 { 100 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; 101 reg = <0x35002f40 0x6c>; 102 }; 103 104 timer@35006000 { 105 compatible = "brcm,kona-timer"; 106 reg = <0x35006000 0x1000>; 107 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; 109 }; 110 111 gpio: gpio@35003000 { 112 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; 113 reg = <0x35003000 0x800>; 114 interrupts = 115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 116 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 117 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 118 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 119 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 120 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 #interrupt-cells = <2>; 123 gpio-controller; 124 interrupt-controller; 125 }; 126 127 sdio1: mmc@3f180000 { 128 compatible = "brcm,kona-sdhci"; 129 reg = <0x3f180000 0x10000>; 130 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; 132 status = "disabled"; 133 }; 134 135 sdio2: mmc@3f190000 { 136 compatible = "brcm,kona-sdhci"; 137 reg = <0x3f190000 0x10000>; 138 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; 140 status = "disabled"; 141 }; 142 143 sdio3: mmc@3f1a0000 { 144 compatible = "brcm,kona-sdhci"; 145 reg = <0x3f1a0000 0x10000>; 146 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; 148 status = "disabled"; 149 }; 150 151 sdio4: mmc@3f1b0000 { 152 compatible = "brcm,kona-sdhci"; 153 reg = <0x3f1b0000 0x10000>; 154 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; 156 status = "disabled"; 157 }; 158 159 pinctrl@35004800 { 160 compatible = "brcm,bcm11351-pinctrl"; 161 reg = <0x35004800 0x430>; 162 }; 163 164 bsc1: i2c@3e016000 { 165 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 166 reg = <0x3e016000 0x80>; 167 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; 171 status = "disabled"; 172 }; 173 174 bsc2: i2c@3e017000 { 175 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 176 reg = <0x3e017000 0x80>; 177 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; 181 status = "disabled"; 182 }; 183 184 bsc3: i2c@3e018000 { 185 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 186 reg = <0x3e018000 0x80>; 187 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; 191 status = "disabled"; 192 }; 193 194 pmu_bsc: i2c@3500d000 { 195 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 196 reg = <0x3500d000 0x80>; 197 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; 201 status = "disabled"; 202 }; 203 204 pwm: pwm@3e01a000 { 205 compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; 206 reg = <0x3e01a000 0xcc>; 207 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; 208 #pwm-cells = <3>; 209 status = "disabled"; 210 }; 211 212 clocks { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges; 216 217 root_ccu: root_ccu@35001000 { 218 compatible = "brcm,bcm11351-root-ccu"; 219 reg = <0x35001000 0x0f00>; 220 #clock-cells = <1>; 221 clock-output-names = "frac_1m"; 222 }; 223 224 hub_ccu: hub_ccu@34000000 { 225 compatible = "brcm,bcm11351-hub-ccu"; 226 reg = <0x34000000 0x0f00>; 227 #clock-cells = <1>; 228 clock-output-names = "tmon_1m"; 229 }; 230 231 aon_ccu: aon_ccu@35002000 { 232 compatible = "brcm,bcm11351-aon-ccu"; 233 reg = <0x35002000 0x0f00>; 234 #clock-cells = <1>; 235 clock-output-names = "hub_timer", 236 "pmu_bsc", 237 "pmu_bsc_var"; 238 }; 239 240 master_ccu: master_ccu@3f001000 { 241 compatible = "brcm,bcm11351-master-ccu"; 242 reg = <0x3f001000 0x0f00>; 243 #clock-cells = <1>; 244 clock-output-names = "sdio1", 245 "sdio2", 246 "sdio3", 247 "sdio4", 248 "usb_ic", 249 "hsic2_48m", 250 "hsic2_12m"; 251 }; 252 253 slave_ccu: slave_ccu@3e011000 { 254 compatible = "brcm,bcm11351-slave-ccu"; 255 reg = <0x3e011000 0x0f00>; 256 #clock-cells = <1>; 257 clock-output-names = "uartb", 258 "uartb2", 259 "uartb3", 260 "uartb4", 261 "ssp0", 262 "ssp2", 263 "bsc1", 264 "bsc2", 265 "bsc3", 266 "pwm"; 267 }; 268 269 ref_1m_clk: ref_1m { 270 #clock-cells = <0>; 271 compatible = "fixed-clock"; 272 clock-frequency = <1000000>; 273 }; 274 275 ref_32k_clk: ref_32k { 276 #clock-cells = <0>; 277 compatible = "fixed-clock"; 278 clock-frequency = <32768>; 279 }; 280 281 bbl_32k_clk: bbl_32k { 282 #clock-cells = <0>; 283 compatible = "fixed-clock"; 284 clock-frequency = <32768>; 285 }; 286 287 ref_13m_clk: ref_13m { 288 #clock-cells = <0>; 289 compatible = "fixed-clock"; 290 clock-frequency = <13000000>; 291 }; 292 293 var_13m_clk: var_13m { 294 #clock-cells = <0>; 295 compatible = "fixed-clock"; 296 clock-frequency = <13000000>; 297 }; 298 299 dft_19_5m_clk: dft_19_5m { 300 #clock-cells = <0>; 301 compatible = "fixed-clock"; 302 clock-frequency = <19500000>; 303 }; 304 305 ref_crystal_clk: ref_crystal { 306 #clock-cells = <0>; 307 compatible = "fixed-clock"; 308 clock-frequency = <26000000>; 309 }; 310 311 ref_cx40_clk: ref_cx40 { 312 #clock-cells = <0>; 313 compatible = "fixed-clock"; 314 clock-frequency = <40000000>; 315 }; 316 317 ref_52m_clk: ref_52m { 318 #clock-cells = <0>; 319 compatible = "fixed-clock"; 320 clock-frequency = <52000000>; 321 }; 322 323 var_52m_clk: var_52m { 324 #clock-cells = <0>; 325 compatible = "fixed-clock"; 326 clock-frequency = <52000000>; 327 }; 328 329 usb_otg_ahb_clk: usb_otg_ahb { 330 compatible = "fixed-clock"; 331 clock-frequency = <52000000>; 332 #clock-cells = <0>; 333 }; 334 335 ref_96m_clk: ref_96m { 336 #clock-cells = <0>; 337 compatible = "fixed-clock"; 338 clock-frequency = <96000000>; 339 }; 340 341 var_96m_clk: var_96m { 342 #clock-cells = <0>; 343 compatible = "fixed-clock"; 344 clock-frequency = <96000000>; 345 }; 346 347 ref_104m_clk: ref_104m { 348 #clock-cells = <0>; 349 compatible = "fixed-clock"; 350 clock-frequency = <104000000>; 351 }; 352 353 var_104m_clk: var_104m { 354 #clock-cells = <0>; 355 compatible = "fixed-clock"; 356 clock-frequency = <104000000>; 357 }; 358 359 ref_156m_clk: ref_156m { 360 #clock-cells = <0>; 361 compatible = "fixed-clock"; 362 clock-frequency = <156000000>; 363 }; 364 365 var_156m_clk: var_156m { 366 #clock-cells = <0>; 367 compatible = "fixed-clock"; 368 clock-frequency = <156000000>; 369 }; 370 371 ref_208m_clk: ref_208m { 372 #clock-cells = <0>; 373 compatible = "fixed-clock"; 374 clock-frequency = <208000000>; 375 }; 376 377 var_208m_clk: var_208m { 378 #clock-cells = <0>; 379 compatible = "fixed-clock"; 380 clock-frequency = <208000000>; 381 }; 382 383 ref_312m_clk: ref_312m { 384 #clock-cells = <0>; 385 compatible = "fixed-clock"; 386 clock-frequency = <312000000>; 387 }; 388 389 var_312m_clk: var_312m { 390 #clock-cells = <0>; 391 compatible = "fixed-clock"; 392 clock-frequency = <312000000>; 393 }; 394 }; 395 396 usbotg: usb@3f120000 { 397 compatible = "snps,dwc2"; 398 reg = <0x3f120000 0x10000>; 399 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&usb_otg_ahb_clk>; 401 clock-names = "otg"; 402 phys = <&usbphy>; 403 phy-names = "usb2-phy"; 404 status = "disabled"; 405 }; 406 407 usbphy: usb-phy@3f130000 { 408 compatible = "brcm,kona-usb2-phy"; 409 reg = <0x3f130000 0x28>; 410 #phy-cells = <0>; 411 status = "disabled"; 412 }; 413}; 414