1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF TX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/spinlock.h> 15 16 #include <sound/asoundef.h> 17 #include <sound/dmaengine_pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 21 /* 22 * ---- S/PDIF Transmitter Controller Register map ---- 23 */ 24 #define SPDIFTX_CR 0x00 /* Control Register */ 25 #define SPDIFTX_MR 0x04 /* Mode Register */ 26 #define SPDIFTX_CDR 0x0C /* Common Data Register */ 27 28 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */ 29 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */ 30 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */ 31 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */ 32 33 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */ 34 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */ 35 36 #define SPDIFTX_VERSION 0xF0 37 38 /* 39 * ---- Control Register (Write-only) ---- 40 */ 41 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */ 42 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */ 43 44 /* 45 * ---- Mode Register (Read/Write) ---- 46 */ 47 /* Transmit Enable */ 48 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0) 49 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0) 50 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0) 51 52 /* Multichannel Transfer */ 53 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1) 54 #define SPDIFTX_MR_MULTICH_MONO (0 << 1) 55 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1) 56 57 /* Data Word Endian Mode */ 58 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2) 59 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2) 60 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2) 61 62 /* Data Justification */ 63 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3) 64 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3) 65 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3) 66 67 /* Common Audio Register Transfer Mode */ 68 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4) 69 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4) 70 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4) 71 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4) 72 73 /* Valid Bits per Sample */ 74 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) 75 #define SPDIFTX_MR_VBPS(bps) FIELD_PREP(SPDIFTX_MR_VBPS_MASK, bps) 76 77 /* Chunk Size */ 78 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) 79 #define SPDIFTX_MR_CHUNK(size) FIELD_PREP(SPDIFTX_MR_CHUNK_MASK, size) 80 81 /* Validity Bits for Channels 1 and 2 */ 82 #define SPDIFTX_MR_VALID1 BIT(24) 83 #define SPDIFTX_MR_VALID2 BIT(25) 84 85 /* Disable Null Frame on underrun */ 86 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27) 87 #define SPDIFTX_MR_DNFR_INVALID (0 << 27) 88 #define SPDIFTX_MR_DNFR_VALID (1 << 27) 89 90 /* Bytes per Sample */ 91 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) 92 #define SPDIFTX_MR_BPS(bytes) FIELD_PREP(SPDIFTX_MR_BPS_MASK, (bytes - 1)) 93 94 /* 95 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 96 */ 97 #define SPDIFTX_IR_TXRDY BIT(0) 98 #define SPDIFTX_IR_TXEMPTY BIT(1) 99 #define SPDIFTX_IR_TXFULL BIT(2) 100 #define SPDIFTX_IR_TXCHUNK BIT(3) 101 #define SPDIFTX_IR_TXUDR BIT(4) 102 #define SPDIFTX_IR_TXOVR BIT(5) 103 #define SPDIFTX_IR_CSRDY BIT(6) 104 #define SPDIFTX_IR_UDRDY BIT(7) 105 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8) 106 #define SPDIFTX_IR_SECE BIT(10) 107 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11) 108 #define SPDIFTX_IR_BEND BIT(13) 109 110 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg) 111 { 112 switch (reg) { 113 case SPDIFTX_MR: 114 case SPDIFTX_IMR: 115 case SPDIFTX_ISR: 116 case SPDIFTX_CH1UD(0): 117 case SPDIFTX_CH1UD(1): 118 case SPDIFTX_CH1UD(2): 119 case SPDIFTX_CH1UD(3): 120 case SPDIFTX_CH1UD(4): 121 case SPDIFTX_CH1UD(5): 122 case SPDIFTX_CH1S(0): 123 case SPDIFTX_CH1S(1): 124 case SPDIFTX_CH1S(2): 125 case SPDIFTX_CH1S(3): 126 case SPDIFTX_CH1S(4): 127 case SPDIFTX_CH1S(5): 128 return true; 129 default: 130 return false; 131 } 132 } 133 134 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg) 135 { 136 switch (reg) { 137 case SPDIFTX_CR: 138 case SPDIFTX_MR: 139 case SPDIFTX_CDR: 140 case SPDIFTX_IER: 141 case SPDIFTX_IDR: 142 case SPDIFTX_CH1UD(0): 143 case SPDIFTX_CH1UD(1): 144 case SPDIFTX_CH1UD(2): 145 case SPDIFTX_CH1UD(3): 146 case SPDIFTX_CH1UD(4): 147 case SPDIFTX_CH1UD(5): 148 case SPDIFTX_CH1S(0): 149 case SPDIFTX_CH1S(1): 150 case SPDIFTX_CH1S(2): 151 case SPDIFTX_CH1S(3): 152 case SPDIFTX_CH1S(4): 153 case SPDIFTX_CH1S(5): 154 return true; 155 default: 156 return false; 157 } 158 } 159 160 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg) 161 { 162 switch (reg) { 163 case SPDIFTX_CDR: 164 case SPDIFTX_ISR: 165 return true; 166 default: 167 return false; 168 } 169 } 170 171 static const struct regmap_config mchp_spdiftx_regmap_config = { 172 .reg_bits = 32, 173 .reg_stride = 4, 174 .val_bits = 32, 175 .max_register = SPDIFTX_VERSION, 176 .readable_reg = mchp_spdiftx_readable_reg, 177 .writeable_reg = mchp_spdiftx_writeable_reg, 178 .precious_reg = mchp_spdiftx_precious_reg, 179 .cache_type = REGCACHE_FLAT, 180 }; 181 182 #define SPDIFTX_GCLK_RATIO 128 183 184 #define SPDIFTX_CS_BITS 192 185 #define SPDIFTX_UD_BITS 192 186 187 struct mchp_spdiftx_mixer_control { 188 unsigned char ch_stat[SPDIFTX_CS_BITS / 8]; 189 unsigned char user_data[SPDIFTX_UD_BITS / 8]; 190 spinlock_t lock; /* exclusive access to control data */ 191 }; 192 193 struct mchp_spdiftx_dev { 194 struct mchp_spdiftx_mixer_control control; 195 struct snd_dmaengine_dai_dma_data playback; 196 struct device *dev; 197 struct regmap *regmap; 198 struct clk *pclk; 199 struct clk *gclk; 200 unsigned int fmt; 201 unsigned int suspend_irq; 202 }; 203 204 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) 205 { 206 u32 mr; 207 208 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 209 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); 210 } 211 212 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev) 213 { 214 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 215 u32 val; 216 int i; 217 218 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { 219 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | 220 (ctrl->ch_stat[(i * 4) + 1] << 8) | 221 (ctrl->ch_stat[(i * 4) + 2] << 16) | 222 (ctrl->ch_stat[(i * 4) + 3] << 24); 223 224 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val); 225 } 226 } 227 228 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev) 229 { 230 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 231 u32 val; 232 int i; 233 234 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) { 235 val = (ctrl->user_data[(i * 4) + 0] << 0) | 236 (ctrl->user_data[(i * 4) + 1] << 8) | 237 (ctrl->user_data[(i * 4) + 2] << 16) | 238 (ctrl->user_data[(i * 4) + 3] << 24); 239 240 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val); 241 } 242 } 243 244 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id) 245 { 246 struct mchp_spdiftx_dev *dev = dev_id; 247 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 248 u32 sr, imr, pending, idr = 0; 249 250 regmap_read(dev->regmap, SPDIFTX_ISR, &sr); 251 regmap_read(dev->regmap, SPDIFTX_IMR, &imr); 252 pending = sr & imr; 253 254 if (!pending) 255 return IRQ_NONE; 256 257 if (pending & SPDIFTX_IR_TXUDR) { 258 dev_warn(dev->dev, "underflow detected\n"); 259 idr |= SPDIFTX_IR_TXUDR; 260 } 261 262 if (pending & SPDIFTX_IR_TXOVR) { 263 dev_warn(dev->dev, "overflow detected\n"); 264 idr |= SPDIFTX_IR_TXOVR; 265 } 266 267 if (pending & SPDIFTX_IR_UDRDY) { 268 spin_lock(&ctrl->lock); 269 mchp_spdiftx_user_data_write(dev); 270 spin_unlock(&ctrl->lock); 271 idr |= SPDIFTX_IR_UDRDY; 272 } 273 274 if (pending & SPDIFTX_IR_CSRDY) { 275 spin_lock(&ctrl->lock); 276 mchp_spdiftx_channel_status_write(dev); 277 spin_unlock(&ctrl->lock); 278 idr |= SPDIFTX_IR_CSRDY; 279 } 280 281 regmap_write(dev->regmap, SPDIFTX_IDR, idr); 282 283 return IRQ_HANDLED; 284 } 285 286 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream, 287 struct snd_soc_dai *dai) 288 { 289 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 290 291 /* Software reset the IP */ 292 regmap_write(dev->regmap, SPDIFTX_CR, 293 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 294 295 return 0; 296 } 297 298 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream, 299 struct snd_soc_dai *dai) 300 { 301 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 302 303 /* Disable interrupts */ 304 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff); 305 } 306 307 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, 308 struct snd_soc_dai *dai) 309 { 310 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 311 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 312 u32 mr; 313 int running; 314 int ret; 315 316 /* do not start/stop while channel status or user data is updated */ 317 spin_lock(&ctrl->lock); 318 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 319 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); 320 321 switch (cmd) { 322 case SNDRV_PCM_TRIGGER_RESUME: 323 case SNDRV_PCM_TRIGGER_START: 324 regmap_write(dev->regmap, SPDIFTX_IER, dev->suspend_irq | 325 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 326 dev->suspend_irq = 0; 327 fallthrough; 328 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 329 if (!running) { 330 mr &= ~SPDIFTX_MR_TXEN_MASK; 331 mr |= SPDIFTX_MR_TXEN_ENABLE; 332 } 333 break; 334 case SNDRV_PCM_TRIGGER_SUSPEND: 335 regmap_read(dev->regmap, SPDIFTX_IMR, &dev->suspend_irq); 336 fallthrough; 337 case SNDRV_PCM_TRIGGER_STOP: 338 regmap_write(dev->regmap, SPDIFTX_IDR, dev->suspend_irq | 339 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 340 fallthrough; 341 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 342 if (running) { 343 mr &= ~SPDIFTX_MR_TXEN_MASK; 344 mr |= SPDIFTX_MR_TXEN_DISABLE; 345 } 346 break; 347 default: 348 spin_unlock(&ctrl->lock); 349 return -EINVAL; 350 } 351 352 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr); 353 spin_unlock(&ctrl->lock); 354 if (ret) 355 dev_err(dev->dev, "unable to disable TX: %d\n", ret); 356 357 return ret; 358 } 359 360 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, 361 struct snd_pcm_hw_params *params, 362 struct snd_soc_dai *dai) 363 { 364 unsigned long flags; 365 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 366 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 367 u32 mr; 368 unsigned int bps = params_physical_width(params) / 8; 369 unsigned char aes3; 370 int ret; 371 372 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 373 __func__, params_rate(params), params_format(params), 374 params_width(params), params_channels(params)); 375 376 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 377 dev_err(dev->dev, "Capture is not supported\n"); 378 return -EINVAL; 379 } 380 381 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 382 383 if (mr & SPDIFTX_MR_TXEN_ENABLE) { 384 dev_err(dev->dev, "PCM already running\n"); 385 return -EBUSY; 386 } 387 388 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */ 389 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB; 390 dev->playback.maxburst = 1; 391 switch (params_channels(params)) { 392 case 1: 393 mr |= SPDIFTX_MR_MULTICH_MONO; 394 break; 395 case 2: 396 mr |= SPDIFTX_MR_MULTICH_DUAL; 397 if (bps > 2) 398 dev->playback.maxburst = 2; 399 break; 400 default: 401 dev_err(dev->dev, "unsupported number of channels: %d\n", 402 params_channels(params)); 403 return -EINVAL; 404 } 405 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst); 406 407 switch (params_format(params)) { 408 case SNDRV_PCM_FORMAT_S8: 409 mr |= SPDIFTX_MR_VBPS(8); 410 break; 411 case SNDRV_PCM_FORMAT_S16_BE: 412 mr |= SPDIFTX_MR_ENDIAN_BIG; 413 fallthrough; 414 case SNDRV_PCM_FORMAT_S16_LE: 415 mr |= SPDIFTX_MR_VBPS(16); 416 break; 417 case SNDRV_PCM_FORMAT_S18_3BE: 418 mr |= SPDIFTX_MR_ENDIAN_BIG; 419 fallthrough; 420 case SNDRV_PCM_FORMAT_S18_3LE: 421 mr |= SPDIFTX_MR_VBPS(18); 422 break; 423 case SNDRV_PCM_FORMAT_S20_3BE: 424 mr |= SPDIFTX_MR_ENDIAN_BIG; 425 fallthrough; 426 case SNDRV_PCM_FORMAT_S20_3LE: 427 mr |= SPDIFTX_MR_VBPS(20); 428 break; 429 case SNDRV_PCM_FORMAT_S24_3BE: 430 mr |= SPDIFTX_MR_ENDIAN_BIG; 431 fallthrough; 432 case SNDRV_PCM_FORMAT_S24_3LE: 433 mr |= SPDIFTX_MR_VBPS(24); 434 break; 435 case SNDRV_PCM_FORMAT_S24_BE: 436 mr |= SPDIFTX_MR_ENDIAN_BIG; 437 fallthrough; 438 case SNDRV_PCM_FORMAT_S24_LE: 439 mr |= SPDIFTX_MR_VBPS(24); 440 break; 441 case SNDRV_PCM_FORMAT_S32_BE: 442 mr |= SPDIFTX_MR_ENDIAN_BIG; 443 fallthrough; 444 case SNDRV_PCM_FORMAT_S32_LE: 445 mr |= SPDIFTX_MR_VBPS(32); 446 break; 447 default: 448 dev_err(dev->dev, "unsupported PCM format: %d\n", 449 params_format(params)); 450 return -EINVAL; 451 } 452 453 mr |= SPDIFTX_MR_BPS(bps); 454 455 switch (params_rate(params)) { 456 case 22050: 457 aes3 = IEC958_AES3_CON_FS_22050; 458 break; 459 case 24000: 460 aes3 = IEC958_AES3_CON_FS_24000; 461 break; 462 case 32000: 463 aes3 = IEC958_AES3_CON_FS_32000; 464 break; 465 case 44100: 466 aes3 = IEC958_AES3_CON_FS_44100; 467 break; 468 case 48000: 469 aes3 = IEC958_AES3_CON_FS_48000; 470 break; 471 case 88200: 472 aes3 = IEC958_AES3_CON_FS_88200; 473 break; 474 case 96000: 475 aes3 = IEC958_AES3_CON_FS_96000; 476 break; 477 case 176400: 478 aes3 = IEC958_AES3_CON_FS_176400; 479 break; 480 case 192000: 481 aes3 = IEC958_AES3_CON_FS_192000; 482 break; 483 case 8000: 484 case 11025: 485 case 16000: 486 case 64000: 487 aes3 = IEC958_AES3_CON_FS_NOTID; 488 break; 489 default: 490 dev_err(dev->dev, "unsupported sample frequency: %u\n", 491 params_rate(params)); 492 return -EINVAL; 493 } 494 spin_lock_irqsave(&ctrl->lock, flags); 495 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; 496 ctrl->ch_stat[3] |= aes3; 497 mchp_spdiftx_channel_status_write(dev); 498 spin_unlock_irqrestore(&ctrl->lock, flags); 499 500 /* GCLK is enabled by runtime PM. */ 501 clk_disable_unprepare(dev->gclk); 502 503 ret = clk_set_rate(dev->gclk, params_rate(params) * 504 SPDIFTX_GCLK_RATIO); 505 if (ret) { 506 dev_err(dev->dev, 507 "unable to change gclk rate to: rate %u * ratio %u\n", 508 params_rate(params), SPDIFTX_GCLK_RATIO); 509 return ret; 510 } 511 ret = clk_prepare_enable(dev->gclk); 512 if (ret) { 513 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 514 return ret; 515 } 516 517 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, 518 params_rate(params) * SPDIFTX_GCLK_RATIO); 519 520 regmap_write(dev->regmap, SPDIFTX_MR, mr); 521 522 return 0; 523 } 524 525 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, 526 struct snd_soc_dai *dai) 527 { 528 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 529 530 return regmap_write(dev->regmap, SPDIFTX_CR, 531 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 532 } 533 534 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = { 535 .startup = mchp_spdiftx_dai_startup, 536 .shutdown = mchp_spdiftx_dai_shutdown, 537 .trigger = mchp_spdiftx_trigger, 538 .hw_params = mchp_spdiftx_hw_params, 539 .hw_free = mchp_spdiftx_hw_free, 540 }; 541 542 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000 543 544 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 545 SNDRV_PCM_FMTBIT_S16_LE | \ 546 SNDRV_PCM_FMTBIT_U16_BE | \ 547 SNDRV_PCM_FMTBIT_S18_3LE | \ 548 SNDRV_PCM_FMTBIT_S18_3BE | \ 549 SNDRV_PCM_FMTBIT_S20_3LE | \ 550 SNDRV_PCM_FMTBIT_S20_3BE | \ 551 SNDRV_PCM_FMTBIT_S24_3LE | \ 552 SNDRV_PCM_FMTBIT_S24_3BE | \ 553 SNDRV_PCM_FMTBIT_S24_LE | \ 554 SNDRV_PCM_FMTBIT_S24_BE | \ 555 SNDRV_PCM_FMTBIT_S32_LE | \ 556 SNDRV_PCM_FMTBIT_S32_BE \ 557 ) 558 559 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol, 560 struct snd_ctl_elem_info *uinfo) 561 { 562 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 563 uinfo->count = 1; 564 565 return 0; 566 } 567 568 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol, 569 struct snd_ctl_elem_value *uvalue) 570 { 571 unsigned long flags; 572 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 573 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 574 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 575 576 spin_lock_irqsave(&ctrl->lock, flags); 577 memcpy(uvalue->value.iec958.status, ctrl->ch_stat, 578 sizeof(ctrl->ch_stat)); 579 spin_unlock_irqrestore(&ctrl->lock, flags); 580 581 return 0; 582 } 583 584 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol, 585 struct snd_ctl_elem_value *uvalue) 586 { 587 unsigned long flags; 588 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 589 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 590 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 591 int changed = 0; 592 int i; 593 594 spin_lock_irqsave(&ctrl->lock, flags); 595 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) { 596 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i]) 597 changed = 1; 598 ctrl->ch_stat[i] = uvalue->value.iec958.status[i]; 599 } 600 601 if (changed) { 602 /* don't enable IP while we copy the channel status */ 603 if (mchp_spdiftx_is_running(dev)) { 604 /* 605 * if SPDIF is running, wait for interrupt to write 606 * channel status 607 */ 608 regmap_write(dev->regmap, SPDIFTX_IER, 609 SPDIFTX_IR_CSRDY); 610 } else { 611 mchp_spdiftx_channel_status_write(dev); 612 } 613 } 614 spin_unlock_irqrestore(&ctrl->lock, flags); 615 616 return changed; 617 } 618 619 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol, 620 struct snd_ctl_elem_value *uvalue) 621 { 622 memset(uvalue->value.iec958.status, 0xff, 623 sizeof(uvalue->value.iec958.status)); 624 625 return 0; 626 } 627 628 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol, 629 struct snd_ctl_elem_value *uvalue) 630 { 631 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 632 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 633 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 634 unsigned long flags; 635 636 spin_lock_irqsave(&ctrl->lock, flags); 637 memcpy(uvalue->value.iec958.subcode, ctrl->user_data, 638 sizeof(ctrl->user_data)); 639 spin_unlock_irqrestore(&ctrl->lock, flags); 640 641 return 0; 642 } 643 644 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol, 645 struct snd_ctl_elem_value *uvalue) 646 { 647 unsigned long flags; 648 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 649 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 650 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 651 int changed = 0; 652 int i; 653 654 spin_lock_irqsave(&ctrl->lock, flags); 655 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) { 656 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i]) 657 changed = 1; 658 659 ctrl->user_data[i] = uvalue->value.iec958.subcode[i]; 660 } 661 if (changed) { 662 if (mchp_spdiftx_is_running(dev)) { 663 /* 664 * if SPDIF is running, wait for interrupt to write 665 * user data 666 */ 667 regmap_write(dev->regmap, SPDIFTX_IER, 668 SPDIFTX_IR_UDRDY); 669 } else { 670 mchp_spdiftx_user_data_write(dev); 671 } 672 } 673 spin_unlock_irqrestore(&ctrl->lock, flags); 674 675 return changed; 676 } 677 678 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { 679 /* Channel status controller */ 680 { 681 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 682 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 683 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 684 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 685 .info = mchp_spdiftx_info, 686 .get = mchp_spdiftx_cs_get, 687 .put = mchp_spdiftx_cs_put, 688 }, 689 { 690 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 691 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 692 .access = SNDRV_CTL_ELEM_ACCESS_READ, 693 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 694 .info = mchp_spdiftx_info, 695 .get = mchp_spdiftx_cs_mask, 696 }, 697 /* User bits controller */ 698 { 699 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 700 .name = "IEC958 Subcode Playback Default", 701 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 702 .info = mchp_spdiftx_info, 703 .get = mchp_spdiftx_subcode_get, 704 .put = mchp_spdiftx_subcode_put, 705 }, 706 }; 707 708 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) 709 { 710 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 711 712 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); 713 714 /* Add controls */ 715 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, 716 ARRAY_SIZE(mchp_spdiftx_ctrls)); 717 718 return 0; 719 } 720 721 static struct snd_soc_dai_driver mchp_spdiftx_dai = { 722 .name = "mchp-spdiftx", 723 .probe = mchp_spdiftx_dai_probe, 724 .playback = { 725 .stream_name = "S/PDIF Playback", 726 .channels_min = 1, 727 .channels_max = 2, 728 .rates = MCHP_SPDIFTX_RATES, 729 .formats = MCHP_SPDIFTX_FORMATS, 730 }, 731 .ops = &mchp_spdiftx_dai_ops, 732 }; 733 734 static const struct snd_soc_component_driver mchp_spdiftx_component = { 735 .name = "mchp-spdiftx", 736 .legacy_dai_naming = 1, 737 }; 738 739 static const struct of_device_id mchp_spdiftx_dt_ids[] = { 740 { 741 .compatible = "microchip,sama7g5-spdiftx", 742 }, 743 { /* sentinel */ } 744 }; 745 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); 746 747 static int mchp_spdiftx_runtime_suspend(struct device *dev) 748 { 749 struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); 750 751 regcache_cache_only(spdiftx->regmap, true); 752 753 clk_disable_unprepare(spdiftx->gclk); 754 clk_disable_unprepare(spdiftx->pclk); 755 756 return 0; 757 } 758 759 static int mchp_spdiftx_runtime_resume(struct device *dev) 760 { 761 struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); 762 int ret; 763 764 ret = clk_prepare_enable(spdiftx->pclk); 765 if (ret) { 766 dev_err(spdiftx->dev, 767 "failed to enable the peripheral clock: %d\n", ret); 768 return ret; 769 } 770 ret = clk_prepare_enable(spdiftx->gclk); 771 if (ret) { 772 dev_err(spdiftx->dev, 773 "failed to enable generic clock: %d\n", ret); 774 goto disable_pclk; 775 } 776 777 regcache_cache_only(spdiftx->regmap, false); 778 regcache_mark_dirty(spdiftx->regmap); 779 ret = regcache_sync(spdiftx->regmap); 780 if (ret) { 781 regcache_cache_only(spdiftx->regmap, true); 782 clk_disable_unprepare(spdiftx->gclk); 783 disable_pclk: 784 clk_disable_unprepare(spdiftx->pclk); 785 } 786 787 return ret; 788 } 789 790 static const struct dev_pm_ops mchp_spdiftx_pm_ops = { 791 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 792 RUNTIME_PM_OPS(mchp_spdiftx_runtime_suspend, mchp_spdiftx_runtime_resume, 793 NULL) 794 }; 795 796 static int mchp_spdiftx_probe(struct platform_device *pdev) 797 { 798 struct mchp_spdiftx_dev *dev; 799 struct resource *mem; 800 struct regmap *regmap; 801 void __iomem *base; 802 struct mchp_spdiftx_mixer_control *ctrl; 803 int irq; 804 int err; 805 806 /* Get memory for driver data. */ 807 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 808 if (!dev) 809 return -ENOMEM; 810 811 /* Map I/O registers. */ 812 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 813 if (IS_ERR(base)) 814 return PTR_ERR(base); 815 816 regmap = devm_regmap_init_mmio(&pdev->dev, base, 817 &mchp_spdiftx_regmap_config); 818 if (IS_ERR(regmap)) 819 return PTR_ERR(regmap); 820 821 /* Request IRQ */ 822 irq = platform_get_irq(pdev, 0); 823 if (irq < 0) 824 return irq; 825 826 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0, 827 dev_name(&pdev->dev), dev); 828 if (err) 829 return err; 830 831 /* Get the peripheral clock */ 832 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 833 if (IS_ERR(dev->pclk)) { 834 err = PTR_ERR(dev->pclk); 835 dev_err(&pdev->dev, 836 "failed to get the peripheral clock: %d\n", err); 837 return err; 838 } 839 840 /* Get the generic clock */ 841 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 842 if (IS_ERR(dev->gclk)) { 843 err = PTR_ERR(dev->gclk); 844 dev_err(&pdev->dev, 845 "failed to get the PMC generic clock: %d\n", err); 846 return err; 847 } 848 849 ctrl = &dev->control; 850 spin_lock_init(&ctrl->lock); 851 852 /* Init channel status */ 853 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 854 IEC958_AES0_CON_EMPHASIS_NONE; 855 856 dev->dev = &pdev->dev; 857 dev->regmap = regmap; 858 platform_set_drvdata(pdev, dev); 859 860 pm_runtime_enable(dev->dev); 861 if (!pm_runtime_enabled(dev->dev)) { 862 err = mchp_spdiftx_runtime_resume(dev->dev); 863 if (err) 864 return err; 865 } 866 867 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; 868 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 869 870 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 871 if (err) { 872 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 873 goto pm_runtime_suspend; 874 } 875 876 err = devm_snd_soc_register_component(&pdev->dev, 877 &mchp_spdiftx_component, 878 &mchp_spdiftx_dai, 1); 879 if (err) { 880 dev_err(&pdev->dev, "failed to register component: %d\n", err); 881 goto pm_runtime_suspend; 882 } 883 884 return 0; 885 886 pm_runtime_suspend: 887 if (!pm_runtime_status_suspended(dev->dev)) 888 mchp_spdiftx_runtime_suspend(dev->dev); 889 pm_runtime_disable(dev->dev); 890 891 return err; 892 } 893 894 static int mchp_spdiftx_remove(struct platform_device *pdev) 895 { 896 struct mchp_spdiftx_dev *dev = platform_get_drvdata(pdev); 897 898 if (!pm_runtime_status_suspended(dev->dev)) 899 mchp_spdiftx_runtime_suspend(dev->dev); 900 901 pm_runtime_disable(dev->dev); 902 903 return 0; 904 } 905 906 static struct platform_driver mchp_spdiftx_driver = { 907 .probe = mchp_spdiftx_probe, 908 .remove = mchp_spdiftx_remove, 909 .driver = { 910 .name = "mchp_spdiftx", 911 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), 912 .pm = pm_ptr(&mchp_spdiftx_pm_ops) 913 }, 914 }; 915 916 module_platform_driver(mchp_spdiftx_driver); 917 918 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 919 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver"); 920 MODULE_LICENSE("GPL v2"); 921