1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Copyright (c) 2022 Collabora Ltd. 5 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8 #include <dt-bindings/clock/mt8173-clk.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include "clk-cpumux.h" 12 #include "clk-gate.h" 13 #include "clk-mtk.h" 14 #include "reset.h" 15 16 #define GATE_ICG(_id, _name, _parent, _shift) \ 17 GATE_MTK(_id, _name, _parent, &infra_cg_regs, \ 18 _shift, &mtk_clk_gate_ops_setclr) 19 20 static struct clk_hw_onecell_data *infra_clk_data; 21 22 static const struct mtk_gate_regs infra_cg_regs = { 23 .set_ofs = 0x0040, 24 .clr_ofs = 0x0044, 25 .sta_ofs = 0x0048, 26 }; 27 28 static const char * const ca53_parents[] __initconst = { 29 "clk26m", 30 "armca7pll", 31 "mainpll", 32 "univpll" 33 }; 34 35 static const char * const ca72_parents[] __initconst = { 36 "clk26m", 37 "armca15pll", 38 "mainpll", 39 "univpll" 40 }; 41 42 static const struct mtk_composite cpu_muxes[] = { 43 MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), 44 MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), 45 }; 46 47 static const struct mtk_fixed_factor infra_early_divs[] = { 48 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 49 }; 50 51 static const struct mtk_gate infra_gates[] = { 52 GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 53 GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), 54 GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), 55 GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 56 GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), 57 GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 58 GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15), 59 GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 60 GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), 61 GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), 62 GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), 63 }; 64 65 static u16 infrasys_rst_ofs[] = { 0x30, 0x34 }; 66 67 static const struct mtk_clk_rst_desc clk_rst_desc = { 68 .version = MTK_RST_SIMPLE, 69 .rst_bank_ofs = infrasys_rst_ofs, 70 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 71 }; 72 73 static const struct of_device_id of_match_clk_mt8173_infracfg[] = { 74 { .compatible = "mediatek,mt8173-infracfg" }, 75 { /* sentinel */ } 76 }; 77 78 static void clk_mt8173_infra_init_early(struct device_node *node) 79 { 80 int i; 81 82 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 83 if (!infra_clk_data) 84 return; 85 86 for (i = 0; i < CLK_INFRA_NR_CLK; i++) 87 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 88 89 mtk_clk_register_factors(infra_early_divs, 90 ARRAY_SIZE(infra_early_divs), infra_clk_data); 91 92 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); 93 } 94 CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", 95 clk_mt8173_infra_init_early); 96 97 static int clk_mt8173_infracfg_probe(struct platform_device *pdev) 98 { 99 struct device_node *node = pdev->dev.of_node; 100 int r; 101 102 r = mtk_clk_register_gates(&pdev->dev, node, infra_gates, 103 ARRAY_SIZE(infra_gates), infra_clk_data); 104 if (r) 105 return r; 106 107 r = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, 108 ARRAY_SIZE(cpu_muxes), infra_clk_data); 109 if (r) 110 goto unregister_gates; 111 112 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); 113 if (r) 114 goto unregister_cpumuxes; 115 116 r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); 117 if (r) 118 goto unregister_clk_hw; 119 120 return 0; 121 122 unregister_clk_hw: 123 of_clk_del_provider(node); 124 unregister_cpumuxes: 125 mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data); 126 unregister_gates: 127 mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data); 128 return r; 129 } 130 131 static int clk_mt8173_infracfg_remove(struct platform_device *pdev) 132 { 133 struct device_node *node = pdev->dev.of_node; 134 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 135 136 of_clk_del_provider(node); 137 mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); 138 mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data); 139 mtk_free_clk_data(clk_data); 140 141 return 0; 142 } 143 144 static struct platform_driver clk_mt8173_infracfg_drv = { 145 .driver = { 146 .name = "clk-mt8173-infracfg", 147 .of_match_table = of_match_clk_mt8173_infracfg, 148 }, 149 .probe = clk_mt8173_infracfg_probe, 150 .remove = clk_mt8173_infracfg_remove, 151 }; 152 module_platform_driver(clk_mt8173_infracfg_drv); 153 154 MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver"); 155 MODULE_LICENSE("GPL"); 156