1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <448>; 103 dynamic-power-coefficient = <205>; 104 next-level-cache = <&L2_0>; 105 power-domains = <&CPU_PD0>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 operating-points-v2 = <&cpu0_opp_table>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 110 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 111 #cooling-cells = <2>; 112 L2_0: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-size = <0x20000>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 L3_0: l3-cache { 119 compatible = "cache"; 120 cache-level = <3>; 121 cache-size = <0x400000>; 122 cache-unified; 123 }; 124 }; 125 }; 126 127 CPU1: cpu@100 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x100>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <205>; 135 next-level-cache = <&L2_100>; 136 power-domains = <&CPU_PD1>; 137 power-domain-names = "psci"; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 142 #cooling-cells = <2>; 143 L2_100: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-size = <0x20000>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU2: cpu@200 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo485"; 155 reg = <0x0 0x200>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <448>; 159 dynamic-power-coefficient = <205>; 160 next-level-cache = <&L2_200>; 161 power-domains = <&CPU_PD2>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 166 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 167 #cooling-cells = <2>; 168 L2_200: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-size = <0x20000>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU3: cpu@300 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x300>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <448>; 184 dynamic-power-coefficient = <205>; 185 next-level-cache = <&L2_300>; 186 power-domains = <&CPU_PD3>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 191 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 192 #cooling-cells = <2>; 193 L2_300: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-size = <0x20000>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo485"; 205 reg = <0x0 0x400>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <379>; 210 next-level-cache = <&L2_400>; 211 power-domains = <&CPU_PD4>; 212 power-domain-names = "psci"; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu4_opp_table>; 215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 216 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 217 #cooling-cells = <2>; 218 L2_400: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-size = <0x40000>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU5: cpu@500 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo485"; 230 reg = <0x0 0x500>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1024>; 234 dynamic-power-coefficient = <379>; 235 next-level-cache = <&L2_500>; 236 power-domains = <&CPU_PD5>; 237 power-domain-names = "psci"; 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 operating-points-v2 = <&cpu4_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 241 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 242 #cooling-cells = <2>; 243 L2_500: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-size = <0x40000>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 CPU6: cpu@600 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo485"; 255 reg = <0x0 0x600>; 256 clocks = <&cpufreq_hw 1>; 257 enable-method = "psci"; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <379>; 260 next-level-cache = <&L2_600>; 261 power-domains = <&CPU_PD6>; 262 power-domain-names = "psci"; 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 operating-points-v2 = <&cpu4_opp_table>; 265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 266 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 267 #cooling-cells = <2>; 268 L2_600: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-size = <0x40000>; 272 cache-unified; 273 next-level-cache = <&L3_0>; 274 }; 275 }; 276 277 CPU7: cpu@700 { 278 device_type = "cpu"; 279 compatible = "qcom,kryo485"; 280 reg = <0x0 0x700>; 281 clocks = <&cpufreq_hw 2>; 282 enable-method = "psci"; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <444>; 285 next-level-cache = <&L2_700>; 286 power-domains = <&CPU_PD7>; 287 power-domain-names = "psci"; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 operating-points-v2 = <&cpu7_opp_table>; 290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 291 <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 292 #cooling-cells = <2>; 293 L2_700: l2-cache { 294 compatible = "cache"; 295 cache-level = <2>; 296 cache-size = <0x80000>; 297 cache-unified; 298 next-level-cache = <&L3_0>; 299 }; 300 }; 301 302 cpu-map { 303 cluster0 { 304 core0 { 305 cpu = <&CPU0>; 306 }; 307 308 core1 { 309 cpu = <&CPU1>; 310 }; 311 312 core2 { 313 cpu = <&CPU2>; 314 }; 315 316 core3 { 317 cpu = <&CPU3>; 318 }; 319 320 core4 { 321 cpu = <&CPU4>; 322 }; 323 324 core5 { 325 cpu = <&CPU5>; 326 }; 327 328 core6 { 329 cpu = <&CPU6>; 330 }; 331 332 core7 { 333 cpu = <&CPU7>; 334 }; 335 }; 336 }; 337 338 idle-states { 339 entry-method = "psci"; 340 341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "silver-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <360>; 346 exit-latency-us = <531>; 347 min-residency-us = <3934>; 348 local-timer-stop; 349 }; 350 351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "gold-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <702>; 356 exit-latency-us = <1061>; 357 min-residency-us = <4488>; 358 local-timer-stop; 359 }; 360 }; 361 362 domain-idle-states { 363 CLUSTER_SLEEP_0: cluster-sleep-0 { 364 compatible = "domain-idle-state"; 365 arm,psci-suspend-param = <0x4100c244>; 366 entry-latency-us = <3264>; 367 exit-latency-us = <6562>; 368 min-residency-us = <9987>; 369 }; 370 }; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 cpu0_opp1: opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <800000 9600000>; 380 }; 381 382 cpu0_opp2: opp-403200000 { 383 opp-hz = /bits/ 64 <403200000>; 384 opp-peak-kBps = <800000 9600000>; 385 }; 386 387 cpu0_opp3: opp-518400000 { 388 opp-hz = /bits/ 64 <518400000>; 389 opp-peak-kBps = <800000 16588800>; 390 }; 391 392 cpu0_opp4: opp-614400000 { 393 opp-hz = /bits/ 64 <614400000>; 394 opp-peak-kBps = <800000 16588800>; 395 }; 396 397 cpu0_opp5: opp-691200000 { 398 opp-hz = /bits/ 64 <691200000>; 399 opp-peak-kBps = <800000 19660800>; 400 }; 401 402 cpu0_opp6: opp-787200000 { 403 opp-hz = /bits/ 64 <787200000>; 404 opp-peak-kBps = <1804000 19660800>; 405 }; 406 407 cpu0_opp7: opp-883200000 { 408 opp-hz = /bits/ 64 <883200000>; 409 opp-peak-kBps = <1804000 23347200>; 410 }; 411 412 cpu0_opp8: opp-979200000 { 413 opp-hz = /bits/ 64 <979200000>; 414 opp-peak-kBps = <1804000 26419200>; 415 }; 416 417 cpu0_opp9: opp-1075200000 { 418 opp-hz = /bits/ 64 <1075200000>; 419 opp-peak-kBps = <1804000 29491200>; 420 }; 421 422 cpu0_opp10: opp-1171200000 { 423 opp-hz = /bits/ 64 <1171200000>; 424 opp-peak-kBps = <1804000 32563200>; 425 }; 426 427 cpu0_opp11: opp-1248000000 { 428 opp-hz = /bits/ 64 <1248000000>; 429 opp-peak-kBps = <1804000 36249600>; 430 }; 431 432 cpu0_opp12: opp-1344000000 { 433 opp-hz = /bits/ 64 <1344000000>; 434 opp-peak-kBps = <2188000 36249600>; 435 }; 436 437 cpu0_opp13: opp-1420800000 { 438 opp-hz = /bits/ 64 <1420800000>; 439 opp-peak-kBps = <2188000 39321600>; 440 }; 441 442 cpu0_opp14: opp-1516800000 { 443 opp-hz = /bits/ 64 <1516800000>; 444 opp-peak-kBps = <3072000 42393600>; 445 }; 446 447 cpu0_opp15: opp-1612800000 { 448 opp-hz = /bits/ 64 <1612800000>; 449 opp-peak-kBps = <3072000 42393600>; 450 }; 451 452 cpu0_opp16: opp-1708800000 { 453 opp-hz = /bits/ 64 <1708800000>; 454 opp-peak-kBps = <4068000 42393600>; 455 }; 456 457 cpu0_opp17: opp-1804800000 { 458 opp-hz = /bits/ 64 <1804800000>; 459 opp-peak-kBps = <4068000 42393600>; 460 }; 461 }; 462 463 cpu4_opp_table: opp-table-cpu4 { 464 compatible = "operating-points-v2"; 465 opp-shared; 466 467 cpu4_opp1: opp-710400000 { 468 opp-hz = /bits/ 64 <710400000>; 469 opp-peak-kBps = <1804000 19660800>; 470 }; 471 472 cpu4_opp2: opp-825600000 { 473 opp-hz = /bits/ 64 <825600000>; 474 opp-peak-kBps = <2188000 23347200>; 475 }; 476 477 cpu4_opp3: opp-940800000 { 478 opp-hz = /bits/ 64 <940800000>; 479 opp-peak-kBps = <2188000 26419200>; 480 }; 481 482 cpu4_opp4: opp-1056000000 { 483 opp-hz = /bits/ 64 <1056000000>; 484 opp-peak-kBps = <3072000 26419200>; 485 }; 486 487 cpu4_opp5: opp-1171200000 { 488 opp-hz = /bits/ 64 <1171200000>; 489 opp-peak-kBps = <3072000 29491200>; 490 }; 491 492 cpu4_opp6: opp-1286400000 { 493 opp-hz = /bits/ 64 <1286400000>; 494 opp-peak-kBps = <4068000 29491200>; 495 }; 496 497 cpu4_opp7: opp-1382400000 { 498 opp-hz = /bits/ 64 <1382400000>; 499 opp-peak-kBps = <4068000 32563200>; 500 }; 501 502 cpu4_opp8: opp-1478400000 { 503 opp-hz = /bits/ 64 <1478400000>; 504 opp-peak-kBps = <4068000 32563200>; 505 }; 506 507 cpu4_opp9: opp-1574400000 { 508 opp-hz = /bits/ 64 <1574400000>; 509 opp-peak-kBps = <5412000 39321600>; 510 }; 511 512 cpu4_opp10: opp-1670400000 { 513 opp-hz = /bits/ 64 <1670400000>; 514 opp-peak-kBps = <5412000 42393600>; 515 }; 516 517 cpu4_opp11: opp-1766400000 { 518 opp-hz = /bits/ 64 <1766400000>; 519 opp-peak-kBps = <5412000 45465600>; 520 }; 521 522 cpu4_opp12: opp-1862400000 { 523 opp-hz = /bits/ 64 <1862400000>; 524 opp-peak-kBps = <6220000 45465600>; 525 }; 526 527 cpu4_opp13: opp-1958400000 { 528 opp-hz = /bits/ 64 <1958400000>; 529 opp-peak-kBps = <6220000 48537600>; 530 }; 531 532 cpu4_opp14: opp-2054400000 { 533 opp-hz = /bits/ 64 <2054400000>; 534 opp-peak-kBps = <7216000 48537600>; 535 }; 536 537 cpu4_opp15: opp-2150400000 { 538 opp-hz = /bits/ 64 <2150400000>; 539 opp-peak-kBps = <7216000 51609600>; 540 }; 541 542 cpu4_opp16: opp-2246400000 { 543 opp-hz = /bits/ 64 <2246400000>; 544 opp-peak-kBps = <7216000 51609600>; 545 }; 546 547 cpu4_opp17: opp-2342400000 { 548 opp-hz = /bits/ 64 <2342400000>; 549 opp-peak-kBps = <8368000 51609600>; 550 }; 551 552 cpu4_opp18: opp-2419200000 { 553 opp-hz = /bits/ 64 <2419200000>; 554 opp-peak-kBps = <8368000 51609600>; 555 }; 556 }; 557 558 cpu7_opp_table: opp-table-cpu7 { 559 compatible = "operating-points-v2"; 560 opp-shared; 561 562 cpu7_opp1: opp-844800000 { 563 opp-hz = /bits/ 64 <844800000>; 564 opp-peak-kBps = <2188000 19660800>; 565 }; 566 567 cpu7_opp2: opp-960000000 { 568 opp-hz = /bits/ 64 <960000000>; 569 opp-peak-kBps = <2188000 26419200>; 570 }; 571 572 cpu7_opp3: opp-1075200000 { 573 opp-hz = /bits/ 64 <1075200000>; 574 opp-peak-kBps = <3072000 26419200>; 575 }; 576 577 cpu7_opp4: opp-1190400000 { 578 opp-hz = /bits/ 64 <1190400000>; 579 opp-peak-kBps = <3072000 29491200>; 580 }; 581 582 cpu7_opp5: opp-1305600000 { 583 opp-hz = /bits/ 64 <1305600000>; 584 opp-peak-kBps = <4068000 32563200>; 585 }; 586 587 cpu7_opp6: opp-1401600000 { 588 opp-hz = /bits/ 64 <1401600000>; 589 opp-peak-kBps = <4068000 32563200>; 590 }; 591 592 cpu7_opp7: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 36249600>; 595 }; 596 597 cpu7_opp8: opp-1632000000 { 598 opp-hz = /bits/ 64 <1632000000>; 599 opp-peak-kBps = <5412000 39321600>; 600 }; 601 602 cpu7_opp9: opp-1747200000 { 603 opp-hz = /bits/ 64 <1708800000>; 604 opp-peak-kBps = <5412000 42393600>; 605 }; 606 607 cpu7_opp10: opp-1862400000 { 608 opp-hz = /bits/ 64 <1862400000>; 609 opp-peak-kBps = <6220000 45465600>; 610 }; 611 612 cpu7_opp11: opp-1977600000 { 613 opp-hz = /bits/ 64 <1977600000>; 614 opp-peak-kBps = <6220000 48537600>; 615 }; 616 617 cpu7_opp12: opp-2073600000 { 618 opp-hz = /bits/ 64 <2073600000>; 619 opp-peak-kBps = <7216000 48537600>; 620 }; 621 622 cpu7_opp13: opp-2169600000 { 623 opp-hz = /bits/ 64 <2169600000>; 624 opp-peak-kBps = <7216000 51609600>; 625 }; 626 627 cpu7_opp14: opp-2265600000 { 628 opp-hz = /bits/ 64 <2265600000>; 629 opp-peak-kBps = <7216000 51609600>; 630 }; 631 632 cpu7_opp15: opp-2361600000 { 633 opp-hz = /bits/ 64 <2361600000>; 634 opp-peak-kBps = <8368000 51609600>; 635 }; 636 637 cpu7_opp16: opp-2457600000 { 638 opp-hz = /bits/ 64 <2457600000>; 639 opp-peak-kBps = <8368000 51609600>; 640 }; 641 642 cpu7_opp17: opp-2553600000 { 643 opp-hz = /bits/ 64 <2553600000>; 644 opp-peak-kBps = <8368000 51609600>; 645 }; 646 647 cpu7_opp18: opp-2649600000 { 648 opp-hz = /bits/ 64 <2649600000>; 649 opp-peak-kBps = <8368000 51609600>; 650 }; 651 652 cpu7_opp19: opp-2745600000 { 653 opp-hz = /bits/ 64 <2745600000>; 654 opp-peak-kBps = <8368000 51609600>; 655 }; 656 657 cpu7_opp20: opp-2841600000 { 658 opp-hz = /bits/ 64 <2841600000>; 659 opp-peak-kBps = <8368000 51609600>; 660 }; 661 }; 662 663 firmware { 664 scm: scm { 665 compatible = "qcom,scm-sm8250", "qcom,scm"; 666 #reset-cells = <1>; 667 }; 668 }; 669 670 memory@80000000 { 671 device_type = "memory"; 672 /* We expect the bootloader to fill in the size */ 673 reg = <0x0 0x80000000 0x0 0x0>; 674 }; 675 676 pmu { 677 compatible = "arm,armv8-pmuv3"; 678 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 679 }; 680 681 psci { 682 compatible = "arm,psci-1.0"; 683 method = "smc"; 684 685 CPU_PD0: power-domain-cpu0 { 686 #power-domain-cells = <0>; 687 power-domains = <&CLUSTER_PD>; 688 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 689 }; 690 691 CPU_PD1: power-domain-cpu1 { 692 #power-domain-cells = <0>; 693 power-domains = <&CLUSTER_PD>; 694 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 695 }; 696 697 CPU_PD2: power-domain-cpu2 { 698 #power-domain-cells = <0>; 699 power-domains = <&CLUSTER_PD>; 700 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 701 }; 702 703 CPU_PD3: power-domain-cpu3 { 704 #power-domain-cells = <0>; 705 power-domains = <&CLUSTER_PD>; 706 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 707 }; 708 709 CPU_PD4: power-domain-cpu4 { 710 #power-domain-cells = <0>; 711 power-domains = <&CLUSTER_PD>; 712 domain-idle-states = <&BIG_CPU_SLEEP_0>; 713 }; 714 715 CPU_PD5: power-domain-cpu5 { 716 #power-domain-cells = <0>; 717 power-domains = <&CLUSTER_PD>; 718 domain-idle-states = <&BIG_CPU_SLEEP_0>; 719 }; 720 721 CPU_PD6: power-domain-cpu6 { 722 #power-domain-cells = <0>; 723 power-domains = <&CLUSTER_PD>; 724 domain-idle-states = <&BIG_CPU_SLEEP_0>; 725 }; 726 727 CPU_PD7: power-domain-cpu7 { 728 #power-domain-cells = <0>; 729 power-domains = <&CLUSTER_PD>; 730 domain-idle-states = <&BIG_CPU_SLEEP_0>; 731 }; 732 733 CLUSTER_PD: power-domain-cpu-cluster0 { 734 #power-domain-cells = <0>; 735 domain-idle-states = <&CLUSTER_SLEEP_0>; 736 }; 737 }; 738 739 qup_opp_table: opp-table-qup { 740 compatible = "operating-points-v2"; 741 742 opp-50000000 { 743 opp-hz = /bits/ 64 <50000000>; 744 required-opps = <&rpmhpd_opp_min_svs>; 745 }; 746 747 opp-75000000 { 748 opp-hz = /bits/ 64 <75000000>; 749 required-opps = <&rpmhpd_opp_low_svs>; 750 }; 751 752 opp-120000000 { 753 opp-hz = /bits/ 64 <120000000>; 754 required-opps = <&rpmhpd_opp_svs>; 755 }; 756 }; 757 758 reserved-memory { 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges; 762 763 hyp_mem: memory@80000000 { 764 reg = <0x0 0x80000000 0x0 0x600000>; 765 no-map; 766 }; 767 768 xbl_aop_mem: memory@80700000 { 769 reg = <0x0 0x80700000 0x0 0x160000>; 770 no-map; 771 }; 772 773 cmd_db: memory@80860000 { 774 compatible = "qcom,cmd-db"; 775 reg = <0x0 0x80860000 0x0 0x20000>; 776 no-map; 777 }; 778 779 smem_mem: memory@80900000 { 780 reg = <0x0 0x80900000 0x0 0x200000>; 781 no-map; 782 }; 783 784 removed_mem: memory@80b00000 { 785 reg = <0x0 0x80b00000 0x0 0x5300000>; 786 no-map; 787 }; 788 789 camera_mem: memory@86200000 { 790 reg = <0x0 0x86200000 0x0 0x500000>; 791 no-map; 792 }; 793 794 wlan_mem: memory@86700000 { 795 reg = <0x0 0x86700000 0x0 0x100000>; 796 no-map; 797 }; 798 799 ipa_fw_mem: memory@86800000 { 800 reg = <0x0 0x86800000 0x0 0x10000>; 801 no-map; 802 }; 803 804 ipa_gsi_mem: memory@86810000 { 805 reg = <0x0 0x86810000 0x0 0xa000>; 806 no-map; 807 }; 808 809 gpu_mem: memory@8681a000 { 810 reg = <0x0 0x8681a000 0x0 0x2000>; 811 no-map; 812 }; 813 814 npu_mem: memory@86900000 { 815 reg = <0x0 0x86900000 0x0 0x500000>; 816 no-map; 817 }; 818 819 video_mem: memory@86e00000 { 820 reg = <0x0 0x86e00000 0x0 0x500000>; 821 no-map; 822 }; 823 824 cvp_mem: memory@87300000 { 825 reg = <0x0 0x87300000 0x0 0x500000>; 826 no-map; 827 }; 828 829 cdsp_mem: memory@87800000 { 830 reg = <0x0 0x87800000 0x0 0x1400000>; 831 no-map; 832 }; 833 834 slpi_mem: memory@88c00000 { 835 reg = <0x0 0x88c00000 0x0 0x1500000>; 836 no-map; 837 }; 838 839 adsp_mem: memory@8a100000 { 840 reg = <0x0 0x8a100000 0x0 0x1d00000>; 841 no-map; 842 }; 843 844 spss_mem: memory@8be00000 { 845 reg = <0x0 0x8be00000 0x0 0x100000>; 846 no-map; 847 }; 848 849 cdsp_secure_heap: memory@8bf00000 { 850 reg = <0x0 0x8bf00000 0x0 0x4600000>; 851 no-map; 852 }; 853 }; 854 855 smem { 856 compatible = "qcom,smem"; 857 memory-region = <&smem_mem>; 858 hwlocks = <&tcsr_mutex 3>; 859 }; 860 861 smp2p-adsp { 862 compatible = "qcom,smp2p"; 863 qcom,smem = <443>, <429>; 864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 865 IPCC_MPROC_SIGNAL_SMP2P 866 IRQ_TYPE_EDGE_RISING>; 867 mboxes = <&ipcc IPCC_CLIENT_LPASS 868 IPCC_MPROC_SIGNAL_SMP2P>; 869 870 qcom,local-pid = <0>; 871 qcom,remote-pid = <2>; 872 873 smp2p_adsp_out: master-kernel { 874 qcom,entry-name = "master-kernel"; 875 #qcom,smem-state-cells = <1>; 876 }; 877 878 smp2p_adsp_in: slave-kernel { 879 qcom,entry-name = "slave-kernel"; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 }; 884 885 smp2p-cdsp { 886 compatible = "qcom,smp2p"; 887 qcom,smem = <94>, <432>; 888 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 889 IPCC_MPROC_SIGNAL_SMP2P 890 IRQ_TYPE_EDGE_RISING>; 891 mboxes = <&ipcc IPCC_CLIENT_CDSP 892 IPCC_MPROC_SIGNAL_SMP2P>; 893 894 qcom,local-pid = <0>; 895 qcom,remote-pid = <5>; 896 897 smp2p_cdsp_out: master-kernel { 898 qcom,entry-name = "master-kernel"; 899 #qcom,smem-state-cells = <1>; 900 }; 901 902 smp2p_cdsp_in: slave-kernel { 903 qcom,entry-name = "slave-kernel"; 904 interrupt-controller; 905 #interrupt-cells = <2>; 906 }; 907 }; 908 909 smp2p-slpi { 910 compatible = "qcom,smp2p"; 911 qcom,smem = <481>, <430>; 912 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 913 IPCC_MPROC_SIGNAL_SMP2P 914 IRQ_TYPE_EDGE_RISING>; 915 mboxes = <&ipcc IPCC_CLIENT_SLPI 916 IPCC_MPROC_SIGNAL_SMP2P>; 917 918 qcom,local-pid = <0>; 919 qcom,remote-pid = <3>; 920 921 smp2p_slpi_out: master-kernel { 922 qcom,entry-name = "master-kernel"; 923 #qcom,smem-state-cells = <1>; 924 }; 925 926 smp2p_slpi_in: slave-kernel { 927 qcom,entry-name = "slave-kernel"; 928 interrupt-controller; 929 #interrupt-cells = <2>; 930 }; 931 }; 932 933 soc: soc@0 { 934 #address-cells = <2>; 935 #size-cells = <2>; 936 ranges = <0 0 0 0 0x10 0>; 937 dma-ranges = <0 0 0 0 0x10 0>; 938 compatible = "simple-bus"; 939 940 gcc: clock-controller@100000 { 941 compatible = "qcom,gcc-sm8250"; 942 reg = <0x0 0x00100000 0x0 0x1f0000>; 943 #clock-cells = <1>; 944 #reset-cells = <1>; 945 #power-domain-cells = <1>; 946 clock-names = "bi_tcxo", 947 "bi_tcxo_ao", 948 "sleep_clk"; 949 clocks = <&rpmhcc RPMH_CXO_CLK>, 950 <&rpmhcc RPMH_CXO_CLK_A>, 951 <&sleep_clk>; 952 }; 953 954 ipcc: mailbox@408000 { 955 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 956 reg = <0 0x00408000 0 0x1000>; 957 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-controller; 959 #interrupt-cells = <3>; 960 #mbox-cells = <2>; 961 }; 962 963 qfprom: efuse@784000 { 964 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 965 reg = <0 0x00784000 0 0x8ff>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 969 gpu_speed_bin: gpu_speed_bin@19b { 970 reg = <0x19b 0x1>; 971 bits = <5 3>; 972 }; 973 }; 974 975 rng: rng@793000 { 976 compatible = "qcom,prng-ee"; 977 reg = <0 0x00793000 0 0x1000>; 978 clocks = <&gcc GCC_PRNG_AHB_CLK>; 979 clock-names = "core"; 980 }; 981 982 gpi_dma2: dma-controller@800000 { 983 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 984 reg = <0 0x00800000 0 0x70000>; 985 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 995 dma-channels = <10>; 996 dma-channel-mask = <0x3f>; 997 iommus = <&apps_smmu 0x76 0x0>; 998 #dma-cells = <3>; 999 status = "disabled"; 1000 }; 1001 1002 qupv3_id_2: geniqup@8c0000 { 1003 compatible = "qcom,geni-se-qup"; 1004 reg = <0x0 0x008c0000 0x0 0x6000>; 1005 clock-names = "m-ahb", "s-ahb"; 1006 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1007 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1008 #address-cells = <2>; 1009 #size-cells = <2>; 1010 iommus = <&apps_smmu 0x63 0x0>; 1011 ranges; 1012 status = "disabled"; 1013 1014 i2c14: i2c@880000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x00880000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c14_default>; 1021 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1022 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1023 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi14: spi@880000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0 0x00880000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1035 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1036 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 power-domains = <&rpmhpd SM8250_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c15: i2c@884000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x00884000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c15_default>; 1053 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1054 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 spi15: spi@884000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x00884000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1067 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1069 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1070 dma-names = "tx", "rx"; 1071 power-domains = <&rpmhpd SM8250_CX>; 1072 operating-points-v2 = <&qup_opp_table>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 i2c16: i2c@888000 { 1079 compatible = "qcom,geni-i2c"; 1080 reg = <0 0x00888000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&qup_i2c16_default>; 1085 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 spi16: spi@888000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0 0x00888000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1099 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1100 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1101 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1102 dma-names = "tx", "rx"; 1103 power-domains = <&rpmhpd SM8250_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c17: i2c@88c000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x0088c000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c17_default>; 1117 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1118 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1119 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 spi17: spi@88c000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x0088c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1131 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1133 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1134 dma-names = "tx", "rx"; 1135 power-domains = <&rpmhpd SM8250_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 uart17: serial@88c000 { 1143 compatible = "qcom,geni-uart"; 1144 reg = <0 0x0088c000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_uart17_default>; 1149 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SM8250_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c18: i2c@890000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00890000 0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_i2c18_default>; 1162 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1163 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1164 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi18: spi@890000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x00890000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd SM8250_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart18: serial@890000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x00890000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart18_default>; 1194 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1195 power-domains = <&rpmhpd SM8250_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c19: i2c@894000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00894000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c19_default>; 1207 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1209 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1210 dma-names = "tx", "rx"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 spi19: spi@894000 { 1217 compatible = "qcom,geni-spi"; 1218 reg = <0 0x00894000 0 0x4000>; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1223 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd SM8250_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 gpi_dma0: dma-controller@900000 { 1234 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1235 reg = <0 0x00900000 0 0x70000>; 1236 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1249 dma-channels = <15>; 1250 dma-channel-mask = <0x7ff>; 1251 iommus = <&apps_smmu 0x5b6 0x0>; 1252 #dma-cells = <3>; 1253 status = "disabled"; 1254 }; 1255 1256 qupv3_id_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-qup"; 1258 reg = <0x0 0x009c0000 0x0 0x6000>; 1259 clock-names = "m-ahb", "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1261 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1262 #address-cells = <2>; 1263 #size-cells = <2>; 1264 iommus = <&apps_smmu 0x5a3 0x0>; 1265 ranges; 1266 status = "disabled"; 1267 1268 i2c0: i2c@980000 { 1269 compatible = "qcom,geni-i2c"; 1270 reg = <0 0x00980000 0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_i2c0_default>; 1275 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1277 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1278 dma-names = "tx", "rx"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 spi0: spi@980000 { 1285 compatible = "qcom,geni-spi"; 1286 reg = <0 0x00980000 0 0x4000>; 1287 clock-names = "se"; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1289 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 i2c1: i2c@984000 { 1301 compatible = "qcom,geni-i2c"; 1302 reg = <0 0x00984000 0 0x4000>; 1303 clock-names = "se"; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&qup_i2c1_default>; 1307 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1309 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 spi1: spi@984000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00984000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1321 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1322 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1323 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1324 dma-names = "tx", "rx"; 1325 power-domains = <&rpmhpd SM8250_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 i2c2: i2c@988000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00988000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c2_default>; 1339 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1340 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1341 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1342 dma-names = "tx", "rx"; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 spi2: spi@988000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00988000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1353 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1354 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1355 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1356 dma-names = "tx", "rx"; 1357 power-domains = <&rpmhpd SM8250_CX>; 1358 operating-points-v2 = <&qup_opp_table>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart2: serial@988000 { 1365 compatible = "qcom,geni-debug-uart"; 1366 reg = <0 0x00988000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_uart2_default>; 1371 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1372 power-domains = <&rpmhpd SM8250_CX>; 1373 operating-points-v2 = <&qup_opp_table>; 1374 status = "disabled"; 1375 }; 1376 1377 i2c3: i2c@98c000 { 1378 compatible = "qcom,geni-i2c"; 1379 reg = <0 0x0098c000 0 0x4000>; 1380 clock-names = "se"; 1381 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_i2c3_default>; 1384 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1386 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1387 dma-names = "tx", "rx"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 spi3: spi@98c000 { 1394 compatible = "qcom,geni-spi"; 1395 reg = <0 0x0098c000 0 0x4000>; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1398 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1399 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1400 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1401 dma-names = "tx", "rx"; 1402 power-domains = <&rpmhpd SM8250_CX>; 1403 operating-points-v2 = <&qup_opp_table>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c4: i2c@990000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00990000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_i2c4_default>; 1416 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1417 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi4: spi@990000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00990000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1430 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1432 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 power-domains = <&rpmhpd SM8250_CX>; 1435 operating-points-v2 = <&qup_opp_table>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 i2c5: i2c@994000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0 0x00994000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_i2c5_default>; 1448 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1450 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1451 dma-names = "tx", "rx"; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 spi5: spi@994000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x00994000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1462 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1463 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1464 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1465 dma-names = "tx", "rx"; 1466 power-domains = <&rpmhpd SM8250_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 i2c6: i2c@998000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0 0x00998000 0 0x4000>; 1476 clock-names = "se"; 1477 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_i2c6_default>; 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1482 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1483 dma-names = "tx", "rx"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 spi6: spi@998000 { 1490 compatible = "qcom,geni-spi"; 1491 reg = <0 0x00998000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1494 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1495 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1496 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1497 dma-names = "tx", "rx"; 1498 power-domains = <&rpmhpd SM8250_CX>; 1499 operating-points-v2 = <&qup_opp_table>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 uart6: serial@998000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x00998000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart6_default>; 1512 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SM8250_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 status = "disabled"; 1516 }; 1517 1518 i2c7: i2c@99c000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x0099c000 0 0x4000>; 1521 clock-names = "se"; 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c7_default>; 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1527 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 spi7: spi@99c000 { 1535 compatible = "qcom,geni-spi"; 1536 reg = <0 0x0099c000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1539 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1540 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 power-domains = <&rpmhpd SM8250_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 gpi_dma1: dma-controller@a00000 { 1552 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1553 reg = <0 0x00a00000 0 0x70000>; 1554 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1564 dma-channels = <10>; 1565 dma-channel-mask = <0x3f>; 1566 iommus = <&apps_smmu 0x56 0x0>; 1567 #dma-cells = <3>; 1568 status = "disabled"; 1569 }; 1570 1571 qupv3_id_1: geniqup@ac0000 { 1572 compatible = "qcom,geni-se-qup"; 1573 reg = <0x0 0x00ac0000 0x0 0x6000>; 1574 clock-names = "m-ahb", "s-ahb"; 1575 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1576 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 iommus = <&apps_smmu 0x43 0x0>; 1580 ranges; 1581 status = "disabled"; 1582 1583 i2c8: i2c@a80000 { 1584 compatible = "qcom,geni-i2c"; 1585 reg = <0 0x00a80000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_i2c8_default>; 1590 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1591 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1592 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1593 dma-names = "tx", "rx"; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 spi8: spi@a80000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00a80000 0 0x4000>; 1602 clock-names = "se"; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1604 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1605 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 power-domains = <&rpmhpd SM8250_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 1615 i2c9: i2c@a84000 { 1616 compatible = "qcom,geni-i2c"; 1617 reg = <0 0x00a84000 0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = <&qup_i2c9_default>; 1622 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1623 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1624 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1625 dma-names = "tx", "rx"; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 status = "disabled"; 1629 }; 1630 1631 spi9: spi@a84000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0 0x00a84000 0 0x4000>; 1634 clock-names = "se"; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1637 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1638 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1639 dma-names = "tx", "rx"; 1640 power-domains = <&rpmhpd SM8250_CX>; 1641 operating-points-v2 = <&qup_opp_table>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 i2c10: i2c@a88000 { 1648 compatible = "qcom,geni-i2c"; 1649 reg = <0 0x00a88000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_i2c10_default>; 1654 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1656 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1657 dma-names = "tx", "rx"; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 status = "disabled"; 1661 }; 1662 1663 spi10: spi@a88000 { 1664 compatible = "qcom,geni-spi"; 1665 reg = <0 0x00a88000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1670 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1671 dma-names = "tx", "rx"; 1672 power-domains = <&rpmhpd SM8250_CX>; 1673 operating-points-v2 = <&qup_opp_table>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 i2c11: i2c@a8c000 { 1680 compatible = "qcom,geni-i2c"; 1681 reg = <0 0x00a8c000 0 0x4000>; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_i2c11_default>; 1686 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1687 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi11: spi@a8c000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0 0x00a8c000 0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1701 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1702 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 power-domains = <&rpmhpd SM8250_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 status = "disabled"; 1709 }; 1710 1711 i2c12: i2c@a90000 { 1712 compatible = "qcom,geni-i2c"; 1713 reg = <0 0x00a90000 0 0x4000>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_i2c12_default>; 1718 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1720 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1721 dma-names = "tx", "rx"; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 spi12: spi@a90000 { 1728 compatible = "qcom,geni-spi"; 1729 reg = <0 0x00a90000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1732 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1734 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd SM8250_CX>; 1737 operating-points-v2 = <&qup_opp_table>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 uart12: serial@a90000 { 1744 compatible = "qcom,geni-debug-uart"; 1745 reg = <0x0 0x00a90000 0x0 0x4000>; 1746 clock-names = "se"; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_uart12_default>; 1750 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1751 power-domains = <&rpmhpd SM8250_CX>; 1752 operating-points-v2 = <&qup_opp_table>; 1753 status = "disabled"; 1754 }; 1755 1756 i2c13: i2c@a94000 { 1757 compatible = "qcom,geni-i2c"; 1758 reg = <0 0x00a94000 0 0x4000>; 1759 clock-names = "se"; 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&qup_i2c13_default>; 1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1764 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 spi13: spi@a94000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a94000 0 0x4000>; 1775 clock-names = "se"; 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1777 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 power-domains = <&rpmhpd SM8250_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 }; 1788 1789 config_noc: interconnect@1500000 { 1790 compatible = "qcom,sm8250-config-noc"; 1791 reg = <0 0x01500000 0 0xa580>; 1792 #interconnect-cells = <2>; 1793 qcom,bcm-voters = <&apps_bcm_voter>; 1794 }; 1795 1796 system_noc: interconnect@1620000 { 1797 compatible = "qcom,sm8250-system-noc"; 1798 reg = <0 0x01620000 0 0x1c200>; 1799 #interconnect-cells = <2>; 1800 qcom,bcm-voters = <&apps_bcm_voter>; 1801 }; 1802 1803 mc_virt: interconnect@163d000 { 1804 compatible = "qcom,sm8250-mc-virt"; 1805 reg = <0 0x0163d000 0 0x1000>; 1806 #interconnect-cells = <2>; 1807 qcom,bcm-voters = <&apps_bcm_voter>; 1808 }; 1809 1810 aggre1_noc: interconnect@16e0000 { 1811 compatible = "qcom,sm8250-aggre1-noc"; 1812 reg = <0 0x016e0000 0 0x1f180>; 1813 #interconnect-cells = <2>; 1814 qcom,bcm-voters = <&apps_bcm_voter>; 1815 }; 1816 1817 aggre2_noc: interconnect@1700000 { 1818 compatible = "qcom,sm8250-aggre2-noc"; 1819 reg = <0 0x01700000 0 0x33000>; 1820 #interconnect-cells = <2>; 1821 qcom,bcm-voters = <&apps_bcm_voter>; 1822 }; 1823 1824 compute_noc: interconnect@1733000 { 1825 compatible = "qcom,sm8250-compute-noc"; 1826 reg = <0 0x01733000 0 0xa180>; 1827 #interconnect-cells = <2>; 1828 qcom,bcm-voters = <&apps_bcm_voter>; 1829 }; 1830 1831 mmss_noc: interconnect@1740000 { 1832 compatible = "qcom,sm8250-mmss-noc"; 1833 reg = <0 0x01740000 0 0x1f080>; 1834 #interconnect-cells = <2>; 1835 qcom,bcm-voters = <&apps_bcm_voter>; 1836 }; 1837 1838 pcie0: pci@1c00000 { 1839 compatible = "qcom,pcie-sm8250"; 1840 reg = <0 0x01c00000 0 0x3000>, 1841 <0 0x60000000 0 0xf1d>, 1842 <0 0x60000f20 0 0xa8>, 1843 <0 0x60001000 0 0x1000>, 1844 <0 0x60100000 0 0x100000>, 1845 <0 0x01c03000 0 0x1000>; 1846 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1847 device_type = "pci"; 1848 linux,pci-domain = <0>; 1849 bus-range = <0x00 0xff>; 1850 num-lanes = <1>; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 1855 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1856 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1857 1858 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1866 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1867 "msi4", "msi5", "msi6", "msi7"; 1868 #interrupt-cells = <1>; 1869 interrupt-map-mask = <0 0 0 0x7>; 1870 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1871 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1872 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1873 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1874 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1876 <&gcc GCC_PCIE_0_AUX_CLK>, 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1880 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1881 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1882 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1883 clock-names = "pipe", 1884 "aux", 1885 "cfg", 1886 "bus_master", 1887 "bus_slave", 1888 "slave_q2a", 1889 "tbu", 1890 "ddrss_sf_tbu"; 1891 1892 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1893 <0x100 &apps_smmu 0x1c01 0x1>; 1894 1895 resets = <&gcc GCC_PCIE_0_BCR>; 1896 reset-names = "pci"; 1897 1898 power-domains = <&gcc PCIE_0_GDSC>; 1899 1900 phys = <&pcie0_lane>; 1901 phy-names = "pciephy"; 1902 1903 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1904 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1905 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&pcie0_default_state>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 pcie0_phy: phy@1c06000 { 1913 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1914 reg = <0 0x01c06000 0 0x1c0>; 1915 #address-cells = <2>; 1916 #size-cells = <2>; 1917 ranges; 1918 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1919 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1920 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1921 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1922 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1923 1924 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1925 reset-names = "phy"; 1926 1927 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1928 assigned-clock-rates = <100000000>; 1929 1930 status = "disabled"; 1931 1932 pcie0_lane: phy@1c06200 { 1933 reg = <0 0x01c06200 0 0x170>, /* tx */ 1934 <0 0x01c06400 0 0x200>, /* rx */ 1935 <0 0x01c06800 0 0x1f0>, /* pcs */ 1936 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1938 clock-names = "pipe0"; 1939 1940 #phy-cells = <0>; 1941 1942 #clock-cells = <0>; 1943 clock-output-names = "pcie_0_pipe_clk"; 1944 }; 1945 }; 1946 1947 pcie1: pci@1c08000 { 1948 compatible = "qcom,pcie-sm8250"; 1949 reg = <0 0x01c08000 0 0x3000>, 1950 <0 0x40000000 0 0xf1d>, 1951 <0 0x40000f20 0 0xa8>, 1952 <0 0x40001000 0 0x1000>, 1953 <0 0x40100000 0 0x100000>, 1954 <0 0x01c0b000 0 0x1000>; 1955 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1956 device_type = "pci"; 1957 linux,pci-domain = <1>; 1958 bus-range = <0x00 0xff>; 1959 num-lanes = <2>; 1960 1961 #address-cells = <3>; 1962 #size-cells = <2>; 1963 1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1966 1967 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1968 interrupt-names = "msi"; 1969 #interrupt-cells = <1>; 1970 interrupt-map-mask = <0 0 0 0x7>; 1971 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1972 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1973 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1974 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1975 1976 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1977 <&gcc GCC_PCIE_1_AUX_CLK>, 1978 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1979 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1980 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1981 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1982 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1983 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1984 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1985 clock-names = "pipe", 1986 "aux", 1987 "cfg", 1988 "bus_master", 1989 "bus_slave", 1990 "slave_q2a", 1991 "ref", 1992 "tbu", 1993 "ddrss_sf_tbu"; 1994 1995 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1996 assigned-clock-rates = <19200000>; 1997 1998 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1999 <0x100 &apps_smmu 0x1c81 0x1>; 2000 2001 resets = <&gcc GCC_PCIE_1_BCR>; 2002 reset-names = "pci"; 2003 2004 power-domains = <&gcc PCIE_1_GDSC>; 2005 2006 phys = <&pcie1_lane>; 2007 phy-names = "pciephy"; 2008 2009 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2010 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2011 2012 pinctrl-names = "default"; 2013 pinctrl-0 = <&pcie1_default_state>; 2014 2015 status = "disabled"; 2016 }; 2017 2018 pcie1_phy: phy@1c0e000 { 2019 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2020 reg = <0 0x01c0e000 0 0x1c0>; 2021 #address-cells = <2>; 2022 #size-cells = <2>; 2023 ranges; 2024 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2025 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2026 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2027 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2028 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2029 2030 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2031 reset-names = "phy"; 2032 2033 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2034 assigned-clock-rates = <100000000>; 2035 2036 status = "disabled"; 2037 2038 pcie1_lane: phy@1c0e200 { 2039 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2040 <0 0x01c0e400 0 0x200>, /* rx0 */ 2041 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2042 <0 0x01c0e600 0 0x170>, /* tx1 */ 2043 <0 0x01c0e800 0 0x200>, /* rx1 */ 2044 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2045 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2046 clock-names = "pipe0"; 2047 2048 #phy-cells = <0>; 2049 2050 #clock-cells = <0>; 2051 clock-output-names = "pcie_1_pipe_clk"; 2052 }; 2053 }; 2054 2055 pcie2: pci@1c10000 { 2056 compatible = "qcom,pcie-sm8250"; 2057 reg = <0 0x01c10000 0 0x3000>, 2058 <0 0x64000000 0 0xf1d>, 2059 <0 0x64000f20 0 0xa8>, 2060 <0 0x64001000 0 0x1000>, 2061 <0 0x64100000 0 0x100000>, 2062 <0 0x01c13000 0 0x1000>; 2063 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2064 device_type = "pci"; 2065 linux,pci-domain = <2>; 2066 bus-range = <0x00 0xff>; 2067 num-lanes = <2>; 2068 2069 #address-cells = <3>; 2070 #size-cells = <2>; 2071 2072 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2073 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2074 2075 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2076 interrupt-names = "msi"; 2077 #interrupt-cells = <1>; 2078 interrupt-map-mask = <0 0 0 0x7>; 2079 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2080 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2081 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2082 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2083 2084 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2085 <&gcc GCC_PCIE_2_AUX_CLK>, 2086 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2087 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2088 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2089 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2090 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2091 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2092 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2093 clock-names = "pipe", 2094 "aux", 2095 "cfg", 2096 "bus_master", 2097 "bus_slave", 2098 "slave_q2a", 2099 "ref", 2100 "tbu", 2101 "ddrss_sf_tbu"; 2102 2103 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2104 assigned-clock-rates = <19200000>; 2105 2106 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2107 <0x100 &apps_smmu 0x1d01 0x1>; 2108 2109 resets = <&gcc GCC_PCIE_2_BCR>; 2110 reset-names = "pci"; 2111 2112 power-domains = <&gcc PCIE_2_GDSC>; 2113 2114 phys = <&pcie2_lane>; 2115 phy-names = "pciephy"; 2116 2117 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2118 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2119 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&pcie2_default_state>; 2122 2123 status = "disabled"; 2124 }; 2125 2126 pcie2_phy: phy@1c16000 { 2127 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2128 reg = <0 0x01c16000 0 0x1c0>; 2129 #address-cells = <2>; 2130 #size-cells = <2>; 2131 ranges; 2132 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2133 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2134 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2135 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2136 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2137 2138 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2139 reset-names = "phy"; 2140 2141 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2142 assigned-clock-rates = <100000000>; 2143 2144 status = "disabled"; 2145 2146 pcie2_lane: phy@1c16200 { 2147 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2148 <0 0x01c16400 0 0x200>, /* rx0 */ 2149 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2150 <0 0x01c16600 0 0x170>, /* tx1 */ 2151 <0 0x01c16800 0 0x200>, /* rx1 */ 2152 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2153 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2154 clock-names = "pipe0"; 2155 2156 #phy-cells = <0>; 2157 2158 #clock-cells = <0>; 2159 clock-output-names = "pcie_2_pipe_clk"; 2160 }; 2161 }; 2162 2163 ufs_mem_hc: ufshc@1d84000 { 2164 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2165 "jedec,ufs-2.0"; 2166 reg = <0 0x01d84000 0 0x3000>; 2167 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2168 phys = <&ufs_mem_phy_lanes>; 2169 phy-names = "ufsphy"; 2170 lanes-per-direction = <2>; 2171 #reset-cells = <1>; 2172 resets = <&gcc GCC_UFS_PHY_BCR>; 2173 reset-names = "rst"; 2174 2175 power-domains = <&gcc UFS_PHY_GDSC>; 2176 2177 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2178 2179 clock-names = 2180 "core_clk", 2181 "bus_aggr_clk", 2182 "iface_clk", 2183 "core_clk_unipro", 2184 "ref_clk", 2185 "tx_lane0_sync_clk", 2186 "rx_lane0_sync_clk", 2187 "rx_lane1_sync_clk"; 2188 clocks = 2189 <&gcc GCC_UFS_PHY_AXI_CLK>, 2190 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2191 <&gcc GCC_UFS_PHY_AHB_CLK>, 2192 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2193 <&rpmhcc RPMH_CXO_CLK>, 2194 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2195 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2196 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2197 freq-table-hz = 2198 <37500000 300000000>, 2199 <0 0>, 2200 <0 0>, 2201 <37500000 300000000>, 2202 <0 0>, 2203 <0 0>, 2204 <0 0>, 2205 <0 0>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 ufs_mem_phy: phy@1d87000 { 2211 compatible = "qcom,sm8250-qmp-ufs-phy"; 2212 reg = <0 0x01d87000 0 0x1c0>; 2213 #address-cells = <2>; 2214 #size-cells = <2>; 2215 ranges; 2216 clock-names = "ref", 2217 "ref_aux"; 2218 clocks = <&rpmhcc RPMH_CXO_CLK>, 2219 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2220 2221 resets = <&ufs_mem_hc 0>; 2222 reset-names = "ufsphy"; 2223 status = "disabled"; 2224 2225 ufs_mem_phy_lanes: phy@1d87400 { 2226 reg = <0 0x01d87400 0 0x16c>, 2227 <0 0x01d87600 0 0x200>, 2228 <0 0x01d87c00 0 0x200>, 2229 <0 0x01d87800 0 0x16c>, 2230 <0 0x01d87a00 0 0x200>; 2231 #phy-cells = <0>; 2232 }; 2233 }; 2234 2235 cryptobam: dma-controller@1dc4000 { 2236 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2237 reg = <0 0x01dc4000 0 0x24000>; 2238 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2239 #dma-cells = <1>; 2240 qcom,ee = <0>; 2241 qcom,controlled-remotely; 2242 num-channels = <8>; 2243 qcom,num-ees = <2>; 2244 iommus = <&apps_smmu 0x592 0x0000>, 2245 <&apps_smmu 0x598 0x0000>, 2246 <&apps_smmu 0x599 0x0000>, 2247 <&apps_smmu 0x59f 0x0000>, 2248 <&apps_smmu 0x586 0x0011>, 2249 <&apps_smmu 0x596 0x0011>; 2250 }; 2251 2252 crypto: crypto@1dfa000 { 2253 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2254 reg = <0 0x01dfa000 0 0x6000>; 2255 dmas = <&cryptobam 4>, <&cryptobam 5>; 2256 dma-names = "rx", "tx"; 2257 iommus = <&apps_smmu 0x592 0x0000>, 2258 <&apps_smmu 0x598 0x0000>, 2259 <&apps_smmu 0x599 0x0000>, 2260 <&apps_smmu 0x59f 0x0000>, 2261 <&apps_smmu 0x586 0x0011>, 2262 <&apps_smmu 0x596 0x0011>; 2263 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2264 interconnect-names = "memory"; 2265 }; 2266 2267 tcsr_mutex: hwlock@1f40000 { 2268 compatible = "qcom,tcsr-mutex"; 2269 reg = <0x0 0x01f40000 0x0 0x40000>; 2270 #hwlock-cells = <1>; 2271 }; 2272 2273 wsamacro: codec@3240000 { 2274 compatible = "qcom,sm8250-lpass-wsa-macro"; 2275 reg = <0 0x03240000 0 0x1000>; 2276 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2277 <&audiocc LPASS_CDC_WSA_NPL>, 2278 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2279 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2280 <&aoncc LPASS_CDC_VA_MCLK>, 2281 <&vamacro>; 2282 2283 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2284 2285 #clock-cells = <0>; 2286 clock-output-names = "mclk"; 2287 #sound-dai-cells = <1>; 2288 2289 pinctrl-names = "default"; 2290 pinctrl-0 = <&wsa_swr_active>; 2291 2292 status = "disabled"; 2293 }; 2294 2295 swr0: soundwire-controller@3250000 { 2296 reg = <0 0x03250000 0 0x2000>; 2297 compatible = "qcom,soundwire-v1.5.1"; 2298 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&wsamacro>; 2300 clock-names = "iface"; 2301 2302 qcom,din-ports = <2>; 2303 qcom,dout-ports = <6>; 2304 2305 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2306 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2307 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2308 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2309 2310 #sound-dai-cells = <1>; 2311 #address-cells = <2>; 2312 #size-cells = <0>; 2313 2314 status = "disabled"; 2315 }; 2316 2317 audiocc: clock-controller@3300000 { 2318 compatible = "qcom,sm8250-lpass-audiocc"; 2319 reg = <0 0x03300000 0 0x30000>; 2320 #clock-cells = <1>; 2321 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2322 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2323 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2324 clock-names = "core", "audio", "bus"; 2325 }; 2326 2327 vamacro: codec@3370000 { 2328 compatible = "qcom,sm8250-lpass-va-macro"; 2329 reg = <0 0x03370000 0 0x1000>; 2330 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2331 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2332 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2333 2334 clock-names = "mclk", "macro", "dcodec"; 2335 2336 #clock-cells = <0>; 2337 clock-output-names = "fsgen"; 2338 #sound-dai-cells = <1>; 2339 }; 2340 2341 rxmacro: rxmacro@3200000 { 2342 pinctrl-names = "default"; 2343 pinctrl-0 = <&rx_swr_active>; 2344 compatible = "qcom,sm8250-lpass-rx-macro"; 2345 reg = <0 0x03200000 0 0x1000>; 2346 status = "disabled"; 2347 2348 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2349 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2350 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2351 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2352 <&vamacro>; 2353 2354 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2355 2356 #clock-cells = <0>; 2357 clock-output-names = "mclk"; 2358 #sound-dai-cells = <1>; 2359 }; 2360 2361 swr1: soundwire-controller@3210000 { 2362 reg = <0 0x03210000 0 0x2000>; 2363 compatible = "qcom,soundwire-v1.5.1"; 2364 status = "disabled"; 2365 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2366 clocks = <&rxmacro>; 2367 clock-names = "iface"; 2368 label = "RX"; 2369 qcom,din-ports = <0>; 2370 qcom,dout-ports = <5>; 2371 2372 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2373 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2374 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2375 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2376 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2377 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2378 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2379 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2380 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2381 2382 #sound-dai-cells = <1>; 2383 #address-cells = <2>; 2384 #size-cells = <0>; 2385 }; 2386 2387 txmacro: txmacro@3220000 { 2388 pinctrl-names = "default"; 2389 pinctrl-0 = <&tx_swr_active>; 2390 compatible = "qcom,sm8250-lpass-tx-macro"; 2391 reg = <0 0x03220000 0 0x1000>; 2392 status = "disabled"; 2393 2394 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2395 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2396 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2397 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2398 <&vamacro>; 2399 2400 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2401 2402 #clock-cells = <0>; 2403 clock-output-names = "mclk"; 2404 #sound-dai-cells = <1>; 2405 }; 2406 2407 /* tx macro */ 2408 swr2: soundwire-controller@3230000 { 2409 reg = <0 0x03230000 0 0x2000>; 2410 compatible = "qcom,soundwire-v1.5.1"; 2411 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2412 interrupt-names = "core"; 2413 status = "disabled"; 2414 2415 clocks = <&txmacro>; 2416 clock-names = "iface"; 2417 label = "TX"; 2418 2419 qcom,din-ports = <5>; 2420 qcom,dout-ports = <0>; 2421 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2422 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2423 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2424 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2425 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2426 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2427 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2428 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2429 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2430 #sound-dai-cells = <1>; 2431 #address-cells = <2>; 2432 #size-cells = <0>; 2433 }; 2434 2435 aoncc: clock-controller@3380000 { 2436 compatible = "qcom,sm8250-lpass-aoncc"; 2437 reg = <0 0x03380000 0 0x40000>; 2438 #clock-cells = <1>; 2439 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2440 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2441 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2442 clock-names = "core", "audio", "bus"; 2443 }; 2444 2445 lpass_tlmm: pinctrl@33c0000 { 2446 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2447 reg = <0 0x033c0000 0x0 0x20000>, 2448 <0 0x03550000 0x0 0x10000>; 2449 gpio-controller; 2450 #gpio-cells = <2>; 2451 gpio-ranges = <&lpass_tlmm 0 0 14>; 2452 2453 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2454 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2455 clock-names = "core", "audio"; 2456 2457 wsa_swr_active: wsa-swr-active-state { 2458 clk-pins { 2459 pins = "gpio10"; 2460 function = "wsa_swr_clk"; 2461 drive-strength = <2>; 2462 slew-rate = <1>; 2463 bias-disable; 2464 }; 2465 2466 data-pins { 2467 pins = "gpio11"; 2468 function = "wsa_swr_data"; 2469 drive-strength = <2>; 2470 slew-rate = <1>; 2471 bias-bus-hold; 2472 }; 2473 }; 2474 2475 wsa_swr_sleep: wsa-swr-sleep-state { 2476 clk-pins { 2477 pins = "gpio10"; 2478 function = "wsa_swr_clk"; 2479 drive-strength = <2>; 2480 bias-pull-down; 2481 }; 2482 2483 data-pins { 2484 pins = "gpio11"; 2485 function = "wsa_swr_data"; 2486 drive-strength = <2>; 2487 bias-pull-down; 2488 }; 2489 }; 2490 2491 dmic01_active: dmic01-active-state { 2492 clk-pins { 2493 pins = "gpio6"; 2494 function = "dmic1_clk"; 2495 drive-strength = <8>; 2496 output-high; 2497 }; 2498 data-pins { 2499 pins = "gpio7"; 2500 function = "dmic1_data"; 2501 drive-strength = <8>; 2502 }; 2503 }; 2504 2505 dmic01_sleep: dmic01-sleep-state { 2506 clk-pins { 2507 pins = "gpio6"; 2508 function = "dmic1_clk"; 2509 drive-strength = <2>; 2510 bias-disable; 2511 output-low; 2512 }; 2513 2514 data-pins { 2515 pins = "gpio7"; 2516 function = "dmic1_data"; 2517 drive-strength = <2>; 2518 bias-pull-down; 2519 }; 2520 }; 2521 2522 rx_swr_active: rx-swr-active-state { 2523 clk-pins { 2524 pins = "gpio3"; 2525 function = "swr_rx_clk"; 2526 drive-strength = <2>; 2527 slew-rate = <1>; 2528 bias-disable; 2529 }; 2530 2531 data-pins { 2532 pins = "gpio4", "gpio5"; 2533 function = "swr_rx_data"; 2534 drive-strength = <2>; 2535 slew-rate = <1>; 2536 bias-bus-hold; 2537 }; 2538 }; 2539 2540 tx_swr_active: tx-swr-active-state { 2541 clk-pins { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 drive-strength = <2>; 2545 slew-rate = <1>; 2546 bias-disable; 2547 }; 2548 2549 data-pins { 2550 pins = "gpio1", "gpio2"; 2551 function = "swr_tx_data"; 2552 drive-strength = <2>; 2553 slew-rate = <1>; 2554 bias-bus-hold; 2555 }; 2556 }; 2557 2558 tx_swr_sleep: tx-swr-sleep-state { 2559 clk-pins { 2560 pins = "gpio0"; 2561 function = "swr_tx_clk"; 2562 drive-strength = <2>; 2563 bias-pull-down; 2564 }; 2565 2566 data1-pins { 2567 pins = "gpio1"; 2568 function = "swr_tx_data"; 2569 drive-strength = <2>; 2570 bias-bus-hold; 2571 }; 2572 2573 data2-pins { 2574 pins = "gpio2"; 2575 function = "swr_tx_data"; 2576 drive-strength = <2>; 2577 bias-pull-down; 2578 }; 2579 }; 2580 }; 2581 2582 gpu: gpu@3d00000 { 2583 compatible = "qcom,adreno-650.2", 2584 "qcom,adreno"; 2585 2586 reg = <0 0x03d00000 0 0x40000>; 2587 reg-names = "kgsl_3d0_reg_memory"; 2588 2589 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2590 2591 iommus = <&adreno_smmu 0 0x401>; 2592 2593 operating-points-v2 = <&gpu_opp_table>; 2594 2595 qcom,gmu = <&gmu>; 2596 2597 nvmem-cells = <&gpu_speed_bin>; 2598 nvmem-cell-names = "speed_bin"; 2599 2600 status = "disabled"; 2601 2602 zap-shader { 2603 memory-region = <&gpu_mem>; 2604 }; 2605 2606 gpu_opp_table: opp-table { 2607 compatible = "operating-points-v2"; 2608 2609 opp-670000000 { 2610 opp-hz = /bits/ 64 <670000000>; 2611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2612 opp-supported-hw = <0xa>; 2613 }; 2614 2615 opp-587000000 { 2616 opp-hz = /bits/ 64 <587000000>; 2617 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2618 opp-supported-hw = <0xb>; 2619 }; 2620 2621 opp-525000000 { 2622 opp-hz = /bits/ 64 <525000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2624 opp-supported-hw = <0xf>; 2625 }; 2626 2627 opp-490000000 { 2628 opp-hz = /bits/ 64 <490000000>; 2629 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2630 opp-supported-hw = <0xf>; 2631 }; 2632 2633 opp-441600000 { 2634 opp-hz = /bits/ 64 <441600000>; 2635 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2636 opp-supported-hw = <0xf>; 2637 }; 2638 2639 opp-400000000 { 2640 opp-hz = /bits/ 64 <400000000>; 2641 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2642 opp-supported-hw = <0xf>; 2643 }; 2644 2645 opp-305000000 { 2646 opp-hz = /bits/ 64 <305000000>; 2647 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2648 opp-supported-hw = <0xf>; 2649 }; 2650 }; 2651 }; 2652 2653 gmu: gmu@3d6a000 { 2654 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2655 2656 reg = <0 0x03d6a000 0 0x30000>, 2657 <0 0x3de0000 0 0x10000>, 2658 <0 0xb290000 0 0x10000>, 2659 <0 0xb490000 0 0x10000>; 2660 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2661 2662 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2664 interrupt-names = "hfi", "gmu"; 2665 2666 clocks = <&gpucc GPU_CC_AHB_CLK>, 2667 <&gpucc GPU_CC_CX_GMU_CLK>, 2668 <&gpucc GPU_CC_CXO_CLK>, 2669 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2670 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2671 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2672 2673 power-domains = <&gpucc GPU_CX_GDSC>, 2674 <&gpucc GPU_GX_GDSC>; 2675 power-domain-names = "cx", "gx"; 2676 2677 iommus = <&adreno_smmu 5 0x400>; 2678 2679 operating-points-v2 = <&gmu_opp_table>; 2680 2681 status = "disabled"; 2682 2683 gmu_opp_table: opp-table { 2684 compatible = "operating-points-v2"; 2685 2686 opp-200000000 { 2687 opp-hz = /bits/ 64 <200000000>; 2688 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2689 }; 2690 }; 2691 }; 2692 2693 gpucc: clock-controller@3d90000 { 2694 compatible = "qcom,sm8250-gpucc"; 2695 reg = <0 0x03d90000 0 0x9000>; 2696 clocks = <&rpmhcc RPMH_CXO_CLK>, 2697 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2698 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2699 clock-names = "bi_tcxo", 2700 "gcc_gpu_gpll0_clk_src", 2701 "gcc_gpu_gpll0_div_clk_src"; 2702 #clock-cells = <1>; 2703 #reset-cells = <1>; 2704 #power-domain-cells = <1>; 2705 }; 2706 2707 adreno_smmu: iommu@3da0000 { 2708 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 2709 "qcom,smmu-500", "arm,mmu-500"; 2710 reg = <0 0x03da0000 0 0x10000>; 2711 #iommu-cells = <2>; 2712 #global-interrupts = <2>; 2713 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2723 clocks = <&gpucc GPU_CC_AHB_CLK>, 2724 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2725 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2726 clock-names = "ahb", "bus", "iface"; 2727 2728 power-domains = <&gpucc GPU_CX_GDSC>; 2729 }; 2730 2731 slpi: remoteproc@5c00000 { 2732 compatible = "qcom,sm8250-slpi-pas"; 2733 reg = <0 0x05c00000 0 0x4000>; 2734 2735 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2736 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2737 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2738 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2739 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2740 interrupt-names = "wdog", "fatal", "ready", 2741 "handover", "stop-ack"; 2742 2743 clocks = <&rpmhcc RPMH_CXO_CLK>; 2744 clock-names = "xo"; 2745 2746 power-domains = <&rpmhpd SM8250_LCX>, 2747 <&rpmhpd SM8250_LMX>; 2748 power-domain-names = "lcx", "lmx"; 2749 2750 memory-region = <&slpi_mem>; 2751 2752 qcom,qmp = <&aoss_qmp>; 2753 2754 qcom,smem-states = <&smp2p_slpi_out 0>; 2755 qcom,smem-state-names = "stop"; 2756 2757 status = "disabled"; 2758 2759 glink-edge { 2760 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2761 IPCC_MPROC_SIGNAL_GLINK_QMP 2762 IRQ_TYPE_EDGE_RISING>; 2763 mboxes = <&ipcc IPCC_CLIENT_SLPI 2764 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2765 2766 label = "slpi"; 2767 qcom,remote-pid = <3>; 2768 2769 fastrpc { 2770 compatible = "qcom,fastrpc"; 2771 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2772 label = "sdsp"; 2773 qcom,non-secure-domain; 2774 #address-cells = <1>; 2775 #size-cells = <0>; 2776 2777 compute-cb@1 { 2778 compatible = "qcom,fastrpc-compute-cb"; 2779 reg = <1>; 2780 iommus = <&apps_smmu 0x0541 0x0>; 2781 }; 2782 2783 compute-cb@2 { 2784 compatible = "qcom,fastrpc-compute-cb"; 2785 reg = <2>; 2786 iommus = <&apps_smmu 0x0542 0x0>; 2787 }; 2788 2789 compute-cb@3 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <3>; 2792 iommus = <&apps_smmu 0x0543 0x0>; 2793 /* note: shared-cb = <4> in downstream */ 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 stm@6002000 { 2800 compatible = "arm,coresight-stm", "arm,primecell"; 2801 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2802 reg-names = "stm-base", "stm-stimulus-base"; 2803 2804 clocks = <&aoss_qmp>; 2805 clock-names = "apb_pclk"; 2806 2807 out-ports { 2808 port { 2809 stm_out: endpoint { 2810 remote-endpoint = <&funnel0_in7>; 2811 }; 2812 }; 2813 }; 2814 }; 2815 2816 tpda@6004000 { 2817 compatible = "qcom,coresight-tpda", "arm,primecell"; 2818 reg = <0 0x06004000 0 0x1000>; 2819 2820 clocks = <&aoss_qmp>; 2821 clock-names = "apb_pclk"; 2822 2823 out-ports { 2824 #address-cells = <1>; 2825 #size-cells = <0>; 2826 2827 port@0 { 2828 reg = <0>; 2829 tpda_out_funnel_qatb: endpoint { 2830 remote-endpoint = <&funnel_qatb_in_tpda>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@9 { 2840 reg = <9>; 2841 tpda_9_in_tpdm_mm: endpoint { 2842 remote-endpoint = <&tpdm_mm_out_tpda9>; 2843 }; 2844 }; 2845 2846 port@17 { 2847 reg = <23>; 2848 tpda_23_in_tpdm_prng: endpoint { 2849 remote-endpoint = <&tpdm_prng_out_tpda_23>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 funnel@6005000 { 2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2857 reg = <0 0x06005000 0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 out-ports { 2863 port { 2864 funnel_qatb_out_funnel_in0: endpoint { 2865 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 2866 }; 2867 }; 2868 }; 2869 2870 in-ports { 2871 #address-cells = <1>; 2872 #size-cells = <0>; 2873 2874 port@0 { 2875 reg = <0>; 2876 funnel_qatb_in_tpda: endpoint { 2877 remote-endpoint = <&tpda_out_funnel_qatb>; 2878 }; 2879 }; 2880 }; 2881 }; 2882 2883 funnel@6041000 { 2884 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2885 reg = <0 0x06041000 0 0x1000>; 2886 2887 clocks = <&aoss_qmp>; 2888 clock-names = "apb_pclk"; 2889 2890 out-ports { 2891 port { 2892 funnel_in0_out_funnel_merg: endpoint { 2893 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2894 }; 2895 }; 2896 }; 2897 2898 in-ports { 2899 #address-cells = <1>; 2900 #size-cells = <0>; 2901 2902 port@6 { 2903 reg = <6>; 2904 funnel_in0_in_funnel_qatb: endpoint { 2905 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 2906 }; 2907 }; 2908 2909 port@7 { 2910 reg = <7>; 2911 funnel0_in7: endpoint { 2912 remote-endpoint = <&stm_out>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 funnel@6042000 { 2919 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2920 reg = <0 0x06042000 0 0x1000>; 2921 2922 clocks = <&aoss_qmp>; 2923 clock-names = "apb_pclk"; 2924 2925 out-ports { 2926 port { 2927 funnel_in1_out_funnel_merg: endpoint { 2928 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2929 }; 2930 }; 2931 }; 2932 2933 in-ports { 2934 #address-cells = <1>; 2935 #size-cells = <0>; 2936 2937 port@4 { 2938 reg = <4>; 2939 funnel_in1_in_funnel_apss_merg: endpoint { 2940 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 funnel@6045000 { 2947 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2948 reg = <0 0x06045000 0 0x1000>; 2949 2950 clocks = <&aoss_qmp>; 2951 clock-names = "apb_pclk"; 2952 2953 out-ports { 2954 port { 2955 funnel_merg_out_funnel_swao: endpoint { 2956 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2957 }; 2958 }; 2959 }; 2960 2961 in-ports { 2962 #address-cells = <1>; 2963 #size-cells = <0>; 2964 2965 port@0 { 2966 reg = <0>; 2967 funnel_merg_in_funnel_in0: endpoint { 2968 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2969 }; 2970 }; 2971 2972 port@1 { 2973 reg = <1>; 2974 funnel_merg_in_funnel_in1: endpoint { 2975 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 replicator@6046000 { 2982 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2983 reg = <0 0x06046000 0 0x1000>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 2988 out-ports { 2989 port { 2990 replicator_out: endpoint { 2991 remote-endpoint = <&etr_in>; 2992 }; 2993 }; 2994 }; 2995 2996 in-ports { 2997 port { 2998 replicator_cx_in_swao_out: endpoint { 2999 remote-endpoint = <&replicator_swao_out_cx_in>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 etr@6048000 { 3006 compatible = "arm,coresight-tmc", "arm,primecell"; 3007 reg = <0 0x06048000 0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 arm,scatter-gather; 3012 3013 in-ports { 3014 port { 3015 etr_in: endpoint { 3016 remote-endpoint = <&replicator_out>; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 tpdm@684c000 { 3023 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3024 reg = <0 0x0684c000 0 0x1000>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 3029 out-ports { 3030 port { 3031 tpdm_prng_out_tpda_23: endpoint { 3032 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 funnel@6b04000 { 3039 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3040 arm,primecell-periphid = <0x000bb908>; 3041 3042 reg = <0 0x06b04000 0 0x1000>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 3047 out-ports { 3048 port { 3049 funnel_swao_out_etf: endpoint { 3050 remote-endpoint = <&etf_in_funnel_swao_out>; 3051 }; 3052 }; 3053 }; 3054 3055 in-ports { 3056 #address-cells = <1>; 3057 #size-cells = <0>; 3058 3059 port@7 { 3060 reg = <7>; 3061 funnel_swao_in_funnel_merg: endpoint { 3062 remote-endpoint= <&funnel_merg_out_funnel_swao>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 etf@6b05000 { 3069 compatible = "arm,coresight-tmc", "arm,primecell"; 3070 reg = <0 0x06b05000 0 0x1000>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 3075 out-ports { 3076 port { 3077 etf_out: endpoint { 3078 remote-endpoint = <&replicator_in>; 3079 }; 3080 }; 3081 }; 3082 3083 in-ports { 3084 #address-cells = <1>; 3085 #size-cells = <0>; 3086 3087 port@0 { 3088 reg = <0>; 3089 etf_in_funnel_swao_out: endpoint { 3090 remote-endpoint = <&funnel_swao_out_etf>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 replicator@6b06000 { 3097 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3098 reg = <0 0x06b06000 0 0x1000>; 3099 3100 clocks = <&aoss_qmp>; 3101 clock-names = "apb_pclk"; 3102 3103 out-ports { 3104 port { 3105 replicator_swao_out_cx_in: endpoint { 3106 remote-endpoint = <&replicator_cx_in_swao_out>; 3107 }; 3108 }; 3109 }; 3110 3111 in-ports { 3112 port { 3113 replicator_in: endpoint { 3114 remote-endpoint = <&etf_out>; 3115 }; 3116 }; 3117 }; 3118 }; 3119 3120 tpdm@6c08000 { 3121 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3122 reg = <0 0x06c08000 0 0x1000>; 3123 3124 clocks = <&aoss_qmp>; 3125 clock-names = "apb_pclk"; 3126 3127 out-ports { 3128 port { 3129 tpdm_mm_out_funnel_dl_mm: endpoint { 3130 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 funnel@6c0b000 { 3137 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3138 reg = <0 0x06c0b000 0 0x1000>; 3139 3140 clocks = <&aoss_qmp>; 3141 clock-names = "apb_pclk"; 3142 3143 out-ports { 3144 port { 3145 funnel_dl_mm_out_funnel_dl_center: endpoint { 3146 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3147 }; 3148 }; 3149 }; 3150 3151 in-ports { 3152 #address-cells = <1>; 3153 #size-cells = <0>; 3154 3155 port@3 { 3156 reg = <3>; 3157 funnel_dl_mm_in_tpdm_mm: endpoint { 3158 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3159 }; 3160 }; 3161 }; 3162 }; 3163 3164 funnel@6c2d000 { 3165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3166 reg = <0 0x06c2d000 0 0x1000>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 3171 out-ports { 3172 #address-cells = <1>; 3173 #size-cells = <0>; 3174 port { 3175 tpdm_mm_out_tpda9: endpoint { 3176 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3177 }; 3178 }; 3179 }; 3180 3181 in-ports { 3182 #address-cells = <1>; 3183 #size-cells = <0>; 3184 3185 port@2 { 3186 reg = <2>; 3187 funnel_dl_center_in_funnel_dl_mm: endpoint { 3188 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3189 }; 3190 }; 3191 }; 3192 }; 3193 3194 etm@7040000 { 3195 compatible = "arm,coresight-etm4x", "arm,primecell"; 3196 reg = <0 0x07040000 0 0x1000>; 3197 3198 cpu = <&CPU0>; 3199 3200 clocks = <&aoss_qmp>; 3201 clock-names = "apb_pclk"; 3202 arm,coresight-loses-context-with-cpu; 3203 3204 out-ports { 3205 port { 3206 etm0_out: endpoint { 3207 remote-endpoint = <&apss_funnel_in0>; 3208 }; 3209 }; 3210 }; 3211 }; 3212 3213 etm@7140000 { 3214 compatible = "arm,coresight-etm4x", "arm,primecell"; 3215 reg = <0 0x07140000 0 0x1000>; 3216 3217 cpu = <&CPU1>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 arm,coresight-loses-context-with-cpu; 3222 3223 out-ports { 3224 port { 3225 etm1_out: endpoint { 3226 remote-endpoint = <&apss_funnel_in1>; 3227 }; 3228 }; 3229 }; 3230 }; 3231 3232 etm@7240000 { 3233 compatible = "arm,coresight-etm4x", "arm,primecell"; 3234 reg = <0 0x07240000 0 0x1000>; 3235 3236 cpu = <&CPU2>; 3237 3238 clocks = <&aoss_qmp>; 3239 clock-names = "apb_pclk"; 3240 arm,coresight-loses-context-with-cpu; 3241 3242 out-ports { 3243 port { 3244 etm2_out: endpoint { 3245 remote-endpoint = <&apss_funnel_in2>; 3246 }; 3247 }; 3248 }; 3249 }; 3250 3251 etm@7340000 { 3252 compatible = "arm,coresight-etm4x", "arm,primecell"; 3253 reg = <0 0x07340000 0 0x1000>; 3254 3255 cpu = <&CPU3>; 3256 3257 clocks = <&aoss_qmp>; 3258 clock-names = "apb_pclk"; 3259 arm,coresight-loses-context-with-cpu; 3260 3261 out-ports { 3262 port { 3263 etm3_out: endpoint { 3264 remote-endpoint = <&apss_funnel_in3>; 3265 }; 3266 }; 3267 }; 3268 }; 3269 3270 etm@7440000 { 3271 compatible = "arm,coresight-etm4x", "arm,primecell"; 3272 reg = <0 0x07440000 0 0x1000>; 3273 3274 cpu = <&CPU4>; 3275 3276 clocks = <&aoss_qmp>; 3277 clock-names = "apb_pclk"; 3278 arm,coresight-loses-context-with-cpu; 3279 3280 out-ports { 3281 port { 3282 etm4_out: endpoint { 3283 remote-endpoint = <&apss_funnel_in4>; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 etm@7540000 { 3290 compatible = "arm,coresight-etm4x", "arm,primecell"; 3291 reg = <0 0x07540000 0 0x1000>; 3292 3293 cpu = <&CPU5>; 3294 3295 clocks = <&aoss_qmp>; 3296 clock-names = "apb_pclk"; 3297 arm,coresight-loses-context-with-cpu; 3298 3299 out-ports { 3300 port { 3301 etm5_out: endpoint { 3302 remote-endpoint = <&apss_funnel_in5>; 3303 }; 3304 }; 3305 }; 3306 }; 3307 3308 etm@7640000 { 3309 compatible = "arm,coresight-etm4x", "arm,primecell"; 3310 reg = <0 0x07640000 0 0x1000>; 3311 3312 cpu = <&CPU6>; 3313 3314 clocks = <&aoss_qmp>; 3315 clock-names = "apb_pclk"; 3316 arm,coresight-loses-context-with-cpu; 3317 3318 out-ports { 3319 port { 3320 etm6_out: endpoint { 3321 remote-endpoint = <&apss_funnel_in6>; 3322 }; 3323 }; 3324 }; 3325 }; 3326 3327 etm@7740000 { 3328 compatible = "arm,coresight-etm4x", "arm,primecell"; 3329 reg = <0 0x07740000 0 0x1000>; 3330 3331 cpu = <&CPU7>; 3332 3333 clocks = <&aoss_qmp>; 3334 clock-names = "apb_pclk"; 3335 arm,coresight-loses-context-with-cpu; 3336 3337 out-ports { 3338 port { 3339 etm7_out: endpoint { 3340 remote-endpoint = <&apss_funnel_in7>; 3341 }; 3342 }; 3343 }; 3344 }; 3345 3346 funnel@7800000 { 3347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3348 reg = <0 0x07800000 0 0x1000>; 3349 3350 clocks = <&aoss_qmp>; 3351 clock-names = "apb_pclk"; 3352 3353 out-ports { 3354 port { 3355 funnel_apss_out_funnel_apss_merg: endpoint { 3356 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3357 }; 3358 }; 3359 }; 3360 3361 in-ports { 3362 #address-cells = <1>; 3363 #size-cells = <0>; 3364 3365 port@0 { 3366 reg = <0>; 3367 apss_funnel_in0: endpoint { 3368 remote-endpoint = <&etm0_out>; 3369 }; 3370 }; 3371 3372 port@1 { 3373 reg = <1>; 3374 apss_funnel_in1: endpoint { 3375 remote-endpoint = <&etm1_out>; 3376 }; 3377 }; 3378 3379 port@2 { 3380 reg = <2>; 3381 apss_funnel_in2: endpoint { 3382 remote-endpoint = <&etm2_out>; 3383 }; 3384 }; 3385 3386 port@3 { 3387 reg = <3>; 3388 apss_funnel_in3: endpoint { 3389 remote-endpoint = <&etm3_out>; 3390 }; 3391 }; 3392 3393 port@4 { 3394 reg = <4>; 3395 apss_funnel_in4: endpoint { 3396 remote-endpoint = <&etm4_out>; 3397 }; 3398 }; 3399 3400 port@5 { 3401 reg = <5>; 3402 apss_funnel_in5: endpoint { 3403 remote-endpoint = <&etm5_out>; 3404 }; 3405 }; 3406 3407 port@6 { 3408 reg = <6>; 3409 apss_funnel_in6: endpoint { 3410 remote-endpoint = <&etm6_out>; 3411 }; 3412 }; 3413 3414 port@7 { 3415 reg = <7>; 3416 apss_funnel_in7: endpoint { 3417 remote-endpoint = <&etm7_out>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 funnel@7810000 { 3424 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3425 reg = <0 0x07810000 0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 3430 out-ports { 3431 port { 3432 funnel_apss_merg_out_funnel_in1: endpoint { 3433 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3434 }; 3435 }; 3436 }; 3437 3438 in-ports { 3439 #address-cells = <1>; 3440 #size-cells = <0>; 3441 3442 port@0 { 3443 reg = <0>; 3444 funnel_apss_merg_in_funnel_apss: endpoint { 3445 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 cdsp: remoteproc@8300000 { 3452 compatible = "qcom,sm8250-cdsp-pas"; 3453 reg = <0 0x08300000 0 0x10000>; 3454 3455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3456 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3457 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3458 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3459 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3460 interrupt-names = "wdog", "fatal", "ready", 3461 "handover", "stop-ack"; 3462 3463 clocks = <&rpmhcc RPMH_CXO_CLK>; 3464 clock-names = "xo"; 3465 3466 power-domains = <&rpmhpd SM8250_CX>; 3467 3468 memory-region = <&cdsp_mem>; 3469 3470 qcom,qmp = <&aoss_qmp>; 3471 3472 qcom,smem-states = <&smp2p_cdsp_out 0>; 3473 qcom,smem-state-names = "stop"; 3474 3475 status = "disabled"; 3476 3477 glink-edge { 3478 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3479 IPCC_MPROC_SIGNAL_GLINK_QMP 3480 IRQ_TYPE_EDGE_RISING>; 3481 mboxes = <&ipcc IPCC_CLIENT_CDSP 3482 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3483 3484 label = "cdsp"; 3485 qcom,remote-pid = <5>; 3486 3487 fastrpc { 3488 compatible = "qcom,fastrpc"; 3489 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3490 label = "cdsp"; 3491 qcom,non-secure-domain; 3492 #address-cells = <1>; 3493 #size-cells = <0>; 3494 3495 compute-cb@1 { 3496 compatible = "qcom,fastrpc-compute-cb"; 3497 reg = <1>; 3498 iommus = <&apps_smmu 0x1001 0x0460>; 3499 }; 3500 3501 compute-cb@2 { 3502 compatible = "qcom,fastrpc-compute-cb"; 3503 reg = <2>; 3504 iommus = <&apps_smmu 0x1002 0x0460>; 3505 }; 3506 3507 compute-cb@3 { 3508 compatible = "qcom,fastrpc-compute-cb"; 3509 reg = <3>; 3510 iommus = <&apps_smmu 0x1003 0x0460>; 3511 }; 3512 3513 compute-cb@4 { 3514 compatible = "qcom,fastrpc-compute-cb"; 3515 reg = <4>; 3516 iommus = <&apps_smmu 0x1004 0x0460>; 3517 }; 3518 3519 compute-cb@5 { 3520 compatible = "qcom,fastrpc-compute-cb"; 3521 reg = <5>; 3522 iommus = <&apps_smmu 0x1005 0x0460>; 3523 }; 3524 3525 compute-cb@6 { 3526 compatible = "qcom,fastrpc-compute-cb"; 3527 reg = <6>; 3528 iommus = <&apps_smmu 0x1006 0x0460>; 3529 }; 3530 3531 compute-cb@7 { 3532 compatible = "qcom,fastrpc-compute-cb"; 3533 reg = <7>; 3534 iommus = <&apps_smmu 0x1007 0x0460>; 3535 }; 3536 3537 compute-cb@8 { 3538 compatible = "qcom,fastrpc-compute-cb"; 3539 reg = <8>; 3540 iommus = <&apps_smmu 0x1008 0x0460>; 3541 }; 3542 3543 /* note: secure cb9 in downstream */ 3544 }; 3545 }; 3546 }; 3547 3548 usb_1_hsphy: phy@88e3000 { 3549 compatible = "qcom,sm8250-usb-hs-phy", 3550 "qcom,usb-snps-hs-7nm-phy"; 3551 reg = <0 0x088e3000 0 0x400>; 3552 status = "disabled"; 3553 #phy-cells = <0>; 3554 3555 clocks = <&rpmhcc RPMH_CXO_CLK>; 3556 clock-names = "ref"; 3557 3558 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3559 }; 3560 3561 usb_2_hsphy: phy@88e4000 { 3562 compatible = "qcom,sm8250-usb-hs-phy", 3563 "qcom,usb-snps-hs-7nm-phy"; 3564 reg = <0 0x088e4000 0 0x400>; 3565 status = "disabled"; 3566 #phy-cells = <0>; 3567 3568 clocks = <&rpmhcc RPMH_CXO_CLK>; 3569 clock-names = "ref"; 3570 3571 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3572 }; 3573 3574 usb_1_qmpphy: phy@88e9000 { 3575 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3576 reg = <0 0x088e9000 0 0x200>, 3577 <0 0x088e8000 0 0x40>, 3578 <0 0x088ea000 0 0x200>; 3579 status = "disabled"; 3580 #address-cells = <2>; 3581 #size-cells = <2>; 3582 ranges; 3583 3584 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3585 <&rpmhcc RPMH_CXO_CLK>, 3586 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3587 clock-names = "aux", "ref_clk_src", "com_aux"; 3588 3589 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3590 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3591 reset-names = "phy", "common"; 3592 3593 usb_1_ssphy: usb3-phy@88e9200 { 3594 reg = <0 0x088e9200 0 0x200>, 3595 <0 0x088e9400 0 0x200>, 3596 <0 0x088e9c00 0 0x400>, 3597 <0 0x088e9600 0 0x200>, 3598 <0 0x088e9800 0 0x200>, 3599 <0 0x088e9a00 0 0x100>; 3600 #clock-cells = <0>; 3601 #phy-cells = <0>; 3602 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3603 clock-names = "pipe0"; 3604 clock-output-names = "usb3_phy_pipe_clk_src"; 3605 }; 3606 3607 dp_phy: dp-phy@88ea200 { 3608 reg = <0 0x088ea200 0 0x200>, 3609 <0 0x088ea400 0 0x200>, 3610 <0 0x088eaa00 0 0x200>, 3611 <0 0x088ea600 0 0x200>, 3612 <0 0x088ea800 0 0x200>; 3613 #phy-cells = <0>; 3614 #clock-cells = <1>; 3615 }; 3616 }; 3617 3618 usb_2_qmpphy: phy@88eb000 { 3619 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3620 reg = <0 0x088eb000 0 0x200>; 3621 status = "disabled"; 3622 #address-cells = <2>; 3623 #size-cells = <2>; 3624 ranges; 3625 3626 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3627 <&rpmhcc RPMH_CXO_CLK>, 3628 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3629 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3630 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3631 3632 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3633 <&gcc GCC_USB3_PHY_SEC_BCR>; 3634 reset-names = "phy", "common"; 3635 3636 usb_2_ssphy: phy@88eb200 { 3637 reg = <0 0x088eb200 0 0x200>, 3638 <0 0x088eb400 0 0x200>, 3639 <0 0x088eb800 0 0x800>; 3640 #clock-cells = <0>; 3641 #phy-cells = <0>; 3642 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3643 clock-names = "pipe0"; 3644 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3645 }; 3646 }; 3647 3648 sdhc_2: mmc@8804000 { 3649 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3650 reg = <0 0x08804000 0 0x1000>; 3651 3652 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3654 interrupt-names = "hc_irq", "pwr_irq"; 3655 3656 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3657 <&gcc GCC_SDCC2_APPS_CLK>, 3658 <&rpmhcc RPMH_CXO_CLK>; 3659 clock-names = "iface", "core", "xo"; 3660 iommus = <&apps_smmu 0x4a0 0x0>; 3661 qcom,dll-config = <0x0007642c>; 3662 qcom,ddr-config = <0x80040868>; 3663 power-domains = <&rpmhpd SM8250_CX>; 3664 operating-points-v2 = <&sdhc2_opp_table>; 3665 3666 status = "disabled"; 3667 3668 sdhc2_opp_table: opp-table { 3669 compatible = "operating-points-v2"; 3670 3671 opp-19200000 { 3672 opp-hz = /bits/ 64 <19200000>; 3673 required-opps = <&rpmhpd_opp_min_svs>; 3674 }; 3675 3676 opp-50000000 { 3677 opp-hz = /bits/ 64 <50000000>; 3678 required-opps = <&rpmhpd_opp_low_svs>; 3679 }; 3680 3681 opp-100000000 { 3682 opp-hz = /bits/ 64 <100000000>; 3683 required-opps = <&rpmhpd_opp_svs>; 3684 }; 3685 3686 opp-202000000 { 3687 opp-hz = /bits/ 64 <202000000>; 3688 required-opps = <&rpmhpd_opp_svs_l1>; 3689 }; 3690 }; 3691 }; 3692 3693 dc_noc: interconnect@90c0000 { 3694 compatible = "qcom,sm8250-dc-noc"; 3695 reg = <0 0x090c0000 0 0x4200>; 3696 #interconnect-cells = <2>; 3697 qcom,bcm-voters = <&apps_bcm_voter>; 3698 }; 3699 3700 gem_noc: interconnect@9100000 { 3701 compatible = "qcom,sm8250-gem-noc"; 3702 reg = <0 0x09100000 0 0xb4000>; 3703 #interconnect-cells = <2>; 3704 qcom,bcm-voters = <&apps_bcm_voter>; 3705 }; 3706 3707 npu_noc: interconnect@9990000 { 3708 compatible = "qcom,sm8250-npu-noc"; 3709 reg = <0 0x09990000 0 0x1600>; 3710 #interconnect-cells = <2>; 3711 qcom,bcm-voters = <&apps_bcm_voter>; 3712 }; 3713 3714 usb_1: usb@a6f8800 { 3715 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3716 reg = <0 0x0a6f8800 0 0x400>; 3717 status = "disabled"; 3718 #address-cells = <2>; 3719 #size-cells = <2>; 3720 ranges; 3721 dma-ranges; 3722 3723 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3724 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3725 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3726 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3727 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3728 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3729 clock-names = "cfg_noc", 3730 "core", 3731 "iface", 3732 "sleep", 3733 "mock_utmi", 3734 "xo"; 3735 3736 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3737 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3738 assigned-clock-rates = <19200000>, <200000000>; 3739 3740 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3741 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3742 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3743 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3744 interrupt-names = "hs_phy_irq", 3745 "ss_phy_irq", 3746 "dm_hs_phy_irq", 3747 "dp_hs_phy_irq"; 3748 3749 power-domains = <&gcc USB30_PRIM_GDSC>; 3750 3751 resets = <&gcc GCC_USB30_PRIM_BCR>; 3752 3753 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3754 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3755 interconnect-names = "usb-ddr", "apps-usb"; 3756 3757 usb_1_dwc3: usb@a600000 { 3758 compatible = "snps,dwc3"; 3759 reg = <0 0x0a600000 0 0xcd00>; 3760 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3761 iommus = <&apps_smmu 0x0 0x0>; 3762 snps,dis_u2_susphy_quirk; 3763 snps,dis_enblslpm_quirk; 3764 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3765 phy-names = "usb2-phy", "usb3-phy"; 3766 }; 3767 }; 3768 3769 system-cache-controller@9200000 { 3770 compatible = "qcom,sm8250-llcc"; 3771 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 3772 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 3773 <0 0x09600000 0 0x50000>; 3774 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3775 "llcc3_base", "llcc_broadcast_base"; 3776 }; 3777 3778 usb_2: usb@a8f8800 { 3779 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3780 reg = <0 0x0a8f8800 0 0x400>; 3781 status = "disabled"; 3782 #address-cells = <2>; 3783 #size-cells = <2>; 3784 ranges; 3785 dma-ranges; 3786 3787 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3788 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3789 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3790 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3791 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3792 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3793 clock-names = "cfg_noc", 3794 "core", 3795 "iface", 3796 "sleep", 3797 "mock_utmi", 3798 "xo"; 3799 3800 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3801 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3802 assigned-clock-rates = <19200000>, <200000000>; 3803 3804 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3805 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3806 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3807 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3808 interrupt-names = "hs_phy_irq", 3809 "ss_phy_irq", 3810 "dm_hs_phy_irq", 3811 "dp_hs_phy_irq"; 3812 3813 power-domains = <&gcc USB30_SEC_GDSC>; 3814 3815 resets = <&gcc GCC_USB30_SEC_BCR>; 3816 3817 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3818 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3819 interconnect-names = "usb-ddr", "apps-usb"; 3820 3821 usb_2_dwc3: usb@a800000 { 3822 compatible = "snps,dwc3"; 3823 reg = <0 0x0a800000 0 0xcd00>; 3824 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3825 iommus = <&apps_smmu 0x20 0>; 3826 snps,dis_u2_susphy_quirk; 3827 snps,dis_enblslpm_quirk; 3828 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3829 phy-names = "usb2-phy", "usb3-phy"; 3830 }; 3831 }; 3832 3833 venus: video-codec@aa00000 { 3834 compatible = "qcom,sm8250-venus"; 3835 reg = <0 0x0aa00000 0 0x100000>; 3836 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3837 power-domains = <&videocc MVS0C_GDSC>, 3838 <&videocc MVS0_GDSC>, 3839 <&rpmhpd SM8250_MX>; 3840 power-domain-names = "venus", "vcodec0", "mx"; 3841 operating-points-v2 = <&venus_opp_table>; 3842 3843 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3844 <&videocc VIDEO_CC_MVS0C_CLK>, 3845 <&videocc VIDEO_CC_MVS0_CLK>; 3846 clock-names = "iface", "core", "vcodec0_core"; 3847 3848 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 3849 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 3850 interconnect-names = "cpu-cfg", "video-mem"; 3851 3852 iommus = <&apps_smmu 0x2100 0x0400>; 3853 memory-region = <&video_mem>; 3854 3855 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3856 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3857 reset-names = "bus", "core"; 3858 3859 status = "disabled"; 3860 3861 video-decoder { 3862 compatible = "venus-decoder"; 3863 }; 3864 3865 video-encoder { 3866 compatible = "venus-encoder"; 3867 }; 3868 3869 venus_opp_table: opp-table { 3870 compatible = "operating-points-v2"; 3871 3872 opp-720000000 { 3873 opp-hz = /bits/ 64 <720000000>; 3874 required-opps = <&rpmhpd_opp_low_svs>; 3875 }; 3876 3877 opp-1014000000 { 3878 opp-hz = /bits/ 64 <1014000000>; 3879 required-opps = <&rpmhpd_opp_svs>; 3880 }; 3881 3882 opp-1098000000 { 3883 opp-hz = /bits/ 64 <1098000000>; 3884 required-opps = <&rpmhpd_opp_svs_l1>; 3885 }; 3886 3887 opp-1332000000 { 3888 opp-hz = /bits/ 64 <1332000000>; 3889 required-opps = <&rpmhpd_opp_nom>; 3890 }; 3891 }; 3892 }; 3893 3894 videocc: clock-controller@abf0000 { 3895 compatible = "qcom,sm8250-videocc"; 3896 reg = <0 0x0abf0000 0 0x10000>; 3897 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3898 <&rpmhcc RPMH_CXO_CLK>, 3899 <&rpmhcc RPMH_CXO_CLK_A>; 3900 power-domains = <&rpmhpd SM8250_MMCX>; 3901 required-opps = <&rpmhpd_opp_low_svs>; 3902 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3903 #clock-cells = <1>; 3904 #reset-cells = <1>; 3905 #power-domain-cells = <1>; 3906 }; 3907 3908 cci0: cci@ac4f000 { 3909 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3910 #address-cells = <1>; 3911 #size-cells = <0>; 3912 3913 reg = <0 0x0ac4f000 0 0x1000>; 3914 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3915 power-domains = <&camcc TITAN_TOP_GDSC>; 3916 3917 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3918 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3919 <&camcc CAM_CC_CPAS_AHB_CLK>, 3920 <&camcc CAM_CC_CCI_0_CLK>, 3921 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3922 clock-names = "camnoc_axi", 3923 "slow_ahb_src", 3924 "cpas_ahb", 3925 "cci", 3926 "cci_src"; 3927 3928 pinctrl-0 = <&cci0_default>; 3929 pinctrl-1 = <&cci0_sleep>; 3930 pinctrl-names = "default", "sleep"; 3931 3932 status = "disabled"; 3933 3934 cci0_i2c0: i2c-bus@0 { 3935 reg = <0>; 3936 clock-frequency = <1000000>; 3937 #address-cells = <1>; 3938 #size-cells = <0>; 3939 }; 3940 3941 cci0_i2c1: i2c-bus@1 { 3942 reg = <1>; 3943 clock-frequency = <1000000>; 3944 #address-cells = <1>; 3945 #size-cells = <0>; 3946 }; 3947 }; 3948 3949 cci1: cci@ac50000 { 3950 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3951 #address-cells = <1>; 3952 #size-cells = <0>; 3953 3954 reg = <0 0x0ac50000 0 0x1000>; 3955 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3956 power-domains = <&camcc TITAN_TOP_GDSC>; 3957 3958 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3959 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3960 <&camcc CAM_CC_CPAS_AHB_CLK>, 3961 <&camcc CAM_CC_CCI_1_CLK>, 3962 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3963 clock-names = "camnoc_axi", 3964 "slow_ahb_src", 3965 "cpas_ahb", 3966 "cci", 3967 "cci_src"; 3968 3969 pinctrl-0 = <&cci1_default>; 3970 pinctrl-1 = <&cci1_sleep>; 3971 pinctrl-names = "default", "sleep"; 3972 3973 status = "disabled"; 3974 3975 cci1_i2c0: i2c-bus@0 { 3976 reg = <0>; 3977 clock-frequency = <1000000>; 3978 #address-cells = <1>; 3979 #size-cells = <0>; 3980 }; 3981 3982 cci1_i2c1: i2c-bus@1 { 3983 reg = <1>; 3984 clock-frequency = <1000000>; 3985 #address-cells = <1>; 3986 #size-cells = <0>; 3987 }; 3988 }; 3989 3990 camss: camss@ac6a000 { 3991 compatible = "qcom,sm8250-camss"; 3992 status = "disabled"; 3993 3994 reg = <0 0x0ac6a000 0 0x2000>, 3995 <0 0x0ac6c000 0 0x2000>, 3996 <0 0x0ac6e000 0 0x1000>, 3997 <0 0x0ac70000 0 0x1000>, 3998 <0 0x0ac72000 0 0x1000>, 3999 <0 0x0ac74000 0 0x1000>, 4000 <0 0x0acb4000 0 0xd000>, 4001 <0 0x0acc3000 0 0xd000>, 4002 <0 0x0acd9000 0 0x2200>, 4003 <0 0x0acdb200 0 0x2200>; 4004 reg-names = "csiphy0", 4005 "csiphy1", 4006 "csiphy2", 4007 "csiphy3", 4008 "csiphy4", 4009 "csiphy5", 4010 "vfe0", 4011 "vfe1", 4012 "vfe_lite0", 4013 "vfe_lite1"; 4014 4015 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4029 interrupt-names = "csiphy0", 4030 "csiphy1", 4031 "csiphy2", 4032 "csiphy3", 4033 "csiphy4", 4034 "csiphy5", 4035 "csid0", 4036 "csid1", 4037 "csid2", 4038 "csid3", 4039 "vfe0", 4040 "vfe1", 4041 "vfe_lite0", 4042 "vfe_lite1"; 4043 4044 power-domains = <&camcc IFE_0_GDSC>, 4045 <&camcc IFE_1_GDSC>, 4046 <&camcc TITAN_TOP_GDSC>; 4047 4048 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4049 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4050 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4051 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4052 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4053 <&camcc CAM_CC_CORE_AHB_CLK>, 4054 <&camcc CAM_CC_CPAS_AHB_CLK>, 4055 <&camcc CAM_CC_CSIPHY0_CLK>, 4056 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4057 <&camcc CAM_CC_CSIPHY1_CLK>, 4058 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4059 <&camcc CAM_CC_CSIPHY2_CLK>, 4060 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4061 <&camcc CAM_CC_CSIPHY3_CLK>, 4062 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4063 <&camcc CAM_CC_CSIPHY4_CLK>, 4064 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4065 <&camcc CAM_CC_CSIPHY5_CLK>, 4066 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4067 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4068 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4069 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4070 <&camcc CAM_CC_IFE_0_CLK>, 4071 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4072 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4073 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4074 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4075 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4076 <&camcc CAM_CC_IFE_1_CLK>, 4077 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4078 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4079 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4080 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4081 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4082 <&camcc CAM_CC_IFE_LITE_CLK>, 4083 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4084 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4085 4086 clock-names = "cam_ahb_clk", 4087 "cam_hf_axi", 4088 "cam_sf_axi", 4089 "camnoc_axi", 4090 "camnoc_axi_src", 4091 "core_ahb", 4092 "cpas_ahb", 4093 "csiphy0", 4094 "csiphy0_timer", 4095 "csiphy1", 4096 "csiphy1_timer", 4097 "csiphy2", 4098 "csiphy2_timer", 4099 "csiphy3", 4100 "csiphy3_timer", 4101 "csiphy4", 4102 "csiphy4_timer", 4103 "csiphy5", 4104 "csiphy5_timer", 4105 "slow_ahb_src", 4106 "vfe0_ahb", 4107 "vfe0_axi", 4108 "vfe0", 4109 "vfe0_cphy_rx", 4110 "vfe0_csid", 4111 "vfe0_areg", 4112 "vfe1_ahb", 4113 "vfe1_axi", 4114 "vfe1", 4115 "vfe1_cphy_rx", 4116 "vfe1_csid", 4117 "vfe1_areg", 4118 "vfe_lite_ahb", 4119 "vfe_lite_axi", 4120 "vfe_lite", 4121 "vfe_lite_cphy_rx", 4122 "vfe_lite_csid"; 4123 4124 iommus = <&apps_smmu 0x800 0x400>, 4125 <&apps_smmu 0x801 0x400>, 4126 <&apps_smmu 0x840 0x400>, 4127 <&apps_smmu 0x841 0x400>, 4128 <&apps_smmu 0xc00 0x400>, 4129 <&apps_smmu 0xc01 0x400>, 4130 <&apps_smmu 0xc40 0x400>, 4131 <&apps_smmu 0xc41 0x400>; 4132 4133 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4134 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4135 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4136 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4137 interconnect-names = "cam_ahb", 4138 "cam_hf_0_mnoc", 4139 "cam_sf_0_mnoc", 4140 "cam_sf_icp_mnoc"; 4141 4142 ports { 4143 #address-cells = <1>; 4144 #size-cells = <0>; 4145 4146 port@0 { 4147 reg = <0>; 4148 }; 4149 4150 port@1 { 4151 reg = <1>; 4152 }; 4153 4154 port@2 { 4155 reg = <2>; 4156 }; 4157 4158 port@3 { 4159 reg = <3>; 4160 }; 4161 4162 port@4 { 4163 reg = <4>; 4164 }; 4165 4166 port@5 { 4167 reg = <5>; 4168 }; 4169 }; 4170 }; 4171 4172 camcc: clock-controller@ad00000 { 4173 compatible = "qcom,sm8250-camcc"; 4174 reg = <0 0x0ad00000 0 0x10000>; 4175 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4176 <&rpmhcc RPMH_CXO_CLK>, 4177 <&rpmhcc RPMH_CXO_CLK_A>, 4178 <&sleep_clk>; 4179 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4180 power-domains = <&rpmhpd SM8250_MMCX>; 4181 required-opps = <&rpmhpd_opp_low_svs>; 4182 status = "disabled"; 4183 #clock-cells = <1>; 4184 #reset-cells = <1>; 4185 #power-domain-cells = <1>; 4186 }; 4187 4188 mdss: display-subsystem@ae00000 { 4189 compatible = "qcom,sm8250-mdss"; 4190 reg = <0 0x0ae00000 0 0x1000>; 4191 reg-names = "mdss"; 4192 4193 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4194 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4195 interconnect-names = "mdp0-mem", "mdp1-mem"; 4196 4197 power-domains = <&dispcc MDSS_GDSC>; 4198 4199 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4200 <&gcc GCC_DISP_HF_AXI_CLK>, 4201 <&gcc GCC_DISP_SF_AXI_CLK>, 4202 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4203 clock-names = "iface", "bus", "nrt_bus", "core"; 4204 4205 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4206 interrupt-controller; 4207 #interrupt-cells = <1>; 4208 4209 iommus = <&apps_smmu 0x820 0x402>; 4210 4211 status = "disabled"; 4212 4213 #address-cells = <2>; 4214 #size-cells = <2>; 4215 ranges; 4216 4217 mdss_mdp: display-controller@ae01000 { 4218 compatible = "qcom,sm8250-dpu"; 4219 reg = <0 0x0ae01000 0 0x8f000>, 4220 <0 0x0aeb0000 0 0x2008>; 4221 reg-names = "mdp", "vbif"; 4222 4223 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4224 <&gcc GCC_DISP_HF_AXI_CLK>, 4225 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4226 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4227 clock-names = "iface", "bus", "core", "vsync"; 4228 4229 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4230 assigned-clock-rates = <19200000>; 4231 4232 operating-points-v2 = <&mdp_opp_table>; 4233 power-domains = <&rpmhpd SM8250_MMCX>; 4234 4235 interrupt-parent = <&mdss>; 4236 interrupts = <0>; 4237 4238 ports { 4239 #address-cells = <1>; 4240 #size-cells = <0>; 4241 4242 port@0 { 4243 reg = <0>; 4244 dpu_intf1_out: endpoint { 4245 remote-endpoint = <&mdss_dsi0_in>; 4246 }; 4247 }; 4248 4249 port@1 { 4250 reg = <1>; 4251 dpu_intf2_out: endpoint { 4252 remote-endpoint = <&mdss_dsi1_in>; 4253 }; 4254 }; 4255 }; 4256 4257 mdp_opp_table: opp-table { 4258 compatible = "operating-points-v2"; 4259 4260 opp-200000000 { 4261 opp-hz = /bits/ 64 <200000000>; 4262 required-opps = <&rpmhpd_opp_low_svs>; 4263 }; 4264 4265 opp-300000000 { 4266 opp-hz = /bits/ 64 <300000000>; 4267 required-opps = <&rpmhpd_opp_svs>; 4268 }; 4269 4270 opp-345000000 { 4271 opp-hz = /bits/ 64 <345000000>; 4272 required-opps = <&rpmhpd_opp_svs_l1>; 4273 }; 4274 4275 opp-460000000 { 4276 opp-hz = /bits/ 64 <460000000>; 4277 required-opps = <&rpmhpd_opp_nom>; 4278 }; 4279 }; 4280 }; 4281 4282 mdss_dsi0: dsi@ae94000 { 4283 compatible = "qcom,sm8250-dsi-ctrl", 4284 "qcom,mdss-dsi-ctrl"; 4285 reg = <0 0x0ae94000 0 0x400>; 4286 reg-names = "dsi_ctrl"; 4287 4288 interrupt-parent = <&mdss>; 4289 interrupts = <4>; 4290 4291 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4292 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4293 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4294 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4295 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4296 <&gcc GCC_DISP_HF_AXI_CLK>; 4297 clock-names = "byte", 4298 "byte_intf", 4299 "pixel", 4300 "core", 4301 "iface", 4302 "bus"; 4303 4304 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4305 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4306 4307 operating-points-v2 = <&dsi_opp_table>; 4308 power-domains = <&rpmhpd SM8250_MMCX>; 4309 4310 phys = <&mdss_dsi0_phy>; 4311 4312 status = "disabled"; 4313 4314 #address-cells = <1>; 4315 #size-cells = <0>; 4316 4317 ports { 4318 #address-cells = <1>; 4319 #size-cells = <0>; 4320 4321 port@0 { 4322 reg = <0>; 4323 mdss_dsi0_in: endpoint { 4324 remote-endpoint = <&dpu_intf1_out>; 4325 }; 4326 }; 4327 4328 port@1 { 4329 reg = <1>; 4330 mdss_dsi0_out: endpoint { 4331 }; 4332 }; 4333 }; 4334 4335 dsi_opp_table: opp-table { 4336 compatible = "operating-points-v2"; 4337 4338 opp-187500000 { 4339 opp-hz = /bits/ 64 <187500000>; 4340 required-opps = <&rpmhpd_opp_low_svs>; 4341 }; 4342 4343 opp-300000000 { 4344 opp-hz = /bits/ 64 <300000000>; 4345 required-opps = <&rpmhpd_opp_svs>; 4346 }; 4347 4348 opp-358000000 { 4349 opp-hz = /bits/ 64 <358000000>; 4350 required-opps = <&rpmhpd_opp_svs_l1>; 4351 }; 4352 }; 4353 }; 4354 4355 mdss_dsi0_phy: phy@ae94400 { 4356 compatible = "qcom,dsi-phy-7nm"; 4357 reg = <0 0x0ae94400 0 0x200>, 4358 <0 0x0ae94600 0 0x280>, 4359 <0 0x0ae94900 0 0x260>; 4360 reg-names = "dsi_phy", 4361 "dsi_phy_lane", 4362 "dsi_pll"; 4363 4364 #clock-cells = <1>; 4365 #phy-cells = <0>; 4366 4367 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4368 <&rpmhcc RPMH_CXO_CLK>; 4369 clock-names = "iface", "ref"; 4370 4371 status = "disabled"; 4372 }; 4373 4374 mdss_dsi1: dsi@ae96000 { 4375 compatible = "qcom,sm8250-dsi-ctrl", 4376 "qcom,mdss-dsi-ctrl"; 4377 reg = <0 0x0ae96000 0 0x400>; 4378 reg-names = "dsi_ctrl"; 4379 4380 interrupt-parent = <&mdss>; 4381 interrupts = <5>; 4382 4383 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4384 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4385 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4386 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4387 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4388 <&gcc GCC_DISP_HF_AXI_CLK>; 4389 clock-names = "byte", 4390 "byte_intf", 4391 "pixel", 4392 "core", 4393 "iface", 4394 "bus"; 4395 4396 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4397 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4398 4399 operating-points-v2 = <&dsi_opp_table>; 4400 power-domains = <&rpmhpd SM8250_MMCX>; 4401 4402 phys = <&mdss_dsi1_phy>; 4403 4404 status = "disabled"; 4405 4406 #address-cells = <1>; 4407 #size-cells = <0>; 4408 4409 ports { 4410 #address-cells = <1>; 4411 #size-cells = <0>; 4412 4413 port@0 { 4414 reg = <0>; 4415 mdss_dsi1_in: endpoint { 4416 remote-endpoint = <&dpu_intf2_out>; 4417 }; 4418 }; 4419 4420 port@1 { 4421 reg = <1>; 4422 mdss_dsi1_out: endpoint { 4423 }; 4424 }; 4425 }; 4426 }; 4427 4428 mdss_dsi1_phy: phy@ae96400 { 4429 compatible = "qcom,dsi-phy-7nm"; 4430 reg = <0 0x0ae96400 0 0x200>, 4431 <0 0x0ae96600 0 0x280>, 4432 <0 0x0ae96900 0 0x260>; 4433 reg-names = "dsi_phy", 4434 "dsi_phy_lane", 4435 "dsi_pll"; 4436 4437 #clock-cells = <1>; 4438 #phy-cells = <0>; 4439 4440 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4441 <&rpmhcc RPMH_CXO_CLK>; 4442 clock-names = "iface", "ref"; 4443 4444 status = "disabled"; 4445 }; 4446 }; 4447 4448 dispcc: clock-controller@af00000 { 4449 compatible = "qcom,sm8250-dispcc"; 4450 reg = <0 0x0af00000 0 0x10000>; 4451 power-domains = <&rpmhpd SM8250_MMCX>; 4452 required-opps = <&rpmhpd_opp_low_svs>; 4453 clocks = <&rpmhcc RPMH_CXO_CLK>, 4454 <&mdss_dsi0_phy 0>, 4455 <&mdss_dsi0_phy 1>, 4456 <&mdss_dsi1_phy 0>, 4457 <&mdss_dsi1_phy 1>, 4458 <&dp_phy 0>, 4459 <&dp_phy 1>; 4460 clock-names = "bi_tcxo", 4461 "dsi0_phy_pll_out_byteclk", 4462 "dsi0_phy_pll_out_dsiclk", 4463 "dsi1_phy_pll_out_byteclk", 4464 "dsi1_phy_pll_out_dsiclk", 4465 "dp_phy_pll_link_clk", 4466 "dp_phy_pll_vco_div_clk"; 4467 #clock-cells = <1>; 4468 #reset-cells = <1>; 4469 #power-domain-cells = <1>; 4470 }; 4471 4472 pdc: interrupt-controller@b220000 { 4473 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4474 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4475 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4476 <125 63 1>, <126 716 12>; 4477 #interrupt-cells = <2>; 4478 interrupt-parent = <&intc>; 4479 interrupt-controller; 4480 }; 4481 4482 tsens0: thermal-sensor@c263000 { 4483 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4484 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4485 <0 0x0c222000 0 0x1ff>; /* SROT */ 4486 #qcom,sensors = <16>; 4487 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4488 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4489 interrupt-names = "uplow", "critical"; 4490 #thermal-sensor-cells = <1>; 4491 }; 4492 4493 tsens1: thermal-sensor@c265000 { 4494 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4495 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4496 <0 0x0c223000 0 0x1ff>; /* SROT */ 4497 #qcom,sensors = <9>; 4498 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4499 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4500 interrupt-names = "uplow", "critical"; 4501 #thermal-sensor-cells = <1>; 4502 }; 4503 4504 aoss_qmp: power-management@c300000 { 4505 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4506 reg = <0 0x0c300000 0 0x400>; 4507 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4508 IPCC_MPROC_SIGNAL_GLINK_QMP 4509 IRQ_TYPE_EDGE_RISING>; 4510 mboxes = <&ipcc IPCC_CLIENT_AOP 4511 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4512 4513 #clock-cells = <0>; 4514 }; 4515 4516 sram@c3f0000 { 4517 compatible = "qcom,rpmh-stats"; 4518 reg = <0 0x0c3f0000 0 0x400>; 4519 }; 4520 4521 spmi_bus: spmi@c440000 { 4522 compatible = "qcom,spmi-pmic-arb"; 4523 reg = <0x0 0x0c440000 0x0 0x0001100>, 4524 <0x0 0x0c600000 0x0 0x2000000>, 4525 <0x0 0x0e600000 0x0 0x0100000>, 4526 <0x0 0x0e700000 0x0 0x00a0000>, 4527 <0x0 0x0c40a000 0x0 0x0026000>; 4528 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4529 interrupt-names = "periph_irq"; 4530 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4531 qcom,ee = <0>; 4532 qcom,channel = <0>; 4533 #address-cells = <2>; 4534 #size-cells = <0>; 4535 interrupt-controller; 4536 #interrupt-cells = <4>; 4537 }; 4538 4539 tlmm: pinctrl@f100000 { 4540 compatible = "qcom,sm8250-pinctrl"; 4541 reg = <0 0x0f100000 0 0x300000>, 4542 <0 0x0f500000 0 0x300000>, 4543 <0 0x0f900000 0 0x300000>; 4544 reg-names = "west", "south", "north"; 4545 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4546 gpio-controller; 4547 #gpio-cells = <2>; 4548 interrupt-controller; 4549 #interrupt-cells = <2>; 4550 gpio-ranges = <&tlmm 0 0 181>; 4551 wakeup-parent = <&pdc>; 4552 4553 cam2_default: cam2-default-state { 4554 rst-pins { 4555 pins = "gpio78"; 4556 function = "gpio"; 4557 drive-strength = <2>; 4558 bias-disable; 4559 }; 4560 4561 mclk-pins { 4562 pins = "gpio96"; 4563 function = "cam_mclk"; 4564 drive-strength = <16>; 4565 bias-disable; 4566 }; 4567 }; 4568 4569 cam2_suspend: cam2-suspend-state { 4570 rst-pins { 4571 pins = "gpio78"; 4572 function = "gpio"; 4573 drive-strength = <2>; 4574 bias-pull-down; 4575 output-low; 4576 }; 4577 4578 mclk-pins { 4579 pins = "gpio96"; 4580 function = "cam_mclk"; 4581 drive-strength = <2>; 4582 bias-disable; 4583 }; 4584 }; 4585 4586 cci0_default: cci0-default-state { 4587 cci0_i2c0_default: cci0-i2c0-default-pins { 4588 /* SDA, SCL */ 4589 pins = "gpio101", "gpio102"; 4590 function = "cci_i2c"; 4591 4592 bias-pull-up; 4593 drive-strength = <2>; /* 2 mA */ 4594 }; 4595 4596 cci0_i2c1_default: cci0-i2c1-default-pins { 4597 /* SDA, SCL */ 4598 pins = "gpio103", "gpio104"; 4599 function = "cci_i2c"; 4600 4601 bias-pull-up; 4602 drive-strength = <2>; /* 2 mA */ 4603 }; 4604 }; 4605 4606 cci0_sleep: cci0-sleep-state { 4607 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4608 /* SDA, SCL */ 4609 pins = "gpio101", "gpio102"; 4610 function = "cci_i2c"; 4611 4612 drive-strength = <2>; /* 2 mA */ 4613 bias-pull-down; 4614 }; 4615 4616 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4617 /* SDA, SCL */ 4618 pins = "gpio103", "gpio104"; 4619 function = "cci_i2c"; 4620 4621 drive-strength = <2>; /* 2 mA */ 4622 bias-pull-down; 4623 }; 4624 }; 4625 4626 cci1_default: cci1-default-state { 4627 cci1_i2c0_default: cci1-i2c0-default-pins { 4628 /* SDA, SCL */ 4629 pins = "gpio105","gpio106"; 4630 function = "cci_i2c"; 4631 4632 bias-pull-up; 4633 drive-strength = <2>; /* 2 mA */ 4634 }; 4635 4636 cci1_i2c1_default: cci1-i2c1-default-pins { 4637 /* SDA, SCL */ 4638 pins = "gpio107","gpio108"; 4639 function = "cci_i2c"; 4640 4641 bias-pull-up; 4642 drive-strength = <2>; /* 2 mA */ 4643 }; 4644 }; 4645 4646 cci1_sleep: cci1-sleep-state { 4647 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4648 /* SDA, SCL */ 4649 pins = "gpio105","gpio106"; 4650 function = "cci_i2c"; 4651 4652 bias-pull-down; 4653 drive-strength = <2>; /* 2 mA */ 4654 }; 4655 4656 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4657 /* SDA, SCL */ 4658 pins = "gpio107","gpio108"; 4659 function = "cci_i2c"; 4660 4661 bias-pull-down; 4662 drive-strength = <2>; /* 2 mA */ 4663 }; 4664 }; 4665 4666 pri_mi2s_active: pri-mi2s-active-state { 4667 sclk-pins { 4668 pins = "gpio138"; 4669 function = "mi2s0_sck"; 4670 drive-strength = <8>; 4671 bias-disable; 4672 }; 4673 4674 ws-pins { 4675 pins = "gpio141"; 4676 function = "mi2s0_ws"; 4677 drive-strength = <8>; 4678 output-high; 4679 }; 4680 4681 data0-pins { 4682 pins = "gpio139"; 4683 function = "mi2s0_data0"; 4684 drive-strength = <8>; 4685 bias-disable; 4686 output-high; 4687 }; 4688 4689 data1-pins { 4690 pins = "gpio140"; 4691 function = "mi2s0_data1"; 4692 drive-strength = <8>; 4693 output-high; 4694 }; 4695 }; 4696 4697 qup_i2c0_default: qup-i2c0-default-state { 4698 pins = "gpio28", "gpio29"; 4699 function = "qup0"; 4700 drive-strength = <2>; 4701 bias-disable; 4702 }; 4703 4704 qup_i2c1_default: qup-i2c1-default-state { 4705 pins = "gpio4", "gpio5"; 4706 function = "qup1"; 4707 drive-strength = <2>; 4708 bias-disable; 4709 }; 4710 4711 qup_i2c2_default: qup-i2c2-default-state { 4712 pins = "gpio115", "gpio116"; 4713 function = "qup2"; 4714 drive-strength = <2>; 4715 bias-disable; 4716 }; 4717 4718 qup_i2c3_default: qup-i2c3-default-state { 4719 pins = "gpio119", "gpio120"; 4720 function = "qup3"; 4721 drive-strength = <2>; 4722 bias-disable; 4723 }; 4724 4725 qup_i2c4_default: qup-i2c4-default-state { 4726 pins = "gpio8", "gpio9"; 4727 function = "qup4"; 4728 drive-strength = <2>; 4729 bias-disable; 4730 }; 4731 4732 qup_i2c5_default: qup-i2c5-default-state { 4733 pins = "gpio12", "gpio13"; 4734 function = "qup5"; 4735 drive-strength = <2>; 4736 bias-disable; 4737 }; 4738 4739 qup_i2c6_default: qup-i2c6-default-state { 4740 pins = "gpio16", "gpio17"; 4741 function = "qup6"; 4742 drive-strength = <2>; 4743 bias-disable; 4744 }; 4745 4746 qup_i2c7_default: qup-i2c7-default-state { 4747 pins = "gpio20", "gpio21"; 4748 function = "qup7"; 4749 drive-strength = <2>; 4750 bias-disable; 4751 }; 4752 4753 qup_i2c8_default: qup-i2c8-default-state { 4754 pins = "gpio24", "gpio25"; 4755 function = "qup8"; 4756 drive-strength = <2>; 4757 bias-disable; 4758 }; 4759 4760 qup_i2c9_default: qup-i2c9-default-state { 4761 pins = "gpio125", "gpio126"; 4762 function = "qup9"; 4763 drive-strength = <2>; 4764 bias-disable; 4765 }; 4766 4767 qup_i2c10_default: qup-i2c10-default-state { 4768 pins = "gpio129", "gpio130"; 4769 function = "qup10"; 4770 drive-strength = <2>; 4771 bias-disable; 4772 }; 4773 4774 qup_i2c11_default: qup-i2c11-default-state { 4775 pins = "gpio60", "gpio61"; 4776 function = "qup11"; 4777 drive-strength = <2>; 4778 bias-disable; 4779 }; 4780 4781 qup_i2c12_default: qup-i2c12-default-state { 4782 pins = "gpio32", "gpio33"; 4783 function = "qup12"; 4784 drive-strength = <2>; 4785 bias-disable; 4786 }; 4787 4788 qup_i2c13_default: qup-i2c13-default-state { 4789 pins = "gpio36", "gpio37"; 4790 function = "qup13"; 4791 drive-strength = <2>; 4792 bias-disable; 4793 }; 4794 4795 qup_i2c14_default: qup-i2c14-default-state { 4796 pins = "gpio40", "gpio41"; 4797 function = "qup14"; 4798 drive-strength = <2>; 4799 bias-disable; 4800 }; 4801 4802 qup_i2c15_default: qup-i2c15-default-state { 4803 pins = "gpio44", "gpio45"; 4804 function = "qup15"; 4805 drive-strength = <2>; 4806 bias-disable; 4807 }; 4808 4809 qup_i2c16_default: qup-i2c16-default-state { 4810 pins = "gpio48", "gpio49"; 4811 function = "qup16"; 4812 drive-strength = <2>; 4813 bias-disable; 4814 }; 4815 4816 qup_i2c17_default: qup-i2c17-default-state { 4817 pins = "gpio52", "gpio53"; 4818 function = "qup17"; 4819 drive-strength = <2>; 4820 bias-disable; 4821 }; 4822 4823 qup_i2c18_default: qup-i2c18-default-state { 4824 pins = "gpio56", "gpio57"; 4825 function = "qup18"; 4826 drive-strength = <2>; 4827 bias-disable; 4828 }; 4829 4830 qup_i2c19_default: qup-i2c19-default-state { 4831 pins = "gpio0", "gpio1"; 4832 function = "qup19"; 4833 drive-strength = <2>; 4834 bias-disable; 4835 }; 4836 4837 qup_spi0_cs: qup-spi0-cs-state { 4838 pins = "gpio31"; 4839 function = "qup0"; 4840 }; 4841 4842 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4843 pins = "gpio31"; 4844 function = "gpio"; 4845 }; 4846 4847 qup_spi0_data_clk: qup-spi0-data-clk-state { 4848 pins = "gpio28", "gpio29", 4849 "gpio30"; 4850 function = "qup0"; 4851 }; 4852 4853 qup_spi1_cs: qup-spi1-cs-state { 4854 pins = "gpio7"; 4855 function = "qup1"; 4856 }; 4857 4858 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4859 pins = "gpio7"; 4860 function = "gpio"; 4861 }; 4862 4863 qup_spi1_data_clk: qup-spi1-data-clk-state { 4864 pins = "gpio4", "gpio5", 4865 "gpio6"; 4866 function = "qup1"; 4867 }; 4868 4869 qup_spi2_cs: qup-spi2-cs-state { 4870 pins = "gpio118"; 4871 function = "qup2"; 4872 }; 4873 4874 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4875 pins = "gpio118"; 4876 function = "gpio"; 4877 }; 4878 4879 qup_spi2_data_clk: qup-spi2-data-clk-state { 4880 pins = "gpio115", "gpio116", 4881 "gpio117"; 4882 function = "qup2"; 4883 }; 4884 4885 qup_spi3_cs: qup-spi3-cs-state { 4886 pins = "gpio122"; 4887 function = "qup3"; 4888 }; 4889 4890 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4891 pins = "gpio122"; 4892 function = "gpio"; 4893 }; 4894 4895 qup_spi3_data_clk: qup-spi3-data-clk-state { 4896 pins = "gpio119", "gpio120", 4897 "gpio121"; 4898 function = "qup3"; 4899 }; 4900 4901 qup_spi4_cs: qup-spi4-cs-state { 4902 pins = "gpio11"; 4903 function = "qup4"; 4904 }; 4905 4906 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4907 pins = "gpio11"; 4908 function = "gpio"; 4909 }; 4910 4911 qup_spi4_data_clk: qup-spi4-data-clk-state { 4912 pins = "gpio8", "gpio9", 4913 "gpio10"; 4914 function = "qup4"; 4915 }; 4916 4917 qup_spi5_cs: qup-spi5-cs-state { 4918 pins = "gpio15"; 4919 function = "qup5"; 4920 }; 4921 4922 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4923 pins = "gpio15"; 4924 function = "gpio"; 4925 }; 4926 4927 qup_spi5_data_clk: qup-spi5-data-clk-state { 4928 pins = "gpio12", "gpio13", 4929 "gpio14"; 4930 function = "qup5"; 4931 }; 4932 4933 qup_spi6_cs: qup-spi6-cs-state { 4934 pins = "gpio19"; 4935 function = "qup6"; 4936 }; 4937 4938 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4939 pins = "gpio19"; 4940 function = "gpio"; 4941 }; 4942 4943 qup_spi6_data_clk: qup-spi6-data-clk-state { 4944 pins = "gpio16", "gpio17", 4945 "gpio18"; 4946 function = "qup6"; 4947 }; 4948 4949 qup_spi7_cs: qup-spi7-cs-state { 4950 pins = "gpio23"; 4951 function = "qup7"; 4952 }; 4953 4954 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4955 pins = "gpio23"; 4956 function = "gpio"; 4957 }; 4958 4959 qup_spi7_data_clk: qup-spi7-data-clk-state { 4960 pins = "gpio20", "gpio21", 4961 "gpio22"; 4962 function = "qup7"; 4963 }; 4964 4965 qup_spi8_cs: qup-spi8-cs-state { 4966 pins = "gpio27"; 4967 function = "qup8"; 4968 }; 4969 4970 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4971 pins = "gpio27"; 4972 function = "gpio"; 4973 }; 4974 4975 qup_spi8_data_clk: qup-spi8-data-clk-state { 4976 pins = "gpio24", "gpio25", 4977 "gpio26"; 4978 function = "qup8"; 4979 }; 4980 4981 qup_spi9_cs: qup-spi9-cs-state { 4982 pins = "gpio128"; 4983 function = "qup9"; 4984 }; 4985 4986 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4987 pins = "gpio128"; 4988 function = "gpio"; 4989 }; 4990 4991 qup_spi9_data_clk: qup-spi9-data-clk-state { 4992 pins = "gpio125", "gpio126", 4993 "gpio127"; 4994 function = "qup9"; 4995 }; 4996 4997 qup_spi10_cs: qup-spi10-cs-state { 4998 pins = "gpio132"; 4999 function = "qup10"; 5000 }; 5001 5002 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5003 pins = "gpio132"; 5004 function = "gpio"; 5005 }; 5006 5007 qup_spi10_data_clk: qup-spi10-data-clk-state { 5008 pins = "gpio129", "gpio130", 5009 "gpio131"; 5010 function = "qup10"; 5011 }; 5012 5013 qup_spi11_cs: qup-spi11-cs-state { 5014 pins = "gpio63"; 5015 function = "qup11"; 5016 }; 5017 5018 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5019 pins = "gpio63"; 5020 function = "gpio"; 5021 }; 5022 5023 qup_spi11_data_clk: qup-spi11-data-clk-state { 5024 pins = "gpio60", "gpio61", 5025 "gpio62"; 5026 function = "qup11"; 5027 }; 5028 5029 qup_spi12_cs: qup-spi12-cs-state { 5030 pins = "gpio35"; 5031 function = "qup12"; 5032 }; 5033 5034 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5035 pins = "gpio35"; 5036 function = "gpio"; 5037 }; 5038 5039 qup_spi12_data_clk: qup-spi12-data-clk-state { 5040 pins = "gpio32", "gpio33", 5041 "gpio34"; 5042 function = "qup12"; 5043 }; 5044 5045 qup_spi13_cs: qup-spi13-cs-state { 5046 pins = "gpio39"; 5047 function = "qup13"; 5048 }; 5049 5050 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5051 pins = "gpio39"; 5052 function = "gpio"; 5053 }; 5054 5055 qup_spi13_data_clk: qup-spi13-data-clk-state { 5056 pins = "gpio36", "gpio37", 5057 "gpio38"; 5058 function = "qup13"; 5059 }; 5060 5061 qup_spi14_cs: qup-spi14-cs-state { 5062 pins = "gpio43"; 5063 function = "qup14"; 5064 }; 5065 5066 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5067 pins = "gpio43"; 5068 function = "gpio"; 5069 }; 5070 5071 qup_spi14_data_clk: qup-spi14-data-clk-state { 5072 pins = "gpio40", "gpio41", 5073 "gpio42"; 5074 function = "qup14"; 5075 }; 5076 5077 qup_spi15_cs: qup-spi15-cs-state { 5078 pins = "gpio47"; 5079 function = "qup15"; 5080 }; 5081 5082 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5083 pins = "gpio47"; 5084 function = "gpio"; 5085 }; 5086 5087 qup_spi15_data_clk: qup-spi15-data-clk-state { 5088 pins = "gpio44", "gpio45", 5089 "gpio46"; 5090 function = "qup15"; 5091 }; 5092 5093 qup_spi16_cs: qup-spi16-cs-state { 5094 pins = "gpio51"; 5095 function = "qup16"; 5096 }; 5097 5098 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5099 pins = "gpio51"; 5100 function = "gpio"; 5101 }; 5102 5103 qup_spi16_data_clk: qup-spi16-data-clk-state { 5104 pins = "gpio48", "gpio49", 5105 "gpio50"; 5106 function = "qup16"; 5107 }; 5108 5109 qup_spi17_cs: qup-spi17-cs-state { 5110 pins = "gpio55"; 5111 function = "qup17"; 5112 }; 5113 5114 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5115 pins = "gpio55"; 5116 function = "gpio"; 5117 }; 5118 5119 qup_spi17_data_clk: qup-spi17-data-clk-state { 5120 pins = "gpio52", "gpio53", 5121 "gpio54"; 5122 function = "qup17"; 5123 }; 5124 5125 qup_spi18_cs: qup-spi18-cs-state { 5126 pins = "gpio59"; 5127 function = "qup18"; 5128 }; 5129 5130 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5131 pins = "gpio59"; 5132 function = "gpio"; 5133 }; 5134 5135 qup_spi18_data_clk: qup-spi18-data-clk-state { 5136 pins = "gpio56", "gpio57", 5137 "gpio58"; 5138 function = "qup18"; 5139 }; 5140 5141 qup_spi19_cs: qup-spi19-cs-state { 5142 pins = "gpio3"; 5143 function = "qup19"; 5144 }; 5145 5146 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5147 pins = "gpio3"; 5148 function = "gpio"; 5149 }; 5150 5151 qup_spi19_data_clk: qup-spi19-data-clk-state { 5152 pins = "gpio0", "gpio1", 5153 "gpio2"; 5154 function = "qup19"; 5155 }; 5156 5157 qup_uart2_default: qup-uart2-default-state { 5158 pins = "gpio117", "gpio118"; 5159 function = "qup2"; 5160 }; 5161 5162 qup_uart6_default: qup-uart6-default-state { 5163 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5164 function = "qup6"; 5165 }; 5166 5167 qup_uart12_default: qup-uart12-default-state { 5168 pins = "gpio34", "gpio35"; 5169 function = "qup12"; 5170 }; 5171 5172 qup_uart17_default: qup-uart17-default-state { 5173 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5174 function = "qup17"; 5175 }; 5176 5177 qup_uart18_default: qup-uart18-default-state { 5178 pins = "gpio58", "gpio59"; 5179 function = "qup18"; 5180 }; 5181 5182 tert_mi2s_active: tert-mi2s-active-state { 5183 sck-pins { 5184 pins = "gpio133"; 5185 function = "mi2s2_sck"; 5186 drive-strength = <8>; 5187 bias-disable; 5188 }; 5189 5190 data0-pins { 5191 pins = "gpio134"; 5192 function = "mi2s2_data0"; 5193 drive-strength = <8>; 5194 bias-disable; 5195 output-high; 5196 }; 5197 5198 ws-pins { 5199 pins = "gpio135"; 5200 function = "mi2s2_ws"; 5201 drive-strength = <8>; 5202 output-high; 5203 }; 5204 }; 5205 5206 sdc2_sleep_state: sdc2-sleep-state { 5207 clk-pins { 5208 pins = "sdc2_clk"; 5209 drive-strength = <2>; 5210 bias-disable; 5211 }; 5212 5213 cmd-pins { 5214 pins = "sdc2_cmd"; 5215 drive-strength = <2>; 5216 bias-pull-up; 5217 }; 5218 5219 data-pins { 5220 pins = "sdc2_data"; 5221 drive-strength = <2>; 5222 bias-pull-up; 5223 }; 5224 }; 5225 5226 pcie0_default_state: pcie0-default-state { 5227 perst-pins { 5228 pins = "gpio79"; 5229 function = "gpio"; 5230 drive-strength = <2>; 5231 bias-pull-down; 5232 }; 5233 5234 clkreq-pins { 5235 pins = "gpio80"; 5236 function = "pci_e0"; 5237 drive-strength = <2>; 5238 bias-pull-up; 5239 }; 5240 5241 wake-pins { 5242 pins = "gpio81"; 5243 function = "gpio"; 5244 drive-strength = <2>; 5245 bias-pull-up; 5246 }; 5247 }; 5248 5249 pcie1_default_state: pcie1-default-state { 5250 perst-pins { 5251 pins = "gpio82"; 5252 function = "gpio"; 5253 drive-strength = <2>; 5254 bias-pull-down; 5255 }; 5256 5257 clkreq-pins { 5258 pins = "gpio83"; 5259 function = "pci_e1"; 5260 drive-strength = <2>; 5261 bias-pull-up; 5262 }; 5263 5264 wake-pins { 5265 pins = "gpio84"; 5266 function = "gpio"; 5267 drive-strength = <2>; 5268 bias-pull-up; 5269 }; 5270 }; 5271 5272 pcie2_default_state: pcie2-default-state { 5273 perst-pins { 5274 pins = "gpio85"; 5275 function = "gpio"; 5276 drive-strength = <2>; 5277 bias-pull-down; 5278 }; 5279 5280 clkreq-pins { 5281 pins = "gpio86"; 5282 function = "pci_e2"; 5283 drive-strength = <2>; 5284 bias-pull-up; 5285 }; 5286 5287 wake-pins { 5288 pins = "gpio87"; 5289 function = "gpio"; 5290 drive-strength = <2>; 5291 bias-pull-up; 5292 }; 5293 }; 5294 }; 5295 5296 apps_smmu: iommu@15000000 { 5297 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5298 reg = <0 0x15000000 0 0x100000>; 5299 #iommu-cells = <2>; 5300 #global-interrupts = <2>; 5301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5302 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5303 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5304 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5305 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5306 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5307 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5308 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5309 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5310 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5345 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5346 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5347 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5348 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5349 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5356 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5357 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5364 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5365 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5366 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5367 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5368 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5369 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5370 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5371 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5372 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5373 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5374 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5375 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5376 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5377 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5378 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5379 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5380 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5381 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5382 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5383 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5384 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5385 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5386 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5387 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5388 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5389 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5390 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5391 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5392 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5393 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5394 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5395 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5396 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5397 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5398 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5399 }; 5400 5401 adsp: remoteproc@17300000 { 5402 compatible = "qcom,sm8250-adsp-pas"; 5403 reg = <0 0x17300000 0 0x100>; 5404 5405 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5406 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5407 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5408 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5409 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5410 interrupt-names = "wdog", "fatal", "ready", 5411 "handover", "stop-ack"; 5412 5413 clocks = <&rpmhcc RPMH_CXO_CLK>; 5414 clock-names = "xo"; 5415 5416 power-domains = <&rpmhpd SM8250_LCX>, 5417 <&rpmhpd SM8250_LMX>; 5418 power-domain-names = "lcx", "lmx"; 5419 5420 memory-region = <&adsp_mem>; 5421 5422 qcom,qmp = <&aoss_qmp>; 5423 5424 qcom,smem-states = <&smp2p_adsp_out 0>; 5425 qcom,smem-state-names = "stop"; 5426 5427 status = "disabled"; 5428 5429 glink-edge { 5430 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5431 IPCC_MPROC_SIGNAL_GLINK_QMP 5432 IRQ_TYPE_EDGE_RISING>; 5433 mboxes = <&ipcc IPCC_CLIENT_LPASS 5434 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5435 5436 label = "lpass"; 5437 qcom,remote-pid = <2>; 5438 5439 apr { 5440 compatible = "qcom,apr-v2"; 5441 qcom,glink-channels = "apr_audio_svc"; 5442 qcom,domain = <APR_DOMAIN_ADSP>; 5443 #address-cells = <1>; 5444 #size-cells = <0>; 5445 5446 service@3 { 5447 reg = <APR_SVC_ADSP_CORE>; 5448 compatible = "qcom,q6core"; 5449 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5450 }; 5451 5452 q6afe: service@4 { 5453 compatible = "qcom,q6afe"; 5454 reg = <APR_SVC_AFE>; 5455 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5456 q6afedai: dais { 5457 compatible = "qcom,q6afe-dais"; 5458 #address-cells = <1>; 5459 #size-cells = <0>; 5460 #sound-dai-cells = <1>; 5461 }; 5462 5463 q6afecc: clock-controller { 5464 compatible = "qcom,q6afe-clocks"; 5465 #clock-cells = <2>; 5466 }; 5467 }; 5468 5469 q6asm: service@7 { 5470 compatible = "qcom,q6asm"; 5471 reg = <APR_SVC_ASM>; 5472 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5473 q6asmdai: dais { 5474 compatible = "qcom,q6asm-dais"; 5475 #address-cells = <1>; 5476 #size-cells = <0>; 5477 #sound-dai-cells = <1>; 5478 iommus = <&apps_smmu 0x1801 0x0>; 5479 }; 5480 }; 5481 5482 q6adm: service@8 { 5483 compatible = "qcom,q6adm"; 5484 reg = <APR_SVC_ADM>; 5485 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5486 q6routing: routing { 5487 compatible = "qcom,q6adm-routing"; 5488 #sound-dai-cells = <0>; 5489 }; 5490 }; 5491 }; 5492 5493 fastrpc { 5494 compatible = "qcom,fastrpc"; 5495 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5496 label = "adsp"; 5497 qcom,non-secure-domain; 5498 #address-cells = <1>; 5499 #size-cells = <0>; 5500 5501 compute-cb@3 { 5502 compatible = "qcom,fastrpc-compute-cb"; 5503 reg = <3>; 5504 iommus = <&apps_smmu 0x1803 0x0>; 5505 }; 5506 5507 compute-cb@4 { 5508 compatible = "qcom,fastrpc-compute-cb"; 5509 reg = <4>; 5510 iommus = <&apps_smmu 0x1804 0x0>; 5511 }; 5512 5513 compute-cb@5 { 5514 compatible = "qcom,fastrpc-compute-cb"; 5515 reg = <5>; 5516 iommus = <&apps_smmu 0x1805 0x0>; 5517 }; 5518 }; 5519 }; 5520 }; 5521 5522 intc: interrupt-controller@17a00000 { 5523 compatible = "arm,gic-v3"; 5524 #interrupt-cells = <3>; 5525 interrupt-controller; 5526 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5527 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5528 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5529 }; 5530 5531 watchdog@17c10000 { 5532 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5533 reg = <0 0x17c10000 0 0x1000>; 5534 clocks = <&sleep_clk>; 5535 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5536 }; 5537 5538 timer@17c20000 { 5539 #address-cells = <1>; 5540 #size-cells = <1>; 5541 ranges = <0 0 0 0x20000000>; 5542 compatible = "arm,armv7-timer-mem"; 5543 reg = <0x0 0x17c20000 0x0 0x1000>; 5544 clock-frequency = <19200000>; 5545 5546 frame@17c21000 { 5547 frame-number = <0>; 5548 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5549 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5550 reg = <0x17c21000 0x1000>, 5551 <0x17c22000 0x1000>; 5552 }; 5553 5554 frame@17c23000 { 5555 frame-number = <1>; 5556 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5557 reg = <0x17c23000 0x1000>; 5558 status = "disabled"; 5559 }; 5560 5561 frame@17c25000 { 5562 frame-number = <2>; 5563 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5564 reg = <0x17c25000 0x1000>; 5565 status = "disabled"; 5566 }; 5567 5568 frame@17c27000 { 5569 frame-number = <3>; 5570 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5571 reg = <0x17c27000 0x1000>; 5572 status = "disabled"; 5573 }; 5574 5575 frame@17c29000 { 5576 frame-number = <4>; 5577 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5578 reg = <0x17c29000 0x1000>; 5579 status = "disabled"; 5580 }; 5581 5582 frame@17c2b000 { 5583 frame-number = <5>; 5584 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5585 reg = <0x17c2b000 0x1000>; 5586 status = "disabled"; 5587 }; 5588 5589 frame@17c2d000 { 5590 frame-number = <6>; 5591 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5592 reg = <0x17c2d000 0x1000>; 5593 status = "disabled"; 5594 }; 5595 }; 5596 5597 apps_rsc: rsc@18200000 { 5598 label = "apps_rsc"; 5599 compatible = "qcom,rpmh-rsc"; 5600 reg = <0x0 0x18200000 0x0 0x10000>, 5601 <0x0 0x18210000 0x0 0x10000>, 5602 <0x0 0x18220000 0x0 0x10000>; 5603 reg-names = "drv-0", "drv-1", "drv-2"; 5604 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5605 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5606 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5607 qcom,tcs-offset = <0xd00>; 5608 qcom,drv-id = <2>; 5609 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5610 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5611 power-domains = <&CLUSTER_PD>; 5612 5613 rpmhcc: clock-controller { 5614 compatible = "qcom,sm8250-rpmh-clk"; 5615 #clock-cells = <1>; 5616 clock-names = "xo"; 5617 clocks = <&xo_board>; 5618 }; 5619 5620 rpmhpd: power-controller { 5621 compatible = "qcom,sm8250-rpmhpd"; 5622 #power-domain-cells = <1>; 5623 operating-points-v2 = <&rpmhpd_opp_table>; 5624 5625 rpmhpd_opp_table: opp-table { 5626 compatible = "operating-points-v2"; 5627 5628 rpmhpd_opp_ret: opp1 { 5629 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5630 }; 5631 5632 rpmhpd_opp_min_svs: opp2 { 5633 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5634 }; 5635 5636 rpmhpd_opp_low_svs: opp3 { 5637 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5638 }; 5639 5640 rpmhpd_opp_svs: opp4 { 5641 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5642 }; 5643 5644 rpmhpd_opp_svs_l1: opp5 { 5645 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5646 }; 5647 5648 rpmhpd_opp_nom: opp6 { 5649 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5650 }; 5651 5652 rpmhpd_opp_nom_l1: opp7 { 5653 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5654 }; 5655 5656 rpmhpd_opp_nom_l2: opp8 { 5657 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5658 }; 5659 5660 rpmhpd_opp_turbo: opp9 { 5661 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5662 }; 5663 5664 rpmhpd_opp_turbo_l1: opp10 { 5665 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5666 }; 5667 }; 5668 }; 5669 5670 apps_bcm_voter: bcm-voter { 5671 compatible = "qcom,bcm-voter"; 5672 }; 5673 }; 5674 5675 epss_l3: interconnect@18590000 { 5676 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5677 reg = <0 0x18590000 0 0x1000>; 5678 5679 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5680 clock-names = "xo", "alternate"; 5681 5682 #interconnect-cells = <2>; 5683 }; 5684 5685 cpufreq_hw: cpufreq@18591000 { 5686 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5687 reg = <0 0x18591000 0 0x1000>, 5688 <0 0x18592000 0 0x1000>, 5689 <0 0x18593000 0 0x1000>; 5690 reg-names = "freq-domain0", "freq-domain1", 5691 "freq-domain2"; 5692 5693 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5694 clock-names = "xo", "alternate"; 5695 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5698 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5699 #freq-domain-cells = <1>; 5700 #clock-cells = <1>; 5701 }; 5702 }; 5703 5704 sound: sound { 5705 }; 5706 5707 timer { 5708 compatible = "arm,armv8-timer"; 5709 interrupts = <GIC_PPI 13 5710 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5711 <GIC_PPI 14 5712 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5713 <GIC_PPI 11 5714 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5715 <GIC_PPI 10 5716 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5717 }; 5718 5719 thermal-zones { 5720 cpu0-thermal { 5721 polling-delay-passive = <250>; 5722 polling-delay = <1000>; 5723 5724 thermal-sensors = <&tsens0 1>; 5725 5726 trips { 5727 cpu0_alert0: trip-point0 { 5728 temperature = <90000>; 5729 hysteresis = <2000>; 5730 type = "passive"; 5731 }; 5732 5733 cpu0_alert1: trip-point1 { 5734 temperature = <95000>; 5735 hysteresis = <2000>; 5736 type = "passive"; 5737 }; 5738 5739 cpu0_crit: cpu-crit { 5740 temperature = <110000>; 5741 hysteresis = <1000>; 5742 type = "critical"; 5743 }; 5744 }; 5745 5746 cooling-maps { 5747 map0 { 5748 trip = <&cpu0_alert0>; 5749 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5751 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5752 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5753 }; 5754 map1 { 5755 trip = <&cpu0_alert1>; 5756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5760 }; 5761 }; 5762 }; 5763 5764 cpu1-thermal { 5765 polling-delay-passive = <250>; 5766 polling-delay = <1000>; 5767 5768 thermal-sensors = <&tsens0 2>; 5769 5770 trips { 5771 cpu1_alert0: trip-point0 { 5772 temperature = <90000>; 5773 hysteresis = <2000>; 5774 type = "passive"; 5775 }; 5776 5777 cpu1_alert1: trip-point1 { 5778 temperature = <95000>; 5779 hysteresis = <2000>; 5780 type = "passive"; 5781 }; 5782 5783 cpu1_crit: cpu-crit { 5784 temperature = <110000>; 5785 hysteresis = <1000>; 5786 type = "critical"; 5787 }; 5788 }; 5789 5790 cooling-maps { 5791 map0 { 5792 trip = <&cpu1_alert0>; 5793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5797 }; 5798 map1 { 5799 trip = <&cpu1_alert1>; 5800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5803 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5804 }; 5805 }; 5806 }; 5807 5808 cpu2-thermal { 5809 polling-delay-passive = <250>; 5810 polling-delay = <1000>; 5811 5812 thermal-sensors = <&tsens0 3>; 5813 5814 trips { 5815 cpu2_alert0: trip-point0 { 5816 temperature = <90000>; 5817 hysteresis = <2000>; 5818 type = "passive"; 5819 }; 5820 5821 cpu2_alert1: trip-point1 { 5822 temperature = <95000>; 5823 hysteresis = <2000>; 5824 type = "passive"; 5825 }; 5826 5827 cpu2_crit: cpu-crit { 5828 temperature = <110000>; 5829 hysteresis = <1000>; 5830 type = "critical"; 5831 }; 5832 }; 5833 5834 cooling-maps { 5835 map0 { 5836 trip = <&cpu2_alert0>; 5837 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5839 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5840 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5841 }; 5842 map1 { 5843 trip = <&cpu2_alert1>; 5844 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5847 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5848 }; 5849 }; 5850 }; 5851 5852 cpu3-thermal { 5853 polling-delay-passive = <250>; 5854 polling-delay = <1000>; 5855 5856 thermal-sensors = <&tsens0 4>; 5857 5858 trips { 5859 cpu3_alert0: trip-point0 { 5860 temperature = <90000>; 5861 hysteresis = <2000>; 5862 type = "passive"; 5863 }; 5864 5865 cpu3_alert1: trip-point1 { 5866 temperature = <95000>; 5867 hysteresis = <2000>; 5868 type = "passive"; 5869 }; 5870 5871 cpu3_crit: cpu-crit { 5872 temperature = <110000>; 5873 hysteresis = <1000>; 5874 type = "critical"; 5875 }; 5876 }; 5877 5878 cooling-maps { 5879 map0 { 5880 trip = <&cpu3_alert0>; 5881 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5883 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5884 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5885 }; 5886 map1 { 5887 trip = <&cpu3_alert1>; 5888 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5891 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5892 }; 5893 }; 5894 }; 5895 5896 cpu4-top-thermal { 5897 polling-delay-passive = <250>; 5898 polling-delay = <1000>; 5899 5900 thermal-sensors = <&tsens0 7>; 5901 5902 trips { 5903 cpu4_top_alert0: trip-point0 { 5904 temperature = <90000>; 5905 hysteresis = <2000>; 5906 type = "passive"; 5907 }; 5908 5909 cpu4_top_alert1: trip-point1 { 5910 temperature = <95000>; 5911 hysteresis = <2000>; 5912 type = "passive"; 5913 }; 5914 5915 cpu4_top_crit: cpu-crit { 5916 temperature = <110000>; 5917 hysteresis = <1000>; 5918 type = "critical"; 5919 }; 5920 }; 5921 5922 cooling-maps { 5923 map0 { 5924 trip = <&cpu4_top_alert0>; 5925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5929 }; 5930 map1 { 5931 trip = <&cpu4_top_alert1>; 5932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5936 }; 5937 }; 5938 }; 5939 5940 cpu5-top-thermal { 5941 polling-delay-passive = <250>; 5942 polling-delay = <1000>; 5943 5944 thermal-sensors = <&tsens0 8>; 5945 5946 trips { 5947 cpu5_top_alert0: trip-point0 { 5948 temperature = <90000>; 5949 hysteresis = <2000>; 5950 type = "passive"; 5951 }; 5952 5953 cpu5_top_alert1: trip-point1 { 5954 temperature = <95000>; 5955 hysteresis = <2000>; 5956 type = "passive"; 5957 }; 5958 5959 cpu5_top_crit: cpu-crit { 5960 temperature = <110000>; 5961 hysteresis = <1000>; 5962 type = "critical"; 5963 }; 5964 }; 5965 5966 cooling-maps { 5967 map0 { 5968 trip = <&cpu5_top_alert0>; 5969 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5971 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5972 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5973 }; 5974 map1 { 5975 trip = <&cpu5_top_alert1>; 5976 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5977 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5978 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5979 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5980 }; 5981 }; 5982 }; 5983 5984 cpu6-top-thermal { 5985 polling-delay-passive = <250>; 5986 polling-delay = <1000>; 5987 5988 thermal-sensors = <&tsens0 9>; 5989 5990 trips { 5991 cpu6_top_alert0: trip-point0 { 5992 temperature = <90000>; 5993 hysteresis = <2000>; 5994 type = "passive"; 5995 }; 5996 5997 cpu6_top_alert1: trip-point1 { 5998 temperature = <95000>; 5999 hysteresis = <2000>; 6000 type = "passive"; 6001 }; 6002 6003 cpu6_top_crit: cpu-crit { 6004 temperature = <110000>; 6005 hysteresis = <1000>; 6006 type = "critical"; 6007 }; 6008 }; 6009 6010 cooling-maps { 6011 map0 { 6012 trip = <&cpu6_top_alert0>; 6013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6014 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6015 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6016 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6017 }; 6018 map1 { 6019 trip = <&cpu6_top_alert1>; 6020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6024 }; 6025 }; 6026 }; 6027 6028 cpu7-top-thermal { 6029 polling-delay-passive = <250>; 6030 polling-delay = <1000>; 6031 6032 thermal-sensors = <&tsens0 10>; 6033 6034 trips { 6035 cpu7_top_alert0: trip-point0 { 6036 temperature = <90000>; 6037 hysteresis = <2000>; 6038 type = "passive"; 6039 }; 6040 6041 cpu7_top_alert1: trip-point1 { 6042 temperature = <95000>; 6043 hysteresis = <2000>; 6044 type = "passive"; 6045 }; 6046 6047 cpu7_top_crit: cpu-crit { 6048 temperature = <110000>; 6049 hysteresis = <1000>; 6050 type = "critical"; 6051 }; 6052 }; 6053 6054 cooling-maps { 6055 map0 { 6056 trip = <&cpu7_top_alert0>; 6057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6058 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6059 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6061 }; 6062 map1 { 6063 trip = <&cpu7_top_alert1>; 6064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6065 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6066 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6068 }; 6069 }; 6070 }; 6071 6072 cpu4-bottom-thermal { 6073 polling-delay-passive = <250>; 6074 polling-delay = <1000>; 6075 6076 thermal-sensors = <&tsens0 11>; 6077 6078 trips { 6079 cpu4_bottom_alert0: trip-point0 { 6080 temperature = <90000>; 6081 hysteresis = <2000>; 6082 type = "passive"; 6083 }; 6084 6085 cpu4_bottom_alert1: trip-point1 { 6086 temperature = <95000>; 6087 hysteresis = <2000>; 6088 type = "passive"; 6089 }; 6090 6091 cpu4_bottom_crit: cpu-crit { 6092 temperature = <110000>; 6093 hysteresis = <1000>; 6094 type = "critical"; 6095 }; 6096 }; 6097 6098 cooling-maps { 6099 map0 { 6100 trip = <&cpu4_bottom_alert0>; 6101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6102 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6103 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6105 }; 6106 map1 { 6107 trip = <&cpu4_bottom_alert1>; 6108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6109 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6110 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6111 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6112 }; 6113 }; 6114 }; 6115 6116 cpu5-bottom-thermal { 6117 polling-delay-passive = <250>; 6118 polling-delay = <1000>; 6119 6120 thermal-sensors = <&tsens0 12>; 6121 6122 trips { 6123 cpu5_bottom_alert0: trip-point0 { 6124 temperature = <90000>; 6125 hysteresis = <2000>; 6126 type = "passive"; 6127 }; 6128 6129 cpu5_bottom_alert1: trip-point1 { 6130 temperature = <95000>; 6131 hysteresis = <2000>; 6132 type = "passive"; 6133 }; 6134 6135 cpu5_bottom_crit: cpu-crit { 6136 temperature = <110000>; 6137 hysteresis = <1000>; 6138 type = "critical"; 6139 }; 6140 }; 6141 6142 cooling-maps { 6143 map0 { 6144 trip = <&cpu5_bottom_alert0>; 6145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6146 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6147 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6148 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6149 }; 6150 map1 { 6151 trip = <&cpu5_bottom_alert1>; 6152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6156 }; 6157 }; 6158 }; 6159 6160 cpu6-bottom-thermal { 6161 polling-delay-passive = <250>; 6162 polling-delay = <1000>; 6163 6164 thermal-sensors = <&tsens0 13>; 6165 6166 trips { 6167 cpu6_bottom_alert0: trip-point0 { 6168 temperature = <90000>; 6169 hysteresis = <2000>; 6170 type = "passive"; 6171 }; 6172 6173 cpu6_bottom_alert1: trip-point1 { 6174 temperature = <95000>; 6175 hysteresis = <2000>; 6176 type = "passive"; 6177 }; 6178 6179 cpu6_bottom_crit: cpu-crit { 6180 temperature = <110000>; 6181 hysteresis = <1000>; 6182 type = "critical"; 6183 }; 6184 }; 6185 6186 cooling-maps { 6187 map0 { 6188 trip = <&cpu6_bottom_alert0>; 6189 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6190 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6191 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6192 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6193 }; 6194 map1 { 6195 trip = <&cpu6_bottom_alert1>; 6196 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6197 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6198 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6200 }; 6201 }; 6202 }; 6203 6204 cpu7-bottom-thermal { 6205 polling-delay-passive = <250>; 6206 polling-delay = <1000>; 6207 6208 thermal-sensors = <&tsens0 14>; 6209 6210 trips { 6211 cpu7_bottom_alert0: trip-point0 { 6212 temperature = <90000>; 6213 hysteresis = <2000>; 6214 type = "passive"; 6215 }; 6216 6217 cpu7_bottom_alert1: trip-point1 { 6218 temperature = <95000>; 6219 hysteresis = <2000>; 6220 type = "passive"; 6221 }; 6222 6223 cpu7_bottom_crit: cpu-crit { 6224 temperature = <110000>; 6225 hysteresis = <1000>; 6226 type = "critical"; 6227 }; 6228 }; 6229 6230 cooling-maps { 6231 map0 { 6232 trip = <&cpu7_bottom_alert0>; 6233 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6234 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6235 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6236 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6237 }; 6238 map1 { 6239 trip = <&cpu7_bottom_alert1>; 6240 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6241 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6242 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6243 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6244 }; 6245 }; 6246 }; 6247 6248 aoss0-thermal { 6249 polling-delay-passive = <250>; 6250 polling-delay = <1000>; 6251 6252 thermal-sensors = <&tsens0 0>; 6253 6254 trips { 6255 aoss0_alert0: trip-point0 { 6256 temperature = <90000>; 6257 hysteresis = <2000>; 6258 type = "hot"; 6259 }; 6260 }; 6261 }; 6262 6263 cluster0-thermal { 6264 polling-delay-passive = <250>; 6265 polling-delay = <1000>; 6266 6267 thermal-sensors = <&tsens0 5>; 6268 6269 trips { 6270 cluster0_alert0: trip-point0 { 6271 temperature = <90000>; 6272 hysteresis = <2000>; 6273 type = "hot"; 6274 }; 6275 cluster0_crit: cluster0_crit { 6276 temperature = <110000>; 6277 hysteresis = <2000>; 6278 type = "critical"; 6279 }; 6280 }; 6281 }; 6282 6283 cluster1-thermal { 6284 polling-delay-passive = <250>; 6285 polling-delay = <1000>; 6286 6287 thermal-sensors = <&tsens0 6>; 6288 6289 trips { 6290 cluster1_alert0: trip-point0 { 6291 temperature = <90000>; 6292 hysteresis = <2000>; 6293 type = "hot"; 6294 }; 6295 cluster1_crit: cluster1_crit { 6296 temperature = <110000>; 6297 hysteresis = <2000>; 6298 type = "critical"; 6299 }; 6300 }; 6301 }; 6302 6303 gpu-top-thermal { 6304 polling-delay-passive = <250>; 6305 polling-delay = <1000>; 6306 6307 thermal-sensors = <&tsens0 15>; 6308 6309 trips { 6310 gpu1_alert0: trip-point0 { 6311 temperature = <90000>; 6312 hysteresis = <2000>; 6313 type = "hot"; 6314 }; 6315 }; 6316 }; 6317 6318 aoss1-thermal { 6319 polling-delay-passive = <250>; 6320 polling-delay = <1000>; 6321 6322 thermal-sensors = <&tsens1 0>; 6323 6324 trips { 6325 aoss1_alert0: trip-point0 { 6326 temperature = <90000>; 6327 hysteresis = <2000>; 6328 type = "hot"; 6329 }; 6330 }; 6331 }; 6332 6333 wlan-thermal { 6334 polling-delay-passive = <250>; 6335 polling-delay = <1000>; 6336 6337 thermal-sensors = <&tsens1 1>; 6338 6339 trips { 6340 wlan_alert0: trip-point0 { 6341 temperature = <90000>; 6342 hysteresis = <2000>; 6343 type = "hot"; 6344 }; 6345 }; 6346 }; 6347 6348 video-thermal { 6349 polling-delay-passive = <250>; 6350 polling-delay = <1000>; 6351 6352 thermal-sensors = <&tsens1 2>; 6353 6354 trips { 6355 video_alert0: trip-point0 { 6356 temperature = <90000>; 6357 hysteresis = <2000>; 6358 type = "hot"; 6359 }; 6360 }; 6361 }; 6362 6363 mem-thermal { 6364 polling-delay-passive = <250>; 6365 polling-delay = <1000>; 6366 6367 thermal-sensors = <&tsens1 3>; 6368 6369 trips { 6370 mem_alert0: trip-point0 { 6371 temperature = <90000>; 6372 hysteresis = <2000>; 6373 type = "hot"; 6374 }; 6375 }; 6376 }; 6377 6378 q6-hvx-thermal { 6379 polling-delay-passive = <250>; 6380 polling-delay = <1000>; 6381 6382 thermal-sensors = <&tsens1 4>; 6383 6384 trips { 6385 q6_hvx_alert0: trip-point0 { 6386 temperature = <90000>; 6387 hysteresis = <2000>; 6388 type = "hot"; 6389 }; 6390 }; 6391 }; 6392 6393 camera-thermal { 6394 polling-delay-passive = <250>; 6395 polling-delay = <1000>; 6396 6397 thermal-sensors = <&tsens1 5>; 6398 6399 trips { 6400 camera_alert0: trip-point0 { 6401 temperature = <90000>; 6402 hysteresis = <2000>; 6403 type = "hot"; 6404 }; 6405 }; 6406 }; 6407 6408 compute-thermal { 6409 polling-delay-passive = <250>; 6410 polling-delay = <1000>; 6411 6412 thermal-sensors = <&tsens1 6>; 6413 6414 trips { 6415 compute_alert0: trip-point0 { 6416 temperature = <90000>; 6417 hysteresis = <2000>; 6418 type = "hot"; 6419 }; 6420 }; 6421 }; 6422 6423 npu-thermal { 6424 polling-delay-passive = <250>; 6425 polling-delay = <1000>; 6426 6427 thermal-sensors = <&tsens1 7>; 6428 6429 trips { 6430 npu_alert0: trip-point0 { 6431 temperature = <90000>; 6432 hysteresis = <2000>; 6433 type = "hot"; 6434 }; 6435 }; 6436 }; 6437 6438 gpu-bottom-thermal { 6439 polling-delay-passive = <250>; 6440 polling-delay = <1000>; 6441 6442 thermal-sensors = <&tsens1 8>; 6443 6444 trips { 6445 gpu2_alert0: trip-point0 { 6446 temperature = <90000>; 6447 hysteresis = <2000>; 6448 type = "hot"; 6449 }; 6450 }; 6451 }; 6452 }; 6453}; 6454