1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 int ql2xfc2target = 1; 364 module_param(ql2xfc2target, int, 0444); 365 MODULE_PARM_DESC(qla2xfc2target, 366 "Enables FC2 Target support. " 367 "0 - FC2 Target support is disabled. " 368 "1 - FC2 Target support is enabled (default)."); 369 370 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 371 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 372 373 /* TODO Convert to inlines 374 * 375 * Timer routines 376 */ 377 378 __inline__ void 379 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 timer_setup(&vha->timer, qla2x00_timer, 0); 382 vha->timer.expires = jiffies + interval * HZ; 383 add_timer(&vha->timer); 384 vha->timer_active = 1; 385 } 386 387 static inline void 388 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 389 { 390 /* Currently used for 82XX only. */ 391 if (vha->device_flags & DFLG_DEV_FAILED) { 392 ql_dbg(ql_dbg_timer, vha, 0x600d, 393 "Device in a failed state, returning.\n"); 394 return; 395 } 396 397 mod_timer(&vha->timer, jiffies + interval * HZ); 398 } 399 400 static __inline__ void 401 qla2x00_stop_timer(scsi_qla_host_t *vha) 402 { 403 del_timer_sync(&vha->timer); 404 vha->timer_active = 0; 405 } 406 407 static int qla2x00_do_dpc(void *data); 408 409 static void qla2x00_rst_aen(scsi_qla_host_t *); 410 411 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 412 struct req_que **, struct rsp_que **); 413 static void qla2x00_free_fw_dump(struct qla_hw_data *); 414 static void qla2x00_mem_free(struct qla_hw_data *); 415 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 416 struct qla_qpair *qpair); 417 418 /* -------------------------------------------------------------------------- */ 419 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 420 struct rsp_que *rsp) 421 { 422 struct qla_hw_data *ha = vha->hw; 423 424 rsp->qpair = ha->base_qpair; 425 rsp->req = req; 426 ha->base_qpair->hw = ha; 427 ha->base_qpair->req = req; 428 ha->base_qpair->rsp = rsp; 429 ha->base_qpair->vha = vha; 430 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 431 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 432 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 433 ha->base_qpair->srb_mempool = ha->srb_mempool; 434 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 435 ha->base_qpair->enable_class_2 = ql2xenableclass2; 436 /* init qpair to this cpu. Will adjust at run time. */ 437 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 438 ha->base_qpair->pdev = ha->pdev; 439 440 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 441 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 442 } 443 444 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 445 struct rsp_que *rsp) 446 { 447 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 448 449 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 450 GFP_KERNEL); 451 if (!ha->req_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003b, 453 "Unable to allocate memory for request queue ptrs.\n"); 454 goto fail_req_map; 455 } 456 457 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 458 GFP_KERNEL); 459 if (!ha->rsp_q_map) { 460 ql_log(ql_log_fatal, vha, 0x003c, 461 "Unable to allocate memory for response queue ptrs.\n"); 462 goto fail_rsp_map; 463 } 464 465 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 466 if (ha->base_qpair == NULL) { 467 ql_log(ql_log_warn, vha, 0x00e0, 468 "Failed to allocate base queue pair memory.\n"); 469 goto fail_base_qpair; 470 } 471 472 qla_init_base_qpair(vha, req, rsp); 473 474 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 475 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 476 GFP_KERNEL); 477 if (!ha->queue_pair_map) { 478 ql_log(ql_log_fatal, vha, 0x0180, 479 "Unable to allocate memory for queue pair ptrs.\n"); 480 goto fail_qpair_map; 481 } 482 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 483 kfree(ha->queue_pair_map); 484 ha->queue_pair_map = NULL; 485 goto fail_qpair_map; 486 } 487 } 488 489 /* 490 * Make sure we record at least the request and response queue zero in 491 * case we need to free them if part of the probe fails. 492 */ 493 ha->rsp_q_map[0] = rsp; 494 ha->req_q_map[0] = req; 495 set_bit(0, ha->rsp_qid_map); 496 set_bit(0, ha->req_qid_map); 497 return 0; 498 499 fail_qpair_map: 500 kfree(ha->base_qpair); 501 ha->base_qpair = NULL; 502 fail_base_qpair: 503 kfree(ha->rsp_q_map); 504 ha->rsp_q_map = NULL; 505 fail_rsp_map: 506 kfree(ha->req_q_map); 507 ha->req_q_map = NULL; 508 fail_req_map: 509 return -ENOMEM; 510 } 511 512 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 513 { 514 if (IS_QLAFX00(ha)) { 515 if (req && req->ring_fx00) 516 dma_free_coherent(&ha->pdev->dev, 517 (req->length_fx00 + 1) * sizeof(request_t), 518 req->ring_fx00, req->dma_fx00); 519 } else if (req && req->ring) 520 dma_free_coherent(&ha->pdev->dev, 521 (req->length + 1) * sizeof(request_t), 522 req->ring, req->dma); 523 524 if (req) 525 kfree(req->outstanding_cmds); 526 527 kfree(req); 528 } 529 530 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 531 { 532 if (IS_QLAFX00(ha)) { 533 if (rsp && rsp->ring_fx00) 534 dma_free_coherent(&ha->pdev->dev, 535 (rsp->length_fx00 + 1) * sizeof(request_t), 536 rsp->ring_fx00, rsp->dma_fx00); 537 } else if (rsp && rsp->ring) { 538 dma_free_coherent(&ha->pdev->dev, 539 (rsp->length + 1) * sizeof(response_t), 540 rsp->ring, rsp->dma); 541 } 542 kfree(rsp); 543 } 544 545 static void qla2x00_free_queues(struct qla_hw_data *ha) 546 { 547 struct req_que *req; 548 struct rsp_que *rsp; 549 int cnt; 550 unsigned long flags; 551 552 if (ha->queue_pair_map) { 553 kfree(ha->queue_pair_map); 554 ha->queue_pair_map = NULL; 555 } 556 if (ha->base_qpair) { 557 kfree(ha->base_qpair); 558 ha->base_qpair = NULL; 559 } 560 561 qla_mapq_free_qp_cpu_map(ha); 562 spin_lock_irqsave(&ha->hardware_lock, flags); 563 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 564 if (!test_bit(cnt, ha->req_qid_map)) 565 continue; 566 567 req = ha->req_q_map[cnt]; 568 clear_bit(cnt, ha->req_qid_map); 569 ha->req_q_map[cnt] = NULL; 570 571 spin_unlock_irqrestore(&ha->hardware_lock, flags); 572 qla2x00_free_req_que(ha, req); 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 } 575 spin_unlock_irqrestore(&ha->hardware_lock, flags); 576 577 kfree(ha->req_q_map); 578 ha->req_q_map = NULL; 579 580 581 spin_lock_irqsave(&ha->hardware_lock, flags); 582 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 583 if (!test_bit(cnt, ha->rsp_qid_map)) 584 continue; 585 586 rsp = ha->rsp_q_map[cnt]; 587 clear_bit(cnt, ha->rsp_qid_map); 588 ha->rsp_q_map[cnt] = NULL; 589 spin_unlock_irqrestore(&ha->hardware_lock, flags); 590 qla2x00_free_rsp_que(ha, rsp); 591 spin_lock_irqsave(&ha->hardware_lock, flags); 592 } 593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 594 595 kfree(ha->rsp_q_map); 596 ha->rsp_q_map = NULL; 597 } 598 599 static char * 600 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 static const char *const pci_bus_modes[] = { 604 "33", "66", "100", "133", 605 }; 606 uint16_t pci_bus; 607 608 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 609 if (pci_bus) { 610 snprintf(str, str_len, "PCI-X (%s MHz)", 611 pci_bus_modes[pci_bus]); 612 } else { 613 pci_bus = (ha->pci_attr & BIT_8) >> 8; 614 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 615 } 616 617 return str; 618 } 619 620 static char * 621 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 622 { 623 static const char *const pci_bus_modes[] = { 624 "33", "66", "100", "133", 625 }; 626 struct qla_hw_data *ha = vha->hw; 627 uint32_t pci_bus; 628 629 if (pci_is_pcie(ha->pdev)) { 630 uint32_t lstat, lspeed, lwidth; 631 const char *speed_str; 632 633 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 634 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 635 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 636 637 switch (lspeed) { 638 case 1: 639 speed_str = "2.5GT/s"; 640 break; 641 case 2: 642 speed_str = "5.0GT/s"; 643 break; 644 case 3: 645 speed_str = "8.0GT/s"; 646 break; 647 case 4: 648 speed_str = "16.0GT/s"; 649 break; 650 default: 651 speed_str = "<unknown>"; 652 break; 653 } 654 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 655 656 return str; 657 } 658 659 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 660 if (pci_bus == 0 || pci_bus == 8) 661 snprintf(str, str_len, "PCI (%s MHz)", 662 pci_bus_modes[pci_bus >> 3]); 663 else 664 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 665 pci_bus & 4 ? 2 : 1, 666 pci_bus_modes[pci_bus & 3]); 667 668 return str; 669 } 670 671 static char * 672 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 673 { 674 char un_str[10]; 675 struct qla_hw_data *ha = vha->hw; 676 677 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 678 ha->fw_minor_version, ha->fw_subminor_version); 679 680 if (ha->fw_attributes & BIT_9) { 681 strcat(str, "FLX"); 682 return (str); 683 } 684 685 switch (ha->fw_attributes & 0xFF) { 686 case 0x7: 687 strcat(str, "EF"); 688 break; 689 case 0x17: 690 strcat(str, "TP"); 691 break; 692 case 0x37: 693 strcat(str, "IP"); 694 break; 695 case 0x77: 696 strcat(str, "VI"); 697 break; 698 default: 699 sprintf(un_str, "(%x)", ha->fw_attributes); 700 strcat(str, un_str); 701 break; 702 } 703 if (ha->fw_attributes & 0x100) 704 strcat(str, "X"); 705 706 return (str); 707 } 708 709 static char * 710 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 711 { 712 struct qla_hw_data *ha = vha->hw; 713 714 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 715 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 716 return str; 717 } 718 719 void qla2x00_sp_free_dma(srb_t *sp) 720 { 721 struct qla_hw_data *ha = sp->vha->hw; 722 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 723 724 if (sp->flags & SRB_DMA_VALID) { 725 scsi_dma_unmap(cmd); 726 sp->flags &= ~SRB_DMA_VALID; 727 } 728 729 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 730 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 731 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 732 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 736 /* List assured to be having elements */ 737 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 738 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 742 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 743 744 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 745 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 746 } 747 748 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 749 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 750 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 752 ctx1->fcp_cmnd_dma); 753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 756 } 757 758 if (sp->flags & SRB_GOT_BUF) 759 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 760 } 761 762 void qla2x00_sp_compl(srb_t *sp, int res) 763 { 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct completion *comp = sp->comp; 766 767 /* kref: INIT */ 768 kref_put(&sp->cmd_kref, qla2x00_sp_release); 769 cmd->result = res; 770 sp->type = 0; 771 scsi_done(cmd); 772 if (comp) 773 complete(comp); 774 } 775 776 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 777 { 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 779 struct qla_hw_data *ha = sp->fcport->vha->hw; 780 781 if (sp->flags & SRB_DMA_VALID) { 782 scsi_dma_unmap(cmd); 783 sp->flags &= ~SRB_DMA_VALID; 784 } 785 786 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 787 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 788 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 789 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 790 } 791 792 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 793 /* List assured to be having elements */ 794 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 795 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 796 } 797 798 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 799 struct crc_context *difctx = sp->u.scmd.crc_ctx; 800 struct dsd_dma *dif_dsd, *nxt_dsd; 801 802 list_for_each_entry_safe(dif_dsd, nxt_dsd, 803 &difctx->ldif_dma_hndl_list, list) { 804 list_del(&dif_dsd->list); 805 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 806 dif_dsd->dsd_list_dma); 807 kfree(dif_dsd); 808 difctx->no_dif_bundl--; 809 } 810 811 list_for_each_entry_safe(dif_dsd, nxt_dsd, 812 &difctx->ldif_dsd_list, list) { 813 list_del(&dif_dsd->list); 814 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 815 dif_dsd->dsd_list_dma); 816 kfree(dif_dsd); 817 difctx->no_ldif_dsd--; 818 } 819 820 if (difctx->no_ldif_dsd) { 821 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 822 "%s: difctx->no_ldif_dsd=%x\n", 823 __func__, difctx->no_ldif_dsd); 824 } 825 826 if (difctx->no_dif_bundl) { 827 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 828 "%s: difctx->no_dif_bundl=%x\n", 829 __func__, difctx->no_dif_bundl); 830 } 831 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 832 } 833 834 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 835 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 836 837 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 838 ctx1->fcp_cmnd_dma); 839 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 840 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 841 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 842 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 843 } 844 845 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 846 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 847 848 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 849 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 850 } 851 852 if (sp->flags & SRB_GOT_BUF) 853 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 854 } 855 856 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 857 { 858 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 859 struct completion *comp = sp->comp; 860 861 /* ref: INIT */ 862 kref_put(&sp->cmd_kref, qla2x00_sp_release); 863 cmd->result = res; 864 sp->type = 0; 865 scsi_done(cmd); 866 if (comp) 867 complete(comp); 868 } 869 870 static int 871 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 872 { 873 scsi_qla_host_t *vha = shost_priv(host); 874 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 875 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 876 struct qla_hw_data *ha = vha->hw; 877 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 878 srb_t *sp; 879 int rval; 880 881 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 882 WARN_ON_ONCE(!rport)) { 883 cmd->result = DID_NO_CONNECT << 16; 884 goto qc24_fail_command; 885 } 886 887 if (ha->mqenable) { 888 uint32_t tag; 889 uint16_t hwq; 890 struct qla_qpair *qpair = NULL; 891 892 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 893 hwq = blk_mq_unique_tag_to_hwq(tag); 894 qpair = ha->queue_pair_map[hwq]; 895 896 if (qpair) 897 return qla2xxx_mqueuecommand(host, cmd, qpair); 898 } 899 900 if (ha->flags.eeh_busy) { 901 if (ha->flags.pci_channel_io_perm_failure) { 902 ql_dbg(ql_dbg_aer, vha, 0x9010, 903 "PCI Channel IO permanent failure, exiting " 904 "cmd=%p.\n", cmd); 905 cmd->result = DID_NO_CONNECT << 16; 906 } else { 907 ql_dbg(ql_dbg_aer, vha, 0x9011, 908 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 909 cmd->result = DID_REQUEUE << 16; 910 } 911 goto qc24_fail_command; 912 } 913 914 rval = fc_remote_port_chkready(rport); 915 if (rval) { 916 cmd->result = rval; 917 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 918 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 919 cmd, rval); 920 goto qc24_fail_command; 921 } 922 923 if (!vha->flags.difdix_supported && 924 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 925 ql_dbg(ql_dbg_io, vha, 0x3004, 926 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 927 cmd); 928 cmd->result = DID_NO_CONNECT << 16; 929 goto qc24_fail_command; 930 } 931 932 if (!fcport || fcport->deleted) { 933 cmd->result = DID_IMM_RETRY << 16; 934 goto qc24_fail_command; 935 } 936 937 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 938 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 939 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 940 ql_dbg(ql_dbg_io, vha, 0x3005, 941 "Returning DNC, fcport_state=%d loop_state=%d.\n", 942 atomic_read(&fcport->state), 943 atomic_read(&base_vha->loop_state)); 944 cmd->result = DID_NO_CONNECT << 16; 945 goto qc24_fail_command; 946 } 947 goto qc24_target_busy; 948 } 949 950 /* 951 * Return target busy if we've received a non-zero retry_delay_timer 952 * in a FCP_RSP. 953 */ 954 if (fcport->retry_delay_timestamp == 0) { 955 /* retry delay not set */ 956 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 957 fcport->retry_delay_timestamp = 0; 958 else 959 goto qc24_target_busy; 960 961 sp = scsi_cmd_priv(cmd); 962 /* ref: INIT */ 963 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 964 965 sp->u.scmd.cmd = cmd; 966 sp->type = SRB_SCSI_CMD; 967 sp->free = qla2x00_sp_free_dma; 968 sp->done = qla2x00_sp_compl; 969 970 rval = ha->isp_ops->start_scsi(sp); 971 if (rval != QLA_SUCCESS) { 972 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 973 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 974 goto qc24_host_busy_free_sp; 975 } 976 977 return 0; 978 979 qc24_host_busy_free_sp: 980 /* ref: INIT */ 981 kref_put(&sp->cmd_kref, qla2x00_sp_release); 982 983 qc24_target_busy: 984 return SCSI_MLQUEUE_TARGET_BUSY; 985 986 qc24_fail_command: 987 scsi_done(cmd); 988 989 return 0; 990 } 991 992 /* For MQ supported I/O */ 993 int 994 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 995 struct qla_qpair *qpair) 996 { 997 scsi_qla_host_t *vha = shost_priv(host); 998 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 999 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1000 struct qla_hw_data *ha = vha->hw; 1001 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1002 srb_t *sp; 1003 int rval; 1004 1005 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1006 if (rval) { 1007 cmd->result = rval; 1008 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1009 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1010 cmd, rval); 1011 goto qc24_fail_command; 1012 } 1013 1014 if (!qpair->online) { 1015 ql_dbg(ql_dbg_io, vha, 0x3077, 1016 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1017 cmd->result = DID_NO_CONNECT << 16; 1018 goto qc24_fail_command; 1019 } 1020 1021 if (!fcport || fcport->deleted) { 1022 cmd->result = DID_IMM_RETRY << 16; 1023 goto qc24_fail_command; 1024 } 1025 1026 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1027 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1028 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1029 ql_dbg(ql_dbg_io, vha, 0x3077, 1030 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1031 atomic_read(&fcport->state), 1032 atomic_read(&base_vha->loop_state)); 1033 cmd->result = DID_NO_CONNECT << 16; 1034 goto qc24_fail_command; 1035 } 1036 goto qc24_target_busy; 1037 } 1038 1039 /* 1040 * Return target busy if we've received a non-zero retry_delay_timer 1041 * in a FCP_RSP. 1042 */ 1043 if (fcport->retry_delay_timestamp == 0) { 1044 /* retry delay not set */ 1045 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1046 fcport->retry_delay_timestamp = 0; 1047 else 1048 goto qc24_target_busy; 1049 1050 sp = scsi_cmd_priv(cmd); 1051 /* ref: INIT */ 1052 qla2xxx_init_sp(sp, vha, qpair, fcport); 1053 1054 sp->u.scmd.cmd = cmd; 1055 sp->type = SRB_SCSI_CMD; 1056 sp->free = qla2xxx_qpair_sp_free_dma; 1057 sp->done = qla2xxx_qpair_sp_compl; 1058 1059 rval = ha->isp_ops->start_scsi_mq(sp); 1060 if (rval != QLA_SUCCESS) { 1061 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1062 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1063 goto qc24_host_busy_free_sp; 1064 } 1065 1066 return 0; 1067 1068 qc24_host_busy_free_sp: 1069 /* ref: INIT */ 1070 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1071 1072 qc24_target_busy: 1073 return SCSI_MLQUEUE_TARGET_BUSY; 1074 1075 qc24_fail_command: 1076 scsi_done(cmd); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * qla2x00_eh_wait_on_command 1083 * Waits for the command to be returned by the Firmware for some 1084 * max time. 1085 * 1086 * Input: 1087 * cmd = Scsi Command to wait on. 1088 * 1089 * Return: 1090 * Completed in time : QLA_SUCCESS 1091 * Did not complete in time : QLA_FUNCTION_FAILED 1092 */ 1093 static int 1094 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1095 { 1096 #define ABORT_POLLING_PERIOD 1000 1097 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1098 unsigned long wait_iter = ABORT_WAIT_ITER; 1099 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1100 struct qla_hw_data *ha = vha->hw; 1101 srb_t *sp = scsi_cmd_priv(cmd); 1102 int ret = QLA_SUCCESS; 1103 1104 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1105 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1106 "Return:eh_wait.\n"); 1107 return ret; 1108 } 1109 1110 while (sp->type && wait_iter--) 1111 msleep(ABORT_POLLING_PERIOD); 1112 if (sp->type) 1113 ret = QLA_FUNCTION_FAILED; 1114 1115 return ret; 1116 } 1117 1118 /* 1119 * qla2x00_wait_for_hba_online 1120 * Wait till the HBA is online after going through 1121 * <= MAX_RETRIES_OF_ISP_ABORT or 1122 * finally HBA is disabled ie marked offline 1123 * 1124 * Input: 1125 * ha - pointer to host adapter structure 1126 * 1127 * Note: 1128 * Does context switching-Release SPIN_LOCK 1129 * (if any) before calling this routine. 1130 * 1131 * Return: 1132 * Success (Adapter is online) : 0 1133 * Failed (Adapter is offline/disabled) : 1 1134 */ 1135 int 1136 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1137 { 1138 int return_status; 1139 unsigned long wait_online; 1140 struct qla_hw_data *ha = vha->hw; 1141 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1142 1143 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1144 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1145 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1146 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1147 ha->dpc_active) && time_before(jiffies, wait_online)) { 1148 1149 msleep(1000); 1150 } 1151 if (base_vha->flags.online) 1152 return_status = QLA_SUCCESS; 1153 else 1154 return_status = QLA_FUNCTION_FAILED; 1155 1156 return (return_status); 1157 } 1158 1159 static inline int test_fcport_count(scsi_qla_host_t *vha) 1160 { 1161 struct qla_hw_data *ha = vha->hw; 1162 unsigned long flags; 1163 int res; 1164 /* Return 0 = sleep, x=wake */ 1165 1166 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1167 ql_dbg(ql_dbg_init, vha, 0x00ec, 1168 "tgt %p, fcport_count=%d\n", 1169 vha, vha->fcport_count); 1170 res = (vha->fcport_count == 0); 1171 if (res) { 1172 struct fc_port *fcport; 1173 1174 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1175 if (fcport->deleted != QLA_SESS_DELETED) { 1176 /* session(s) may not be fully logged in 1177 * (ie fcport_count=0), but session 1178 * deletion thread(s) may be inflight. 1179 */ 1180 1181 res = 0; 1182 break; 1183 } 1184 } 1185 } 1186 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1187 1188 return res; 1189 } 1190 1191 /* 1192 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1193 * it has dependency on UNLOADING flag to stop device discovery 1194 */ 1195 void 1196 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1197 { 1198 u8 i; 1199 1200 qla2x00_mark_all_devices_lost(vha); 1201 1202 for (i = 0; i < 10; i++) { 1203 if (wait_event_timeout(vha->fcport_waitQ, 1204 test_fcport_count(vha), HZ) > 0) 1205 break; 1206 } 1207 1208 flush_workqueue(vha->hw->wq); 1209 } 1210 1211 /* 1212 * qla2x00_wait_for_hba_ready 1213 * Wait till the HBA is ready before doing driver unload 1214 * 1215 * Input: 1216 * ha - pointer to host adapter structure 1217 * 1218 * Note: 1219 * Does context switching-Release SPIN_LOCK 1220 * (if any) before calling this routine. 1221 * 1222 */ 1223 static void 1224 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1225 { 1226 struct qla_hw_data *ha = vha->hw; 1227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1228 1229 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1230 ha->flags.mbox_busy) || 1231 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1232 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1233 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1234 break; 1235 msleep(1000); 1236 } 1237 } 1238 1239 int 1240 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1241 { 1242 int return_status; 1243 unsigned long wait_reset; 1244 struct qla_hw_data *ha = vha->hw; 1245 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1246 1247 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1248 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1249 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1250 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1251 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1252 1253 msleep(1000); 1254 1255 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1256 ha->flags.chip_reset_done) 1257 break; 1258 } 1259 if (ha->flags.chip_reset_done) 1260 return_status = QLA_SUCCESS; 1261 else 1262 return_status = QLA_FUNCTION_FAILED; 1263 1264 return return_status; 1265 } 1266 1267 /************************************************************************** 1268 * qla2xxx_eh_abort 1269 * 1270 * Description: 1271 * The abort function will abort the specified command. 1272 * 1273 * Input: 1274 * cmd = Linux SCSI command packet to be aborted. 1275 * 1276 * Returns: 1277 * Either SUCCESS or FAILED. 1278 * 1279 * Note: 1280 * Only return FAILED if command not returned by firmware. 1281 **************************************************************************/ 1282 static int 1283 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1284 { 1285 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1286 DECLARE_COMPLETION_ONSTACK(comp); 1287 srb_t *sp; 1288 int ret; 1289 unsigned int id; 1290 uint64_t lun; 1291 int rval; 1292 struct qla_hw_data *ha = vha->hw; 1293 uint32_t ratov_j; 1294 struct qla_qpair *qpair; 1295 unsigned long flags; 1296 int fast_fail_status = SUCCESS; 1297 1298 if (qla2x00_isp_reg_stat(ha)) { 1299 ql_log(ql_log_info, vha, 0x8042, 1300 "PCI/Register disconnect, exiting.\n"); 1301 qla_pci_set_eeh_busy(vha); 1302 return FAILED; 1303 } 1304 1305 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1306 ret = fc_block_scsi_eh(cmd); 1307 if (ret != 0) 1308 fast_fail_status = ret; 1309 1310 sp = scsi_cmd_priv(cmd); 1311 qpair = sp->qpair; 1312 1313 vha->cmd_timeout_cnt++; 1314 1315 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1316 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1317 1318 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1319 sp->comp = ∁ 1320 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1321 1322 1323 id = cmd->device->id; 1324 lun = cmd->device->lun; 1325 1326 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1327 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1328 vha->host_no, id, lun, sp, cmd, sp->handle); 1329 1330 /* 1331 * Abort will release the original Command/sp from FW. Let the 1332 * original command call scsi_done. In return, he will wakeup 1333 * this sleeping thread. 1334 */ 1335 rval = ha->isp_ops->abort_command(sp); 1336 1337 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1338 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1339 1340 /* Wait for the command completion. */ 1341 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1342 ratov_j = msecs_to_jiffies(ratov_j); 1343 switch (rval) { 1344 case QLA_SUCCESS: 1345 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1346 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1347 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1348 __func__, ha->r_a_tov/10); 1349 ret = FAILED; 1350 } else { 1351 ret = fast_fail_status; 1352 } 1353 break; 1354 default: 1355 ret = FAILED; 1356 break; 1357 } 1358 1359 sp->comp = NULL; 1360 1361 ql_log(ql_log_info, vha, 0x801c, 1362 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1363 vha->host_no, id, lun, ret); 1364 1365 return ret; 1366 } 1367 1368 /* 1369 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1370 */ 1371 static int 1372 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1373 uint64_t l, enum nexus_wait_type type) 1374 { 1375 int cnt, match, status; 1376 unsigned long flags; 1377 scsi_qla_host_t *vha = qpair->vha; 1378 struct req_que *req = qpair->req; 1379 srb_t *sp; 1380 struct scsi_cmnd *cmd; 1381 1382 status = QLA_SUCCESS; 1383 1384 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1385 for (cnt = 1; status == QLA_SUCCESS && 1386 cnt < req->num_outstanding_cmds; cnt++) { 1387 sp = req->outstanding_cmds[cnt]; 1388 if (!sp) 1389 continue; 1390 if (sp->type != SRB_SCSI_CMD) 1391 continue; 1392 if (vha->vp_idx != sp->vha->vp_idx) 1393 continue; 1394 match = 0; 1395 cmd = GET_CMD_SP(sp); 1396 switch (type) { 1397 case WAIT_HOST: 1398 match = 1; 1399 break; 1400 case WAIT_TARGET: 1401 match = cmd->device->id == t; 1402 break; 1403 case WAIT_LUN: 1404 match = (cmd->device->id == t && 1405 cmd->device->lun == l); 1406 break; 1407 } 1408 if (!match) 1409 continue; 1410 1411 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1412 status = qla2x00_eh_wait_on_command(cmd); 1413 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1414 } 1415 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1416 1417 return status; 1418 } 1419 1420 int 1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1422 uint64_t l, enum nexus_wait_type type) 1423 { 1424 struct qla_qpair *qpair; 1425 struct qla_hw_data *ha = vha->hw; 1426 int i, status = QLA_SUCCESS; 1427 1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1429 type); 1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1431 qpair = ha->queue_pair_map[i]; 1432 if (!qpair) 1433 continue; 1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1435 type); 1436 } 1437 return status; 1438 } 1439 1440 static char *reset_errors[] = { 1441 "HBA not online", 1442 "HBA not ready", 1443 "Task management failed", 1444 "Waiting for command completions", 1445 }; 1446 1447 static int 1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 struct scsi_device *sdev = cmd->device; 1451 scsi_qla_host_t *vha = shost_priv(sdev->host); 1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1454 struct qla_hw_data *ha = vha->hw; 1455 int err; 1456 1457 if (qla2x00_isp_reg_stat(ha)) { 1458 ql_log(ql_log_info, vha, 0x803e, 1459 "PCI/Register disconnect, exiting.\n"); 1460 qla_pci_set_eeh_busy(vha); 1461 return FAILED; 1462 } 1463 1464 if (!fcport) { 1465 return FAILED; 1466 } 1467 1468 err = fc_block_rport(rport); 1469 if (err != 0) 1470 return err; 1471 1472 if (fcport->deleted) 1473 return FAILED; 1474 1475 ql_log(ql_log_info, vha, 0x8009, 1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1477 sdev->id, sdev->lun, cmd); 1478 1479 err = 0; 1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1481 ql_log(ql_log_warn, vha, 0x800a, 1482 "Wait for hba online failed for cmd=%p.\n", cmd); 1483 goto eh_reset_failed; 1484 } 1485 err = 2; 1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1487 != QLA_SUCCESS) { 1488 ql_log(ql_log_warn, vha, 0x800c, 1489 "do_reset failed for cmd=%p.\n", cmd); 1490 goto eh_reset_failed; 1491 } 1492 err = 3; 1493 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1494 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1495 ql_log(ql_log_warn, vha, 0x800d, 1496 "wait for pending cmds failed for cmd=%p.\n", cmd); 1497 goto eh_reset_failed; 1498 } 1499 1500 ql_log(ql_log_info, vha, 0x800e, 1501 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1502 vha->host_no, sdev->id, sdev->lun, cmd); 1503 1504 return SUCCESS; 1505 1506 eh_reset_failed: 1507 ql_log(ql_log_info, vha, 0x800f, 1508 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1509 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1510 cmd); 1511 vha->reset_cmd_err_cnt++; 1512 return FAILED; 1513 } 1514 1515 static int 1516 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1517 { 1518 struct scsi_device *sdev = cmd->device; 1519 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1520 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1521 struct qla_hw_data *ha = vha->hw; 1522 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1523 int err; 1524 1525 if (qla2x00_isp_reg_stat(ha)) { 1526 ql_log(ql_log_info, vha, 0x803f, 1527 "PCI/Register disconnect, exiting.\n"); 1528 qla_pci_set_eeh_busy(vha); 1529 return FAILED; 1530 } 1531 1532 if (!fcport) { 1533 return FAILED; 1534 } 1535 1536 err = fc_block_rport(rport); 1537 if (err != 0) 1538 return err; 1539 1540 if (fcport->deleted) 1541 return FAILED; 1542 1543 ql_log(ql_log_info, vha, 0x8009, 1544 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1545 sdev->id, cmd); 1546 1547 err = 0; 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1549 ql_log(ql_log_warn, vha, 0x800a, 1550 "Wait for hba online failed for cmd=%p.\n", cmd); 1551 goto eh_reset_failed; 1552 } 1553 err = 2; 1554 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1555 ql_log(ql_log_warn, vha, 0x800c, 1556 "target_reset failed for cmd=%p.\n", cmd); 1557 goto eh_reset_failed; 1558 } 1559 err = 3; 1560 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1561 0, WAIT_TARGET) != QLA_SUCCESS) { 1562 ql_log(ql_log_warn, vha, 0x800d, 1563 "wait for pending cmds failed for cmd=%p.\n", cmd); 1564 goto eh_reset_failed; 1565 } 1566 1567 ql_log(ql_log_info, vha, 0x800e, 1568 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1569 vha->host_no, sdev->id, cmd); 1570 1571 return SUCCESS; 1572 1573 eh_reset_failed: 1574 ql_log(ql_log_info, vha, 0x800f, 1575 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1576 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1577 cmd); 1578 vha->reset_cmd_err_cnt++; 1579 return FAILED; 1580 } 1581 1582 /************************************************************************** 1583 * qla2xxx_eh_bus_reset 1584 * 1585 * Description: 1586 * The bus reset function will reset the bus and abort any executing 1587 * commands. 1588 * 1589 * Input: 1590 * cmd = Linux SCSI command packet of the command that cause the 1591 * bus reset. 1592 * 1593 * Returns: 1594 * SUCCESS/FAILURE (defined as macro in scsi.h). 1595 * 1596 **************************************************************************/ 1597 static int 1598 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1599 { 1600 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1601 int ret = FAILED; 1602 unsigned int id; 1603 uint64_t lun; 1604 struct qla_hw_data *ha = vha->hw; 1605 1606 if (qla2x00_isp_reg_stat(ha)) { 1607 ql_log(ql_log_info, vha, 0x8040, 1608 "PCI/Register disconnect, exiting.\n"); 1609 qla_pci_set_eeh_busy(vha); 1610 return FAILED; 1611 } 1612 1613 id = cmd->device->id; 1614 lun = cmd->device->lun; 1615 1616 if (qla2x00_chip_is_down(vha)) 1617 return ret; 1618 1619 ql_log(ql_log_info, vha, 0x8012, 1620 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1621 1622 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1623 ql_log(ql_log_fatal, vha, 0x8013, 1624 "Wait for hba online failed board disabled.\n"); 1625 goto eh_bus_reset_done; 1626 } 1627 1628 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1629 ret = SUCCESS; 1630 1631 if (ret == FAILED) 1632 goto eh_bus_reset_done; 1633 1634 /* Flush outstanding commands. */ 1635 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1636 QLA_SUCCESS) { 1637 ql_log(ql_log_warn, vha, 0x8014, 1638 "Wait for pending commands failed.\n"); 1639 ret = FAILED; 1640 } 1641 1642 eh_bus_reset_done: 1643 ql_log(ql_log_warn, vha, 0x802b, 1644 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1645 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1646 1647 return ret; 1648 } 1649 1650 /************************************************************************** 1651 * qla2xxx_eh_host_reset 1652 * 1653 * Description: 1654 * The reset function will reset the Adapter. 1655 * 1656 * Input: 1657 * cmd = Linux SCSI command packet of the command that cause the 1658 * adapter reset. 1659 * 1660 * Returns: 1661 * Either SUCCESS or FAILED. 1662 * 1663 * Note: 1664 **************************************************************************/ 1665 static int 1666 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1667 { 1668 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1669 struct qla_hw_data *ha = vha->hw; 1670 int ret = FAILED; 1671 unsigned int id; 1672 uint64_t lun; 1673 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1674 1675 if (qla2x00_isp_reg_stat(ha)) { 1676 ql_log(ql_log_info, vha, 0x8041, 1677 "PCI/Register disconnect, exiting.\n"); 1678 qla_pci_set_eeh_busy(vha); 1679 return SUCCESS; 1680 } 1681 1682 id = cmd->device->id; 1683 lun = cmd->device->lun; 1684 1685 ql_log(ql_log_info, vha, 0x8018, 1686 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1687 1688 /* 1689 * No point in issuing another reset if one is active. Also do not 1690 * attempt a reset if we are updating flash. 1691 */ 1692 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1693 goto eh_host_reset_lock; 1694 1695 if (vha != base_vha) { 1696 if (qla2x00_vp_abort_isp(vha)) 1697 goto eh_host_reset_lock; 1698 } else { 1699 if (IS_P3P_TYPE(vha->hw)) { 1700 if (!qla82xx_fcoe_ctx_reset(vha)) { 1701 /* Ctx reset success */ 1702 ret = SUCCESS; 1703 goto eh_host_reset_lock; 1704 } 1705 /* fall thru if ctx reset failed */ 1706 } 1707 if (ha->wq) 1708 flush_workqueue(ha->wq); 1709 1710 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1711 if (ha->isp_ops->abort_isp(base_vha)) { 1712 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1713 /* failed. schedule dpc to try */ 1714 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1715 1716 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1717 ql_log(ql_log_warn, vha, 0x802a, 1718 "wait for hba online failed.\n"); 1719 goto eh_host_reset_lock; 1720 } 1721 } 1722 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1723 } 1724 1725 /* Waiting for command to be returned to OS.*/ 1726 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1727 QLA_SUCCESS) 1728 ret = SUCCESS; 1729 1730 eh_host_reset_lock: 1731 ql_log(ql_log_info, vha, 0x8017, 1732 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1733 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1734 1735 return ret; 1736 } 1737 1738 /* 1739 * qla2x00_loop_reset 1740 * Issue loop reset. 1741 * 1742 * Input: 1743 * ha = adapter block pointer. 1744 * 1745 * Returns: 1746 * 0 = success 1747 */ 1748 int 1749 qla2x00_loop_reset(scsi_qla_host_t *vha) 1750 { 1751 int ret; 1752 struct qla_hw_data *ha = vha->hw; 1753 1754 if (IS_QLAFX00(ha)) 1755 return QLA_SUCCESS; 1756 1757 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1758 atomic_set(&vha->loop_state, LOOP_DOWN); 1759 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1760 qla2x00_mark_all_devices_lost(vha); 1761 ret = qla2x00_full_login_lip(vha); 1762 if (ret != QLA_SUCCESS) { 1763 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1764 "full_login_lip=%d.\n", ret); 1765 } 1766 } 1767 1768 if (ha->flags.enable_lip_reset) { 1769 ret = qla2x00_lip_reset(vha); 1770 if (ret != QLA_SUCCESS) 1771 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1772 "lip_reset failed (%d).\n", ret); 1773 } 1774 1775 /* Issue marker command only when we are going to start the I/O */ 1776 vha->marker_needed = 1; 1777 1778 return QLA_SUCCESS; 1779 } 1780 1781 /* 1782 * The caller must ensure that no completion interrupts will happen 1783 * while this function is in progress. 1784 */ 1785 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1786 unsigned long *flags) 1787 __releases(qp->qp_lock_ptr) 1788 __acquires(qp->qp_lock_ptr) 1789 { 1790 DECLARE_COMPLETION_ONSTACK(comp); 1791 scsi_qla_host_t *vha = qp->vha; 1792 struct qla_hw_data *ha = vha->hw; 1793 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1794 int rval; 1795 bool ret_cmd; 1796 uint32_t ratov_j; 1797 1798 lockdep_assert_held(qp->qp_lock_ptr); 1799 1800 if (qla2x00_chip_is_down(vha)) { 1801 sp->done(sp, res); 1802 return; 1803 } 1804 1805 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1806 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1807 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1808 !qla2x00_isp_reg_stat(ha))) { 1809 if (sp->comp) { 1810 sp->done(sp, res); 1811 return; 1812 } 1813 1814 sp->comp = ∁ 1815 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1816 1817 rval = ha->isp_ops->abort_command(sp); 1818 /* Wait for command completion. */ 1819 ret_cmd = false; 1820 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1821 ratov_j = msecs_to_jiffies(ratov_j); 1822 switch (rval) { 1823 case QLA_SUCCESS: 1824 if (wait_for_completion_timeout(&comp, ratov_j)) { 1825 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1826 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1827 __func__, ha->r_a_tov/10); 1828 ret_cmd = true; 1829 } 1830 /* else FW return SP to driver */ 1831 break; 1832 default: 1833 ret_cmd = true; 1834 break; 1835 } 1836 1837 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1838 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1839 sp->done(sp, res); 1840 } else { 1841 sp->done(sp, res); 1842 } 1843 } 1844 1845 /* 1846 * The caller must ensure that no completion interrupts will happen 1847 * while this function is in progress. 1848 */ 1849 static void 1850 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1851 { 1852 int cnt; 1853 unsigned long flags; 1854 srb_t *sp; 1855 scsi_qla_host_t *vha = qp->vha; 1856 struct qla_hw_data *ha = vha->hw; 1857 struct req_que *req; 1858 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1859 struct qla_tgt_cmd *cmd; 1860 1861 if (!ha->req_q_map) 1862 return; 1863 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1864 req = qp->req; 1865 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1866 sp = req->outstanding_cmds[cnt]; 1867 if (sp) { 1868 switch (sp->cmd_type) { 1869 case TYPE_SRB: 1870 qla2x00_abort_srb(qp, sp, res, &flags); 1871 break; 1872 case TYPE_TGT_CMD: 1873 if (!vha->hw->tgt.tgt_ops || !tgt || 1874 qla_ini_mode_enabled(vha)) { 1875 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1876 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1877 vha->dpc_flags); 1878 continue; 1879 } 1880 cmd = (struct qla_tgt_cmd *)sp; 1881 cmd->aborted = 1; 1882 break; 1883 case TYPE_TGT_TMCMD: 1884 /* Skip task management functions. */ 1885 break; 1886 default: 1887 break; 1888 } 1889 req->outstanding_cmds[cnt] = NULL; 1890 } 1891 } 1892 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1893 } 1894 1895 /* 1896 * The caller must ensure that no completion interrupts will happen 1897 * while this function is in progress. 1898 */ 1899 void 1900 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1901 { 1902 int que; 1903 struct qla_hw_data *ha = vha->hw; 1904 1905 /* Continue only if initialization complete. */ 1906 if (!ha->base_qpair) 1907 return; 1908 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1909 1910 if (!ha->queue_pair_map) 1911 return; 1912 for (que = 0; que < ha->max_qpairs; que++) { 1913 if (!ha->queue_pair_map[que]) 1914 continue; 1915 1916 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1917 } 1918 } 1919 1920 static int 1921 qla2xxx_slave_alloc(struct scsi_device *sdev) 1922 { 1923 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1924 1925 if (!rport || fc_remote_port_chkready(rport)) 1926 return -ENXIO; 1927 1928 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1929 1930 return 0; 1931 } 1932 1933 static int 1934 qla2xxx_slave_configure(struct scsi_device *sdev) 1935 { 1936 scsi_qla_host_t *vha = shost_priv(sdev->host); 1937 struct req_que *req = vha->req; 1938 1939 if (IS_T10_PI_CAPABLE(vha->hw)) 1940 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1941 1942 scsi_change_queue_depth(sdev, req->max_q_depth); 1943 return 0; 1944 } 1945 1946 static void 1947 qla2xxx_slave_destroy(struct scsi_device *sdev) 1948 { 1949 sdev->hostdata = NULL; 1950 } 1951 1952 /** 1953 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1954 * @ha: HA context 1955 * 1956 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1957 * supported addressing method. 1958 */ 1959 static void 1960 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1961 { 1962 /* Assume a 32bit DMA mask. */ 1963 ha->flags.enable_64bit_addressing = 0; 1964 1965 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1966 /* Any upper-dword bits set? */ 1967 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1968 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1969 /* Ok, a 64bit DMA mask is applicable. */ 1970 ha->flags.enable_64bit_addressing = 1; 1971 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1972 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1973 return; 1974 } 1975 } 1976 1977 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1978 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1979 } 1980 1981 static void 1982 qla2x00_enable_intrs(struct qla_hw_data *ha) 1983 { 1984 unsigned long flags = 0; 1985 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1986 1987 spin_lock_irqsave(&ha->hardware_lock, flags); 1988 ha->interrupts_on = 1; 1989 /* enable risc and host interrupts */ 1990 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1991 rd_reg_word(®->ictrl); 1992 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1993 1994 } 1995 1996 static void 1997 qla2x00_disable_intrs(struct qla_hw_data *ha) 1998 { 1999 unsigned long flags = 0; 2000 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2001 2002 spin_lock_irqsave(&ha->hardware_lock, flags); 2003 ha->interrupts_on = 0; 2004 /* disable risc and host interrupts */ 2005 wrt_reg_word(®->ictrl, 0); 2006 rd_reg_word(®->ictrl); 2007 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2008 } 2009 2010 static void 2011 qla24xx_enable_intrs(struct qla_hw_data *ha) 2012 { 2013 unsigned long flags = 0; 2014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2015 2016 spin_lock_irqsave(&ha->hardware_lock, flags); 2017 ha->interrupts_on = 1; 2018 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2019 rd_reg_dword(®->ictrl); 2020 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2021 } 2022 2023 static void 2024 qla24xx_disable_intrs(struct qla_hw_data *ha) 2025 { 2026 unsigned long flags = 0; 2027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2028 2029 if (IS_NOPOLLING_TYPE(ha)) 2030 return; 2031 spin_lock_irqsave(&ha->hardware_lock, flags); 2032 ha->interrupts_on = 0; 2033 wrt_reg_dword(®->ictrl, 0); 2034 rd_reg_dword(®->ictrl); 2035 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2036 } 2037 2038 static int 2039 qla2x00_iospace_config(struct qla_hw_data *ha) 2040 { 2041 resource_size_t pio; 2042 uint16_t msix; 2043 2044 if (pci_request_selected_regions(ha->pdev, ha->bars, 2045 QLA2XXX_DRIVER_NAME)) { 2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2047 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2048 pci_name(ha->pdev)); 2049 goto iospace_error_exit; 2050 } 2051 if (!(ha->bars & 1)) 2052 goto skip_pio; 2053 2054 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2055 pio = pci_resource_start(ha->pdev, 0); 2056 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2057 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2058 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2059 "Invalid pci I/O region size (%s).\n", 2060 pci_name(ha->pdev)); 2061 pio = 0; 2062 } 2063 } else { 2064 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2065 "Region #0 no a PIO resource (%s).\n", 2066 pci_name(ha->pdev)); 2067 pio = 0; 2068 } 2069 ha->pio_address = pio; 2070 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2071 "PIO address=%llu.\n", 2072 (unsigned long long)ha->pio_address); 2073 2074 skip_pio: 2075 /* Use MMIO operations for all accesses. */ 2076 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2077 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2078 "Region #1 not an MMIO resource (%s), aborting.\n", 2079 pci_name(ha->pdev)); 2080 goto iospace_error_exit; 2081 } 2082 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2084 "Invalid PCI mem region size (%s), aborting.\n", 2085 pci_name(ha->pdev)); 2086 goto iospace_error_exit; 2087 } 2088 2089 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2090 if (!ha->iobase) { 2091 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2092 "Cannot remap MMIO (%s), aborting.\n", 2093 pci_name(ha->pdev)); 2094 goto iospace_error_exit; 2095 } 2096 2097 /* Determine queue resources */ 2098 ha->max_req_queues = ha->max_rsp_queues = 1; 2099 ha->msix_count = QLA_BASE_VECTORS; 2100 2101 /* Check if FW supports MQ or not */ 2102 if (!(ha->fw_attributes & BIT_6)) 2103 goto mqiobase_exit; 2104 2105 if (!ql2xmqsupport || !ql2xnvmeenable || 2106 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2107 goto mqiobase_exit; 2108 2109 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2110 pci_resource_len(ha->pdev, 3)); 2111 if (ha->mqiobase) { 2112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2113 "MQIO Base=%p.\n", ha->mqiobase); 2114 /* Read MSIX vector size of the board */ 2115 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2116 ha->msix_count = msix + 1; 2117 /* Max queues are bounded by available msix vectors */ 2118 /* MB interrupt uses 1 vector */ 2119 ha->max_req_queues = ha->msix_count - 1; 2120 ha->max_rsp_queues = ha->max_req_queues; 2121 /* Queue pairs is the max value minus the base queue pair */ 2122 ha->max_qpairs = ha->max_rsp_queues - 1; 2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2124 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2125 2126 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2127 "MSI-X vector count: %d.\n", ha->msix_count); 2128 } else 2129 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2130 "BAR 3 not enabled.\n"); 2131 2132 mqiobase_exit: 2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2134 "MSIX Count: %d.\n", ha->msix_count); 2135 return (0); 2136 2137 iospace_error_exit: 2138 return (-ENOMEM); 2139 } 2140 2141 2142 static int 2143 qla83xx_iospace_config(struct qla_hw_data *ha) 2144 { 2145 uint16_t msix; 2146 2147 if (pci_request_selected_regions(ha->pdev, ha->bars, 2148 QLA2XXX_DRIVER_NAME)) { 2149 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2150 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2151 pci_name(ha->pdev)); 2152 2153 goto iospace_error_exit; 2154 } 2155 2156 /* Use MMIO operations for all accesses. */ 2157 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2158 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2159 "Invalid pci I/O region size (%s).\n", 2160 pci_name(ha->pdev)); 2161 goto iospace_error_exit; 2162 } 2163 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2164 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2165 "Invalid PCI mem region size (%s), aborting\n", 2166 pci_name(ha->pdev)); 2167 goto iospace_error_exit; 2168 } 2169 2170 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2171 if (!ha->iobase) { 2172 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2173 "Cannot remap MMIO (%s), aborting.\n", 2174 pci_name(ha->pdev)); 2175 goto iospace_error_exit; 2176 } 2177 2178 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2179 /* 83XX 26XX always use MQ type access for queues 2180 * - mbar 2, a.k.a region 4 */ 2181 ha->max_req_queues = ha->max_rsp_queues = 1; 2182 ha->msix_count = QLA_BASE_VECTORS; 2183 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2184 pci_resource_len(ha->pdev, 4)); 2185 2186 if (!ha->mqiobase) { 2187 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2188 "BAR2/region4 not enabled\n"); 2189 goto mqiobase_exit; 2190 } 2191 2192 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2193 pci_resource_len(ha->pdev, 2)); 2194 if (ha->msixbase) { 2195 /* Read MSIX vector size of the board */ 2196 pci_read_config_word(ha->pdev, 2197 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2198 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2199 /* 2200 * By default, driver uses at least two msix vectors 2201 * (default & rspq) 2202 */ 2203 if (ql2xmqsupport || ql2xnvmeenable) { 2204 /* MB interrupt uses 1 vector */ 2205 ha->max_req_queues = ha->msix_count - 1; 2206 2207 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2208 if (QLA_TGT_MODE_ENABLED()) 2209 ha->max_req_queues--; 2210 2211 ha->max_rsp_queues = ha->max_req_queues; 2212 2213 /* Queue pairs is the max value minus 2214 * the base queue pair */ 2215 ha->max_qpairs = ha->max_req_queues - 1; 2216 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2217 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2218 } 2219 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2220 "MSI-X vector count: %d.\n", ha->msix_count); 2221 } else 2222 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2223 "BAR 1 not enabled.\n"); 2224 2225 mqiobase_exit: 2226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2227 "MSIX Count: %d.\n", ha->msix_count); 2228 return 0; 2229 2230 iospace_error_exit: 2231 return -ENOMEM; 2232 } 2233 2234 static struct isp_operations qla2100_isp_ops = { 2235 .pci_config = qla2100_pci_config, 2236 .reset_chip = qla2x00_reset_chip, 2237 .chip_diag = qla2x00_chip_diag, 2238 .config_rings = qla2x00_config_rings, 2239 .reset_adapter = qla2x00_reset_adapter, 2240 .nvram_config = qla2x00_nvram_config, 2241 .update_fw_options = qla2x00_update_fw_options, 2242 .load_risc = qla2x00_load_risc, 2243 .pci_info_str = qla2x00_pci_info_str, 2244 .fw_version_str = qla2x00_fw_version_str, 2245 .intr_handler = qla2100_intr_handler, 2246 .enable_intrs = qla2x00_enable_intrs, 2247 .disable_intrs = qla2x00_disable_intrs, 2248 .abort_command = qla2x00_abort_command, 2249 .target_reset = qla2x00_abort_target, 2250 .lun_reset = qla2x00_lun_reset, 2251 .fabric_login = qla2x00_login_fabric, 2252 .fabric_logout = qla2x00_fabric_logout, 2253 .calc_req_entries = qla2x00_calc_iocbs_32, 2254 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2255 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2256 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2257 .read_nvram = qla2x00_read_nvram_data, 2258 .write_nvram = qla2x00_write_nvram_data, 2259 .fw_dump = qla2100_fw_dump, 2260 .beacon_on = NULL, 2261 .beacon_off = NULL, 2262 .beacon_blink = NULL, 2263 .read_optrom = qla2x00_read_optrom_data, 2264 .write_optrom = qla2x00_write_optrom_data, 2265 .get_flash_version = qla2x00_get_flash_version, 2266 .start_scsi = qla2x00_start_scsi, 2267 .start_scsi_mq = NULL, 2268 .abort_isp = qla2x00_abort_isp, 2269 .iospace_config = qla2x00_iospace_config, 2270 .initialize_adapter = qla2x00_initialize_adapter, 2271 }; 2272 2273 static struct isp_operations qla2300_isp_ops = { 2274 .pci_config = qla2300_pci_config, 2275 .reset_chip = qla2x00_reset_chip, 2276 .chip_diag = qla2x00_chip_diag, 2277 .config_rings = qla2x00_config_rings, 2278 .reset_adapter = qla2x00_reset_adapter, 2279 .nvram_config = qla2x00_nvram_config, 2280 .update_fw_options = qla2x00_update_fw_options, 2281 .load_risc = qla2x00_load_risc, 2282 .pci_info_str = qla2x00_pci_info_str, 2283 .fw_version_str = qla2x00_fw_version_str, 2284 .intr_handler = qla2300_intr_handler, 2285 .enable_intrs = qla2x00_enable_intrs, 2286 .disable_intrs = qla2x00_disable_intrs, 2287 .abort_command = qla2x00_abort_command, 2288 .target_reset = qla2x00_abort_target, 2289 .lun_reset = qla2x00_lun_reset, 2290 .fabric_login = qla2x00_login_fabric, 2291 .fabric_logout = qla2x00_fabric_logout, 2292 .calc_req_entries = qla2x00_calc_iocbs_32, 2293 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2294 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2295 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2296 .read_nvram = qla2x00_read_nvram_data, 2297 .write_nvram = qla2x00_write_nvram_data, 2298 .fw_dump = qla2300_fw_dump, 2299 .beacon_on = qla2x00_beacon_on, 2300 .beacon_off = qla2x00_beacon_off, 2301 .beacon_blink = qla2x00_beacon_blink, 2302 .read_optrom = qla2x00_read_optrom_data, 2303 .write_optrom = qla2x00_write_optrom_data, 2304 .get_flash_version = qla2x00_get_flash_version, 2305 .start_scsi = qla2x00_start_scsi, 2306 .start_scsi_mq = NULL, 2307 .abort_isp = qla2x00_abort_isp, 2308 .iospace_config = qla2x00_iospace_config, 2309 .initialize_adapter = qla2x00_initialize_adapter, 2310 }; 2311 2312 static struct isp_operations qla24xx_isp_ops = { 2313 .pci_config = qla24xx_pci_config, 2314 .reset_chip = qla24xx_reset_chip, 2315 .chip_diag = qla24xx_chip_diag, 2316 .config_rings = qla24xx_config_rings, 2317 .reset_adapter = qla24xx_reset_adapter, 2318 .nvram_config = qla24xx_nvram_config, 2319 .update_fw_options = qla24xx_update_fw_options, 2320 .load_risc = qla24xx_load_risc, 2321 .pci_info_str = qla24xx_pci_info_str, 2322 .fw_version_str = qla24xx_fw_version_str, 2323 .intr_handler = qla24xx_intr_handler, 2324 .enable_intrs = qla24xx_enable_intrs, 2325 .disable_intrs = qla24xx_disable_intrs, 2326 .abort_command = qla24xx_abort_command, 2327 .target_reset = qla24xx_abort_target, 2328 .lun_reset = qla24xx_lun_reset, 2329 .fabric_login = qla24xx_login_fabric, 2330 .fabric_logout = qla24xx_fabric_logout, 2331 .calc_req_entries = NULL, 2332 .build_iocbs = NULL, 2333 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2334 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2335 .read_nvram = qla24xx_read_nvram_data, 2336 .write_nvram = qla24xx_write_nvram_data, 2337 .fw_dump = qla24xx_fw_dump, 2338 .beacon_on = qla24xx_beacon_on, 2339 .beacon_off = qla24xx_beacon_off, 2340 .beacon_blink = qla24xx_beacon_blink, 2341 .read_optrom = qla24xx_read_optrom_data, 2342 .write_optrom = qla24xx_write_optrom_data, 2343 .get_flash_version = qla24xx_get_flash_version, 2344 .start_scsi = qla24xx_start_scsi, 2345 .start_scsi_mq = NULL, 2346 .abort_isp = qla2x00_abort_isp, 2347 .iospace_config = qla2x00_iospace_config, 2348 .initialize_adapter = qla2x00_initialize_adapter, 2349 }; 2350 2351 static struct isp_operations qla25xx_isp_ops = { 2352 .pci_config = qla25xx_pci_config, 2353 .reset_chip = qla24xx_reset_chip, 2354 .chip_diag = qla24xx_chip_diag, 2355 .config_rings = qla24xx_config_rings, 2356 .reset_adapter = qla24xx_reset_adapter, 2357 .nvram_config = qla24xx_nvram_config, 2358 .update_fw_options = qla24xx_update_fw_options, 2359 .load_risc = qla24xx_load_risc, 2360 .pci_info_str = qla24xx_pci_info_str, 2361 .fw_version_str = qla24xx_fw_version_str, 2362 .intr_handler = qla24xx_intr_handler, 2363 .enable_intrs = qla24xx_enable_intrs, 2364 .disable_intrs = qla24xx_disable_intrs, 2365 .abort_command = qla24xx_abort_command, 2366 .target_reset = qla24xx_abort_target, 2367 .lun_reset = qla24xx_lun_reset, 2368 .fabric_login = qla24xx_login_fabric, 2369 .fabric_logout = qla24xx_fabric_logout, 2370 .calc_req_entries = NULL, 2371 .build_iocbs = NULL, 2372 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2373 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2374 .read_nvram = qla25xx_read_nvram_data, 2375 .write_nvram = qla25xx_write_nvram_data, 2376 .fw_dump = qla25xx_fw_dump, 2377 .beacon_on = qla24xx_beacon_on, 2378 .beacon_off = qla24xx_beacon_off, 2379 .beacon_blink = qla24xx_beacon_blink, 2380 .read_optrom = qla25xx_read_optrom_data, 2381 .write_optrom = qla24xx_write_optrom_data, 2382 .get_flash_version = qla24xx_get_flash_version, 2383 .start_scsi = qla24xx_dif_start_scsi, 2384 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2385 .abort_isp = qla2x00_abort_isp, 2386 .iospace_config = qla2x00_iospace_config, 2387 .initialize_adapter = qla2x00_initialize_adapter, 2388 }; 2389 2390 static struct isp_operations qla81xx_isp_ops = { 2391 .pci_config = qla25xx_pci_config, 2392 .reset_chip = qla24xx_reset_chip, 2393 .chip_diag = qla24xx_chip_diag, 2394 .config_rings = qla24xx_config_rings, 2395 .reset_adapter = qla24xx_reset_adapter, 2396 .nvram_config = qla81xx_nvram_config, 2397 .update_fw_options = qla24xx_update_fw_options, 2398 .load_risc = qla81xx_load_risc, 2399 .pci_info_str = qla24xx_pci_info_str, 2400 .fw_version_str = qla24xx_fw_version_str, 2401 .intr_handler = qla24xx_intr_handler, 2402 .enable_intrs = qla24xx_enable_intrs, 2403 .disable_intrs = qla24xx_disable_intrs, 2404 .abort_command = qla24xx_abort_command, 2405 .target_reset = qla24xx_abort_target, 2406 .lun_reset = qla24xx_lun_reset, 2407 .fabric_login = qla24xx_login_fabric, 2408 .fabric_logout = qla24xx_fabric_logout, 2409 .calc_req_entries = NULL, 2410 .build_iocbs = NULL, 2411 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2412 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2413 .read_nvram = NULL, 2414 .write_nvram = NULL, 2415 .fw_dump = qla81xx_fw_dump, 2416 .beacon_on = qla24xx_beacon_on, 2417 .beacon_off = qla24xx_beacon_off, 2418 .beacon_blink = qla83xx_beacon_blink, 2419 .read_optrom = qla25xx_read_optrom_data, 2420 .write_optrom = qla24xx_write_optrom_data, 2421 .get_flash_version = qla24xx_get_flash_version, 2422 .start_scsi = qla24xx_dif_start_scsi, 2423 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2424 .abort_isp = qla2x00_abort_isp, 2425 .iospace_config = qla2x00_iospace_config, 2426 .initialize_adapter = qla2x00_initialize_adapter, 2427 }; 2428 2429 static struct isp_operations qla82xx_isp_ops = { 2430 .pci_config = qla82xx_pci_config, 2431 .reset_chip = qla82xx_reset_chip, 2432 .chip_diag = qla24xx_chip_diag, 2433 .config_rings = qla82xx_config_rings, 2434 .reset_adapter = qla24xx_reset_adapter, 2435 .nvram_config = qla81xx_nvram_config, 2436 .update_fw_options = qla24xx_update_fw_options, 2437 .load_risc = qla82xx_load_risc, 2438 .pci_info_str = qla24xx_pci_info_str, 2439 .fw_version_str = qla24xx_fw_version_str, 2440 .intr_handler = qla82xx_intr_handler, 2441 .enable_intrs = qla82xx_enable_intrs, 2442 .disable_intrs = qla82xx_disable_intrs, 2443 .abort_command = qla24xx_abort_command, 2444 .target_reset = qla24xx_abort_target, 2445 .lun_reset = qla24xx_lun_reset, 2446 .fabric_login = qla24xx_login_fabric, 2447 .fabric_logout = qla24xx_fabric_logout, 2448 .calc_req_entries = NULL, 2449 .build_iocbs = NULL, 2450 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2451 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2452 .read_nvram = qla24xx_read_nvram_data, 2453 .write_nvram = qla24xx_write_nvram_data, 2454 .fw_dump = qla82xx_fw_dump, 2455 .beacon_on = qla82xx_beacon_on, 2456 .beacon_off = qla82xx_beacon_off, 2457 .beacon_blink = NULL, 2458 .read_optrom = qla82xx_read_optrom_data, 2459 .write_optrom = qla82xx_write_optrom_data, 2460 .get_flash_version = qla82xx_get_flash_version, 2461 .start_scsi = qla82xx_start_scsi, 2462 .start_scsi_mq = NULL, 2463 .abort_isp = qla82xx_abort_isp, 2464 .iospace_config = qla82xx_iospace_config, 2465 .initialize_adapter = qla2x00_initialize_adapter, 2466 }; 2467 2468 static struct isp_operations qla8044_isp_ops = { 2469 .pci_config = qla82xx_pci_config, 2470 .reset_chip = qla82xx_reset_chip, 2471 .chip_diag = qla24xx_chip_diag, 2472 .config_rings = qla82xx_config_rings, 2473 .reset_adapter = qla24xx_reset_adapter, 2474 .nvram_config = qla81xx_nvram_config, 2475 .update_fw_options = qla24xx_update_fw_options, 2476 .load_risc = qla82xx_load_risc, 2477 .pci_info_str = qla24xx_pci_info_str, 2478 .fw_version_str = qla24xx_fw_version_str, 2479 .intr_handler = qla8044_intr_handler, 2480 .enable_intrs = qla82xx_enable_intrs, 2481 .disable_intrs = qla82xx_disable_intrs, 2482 .abort_command = qla24xx_abort_command, 2483 .target_reset = qla24xx_abort_target, 2484 .lun_reset = qla24xx_lun_reset, 2485 .fabric_login = qla24xx_login_fabric, 2486 .fabric_logout = qla24xx_fabric_logout, 2487 .calc_req_entries = NULL, 2488 .build_iocbs = NULL, 2489 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2490 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2491 .read_nvram = NULL, 2492 .write_nvram = NULL, 2493 .fw_dump = qla8044_fw_dump, 2494 .beacon_on = qla82xx_beacon_on, 2495 .beacon_off = qla82xx_beacon_off, 2496 .beacon_blink = NULL, 2497 .read_optrom = qla8044_read_optrom_data, 2498 .write_optrom = qla8044_write_optrom_data, 2499 .get_flash_version = qla82xx_get_flash_version, 2500 .start_scsi = qla82xx_start_scsi, 2501 .start_scsi_mq = NULL, 2502 .abort_isp = qla8044_abort_isp, 2503 .iospace_config = qla82xx_iospace_config, 2504 .initialize_adapter = qla2x00_initialize_adapter, 2505 }; 2506 2507 static struct isp_operations qla83xx_isp_ops = { 2508 .pci_config = qla25xx_pci_config, 2509 .reset_chip = qla24xx_reset_chip, 2510 .chip_diag = qla24xx_chip_diag, 2511 .config_rings = qla24xx_config_rings, 2512 .reset_adapter = qla24xx_reset_adapter, 2513 .nvram_config = qla81xx_nvram_config, 2514 .update_fw_options = qla24xx_update_fw_options, 2515 .load_risc = qla81xx_load_risc, 2516 .pci_info_str = qla24xx_pci_info_str, 2517 .fw_version_str = qla24xx_fw_version_str, 2518 .intr_handler = qla24xx_intr_handler, 2519 .enable_intrs = qla24xx_enable_intrs, 2520 .disable_intrs = qla24xx_disable_intrs, 2521 .abort_command = qla24xx_abort_command, 2522 .target_reset = qla24xx_abort_target, 2523 .lun_reset = qla24xx_lun_reset, 2524 .fabric_login = qla24xx_login_fabric, 2525 .fabric_logout = qla24xx_fabric_logout, 2526 .calc_req_entries = NULL, 2527 .build_iocbs = NULL, 2528 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2529 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2530 .read_nvram = NULL, 2531 .write_nvram = NULL, 2532 .fw_dump = qla83xx_fw_dump, 2533 .beacon_on = qla24xx_beacon_on, 2534 .beacon_off = qla24xx_beacon_off, 2535 .beacon_blink = qla83xx_beacon_blink, 2536 .read_optrom = qla25xx_read_optrom_data, 2537 .write_optrom = qla24xx_write_optrom_data, 2538 .get_flash_version = qla24xx_get_flash_version, 2539 .start_scsi = qla24xx_dif_start_scsi, 2540 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2541 .abort_isp = qla2x00_abort_isp, 2542 .iospace_config = qla83xx_iospace_config, 2543 .initialize_adapter = qla2x00_initialize_adapter, 2544 }; 2545 2546 static struct isp_operations qlafx00_isp_ops = { 2547 .pci_config = qlafx00_pci_config, 2548 .reset_chip = qlafx00_soft_reset, 2549 .chip_diag = qlafx00_chip_diag, 2550 .config_rings = qlafx00_config_rings, 2551 .reset_adapter = qlafx00_soft_reset, 2552 .nvram_config = NULL, 2553 .update_fw_options = NULL, 2554 .load_risc = NULL, 2555 .pci_info_str = qlafx00_pci_info_str, 2556 .fw_version_str = qlafx00_fw_version_str, 2557 .intr_handler = qlafx00_intr_handler, 2558 .enable_intrs = qlafx00_enable_intrs, 2559 .disable_intrs = qlafx00_disable_intrs, 2560 .abort_command = qla24xx_async_abort_command, 2561 .target_reset = qlafx00_abort_target, 2562 .lun_reset = qlafx00_lun_reset, 2563 .fabric_login = NULL, 2564 .fabric_logout = NULL, 2565 .calc_req_entries = NULL, 2566 .build_iocbs = NULL, 2567 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2568 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2569 .read_nvram = qla24xx_read_nvram_data, 2570 .write_nvram = qla24xx_write_nvram_data, 2571 .fw_dump = NULL, 2572 .beacon_on = qla24xx_beacon_on, 2573 .beacon_off = qla24xx_beacon_off, 2574 .beacon_blink = NULL, 2575 .read_optrom = qla24xx_read_optrom_data, 2576 .write_optrom = qla24xx_write_optrom_data, 2577 .get_flash_version = qla24xx_get_flash_version, 2578 .start_scsi = qlafx00_start_scsi, 2579 .start_scsi_mq = NULL, 2580 .abort_isp = qlafx00_abort_isp, 2581 .iospace_config = qlafx00_iospace_config, 2582 .initialize_adapter = qlafx00_initialize_adapter, 2583 }; 2584 2585 static struct isp_operations qla27xx_isp_ops = { 2586 .pci_config = qla25xx_pci_config, 2587 .reset_chip = qla24xx_reset_chip, 2588 .chip_diag = qla24xx_chip_diag, 2589 .config_rings = qla24xx_config_rings, 2590 .reset_adapter = qla24xx_reset_adapter, 2591 .nvram_config = qla81xx_nvram_config, 2592 .update_fw_options = qla24xx_update_fw_options, 2593 .load_risc = qla81xx_load_risc, 2594 .pci_info_str = qla24xx_pci_info_str, 2595 .fw_version_str = qla24xx_fw_version_str, 2596 .intr_handler = qla24xx_intr_handler, 2597 .enable_intrs = qla24xx_enable_intrs, 2598 .disable_intrs = qla24xx_disable_intrs, 2599 .abort_command = qla24xx_abort_command, 2600 .target_reset = qla24xx_abort_target, 2601 .lun_reset = qla24xx_lun_reset, 2602 .fabric_login = qla24xx_login_fabric, 2603 .fabric_logout = qla24xx_fabric_logout, 2604 .calc_req_entries = NULL, 2605 .build_iocbs = NULL, 2606 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2607 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2608 .read_nvram = NULL, 2609 .write_nvram = NULL, 2610 .fw_dump = qla27xx_fwdump, 2611 .mpi_fw_dump = qla27xx_mpi_fwdump, 2612 .beacon_on = qla24xx_beacon_on, 2613 .beacon_off = qla24xx_beacon_off, 2614 .beacon_blink = qla83xx_beacon_blink, 2615 .read_optrom = qla25xx_read_optrom_data, 2616 .write_optrom = qla24xx_write_optrom_data, 2617 .get_flash_version = qla24xx_get_flash_version, 2618 .start_scsi = qla24xx_dif_start_scsi, 2619 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2620 .abort_isp = qla2x00_abort_isp, 2621 .iospace_config = qla83xx_iospace_config, 2622 .initialize_adapter = qla2x00_initialize_adapter, 2623 }; 2624 2625 static inline void 2626 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2627 { 2628 ha->device_type = DT_EXTENDED_IDS; 2629 switch (ha->pdev->device) { 2630 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2631 ha->isp_type |= DT_ISP2100; 2632 ha->device_type &= ~DT_EXTENDED_IDS; 2633 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2634 break; 2635 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2636 ha->isp_type |= DT_ISP2200; 2637 ha->device_type &= ~DT_EXTENDED_IDS; 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2639 break; 2640 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2641 ha->isp_type |= DT_ISP2300; 2642 ha->device_type |= DT_ZIO_SUPPORTED; 2643 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2644 break; 2645 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2646 ha->isp_type |= DT_ISP2312; 2647 ha->device_type |= DT_ZIO_SUPPORTED; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2651 ha->isp_type |= DT_ISP2322; 2652 ha->device_type |= DT_ZIO_SUPPORTED; 2653 if (ha->pdev->subsystem_vendor == 0x1028 && 2654 ha->pdev->subsystem_device == 0x0170) 2655 ha->device_type |= DT_OEM_001; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2657 break; 2658 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2659 ha->isp_type |= DT_ISP6312; 2660 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2661 break; 2662 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2663 ha->isp_type |= DT_ISP6322; 2664 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2665 break; 2666 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2667 ha->isp_type |= DT_ISP2422; 2668 ha->device_type |= DT_ZIO_SUPPORTED; 2669 ha->device_type |= DT_FWI2; 2670 ha->device_type |= DT_IIDMA; 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2672 break; 2673 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2674 ha->isp_type |= DT_ISP2432; 2675 ha->device_type |= DT_ZIO_SUPPORTED; 2676 ha->device_type |= DT_FWI2; 2677 ha->device_type |= DT_IIDMA; 2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2679 break; 2680 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2681 ha->isp_type |= DT_ISP8432; 2682 ha->device_type |= DT_ZIO_SUPPORTED; 2683 ha->device_type |= DT_FWI2; 2684 ha->device_type |= DT_IIDMA; 2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2686 break; 2687 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2688 ha->isp_type |= DT_ISP5422; 2689 ha->device_type |= DT_FWI2; 2690 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2691 break; 2692 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2693 ha->isp_type |= DT_ISP5432; 2694 ha->device_type |= DT_FWI2; 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2696 break; 2697 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2698 ha->isp_type |= DT_ISP2532; 2699 ha->device_type |= DT_ZIO_SUPPORTED; 2700 ha->device_type |= DT_FWI2; 2701 ha->device_type |= DT_IIDMA; 2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2703 break; 2704 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2705 ha->isp_type |= DT_ISP8001; 2706 ha->device_type |= DT_ZIO_SUPPORTED; 2707 ha->device_type |= DT_FWI2; 2708 ha->device_type |= DT_IIDMA; 2709 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2710 break; 2711 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2712 ha->isp_type |= DT_ISP8021; 2713 ha->device_type |= DT_ZIO_SUPPORTED; 2714 ha->device_type |= DT_FWI2; 2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2716 /* Initialize 82XX ISP flags */ 2717 qla82xx_init_flags(ha); 2718 break; 2719 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2720 ha->isp_type |= DT_ISP8044; 2721 ha->device_type |= DT_ZIO_SUPPORTED; 2722 ha->device_type |= DT_FWI2; 2723 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2724 /* Initialize 82XX ISP flags */ 2725 qla82xx_init_flags(ha); 2726 break; 2727 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2728 ha->isp_type |= DT_ISP2031; 2729 ha->device_type |= DT_ZIO_SUPPORTED; 2730 ha->device_type |= DT_FWI2; 2731 ha->device_type |= DT_IIDMA; 2732 ha->device_type |= DT_T10_PI; 2733 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2734 break; 2735 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2736 ha->isp_type |= DT_ISP8031; 2737 ha->device_type |= DT_ZIO_SUPPORTED; 2738 ha->device_type |= DT_FWI2; 2739 ha->device_type |= DT_IIDMA; 2740 ha->device_type |= DT_T10_PI; 2741 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2742 break; 2743 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2744 ha->isp_type |= DT_ISPFX00; 2745 break; 2746 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2747 ha->isp_type |= DT_ISP2071; 2748 ha->device_type |= DT_ZIO_SUPPORTED; 2749 ha->device_type |= DT_FWI2; 2750 ha->device_type |= DT_IIDMA; 2751 ha->device_type |= DT_T10_PI; 2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2753 break; 2754 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2755 ha->isp_type |= DT_ISP2271; 2756 ha->device_type |= DT_ZIO_SUPPORTED; 2757 ha->device_type |= DT_FWI2; 2758 ha->device_type |= DT_IIDMA; 2759 ha->device_type |= DT_T10_PI; 2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2761 break; 2762 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2763 ha->isp_type |= DT_ISP2261; 2764 ha->device_type |= DT_ZIO_SUPPORTED; 2765 ha->device_type |= DT_FWI2; 2766 ha->device_type |= DT_IIDMA; 2767 ha->device_type |= DT_T10_PI; 2768 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2769 break; 2770 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2771 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2772 ha->isp_type |= DT_ISP2081; 2773 ha->device_type |= DT_ZIO_SUPPORTED; 2774 ha->device_type |= DT_FWI2; 2775 ha->device_type |= DT_IIDMA; 2776 ha->device_type |= DT_T10_PI; 2777 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2778 break; 2779 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2780 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2781 ha->isp_type |= DT_ISP2281; 2782 ha->device_type |= DT_ZIO_SUPPORTED; 2783 ha->device_type |= DT_FWI2; 2784 ha->device_type |= DT_IIDMA; 2785 ha->device_type |= DT_T10_PI; 2786 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2787 break; 2788 } 2789 2790 if (IS_QLA82XX(ha)) 2791 ha->port_no = ha->portnum & 1; 2792 else { 2793 /* Get adapter physical port no from interrupt pin register. */ 2794 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2795 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2796 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2797 ha->port_no--; 2798 else 2799 ha->port_no = !(ha->port_no & 1); 2800 } 2801 2802 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2803 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2804 ha->device_type, ha->port_no, ha->fw_srisc_address); 2805 } 2806 2807 static void 2808 qla2xxx_scan_start(struct Scsi_Host *shost) 2809 { 2810 scsi_qla_host_t *vha = shost_priv(shost); 2811 2812 if (vha->hw->flags.running_gold_fw) 2813 return; 2814 2815 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2816 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2817 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2818 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2819 } 2820 2821 static int 2822 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2823 { 2824 scsi_qla_host_t *vha = shost_priv(shost); 2825 2826 if (test_bit(UNLOADING, &vha->dpc_flags)) 2827 return 1; 2828 if (!vha->host) 2829 return 1; 2830 if (time > vha->hw->loop_reset_delay * HZ) 2831 return 1; 2832 2833 return atomic_read(&vha->loop_state) == LOOP_READY; 2834 } 2835 2836 static void qla_heartbeat_work_fn(struct work_struct *work) 2837 { 2838 struct qla_hw_data *ha = container_of(work, 2839 struct qla_hw_data, heartbeat_work); 2840 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2841 2842 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2843 qla_no_op_mb(base_vha); 2844 } 2845 2846 static void qla2x00_iocb_work_fn(struct work_struct *work) 2847 { 2848 struct scsi_qla_host *vha = container_of(work, 2849 struct scsi_qla_host, iocb_work); 2850 struct qla_hw_data *ha = vha->hw; 2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2852 int i = 2; 2853 unsigned long flags; 2854 2855 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2856 return; 2857 2858 while (!list_empty(&vha->work_list) && i > 0) { 2859 qla2x00_do_work(vha); 2860 i--; 2861 } 2862 2863 spin_lock_irqsave(&vha->work_lock, flags); 2864 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2865 spin_unlock_irqrestore(&vha->work_lock, flags); 2866 } 2867 2868 static void 2869 qla_trace_init(void) 2870 { 2871 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2872 if (!qla_trc_array) { 2873 ql_log(ql_log_fatal, NULL, 0x0001, 2874 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2875 return; 2876 } 2877 2878 QLA_TRACE_ENABLE(qla_trc_array); 2879 } 2880 2881 static void 2882 qla_trace_uninit(void) 2883 { 2884 if (!qla_trc_array) 2885 return; 2886 trace_array_put(qla_trc_array); 2887 } 2888 2889 /* 2890 * PCI driver interface 2891 */ 2892 static int 2893 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2894 { 2895 int ret = -ENODEV; 2896 struct Scsi_Host *host; 2897 scsi_qla_host_t *base_vha = NULL; 2898 struct qla_hw_data *ha; 2899 char pci_info[30]; 2900 char fw_str[30], wq_name[30]; 2901 struct scsi_host_template *sht; 2902 int bars, mem_only = 0; 2903 uint16_t req_length = 0, rsp_length = 0; 2904 struct req_que *req = NULL; 2905 struct rsp_que *rsp = NULL; 2906 int i; 2907 2908 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2909 sht = &qla2xxx_driver_template; 2910 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2911 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2912 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2913 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2914 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2915 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2916 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2917 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2918 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2919 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2920 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2929 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2930 mem_only = 1; 2931 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2932 "Mem only adapter.\n"); 2933 } 2934 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2935 "Bars=%d.\n", bars); 2936 2937 if (mem_only) { 2938 if (pci_enable_device_mem(pdev)) 2939 return ret; 2940 } else { 2941 if (pci_enable_device(pdev)) 2942 return ret; 2943 } 2944 2945 if (is_kdump_kernel()) { 2946 ql2xmqsupport = 0; 2947 ql2xallocfwdump = 0; 2948 } 2949 2950 /* This may fail but that's ok */ 2951 pci_enable_pcie_error_reporting(pdev); 2952 2953 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2954 if (!ha) { 2955 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2956 "Unable to allocate memory for ha.\n"); 2957 goto disable_device; 2958 } 2959 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2960 "Memory allocated for ha=%p.\n", ha); 2961 ha->pdev = pdev; 2962 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2963 spin_lock_init(&ha->tgt.q_full_lock); 2964 spin_lock_init(&ha->tgt.sess_lock); 2965 spin_lock_init(&ha->tgt.atio_lock); 2966 2967 spin_lock_init(&ha->sadb_lock); 2968 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2969 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2970 2971 spin_lock_init(&ha->sadb_fp_lock); 2972 2973 if (qla_edif_sadb_build_free_pool(ha)) { 2974 kfree(ha); 2975 goto disable_device; 2976 } 2977 2978 atomic_set(&ha->nvme_active_aen_cnt, 0); 2979 2980 /* Clear our data area */ 2981 ha->bars = bars; 2982 ha->mem_only = mem_only; 2983 spin_lock_init(&ha->hardware_lock); 2984 spin_lock_init(&ha->vport_slock); 2985 mutex_init(&ha->selflogin_lock); 2986 mutex_init(&ha->optrom_mutex); 2987 2988 /* Set ISP-type information. */ 2989 qla2x00_set_isp_flags(ha); 2990 2991 /* Set EEH reset type to fundamental if required by hba */ 2992 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2993 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2994 pdev->needs_freset = 1; 2995 2996 ha->prev_topology = 0; 2997 ha->init_cb_size = sizeof(init_cb_t); 2998 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2999 ha->optrom_size = OPTROM_SIZE_2300; 3000 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3001 atomic_set(&ha->num_pend_mbx_stage1, 0); 3002 atomic_set(&ha->num_pend_mbx_stage2, 0); 3003 atomic_set(&ha->num_pend_mbx_stage3, 0); 3004 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3005 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3006 3007 /* Assign ISP specific operations. */ 3008 if (IS_QLA2100(ha)) { 3009 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3010 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3011 req_length = REQUEST_ENTRY_CNT_2100; 3012 rsp_length = RESPONSE_ENTRY_CNT_2100; 3013 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3014 ha->gid_list_info_size = 4; 3015 ha->flash_conf_off = ~0; 3016 ha->flash_data_off = ~0; 3017 ha->nvram_conf_off = ~0; 3018 ha->nvram_data_off = ~0; 3019 ha->isp_ops = &qla2100_isp_ops; 3020 } else if (IS_QLA2200(ha)) { 3021 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3022 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3023 req_length = REQUEST_ENTRY_CNT_2200; 3024 rsp_length = RESPONSE_ENTRY_CNT_2100; 3025 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3026 ha->gid_list_info_size = 4; 3027 ha->flash_conf_off = ~0; 3028 ha->flash_data_off = ~0; 3029 ha->nvram_conf_off = ~0; 3030 ha->nvram_data_off = ~0; 3031 ha->isp_ops = &qla2100_isp_ops; 3032 } else if (IS_QLA23XX(ha)) { 3033 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3034 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3035 req_length = REQUEST_ENTRY_CNT_2200; 3036 rsp_length = RESPONSE_ENTRY_CNT_2300; 3037 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3038 ha->gid_list_info_size = 6; 3039 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3040 ha->optrom_size = OPTROM_SIZE_2322; 3041 ha->flash_conf_off = ~0; 3042 ha->flash_data_off = ~0; 3043 ha->nvram_conf_off = ~0; 3044 ha->nvram_data_off = ~0; 3045 ha->isp_ops = &qla2300_isp_ops; 3046 } else if (IS_QLA24XX_TYPE(ha)) { 3047 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3048 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3049 req_length = REQUEST_ENTRY_CNT_24XX; 3050 rsp_length = RESPONSE_ENTRY_CNT_2300; 3051 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3052 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3053 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3054 ha->gid_list_info_size = 8; 3055 ha->optrom_size = OPTROM_SIZE_24XX; 3056 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3057 ha->isp_ops = &qla24xx_isp_ops; 3058 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3059 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3060 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3061 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3062 } else if (IS_QLA25XX(ha)) { 3063 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3064 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3065 req_length = REQUEST_ENTRY_CNT_24XX; 3066 rsp_length = RESPONSE_ENTRY_CNT_2300; 3067 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3068 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3069 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3070 ha->gid_list_info_size = 8; 3071 ha->optrom_size = OPTROM_SIZE_25XX; 3072 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3073 ha->isp_ops = &qla25xx_isp_ops; 3074 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3075 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3076 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3077 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3078 } else if (IS_QLA81XX(ha)) { 3079 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3080 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3081 req_length = REQUEST_ENTRY_CNT_24XX; 3082 rsp_length = RESPONSE_ENTRY_CNT_2300; 3083 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3084 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3085 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3086 ha->gid_list_info_size = 8; 3087 ha->optrom_size = OPTROM_SIZE_81XX; 3088 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3089 ha->isp_ops = &qla81xx_isp_ops; 3090 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3091 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3092 ha->nvram_conf_off = ~0; 3093 ha->nvram_data_off = ~0; 3094 } else if (IS_QLA82XX(ha)) { 3095 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3096 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3097 req_length = REQUEST_ENTRY_CNT_82XX; 3098 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3099 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3100 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3101 ha->gid_list_info_size = 8; 3102 ha->optrom_size = OPTROM_SIZE_82XX; 3103 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3104 ha->isp_ops = &qla82xx_isp_ops; 3105 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3106 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3107 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3108 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3109 } else if (IS_QLA8044(ha)) { 3110 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3111 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3112 req_length = REQUEST_ENTRY_CNT_82XX; 3113 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3114 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3115 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3116 ha->gid_list_info_size = 8; 3117 ha->optrom_size = OPTROM_SIZE_83XX; 3118 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3119 ha->isp_ops = &qla8044_isp_ops; 3120 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3121 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3122 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3123 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3124 } else if (IS_QLA83XX(ha)) { 3125 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3126 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3127 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3128 req_length = REQUEST_ENTRY_CNT_83XX; 3129 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3130 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3131 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3132 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3133 ha->gid_list_info_size = 8; 3134 ha->optrom_size = OPTROM_SIZE_83XX; 3135 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3136 ha->isp_ops = &qla83xx_isp_ops; 3137 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3138 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3139 ha->nvram_conf_off = ~0; 3140 ha->nvram_data_off = ~0; 3141 } else if (IS_QLAFX00(ha)) { 3142 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3143 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3144 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3145 req_length = REQUEST_ENTRY_CNT_FX00; 3146 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3147 ha->isp_ops = &qlafx00_isp_ops; 3148 ha->port_down_retry_count = 30; /* default value */ 3149 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3150 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3151 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3152 ha->mr.fw_hbt_en = 1; 3153 ha->mr.host_info_resend = false; 3154 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3155 } else if (IS_QLA27XX(ha)) { 3156 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3157 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3158 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3159 req_length = REQUEST_ENTRY_CNT_83XX; 3160 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3161 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3162 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3163 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3164 ha->gid_list_info_size = 8; 3165 ha->optrom_size = OPTROM_SIZE_83XX; 3166 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3167 ha->isp_ops = &qla27xx_isp_ops; 3168 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3169 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3170 ha->nvram_conf_off = ~0; 3171 ha->nvram_data_off = ~0; 3172 } else if (IS_QLA28XX(ha)) { 3173 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3174 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3175 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3176 req_length = REQUEST_ENTRY_CNT_83XX; 3177 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3178 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3179 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3180 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3181 ha->gid_list_info_size = 8; 3182 ha->optrom_size = OPTROM_SIZE_28XX; 3183 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3184 ha->isp_ops = &qla27xx_isp_ops; 3185 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3186 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3187 ha->nvram_conf_off = ~0; 3188 ha->nvram_data_off = ~0; 3189 } 3190 3191 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3192 "mbx_count=%d, req_length=%d, " 3193 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3194 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3195 "max_fibre_devices=%d.\n", 3196 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3197 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3198 ha->nvram_npiv_size, ha->max_fibre_devices); 3199 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3200 "isp_ops=%p, flash_conf_off=%d, " 3201 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3202 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3203 ha->nvram_conf_off, ha->nvram_data_off); 3204 3205 /* Configure PCI I/O space */ 3206 ret = ha->isp_ops->iospace_config(ha); 3207 if (ret) 3208 goto iospace_config_failed; 3209 3210 ql_log_pci(ql_log_info, pdev, 0x001d, 3211 "Found an ISP%04X irq %d iobase 0x%p.\n", 3212 pdev->device, pdev->irq, ha->iobase); 3213 mutex_init(&ha->vport_lock); 3214 mutex_init(&ha->mq_lock); 3215 init_completion(&ha->mbx_cmd_comp); 3216 complete(&ha->mbx_cmd_comp); 3217 init_completion(&ha->mbx_intr_comp); 3218 init_completion(&ha->dcbx_comp); 3219 init_completion(&ha->lb_portup_comp); 3220 3221 set_bit(0, (unsigned long *) ha->vp_idx_map); 3222 3223 qla2x00_config_dma_addressing(ha); 3224 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3225 "64 Bit addressing is %s.\n", 3226 ha->flags.enable_64bit_addressing ? "enable" : 3227 "disable"); 3228 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3229 if (ret) { 3230 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3231 "Failed to allocate memory for adapter, aborting.\n"); 3232 3233 goto probe_hw_failed; 3234 } 3235 3236 req->max_q_depth = MAX_Q_DEPTH; 3237 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3238 req->max_q_depth = ql2xmaxqdepth; 3239 3240 3241 base_vha = qla2x00_create_host(sht, ha); 3242 if (!base_vha) { 3243 ret = -ENOMEM; 3244 goto probe_hw_failed; 3245 } 3246 3247 pci_set_drvdata(pdev, base_vha); 3248 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3249 3250 host = base_vha->host; 3251 base_vha->req = req; 3252 if (IS_QLA2XXX_MIDTYPE(ha)) 3253 base_vha->mgmt_svr_loop_id = 3254 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3255 else 3256 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3257 base_vha->vp_idx; 3258 3259 /* Setup fcport template structure. */ 3260 ha->mr.fcport.vha = base_vha; 3261 ha->mr.fcport.port_type = FCT_UNKNOWN; 3262 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3263 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3264 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3265 ha->mr.fcport.scan_state = 1; 3266 3267 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3268 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3269 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3270 3271 /* Set the SG table size based on ISP type */ 3272 if (!IS_FWI2_CAPABLE(ha)) { 3273 if (IS_QLA2100(ha)) 3274 host->sg_tablesize = 32; 3275 } else { 3276 if (!IS_QLA82XX(ha)) 3277 host->sg_tablesize = QLA_SG_ALL; 3278 } 3279 host->max_id = ha->max_fibre_devices; 3280 host->cmd_per_lun = 3; 3281 host->unique_id = host->host_no; 3282 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3283 host->max_cmd_len = 32; 3284 else 3285 host->max_cmd_len = MAX_CMDSZ; 3286 host->max_channel = MAX_BUSES - 1; 3287 /* Older HBAs support only 16-bit LUNs */ 3288 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3289 ql2xmaxlun > 0xffff) 3290 host->max_lun = 0xffff; 3291 else 3292 host->max_lun = ql2xmaxlun; 3293 host->transportt = qla2xxx_transport_template; 3294 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3295 3296 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3297 "max_id=%d this_id=%d " 3298 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3299 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3300 host->this_id, host->cmd_per_lun, host->unique_id, 3301 host->max_cmd_len, host->max_channel, host->max_lun, 3302 host->transportt, sht->vendor_id); 3303 3304 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3305 3306 /* Set up the irqs */ 3307 ret = qla2x00_request_irqs(ha, rsp); 3308 if (ret) 3309 goto probe_failed; 3310 3311 /* Alloc arrays of request and response ring ptrs */ 3312 ret = qla2x00_alloc_queues(ha, req, rsp); 3313 if (ret) { 3314 ql_log(ql_log_fatal, base_vha, 0x003d, 3315 "Failed to allocate memory for queue pointers..." 3316 "aborting.\n"); 3317 ret = -ENODEV; 3318 goto probe_failed; 3319 } 3320 3321 if (ha->mqenable) { 3322 /* number of hardware queues supported by blk/scsi-mq*/ 3323 host->nr_hw_queues = ha->max_qpairs; 3324 3325 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3326 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3327 } else { 3328 if (ql2xnvmeenable) { 3329 host->nr_hw_queues = ha->max_qpairs; 3330 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3331 "FC-NVMe support is enabled, HW queues=%d\n", 3332 host->nr_hw_queues); 3333 } else { 3334 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3335 "blk/scsi-mq disabled.\n"); 3336 } 3337 } 3338 3339 qlt_probe_one_stage1(base_vha, ha); 3340 3341 pci_save_state(pdev); 3342 3343 /* Assign back pointers */ 3344 rsp->req = req; 3345 req->rsp = rsp; 3346 3347 if (IS_QLAFX00(ha)) { 3348 ha->rsp_q_map[0] = rsp; 3349 ha->req_q_map[0] = req; 3350 set_bit(0, ha->req_qid_map); 3351 set_bit(0, ha->rsp_qid_map); 3352 } 3353 3354 /* FWI2-capable only. */ 3355 req->req_q_in = &ha->iobase->isp24.req_q_in; 3356 req->req_q_out = &ha->iobase->isp24.req_q_out; 3357 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3358 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3359 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3360 IS_QLA28XX(ha)) { 3361 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3362 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3363 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3364 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3365 } 3366 3367 if (IS_QLAFX00(ha)) { 3368 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3369 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3370 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3371 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3372 } 3373 3374 if (IS_P3P_TYPE(ha)) { 3375 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3376 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3377 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3378 } 3379 3380 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3381 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3382 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3383 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3384 "req->req_q_in=%p req->req_q_out=%p " 3385 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3386 req->req_q_in, req->req_q_out, 3387 rsp->rsp_q_in, rsp->rsp_q_out); 3388 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3389 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3390 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3391 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3392 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3393 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3394 3395 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3396 if (unlikely(!ha->wq)) { 3397 ret = -ENOMEM; 3398 goto probe_failed; 3399 } 3400 3401 if (ha->isp_ops->initialize_adapter(base_vha)) { 3402 ql_log(ql_log_fatal, base_vha, 0x00d6, 3403 "Failed to initialize adapter - Adapter flags %x.\n", 3404 base_vha->device_flags); 3405 3406 if (IS_QLA82XX(ha)) { 3407 qla82xx_idc_lock(ha); 3408 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3409 QLA8XXX_DEV_FAILED); 3410 qla82xx_idc_unlock(ha); 3411 ql_log(ql_log_fatal, base_vha, 0x00d7, 3412 "HW State: FAILED.\n"); 3413 } else if (IS_QLA8044(ha)) { 3414 qla8044_idc_lock(ha); 3415 qla8044_wr_direct(base_vha, 3416 QLA8044_CRB_DEV_STATE_INDEX, 3417 QLA8XXX_DEV_FAILED); 3418 qla8044_idc_unlock(ha); 3419 ql_log(ql_log_fatal, base_vha, 0x0150, 3420 "HW State: FAILED.\n"); 3421 } 3422 3423 ret = -ENODEV; 3424 goto probe_failed; 3425 } 3426 3427 if (IS_QLAFX00(ha)) 3428 host->can_queue = QLAFX00_MAX_CANQUEUE; 3429 else 3430 host->can_queue = req->num_outstanding_cmds - 10; 3431 3432 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3433 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3434 host->can_queue, base_vha->req, 3435 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3436 3437 /* Check if FW supports MQ or not for ISP25xx */ 3438 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3439 ha->mqenable = 0; 3440 3441 if (ha->mqenable) { 3442 bool startit = false; 3443 3444 if (QLA_TGT_MODE_ENABLED()) 3445 startit = false; 3446 3447 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3448 startit = true; 3449 3450 /* Create start of day qpairs for Block MQ */ 3451 for (i = 0; i < ha->max_qpairs; i++) 3452 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3453 } 3454 qla_init_iocb_limit(base_vha); 3455 3456 if (ha->flags.running_gold_fw) 3457 goto skip_dpc; 3458 3459 /* 3460 * Startup the kernel thread for this host adapter 3461 */ 3462 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3463 "%s_dpc", base_vha->host_str); 3464 if (IS_ERR(ha->dpc_thread)) { 3465 ql_log(ql_log_fatal, base_vha, 0x00ed, 3466 "Failed to start DPC thread.\n"); 3467 ret = PTR_ERR(ha->dpc_thread); 3468 ha->dpc_thread = NULL; 3469 goto probe_failed; 3470 } 3471 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3472 "DPC thread started successfully.\n"); 3473 3474 /* 3475 * If we're not coming up in initiator mode, we might sit for 3476 * a while without waking up the dpc thread, which leads to a 3477 * stuck process warning. So just kick the dpc once here and 3478 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3479 */ 3480 qla2xxx_wake_dpc(base_vha); 3481 3482 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3483 3484 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3485 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3486 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3487 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3488 3489 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3490 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3491 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3492 INIT_WORK(&ha->idc_state_handler, 3493 qla83xx_idc_state_handler_work); 3494 INIT_WORK(&ha->nic_core_unrecoverable, 3495 qla83xx_nic_core_unrecoverable_work); 3496 } 3497 3498 skip_dpc: 3499 list_add_tail(&base_vha->list, &ha->vp_list); 3500 base_vha->host->irq = ha->pdev->irq; 3501 3502 /* Initialized the timer */ 3503 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3504 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3505 "Started qla2x00_timer with " 3506 "interval=%d.\n", WATCH_INTERVAL); 3507 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3508 "Detected hba at address=%p.\n", 3509 ha); 3510 3511 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3512 if (ha->fw_attributes & BIT_4) { 3513 int prot = 0, guard; 3514 3515 base_vha->flags.difdix_supported = 1; 3516 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3517 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3518 if (ql2xenabledif == 1) 3519 prot = SHOST_DIX_TYPE0_PROTECTION; 3520 if (ql2xprotmask) 3521 scsi_host_set_prot(host, ql2xprotmask); 3522 else 3523 scsi_host_set_prot(host, 3524 prot | SHOST_DIF_TYPE1_PROTECTION 3525 | SHOST_DIF_TYPE2_PROTECTION 3526 | SHOST_DIF_TYPE3_PROTECTION 3527 | SHOST_DIX_TYPE1_PROTECTION 3528 | SHOST_DIX_TYPE2_PROTECTION 3529 | SHOST_DIX_TYPE3_PROTECTION); 3530 3531 guard = SHOST_DIX_GUARD_CRC; 3532 3533 if (IS_PI_IPGUARD_CAPABLE(ha) && 3534 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3535 guard |= SHOST_DIX_GUARD_IP; 3536 3537 if (ql2xprotguard) 3538 scsi_host_set_guard(host, ql2xprotguard); 3539 else 3540 scsi_host_set_guard(host, guard); 3541 } else 3542 base_vha->flags.difdix_supported = 0; 3543 } 3544 3545 ha->isp_ops->enable_intrs(ha); 3546 3547 if (IS_QLAFX00(ha)) { 3548 ret = qlafx00_fx_disc(base_vha, 3549 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3550 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3551 QLA_SG_ALL : 128; 3552 } 3553 3554 ret = scsi_add_host(host, &pdev->dev); 3555 if (ret) 3556 goto probe_failed; 3557 3558 base_vha->flags.init_done = 1; 3559 base_vha->flags.online = 1; 3560 ha->prev_minidump_failed = 0; 3561 3562 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3563 "Init done and hba is online.\n"); 3564 3565 if (qla_ini_mode_enabled(base_vha) || 3566 qla_dual_mode_enabled(base_vha)) 3567 scsi_scan_host(host); 3568 else 3569 ql_log(ql_log_info, base_vha, 0x0122, 3570 "skipping scsi_scan_host() for non-initiator port\n"); 3571 3572 qla2x00_alloc_sysfs_attr(base_vha); 3573 3574 if (IS_QLAFX00(ha)) { 3575 ret = qlafx00_fx_disc(base_vha, 3576 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3577 3578 /* Register system information */ 3579 ret = qlafx00_fx_disc(base_vha, 3580 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3581 } 3582 3583 qla2x00_init_host_attr(base_vha); 3584 3585 qla2x00_dfs_setup(base_vha); 3586 3587 ql_log(ql_log_info, base_vha, 0x00fb, 3588 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3589 ql_log(ql_log_info, base_vha, 0x00fc, 3590 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3591 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3592 sizeof(pci_info)), 3593 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3594 base_vha->host_no, 3595 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3596 3597 qlt_add_target(ha, base_vha); 3598 3599 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3600 3601 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3602 return -ENODEV; 3603 3604 return 0; 3605 3606 probe_failed: 3607 qla_enode_stop(base_vha); 3608 qla_edb_stop(base_vha); 3609 if (base_vha->gnl.l) { 3610 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3611 base_vha->gnl.l, base_vha->gnl.ldma); 3612 base_vha->gnl.l = NULL; 3613 } 3614 3615 if (base_vha->timer_active) 3616 qla2x00_stop_timer(base_vha); 3617 base_vha->flags.online = 0; 3618 if (ha->dpc_thread) { 3619 struct task_struct *t = ha->dpc_thread; 3620 3621 ha->dpc_thread = NULL; 3622 kthread_stop(t); 3623 } 3624 3625 qla2x00_free_device(base_vha); 3626 scsi_host_put(base_vha->host); 3627 /* 3628 * Need to NULL out local req/rsp after 3629 * qla2x00_free_device => qla2x00_free_queues frees 3630 * what these are pointing to. Or else we'll 3631 * fall over below in qla2x00_free_req/rsp_que. 3632 */ 3633 req = NULL; 3634 rsp = NULL; 3635 3636 probe_hw_failed: 3637 qla2x00_mem_free(ha); 3638 qla2x00_free_req_que(ha, req); 3639 qla2x00_free_rsp_que(ha, rsp); 3640 qla2x00_clear_drv_active(ha); 3641 3642 iospace_config_failed: 3643 if (IS_P3P_TYPE(ha)) { 3644 if (!ha->nx_pcibase) 3645 iounmap((device_reg_t *)ha->nx_pcibase); 3646 if (!ql2xdbwr) 3647 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3648 } else { 3649 if (ha->iobase) 3650 iounmap(ha->iobase); 3651 if (ha->cregbase) 3652 iounmap(ha->cregbase); 3653 } 3654 pci_release_selected_regions(ha->pdev, ha->bars); 3655 kfree(ha); 3656 3657 disable_device: 3658 pci_disable_device(pdev); 3659 return ret; 3660 } 3661 3662 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3663 { 3664 scsi_qla_host_t *vp; 3665 unsigned long flags; 3666 struct qla_hw_data *ha; 3667 3668 if (!base_vha) 3669 return; 3670 3671 ha = base_vha->hw; 3672 3673 spin_lock_irqsave(&ha->vport_slock, flags); 3674 list_for_each_entry(vp, &ha->vp_list, list) 3675 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3676 3677 /* 3678 * Indicate device removal to prevent future board_disable 3679 * and wait until any pending board_disable has completed. 3680 */ 3681 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3682 spin_unlock_irqrestore(&ha->vport_slock, flags); 3683 } 3684 3685 static void 3686 qla2x00_shutdown(struct pci_dev *pdev) 3687 { 3688 scsi_qla_host_t *vha; 3689 struct qla_hw_data *ha; 3690 3691 vha = pci_get_drvdata(pdev); 3692 ha = vha->hw; 3693 3694 ql_log(ql_log_info, vha, 0xfffa, 3695 "Adapter shutdown\n"); 3696 3697 /* 3698 * Prevent future board_disable and wait 3699 * until any pending board_disable has completed. 3700 */ 3701 __qla_set_remove_flag(vha); 3702 cancel_work_sync(&ha->board_disable); 3703 3704 if (!atomic_read(&pdev->enable_cnt)) 3705 return; 3706 3707 /* Notify ISPFX00 firmware */ 3708 if (IS_QLAFX00(ha)) 3709 qlafx00_driver_shutdown(vha, 20); 3710 3711 /* Turn-off FCE trace */ 3712 if (ha->flags.fce_enabled) { 3713 qla2x00_disable_fce_trace(vha, NULL, NULL); 3714 ha->flags.fce_enabled = 0; 3715 } 3716 3717 /* Turn-off EFT trace */ 3718 if (ha->eft) 3719 qla2x00_disable_eft_trace(vha); 3720 3721 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3722 IS_QLA28XX(ha)) { 3723 if (ha->flags.fw_started) 3724 qla2x00_abort_isp_cleanup(vha); 3725 } else { 3726 /* Stop currently executing firmware. */ 3727 qla2x00_try_to_stop_firmware(vha); 3728 } 3729 3730 /* Disable timer */ 3731 if (vha->timer_active) 3732 qla2x00_stop_timer(vha); 3733 3734 /* Turn adapter off line */ 3735 vha->flags.online = 0; 3736 3737 /* turn-off interrupts on the card */ 3738 if (ha->interrupts_on) { 3739 vha->flags.init_done = 0; 3740 ha->isp_ops->disable_intrs(ha); 3741 } 3742 3743 qla2x00_free_irqs(vha); 3744 3745 qla2x00_free_fw_dump(ha); 3746 3747 pci_disable_device(pdev); 3748 ql_log(ql_log_info, vha, 0xfffe, 3749 "Adapter shutdown successfully.\n"); 3750 } 3751 3752 /* Deletes all the virtual ports for a given ha */ 3753 static void 3754 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3755 { 3756 scsi_qla_host_t *vha; 3757 unsigned long flags; 3758 3759 mutex_lock(&ha->vport_lock); 3760 while (ha->cur_vport_count) { 3761 spin_lock_irqsave(&ha->vport_slock, flags); 3762 3763 BUG_ON(base_vha->list.next == &ha->vp_list); 3764 /* This assumes first entry in ha->vp_list is always base vha */ 3765 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3766 scsi_host_get(vha->host); 3767 3768 spin_unlock_irqrestore(&ha->vport_slock, flags); 3769 mutex_unlock(&ha->vport_lock); 3770 3771 qla_nvme_delete(vha); 3772 3773 fc_vport_terminate(vha->fc_vport); 3774 scsi_host_put(vha->host); 3775 3776 mutex_lock(&ha->vport_lock); 3777 } 3778 mutex_unlock(&ha->vport_lock); 3779 } 3780 3781 /* Stops all deferred work threads */ 3782 static void 3783 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3784 { 3785 /* Cancel all work and destroy DPC workqueues */ 3786 if (ha->dpc_lp_wq) { 3787 cancel_work_sync(&ha->idc_aen); 3788 destroy_workqueue(ha->dpc_lp_wq); 3789 ha->dpc_lp_wq = NULL; 3790 } 3791 3792 if (ha->dpc_hp_wq) { 3793 cancel_work_sync(&ha->nic_core_reset); 3794 cancel_work_sync(&ha->idc_state_handler); 3795 cancel_work_sync(&ha->nic_core_unrecoverable); 3796 destroy_workqueue(ha->dpc_hp_wq); 3797 ha->dpc_hp_wq = NULL; 3798 } 3799 3800 /* Kill the kernel thread for this host */ 3801 if (ha->dpc_thread) { 3802 struct task_struct *t = ha->dpc_thread; 3803 3804 /* 3805 * qla2xxx_wake_dpc checks for ->dpc_thread 3806 * so we need to zero it out. 3807 */ 3808 ha->dpc_thread = NULL; 3809 kthread_stop(t); 3810 } 3811 } 3812 3813 static void 3814 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3815 { 3816 if (IS_QLA82XX(ha)) { 3817 3818 iounmap((device_reg_t *)ha->nx_pcibase); 3819 if (!ql2xdbwr) 3820 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3821 } else { 3822 if (ha->iobase) 3823 iounmap(ha->iobase); 3824 3825 if (ha->cregbase) 3826 iounmap(ha->cregbase); 3827 3828 if (ha->mqiobase) 3829 iounmap(ha->mqiobase); 3830 3831 if (ha->msixbase) 3832 iounmap(ha->msixbase); 3833 } 3834 } 3835 3836 static void 3837 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3838 { 3839 if (IS_QLA8044(ha)) { 3840 qla8044_idc_lock(ha); 3841 qla8044_clear_drv_active(ha); 3842 qla8044_idc_unlock(ha); 3843 } else if (IS_QLA82XX(ha)) { 3844 qla82xx_idc_lock(ha); 3845 qla82xx_clear_drv_active(ha); 3846 qla82xx_idc_unlock(ha); 3847 } 3848 } 3849 3850 static void 3851 qla2x00_remove_one(struct pci_dev *pdev) 3852 { 3853 scsi_qla_host_t *base_vha; 3854 struct qla_hw_data *ha; 3855 3856 base_vha = pci_get_drvdata(pdev); 3857 ha = base_vha->hw; 3858 ql_log(ql_log_info, base_vha, 0xb079, 3859 "Removing driver\n"); 3860 __qla_set_remove_flag(base_vha); 3861 cancel_work_sync(&ha->board_disable); 3862 3863 /* 3864 * If the PCI device is disabled then there was a PCI-disconnect and 3865 * qla2x00_disable_board_on_pci_error has taken care of most of the 3866 * resources. 3867 */ 3868 if (!atomic_read(&pdev->enable_cnt)) { 3869 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3870 base_vha->gnl.l, base_vha->gnl.ldma); 3871 base_vha->gnl.l = NULL; 3872 scsi_host_put(base_vha->host); 3873 kfree(ha); 3874 pci_set_drvdata(pdev, NULL); 3875 return; 3876 } 3877 qla2x00_wait_for_hba_ready(base_vha); 3878 3879 /* 3880 * if UNLOADING flag is already set, then continue unload, 3881 * where it was set first. 3882 */ 3883 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3884 return; 3885 3886 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3887 IS_QLA28XX(ha)) { 3888 if (ha->flags.fw_started) 3889 qla2x00_abort_isp_cleanup(base_vha); 3890 } else if (!IS_QLAFX00(ha)) { 3891 if (IS_QLA8031(ha)) { 3892 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3893 "Clearing fcoe driver presence.\n"); 3894 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3895 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3896 "Error while clearing DRV-Presence.\n"); 3897 } 3898 3899 qla2x00_try_to_stop_firmware(base_vha); 3900 } 3901 3902 qla2x00_wait_for_sess_deletion(base_vha); 3903 3904 qla_nvme_delete(base_vha); 3905 3906 dma_free_coherent(&ha->pdev->dev, 3907 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3908 3909 base_vha->gnl.l = NULL; 3910 qla_enode_stop(base_vha); 3911 qla_edb_stop(base_vha); 3912 3913 vfree(base_vha->scan.l); 3914 3915 if (IS_QLAFX00(ha)) 3916 qlafx00_driver_shutdown(base_vha, 20); 3917 3918 qla2x00_delete_all_vps(ha, base_vha); 3919 3920 qla2x00_dfs_remove(base_vha); 3921 3922 qla84xx_put_chip(base_vha); 3923 3924 /* Disable timer */ 3925 if (base_vha->timer_active) 3926 qla2x00_stop_timer(base_vha); 3927 3928 base_vha->flags.online = 0; 3929 3930 /* free DMA memory */ 3931 if (ha->exlogin_buf) 3932 qla2x00_free_exlogin_buffer(ha); 3933 3934 /* free DMA memory */ 3935 if (ha->exchoffld_buf) 3936 qla2x00_free_exchoffld_buffer(ha); 3937 3938 qla2x00_destroy_deferred_work(ha); 3939 3940 qlt_remove_target(ha, base_vha); 3941 3942 qla2x00_free_sysfs_attr(base_vha, true); 3943 3944 fc_remove_host(base_vha->host); 3945 3946 scsi_remove_host(base_vha->host); 3947 3948 qla2x00_free_device(base_vha); 3949 3950 qla2x00_clear_drv_active(ha); 3951 3952 scsi_host_put(base_vha->host); 3953 3954 qla2x00_unmap_iobases(ha); 3955 3956 pci_release_selected_regions(ha->pdev, ha->bars); 3957 kfree(ha); 3958 3959 pci_disable_pcie_error_reporting(pdev); 3960 3961 pci_disable_device(pdev); 3962 } 3963 3964 static inline void 3965 qla24xx_free_purex_list(struct purex_list *list) 3966 { 3967 struct purex_item *item, *next; 3968 ulong flags; 3969 3970 spin_lock_irqsave(&list->lock, flags); 3971 list_for_each_entry_safe(item, next, &list->head, list) { 3972 list_del(&item->list); 3973 if (item == &item->vha->default_item) 3974 continue; 3975 kfree(item); 3976 } 3977 spin_unlock_irqrestore(&list->lock, flags); 3978 } 3979 3980 static void 3981 qla2x00_free_device(scsi_qla_host_t *vha) 3982 { 3983 struct qla_hw_data *ha = vha->hw; 3984 3985 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3986 3987 /* Disable timer */ 3988 if (vha->timer_active) 3989 qla2x00_stop_timer(vha); 3990 3991 qla25xx_delete_queues(vha); 3992 vha->flags.online = 0; 3993 3994 /* turn-off interrupts on the card */ 3995 if (ha->interrupts_on) { 3996 vha->flags.init_done = 0; 3997 ha->isp_ops->disable_intrs(ha); 3998 } 3999 4000 qla2x00_free_fcports(vha); 4001 4002 qla2x00_free_irqs(vha); 4003 4004 /* Flush the work queue and remove it */ 4005 if (ha->wq) { 4006 destroy_workqueue(ha->wq); 4007 ha->wq = NULL; 4008 } 4009 4010 4011 qla24xx_free_purex_list(&vha->purex_list); 4012 4013 qla2x00_mem_free(ha); 4014 4015 qla82xx_md_free(vha); 4016 4017 qla_edif_sadb_release_free_pool(ha); 4018 qla_edif_sadb_release(ha); 4019 4020 qla2x00_free_queues(ha); 4021 } 4022 4023 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4024 { 4025 fc_port_t *fcport, *tfcport; 4026 4027 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4028 qla2x00_free_fcport(fcport); 4029 } 4030 4031 static inline void 4032 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4033 { 4034 int now; 4035 4036 if (!fcport->rport) 4037 return; 4038 4039 if (fcport->rport) { 4040 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4041 "%s %8phN. rport %p roles %x\n", 4042 __func__, fcport->port_name, fcport->rport, 4043 fcport->rport->roles); 4044 fc_remote_port_delete(fcport->rport); 4045 } 4046 qlt_do_generation_tick(vha, &now); 4047 } 4048 4049 /* 4050 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4051 * 4052 * Input: ha = adapter block pointer. fcport = port structure pointer. 4053 * 4054 * Return: None. 4055 * 4056 * Context: 4057 */ 4058 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4059 int do_login) 4060 { 4061 if (IS_QLAFX00(vha->hw)) { 4062 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4063 qla2x00_schedule_rport_del(vha, fcport); 4064 return; 4065 } 4066 4067 if (atomic_read(&fcport->state) == FCS_ONLINE && 4068 vha->vp_idx == fcport->vha->vp_idx) { 4069 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4070 qla2x00_schedule_rport_del(vha, fcport); 4071 } 4072 4073 /* 4074 * We may need to retry the login, so don't change the state of the 4075 * port but do the retries. 4076 */ 4077 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4078 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4079 4080 if (!do_login) 4081 return; 4082 4083 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4084 } 4085 4086 void 4087 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4088 { 4089 fc_port_t *fcport; 4090 4091 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4092 "Mark all dev lost\n"); 4093 4094 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4095 if (ql2xfc2target && 4096 fcport->loop_id != FC_NO_LOOP_ID && 4097 (fcport->flags & FCF_FCP2_DEVICE) && 4098 fcport->port_type == FCT_TARGET && 4099 !qla2x00_reset_active(vha)) { 4100 ql_dbg(ql_dbg_disc, vha, 0x211a, 4101 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4102 fcport->flags, fcport->port_type, 4103 fcport->d_id.b24, fcport->port_name); 4104 continue; 4105 } 4106 fcport->scan_state = 0; 4107 qlt_schedule_sess_for_deletion(fcport); 4108 } 4109 } 4110 4111 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4112 { 4113 int i; 4114 4115 if (IS_FWI2_CAPABLE(ha)) 4116 return; 4117 4118 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4119 set_bit(i, ha->loop_id_map); 4120 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4121 set_bit(BROADCAST, ha->loop_id_map); 4122 } 4123 4124 /* 4125 * qla2x00_mem_alloc 4126 * Allocates adapter memory. 4127 * 4128 * Returns: 4129 * 0 = success. 4130 * !0 = failure. 4131 */ 4132 static int 4133 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4134 struct req_que **req, struct rsp_que **rsp) 4135 { 4136 char name[16]; 4137 int rc; 4138 4139 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4140 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4141 if (!ha->vp_map) 4142 goto fail; 4143 } 4144 4145 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4146 &ha->init_cb_dma, GFP_KERNEL); 4147 if (!ha->init_cb) 4148 goto fail_free_vp_map; 4149 4150 rc = btree_init32(&ha->host_map); 4151 if (rc) 4152 goto fail_free_init_cb; 4153 4154 if (qlt_mem_alloc(ha) < 0) 4155 goto fail_free_btree; 4156 4157 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4158 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4159 if (!ha->gid_list) 4160 goto fail_free_tgt_mem; 4161 4162 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4163 if (!ha->srb_mempool) 4164 goto fail_free_gid_list; 4165 4166 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4167 /* Allocate cache for CT6 Ctx. */ 4168 if (!ctx_cachep) { 4169 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4170 sizeof(struct ct6_dsd), 0, 4171 SLAB_HWCACHE_ALIGN, NULL); 4172 if (!ctx_cachep) 4173 goto fail_free_srb_mempool; 4174 } 4175 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4176 ctx_cachep); 4177 if (!ha->ctx_mempool) 4178 goto fail_free_srb_mempool; 4179 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4180 "ctx_cachep=%p ctx_mempool=%p.\n", 4181 ctx_cachep, ha->ctx_mempool); 4182 } 4183 4184 /* Get memory for cached NVRAM */ 4185 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4186 if (!ha->nvram) 4187 goto fail_free_ctx_mempool; 4188 4189 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4190 ha->pdev->device); 4191 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4192 DMA_POOL_SIZE, 8, 0); 4193 if (!ha->s_dma_pool) 4194 goto fail_free_nvram; 4195 4196 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4197 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4198 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4199 4200 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4201 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4202 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4203 if (!ha->dl_dma_pool) { 4204 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4205 "Failed to allocate memory for dl_dma_pool.\n"); 4206 goto fail_s_dma_pool; 4207 } 4208 4209 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4210 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4211 if (!ha->fcp_cmnd_dma_pool) { 4212 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4213 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4214 goto fail_dl_dma_pool; 4215 } 4216 4217 if (ql2xenabledif) { 4218 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4219 struct dsd_dma *dsd, *nxt; 4220 uint i; 4221 /* Creata a DMA pool of buffers for DIF bundling */ 4222 ha->dif_bundl_pool = dma_pool_create(name, 4223 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4224 if (!ha->dif_bundl_pool) { 4225 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4226 "%s: failed create dif_bundl_pool\n", 4227 __func__); 4228 goto fail_dif_bundl_dma_pool; 4229 } 4230 4231 INIT_LIST_HEAD(&ha->pool.good.head); 4232 INIT_LIST_HEAD(&ha->pool.unusable.head); 4233 ha->pool.good.count = 0; 4234 ha->pool.unusable.count = 0; 4235 for (i = 0; i < 128; i++) { 4236 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4237 if (!dsd) { 4238 ql_dbg_pci(ql_dbg_init, ha->pdev, 4239 0xe0ee, "%s: failed alloc dsd\n", 4240 __func__); 4241 return -ENOMEM; 4242 } 4243 ha->dif_bundle_kallocs++; 4244 4245 dsd->dsd_addr = dma_pool_alloc( 4246 ha->dif_bundl_pool, GFP_ATOMIC, 4247 &dsd->dsd_list_dma); 4248 if (!dsd->dsd_addr) { 4249 ql_dbg_pci(ql_dbg_init, ha->pdev, 4250 0xe0ee, 4251 "%s: failed alloc ->dsd_addr\n", 4252 __func__); 4253 kfree(dsd); 4254 ha->dif_bundle_kallocs--; 4255 continue; 4256 } 4257 ha->dif_bundle_dma_allocs++; 4258 4259 /* 4260 * if DMA buffer crosses 4G boundary, 4261 * put it on bad list 4262 */ 4263 if (MSD(dsd->dsd_list_dma) ^ 4264 MSD(dsd->dsd_list_dma + bufsize)) { 4265 list_add_tail(&dsd->list, 4266 &ha->pool.unusable.head); 4267 ha->pool.unusable.count++; 4268 } else { 4269 list_add_tail(&dsd->list, 4270 &ha->pool.good.head); 4271 ha->pool.good.count++; 4272 } 4273 } 4274 4275 /* return the good ones back to the pool */ 4276 list_for_each_entry_safe(dsd, nxt, 4277 &ha->pool.good.head, list) { 4278 list_del(&dsd->list); 4279 dma_pool_free(ha->dif_bundl_pool, 4280 dsd->dsd_addr, dsd->dsd_list_dma); 4281 ha->dif_bundle_dma_allocs--; 4282 kfree(dsd); 4283 ha->dif_bundle_kallocs--; 4284 } 4285 4286 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4287 "%s: dif dma pool (good=%u unusable=%u)\n", 4288 __func__, ha->pool.good.count, 4289 ha->pool.unusable.count); 4290 } 4291 4292 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4293 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4294 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4295 ha->dif_bundl_pool); 4296 } 4297 4298 /* Allocate memory for SNS commands */ 4299 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4300 /* Get consistent memory allocated for SNS commands */ 4301 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4302 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4303 if (!ha->sns_cmd) 4304 goto fail_dma_pool; 4305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4306 "sns_cmd: %p.\n", ha->sns_cmd); 4307 } else { 4308 /* Get consistent memory allocated for MS IOCB */ 4309 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4310 &ha->ms_iocb_dma); 4311 if (!ha->ms_iocb) 4312 goto fail_dma_pool; 4313 /* Get consistent memory allocated for CT SNS commands */ 4314 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4315 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4316 if (!ha->ct_sns) 4317 goto fail_free_ms_iocb; 4318 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4319 "ms_iocb=%p ct_sns=%p.\n", 4320 ha->ms_iocb, ha->ct_sns); 4321 } 4322 4323 /* Allocate memory for request ring */ 4324 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4325 if (!*req) { 4326 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4327 "Failed to allocate memory for req.\n"); 4328 goto fail_req; 4329 } 4330 (*req)->length = req_len; 4331 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4332 ((*req)->length + 1) * sizeof(request_t), 4333 &(*req)->dma, GFP_KERNEL); 4334 if (!(*req)->ring) { 4335 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4336 "Failed to allocate memory for req_ring.\n"); 4337 goto fail_req_ring; 4338 } 4339 /* Allocate memory for response ring */ 4340 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4341 if (!*rsp) { 4342 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4343 "Failed to allocate memory for rsp.\n"); 4344 goto fail_rsp; 4345 } 4346 (*rsp)->hw = ha; 4347 (*rsp)->length = rsp_len; 4348 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4349 ((*rsp)->length + 1) * sizeof(response_t), 4350 &(*rsp)->dma, GFP_KERNEL); 4351 if (!(*rsp)->ring) { 4352 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4353 "Failed to allocate memory for rsp_ring.\n"); 4354 goto fail_rsp_ring; 4355 } 4356 (*req)->rsp = *rsp; 4357 (*rsp)->req = *req; 4358 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4359 "req=%p req->length=%d req->ring=%p rsp=%p " 4360 "rsp->length=%d rsp->ring=%p.\n", 4361 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4362 (*rsp)->ring); 4363 /* Allocate memory for NVRAM data for vports */ 4364 if (ha->nvram_npiv_size) { 4365 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4366 sizeof(struct qla_npiv_entry), 4367 GFP_KERNEL); 4368 if (!ha->npiv_info) { 4369 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4370 "Failed to allocate memory for npiv_info.\n"); 4371 goto fail_npiv_info; 4372 } 4373 } else 4374 ha->npiv_info = NULL; 4375 4376 /* Get consistent memory allocated for EX-INIT-CB. */ 4377 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4378 IS_QLA28XX(ha)) { 4379 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4380 &ha->ex_init_cb_dma); 4381 if (!ha->ex_init_cb) 4382 goto fail_ex_init_cb; 4383 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4384 "ex_init_cb=%p.\n", ha->ex_init_cb); 4385 } 4386 4387 /* Get consistent memory allocated for Special Features-CB. */ 4388 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4389 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4390 &ha->sf_init_cb_dma); 4391 if (!ha->sf_init_cb) 4392 goto fail_sf_init_cb; 4393 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4394 "sf_init_cb=%p.\n", ha->sf_init_cb); 4395 } 4396 4397 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4398 4399 /* Get consistent memory allocated for Async Port-Database. */ 4400 if (!IS_FWI2_CAPABLE(ha)) { 4401 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4402 &ha->async_pd_dma); 4403 if (!ha->async_pd) 4404 goto fail_async_pd; 4405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4406 "async_pd=%p.\n", ha->async_pd); 4407 } 4408 4409 INIT_LIST_HEAD(&ha->vp_list); 4410 4411 /* Allocate memory for our loop_id bitmap */ 4412 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4413 sizeof(long), 4414 GFP_KERNEL); 4415 if (!ha->loop_id_map) 4416 goto fail_loop_id_map; 4417 else { 4418 qla2x00_set_reserved_loop_ids(ha); 4419 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4420 "loop_id_map=%p.\n", ha->loop_id_map); 4421 } 4422 4423 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4424 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4425 if (!ha->sfp_data) { 4426 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4427 "Unable to allocate memory for SFP read-data.\n"); 4428 goto fail_sfp_data; 4429 } 4430 4431 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4432 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4433 GFP_KERNEL); 4434 if (!ha->flt) { 4435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4436 "Unable to allocate memory for FLT.\n"); 4437 goto fail_flt_buffer; 4438 } 4439 4440 /* allocate the purex dma pool */ 4441 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4442 ELS_MAX_PAYLOAD, 8, 0); 4443 4444 if (!ha->purex_dma_pool) { 4445 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4446 "Unable to allocate purex_dma_pool.\n"); 4447 goto fail_flt; 4448 } 4449 4450 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4451 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4452 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4453 4454 if (!ha->elsrej.c) { 4455 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4456 "Alloc failed for els reject cmd.\n"); 4457 goto fail_elsrej; 4458 } 4459 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4460 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4461 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4462 return 0; 4463 4464 fail_elsrej: 4465 dma_pool_destroy(ha->purex_dma_pool); 4466 fail_flt: 4467 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4468 ha->flt, ha->flt_dma); 4469 4470 fail_flt_buffer: 4471 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4472 ha->sfp_data, ha->sfp_data_dma); 4473 fail_sfp_data: 4474 kfree(ha->loop_id_map); 4475 fail_loop_id_map: 4476 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4477 fail_async_pd: 4478 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4479 fail_sf_init_cb: 4480 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4481 fail_ex_init_cb: 4482 kfree(ha->npiv_info); 4483 fail_npiv_info: 4484 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4485 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4486 (*rsp)->ring = NULL; 4487 (*rsp)->dma = 0; 4488 fail_rsp_ring: 4489 kfree(*rsp); 4490 *rsp = NULL; 4491 fail_rsp: 4492 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4493 sizeof(request_t), (*req)->ring, (*req)->dma); 4494 (*req)->ring = NULL; 4495 (*req)->dma = 0; 4496 fail_req_ring: 4497 kfree(*req); 4498 *req = NULL; 4499 fail_req: 4500 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4501 ha->ct_sns, ha->ct_sns_dma); 4502 ha->ct_sns = NULL; 4503 ha->ct_sns_dma = 0; 4504 fail_free_ms_iocb: 4505 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4506 ha->ms_iocb = NULL; 4507 ha->ms_iocb_dma = 0; 4508 4509 if (ha->sns_cmd) 4510 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4511 ha->sns_cmd, ha->sns_cmd_dma); 4512 fail_dma_pool: 4513 if (ql2xenabledif) { 4514 struct dsd_dma *dsd, *nxt; 4515 4516 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4517 list) { 4518 list_del(&dsd->list); 4519 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4520 dsd->dsd_list_dma); 4521 ha->dif_bundle_dma_allocs--; 4522 kfree(dsd); 4523 ha->dif_bundle_kallocs--; 4524 ha->pool.unusable.count--; 4525 } 4526 dma_pool_destroy(ha->dif_bundl_pool); 4527 ha->dif_bundl_pool = NULL; 4528 } 4529 4530 fail_dif_bundl_dma_pool: 4531 if (IS_QLA82XX(ha) || ql2xenabledif) { 4532 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4533 ha->fcp_cmnd_dma_pool = NULL; 4534 } 4535 fail_dl_dma_pool: 4536 if (IS_QLA82XX(ha) || ql2xenabledif) { 4537 dma_pool_destroy(ha->dl_dma_pool); 4538 ha->dl_dma_pool = NULL; 4539 } 4540 fail_s_dma_pool: 4541 dma_pool_destroy(ha->s_dma_pool); 4542 ha->s_dma_pool = NULL; 4543 fail_free_nvram: 4544 kfree(ha->nvram); 4545 ha->nvram = NULL; 4546 fail_free_ctx_mempool: 4547 mempool_destroy(ha->ctx_mempool); 4548 ha->ctx_mempool = NULL; 4549 fail_free_srb_mempool: 4550 mempool_destroy(ha->srb_mempool); 4551 ha->srb_mempool = NULL; 4552 fail_free_gid_list: 4553 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4554 ha->gid_list, 4555 ha->gid_list_dma); 4556 ha->gid_list = NULL; 4557 ha->gid_list_dma = 0; 4558 fail_free_tgt_mem: 4559 qlt_mem_free(ha); 4560 fail_free_btree: 4561 btree_destroy32(&ha->host_map); 4562 fail_free_init_cb: 4563 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4564 ha->init_cb_dma); 4565 ha->init_cb = NULL; 4566 ha->init_cb_dma = 0; 4567 fail_free_vp_map: 4568 kfree(ha->vp_map); 4569 fail: 4570 ql_log(ql_log_fatal, NULL, 0x0030, 4571 "Memory allocation failure.\n"); 4572 return -ENOMEM; 4573 } 4574 4575 int 4576 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4577 { 4578 int rval; 4579 uint16_t size, max_cnt; 4580 uint32_t temp; 4581 struct qla_hw_data *ha = vha->hw; 4582 4583 /* Return if we don't need to alloacate any extended logins */ 4584 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4585 return QLA_SUCCESS; 4586 4587 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4588 return QLA_SUCCESS; 4589 4590 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4591 max_cnt = 0; 4592 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4593 if (rval != QLA_SUCCESS) { 4594 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4595 "Failed to get exlogin status.\n"); 4596 return rval; 4597 } 4598 4599 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4600 temp *= size; 4601 4602 if (temp != ha->exlogin_size) { 4603 qla2x00_free_exlogin_buffer(ha); 4604 ha->exlogin_size = temp; 4605 4606 ql_log(ql_log_info, vha, 0xd024, 4607 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4608 max_cnt, size, temp); 4609 4610 ql_log(ql_log_info, vha, 0xd025, 4611 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4612 4613 /* Get consistent memory for extended logins */ 4614 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4615 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4616 if (!ha->exlogin_buf) { 4617 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4618 "Failed to allocate memory for exlogin_buf_dma.\n"); 4619 return -ENOMEM; 4620 } 4621 } 4622 4623 /* Now configure the dma buffer */ 4624 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4625 if (rval) { 4626 ql_log(ql_log_fatal, vha, 0xd033, 4627 "Setup extended login buffer ****FAILED****.\n"); 4628 qla2x00_free_exlogin_buffer(ha); 4629 } 4630 4631 return rval; 4632 } 4633 4634 /* 4635 * qla2x00_free_exlogin_buffer 4636 * 4637 * Input: 4638 * ha = adapter block pointer 4639 */ 4640 void 4641 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4642 { 4643 if (ha->exlogin_buf) { 4644 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4645 ha->exlogin_buf, ha->exlogin_buf_dma); 4646 ha->exlogin_buf = NULL; 4647 ha->exlogin_size = 0; 4648 } 4649 } 4650 4651 static void 4652 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4653 { 4654 u32 temp; 4655 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4656 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4657 4658 if (max_cnt > vha->hw->max_exchg) 4659 max_cnt = vha->hw->max_exchg; 4660 4661 if (qla_ini_mode_enabled(vha)) { 4662 if (vha->ql2xiniexchg > max_cnt) 4663 vha->ql2xiniexchg = max_cnt; 4664 4665 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4666 *ret_cnt = vha->ql2xiniexchg; 4667 4668 } else if (qla_tgt_mode_enabled(vha)) { 4669 if (vha->ql2xexchoffld > max_cnt) { 4670 vha->ql2xexchoffld = max_cnt; 4671 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4672 } 4673 4674 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4675 *ret_cnt = vha->ql2xexchoffld; 4676 } else if (qla_dual_mode_enabled(vha)) { 4677 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4678 if (temp > max_cnt) { 4679 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4680 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4681 temp = max_cnt; 4682 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4683 } 4684 4685 if (temp > FW_DEF_EXCHANGES_CNT) 4686 *ret_cnt = temp; 4687 } 4688 } 4689 4690 int 4691 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4692 { 4693 int rval; 4694 u16 size, max_cnt; 4695 u32 actual_cnt, totsz; 4696 struct qla_hw_data *ha = vha->hw; 4697 4698 if (!ha->flags.exchoffld_enabled) 4699 return QLA_SUCCESS; 4700 4701 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4702 return QLA_SUCCESS; 4703 4704 max_cnt = 0; 4705 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4706 if (rval != QLA_SUCCESS) { 4707 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4708 "Failed to get exlogin status.\n"); 4709 return rval; 4710 } 4711 4712 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4713 ql_log(ql_log_info, vha, 0xd014, 4714 "Actual exchange offload count: %d.\n", actual_cnt); 4715 4716 totsz = actual_cnt * size; 4717 4718 if (totsz != ha->exchoffld_size) { 4719 qla2x00_free_exchoffld_buffer(ha); 4720 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4721 ha->exchoffld_size = 0; 4722 ha->flags.exchoffld_enabled = 0; 4723 return QLA_SUCCESS; 4724 } 4725 4726 ha->exchoffld_size = totsz; 4727 4728 ql_log(ql_log_info, vha, 0xd016, 4729 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4730 max_cnt, actual_cnt, size, totsz); 4731 4732 ql_log(ql_log_info, vha, 0xd017, 4733 "Exchange Buffers requested size = 0x%x\n", 4734 ha->exchoffld_size); 4735 4736 /* Get consistent memory for extended logins */ 4737 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4738 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4739 if (!ha->exchoffld_buf) { 4740 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4741 "Failed to allocate memory for Exchange Offload.\n"); 4742 4743 if (ha->max_exchg > 4744 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4745 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4746 } else if (ha->max_exchg > 4747 (FW_DEF_EXCHANGES_CNT + 512)) { 4748 ha->max_exchg -= 512; 4749 } else { 4750 ha->flags.exchoffld_enabled = 0; 4751 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4752 "Disabling Exchange offload due to lack of memory\n"); 4753 } 4754 ha->exchoffld_size = 0; 4755 4756 return -ENOMEM; 4757 } 4758 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4759 /* pathological case */ 4760 qla2x00_free_exchoffld_buffer(ha); 4761 ha->exchoffld_size = 0; 4762 ha->flags.exchoffld_enabled = 0; 4763 ql_log(ql_log_info, vha, 0xd016, 4764 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4765 ha->exchoffld_size, actual_cnt, size, totsz); 4766 return 0; 4767 } 4768 4769 /* Now configure the dma buffer */ 4770 rval = qla_set_exchoffld_mem_cfg(vha); 4771 if (rval) { 4772 ql_log(ql_log_fatal, vha, 0xd02e, 4773 "Setup exchange offload buffer ****FAILED****.\n"); 4774 qla2x00_free_exchoffld_buffer(ha); 4775 } else { 4776 /* re-adjust number of target exchange */ 4777 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4778 4779 if (qla_ini_mode_enabled(vha)) 4780 icb->exchange_count = 0; 4781 else 4782 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4783 } 4784 4785 return rval; 4786 } 4787 4788 /* 4789 * qla2x00_free_exchoffld_buffer 4790 * 4791 * Input: 4792 * ha = adapter block pointer 4793 */ 4794 void 4795 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4796 { 4797 if (ha->exchoffld_buf) { 4798 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4799 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4800 ha->exchoffld_buf = NULL; 4801 ha->exchoffld_size = 0; 4802 } 4803 } 4804 4805 /* 4806 * qla2x00_free_fw_dump 4807 * Frees fw dump stuff. 4808 * 4809 * Input: 4810 * ha = adapter block pointer 4811 */ 4812 static void 4813 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4814 { 4815 struct fwdt *fwdt = ha->fwdt; 4816 uint j; 4817 4818 if (ha->fce) 4819 dma_free_coherent(&ha->pdev->dev, 4820 FCE_SIZE, ha->fce, ha->fce_dma); 4821 4822 if (ha->eft) 4823 dma_free_coherent(&ha->pdev->dev, 4824 EFT_SIZE, ha->eft, ha->eft_dma); 4825 4826 vfree(ha->fw_dump); 4827 4828 ha->fce = NULL; 4829 ha->fce_dma = 0; 4830 ha->flags.fce_enabled = 0; 4831 ha->eft = NULL; 4832 ha->eft_dma = 0; 4833 ha->fw_dumped = false; 4834 ha->fw_dump_cap_flags = 0; 4835 ha->fw_dump_reading = 0; 4836 ha->fw_dump = NULL; 4837 ha->fw_dump_len = 0; 4838 4839 for (j = 0; j < 2; j++, fwdt++) { 4840 vfree(fwdt->template); 4841 fwdt->template = NULL; 4842 fwdt->length = 0; 4843 } 4844 } 4845 4846 /* 4847 * qla2x00_mem_free 4848 * Frees all adapter allocated memory. 4849 * 4850 * Input: 4851 * ha = adapter block pointer. 4852 */ 4853 static void 4854 qla2x00_mem_free(struct qla_hw_data *ha) 4855 { 4856 qla2x00_free_fw_dump(ha); 4857 4858 if (ha->mctp_dump) 4859 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4860 ha->mctp_dump_dma); 4861 ha->mctp_dump = NULL; 4862 4863 mempool_destroy(ha->srb_mempool); 4864 ha->srb_mempool = NULL; 4865 4866 if (ha->dcbx_tlv) 4867 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4868 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4869 ha->dcbx_tlv = NULL; 4870 4871 if (ha->xgmac_data) 4872 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4873 ha->xgmac_data, ha->xgmac_data_dma); 4874 ha->xgmac_data = NULL; 4875 4876 if (ha->sns_cmd) 4877 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4878 ha->sns_cmd, ha->sns_cmd_dma); 4879 ha->sns_cmd = NULL; 4880 ha->sns_cmd_dma = 0; 4881 4882 if (ha->ct_sns) 4883 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4884 ha->ct_sns, ha->ct_sns_dma); 4885 ha->ct_sns = NULL; 4886 ha->ct_sns_dma = 0; 4887 4888 if (ha->sfp_data) 4889 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4890 ha->sfp_data_dma); 4891 ha->sfp_data = NULL; 4892 4893 if (ha->flt) 4894 dma_free_coherent(&ha->pdev->dev, 4895 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4896 ha->flt, ha->flt_dma); 4897 ha->flt = NULL; 4898 ha->flt_dma = 0; 4899 4900 if (ha->ms_iocb) 4901 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4902 ha->ms_iocb = NULL; 4903 ha->ms_iocb_dma = 0; 4904 4905 if (ha->sf_init_cb) 4906 dma_pool_free(ha->s_dma_pool, 4907 ha->sf_init_cb, ha->sf_init_cb_dma); 4908 4909 if (ha->ex_init_cb) 4910 dma_pool_free(ha->s_dma_pool, 4911 ha->ex_init_cb, ha->ex_init_cb_dma); 4912 ha->ex_init_cb = NULL; 4913 ha->ex_init_cb_dma = 0; 4914 4915 if (ha->async_pd) 4916 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4917 ha->async_pd = NULL; 4918 ha->async_pd_dma = 0; 4919 4920 dma_pool_destroy(ha->s_dma_pool); 4921 ha->s_dma_pool = NULL; 4922 4923 if (ha->gid_list) 4924 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4925 ha->gid_list, ha->gid_list_dma); 4926 ha->gid_list = NULL; 4927 ha->gid_list_dma = 0; 4928 4929 if (IS_QLA82XX(ha)) { 4930 if (!list_empty(&ha->gbl_dsd_list)) { 4931 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4932 4933 /* clean up allocated prev pool */ 4934 list_for_each_entry_safe(dsd_ptr, 4935 tdsd_ptr, &ha->gbl_dsd_list, list) { 4936 dma_pool_free(ha->dl_dma_pool, 4937 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4938 list_del(&dsd_ptr->list); 4939 kfree(dsd_ptr); 4940 } 4941 } 4942 } 4943 4944 dma_pool_destroy(ha->dl_dma_pool); 4945 ha->dl_dma_pool = NULL; 4946 4947 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4948 ha->fcp_cmnd_dma_pool = NULL; 4949 4950 mempool_destroy(ha->ctx_mempool); 4951 ha->ctx_mempool = NULL; 4952 4953 if (ql2xenabledif && ha->dif_bundl_pool) { 4954 struct dsd_dma *dsd, *nxt; 4955 4956 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4957 list) { 4958 list_del(&dsd->list); 4959 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4960 dsd->dsd_list_dma); 4961 ha->dif_bundle_dma_allocs--; 4962 kfree(dsd); 4963 ha->dif_bundle_kallocs--; 4964 ha->pool.unusable.count--; 4965 } 4966 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4967 list_del(&dsd->list); 4968 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4969 dsd->dsd_list_dma); 4970 ha->dif_bundle_dma_allocs--; 4971 kfree(dsd); 4972 ha->dif_bundle_kallocs--; 4973 } 4974 } 4975 4976 dma_pool_destroy(ha->dif_bundl_pool); 4977 ha->dif_bundl_pool = NULL; 4978 4979 qlt_mem_free(ha); 4980 qla_remove_hostmap(ha); 4981 4982 if (ha->init_cb) 4983 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4984 ha->init_cb, ha->init_cb_dma); 4985 4986 dma_pool_destroy(ha->purex_dma_pool); 4987 ha->purex_dma_pool = NULL; 4988 4989 if (ha->elsrej.c) { 4990 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4991 ha->elsrej.c, ha->elsrej.cdma); 4992 ha->elsrej.c = NULL; 4993 } 4994 4995 ha->init_cb = NULL; 4996 ha->init_cb_dma = 0; 4997 4998 vfree(ha->optrom_buffer); 4999 ha->optrom_buffer = NULL; 5000 kfree(ha->nvram); 5001 ha->nvram = NULL; 5002 kfree(ha->npiv_info); 5003 ha->npiv_info = NULL; 5004 kfree(ha->swl); 5005 ha->swl = NULL; 5006 kfree(ha->loop_id_map); 5007 ha->sf_init_cb = NULL; 5008 ha->sf_init_cb_dma = 0; 5009 ha->loop_id_map = NULL; 5010 5011 kfree(ha->vp_map); 5012 ha->vp_map = NULL; 5013 } 5014 5015 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 5016 struct qla_hw_data *ha) 5017 { 5018 struct Scsi_Host *host; 5019 struct scsi_qla_host *vha = NULL; 5020 5021 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5022 if (!host) { 5023 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5024 "Failed to allocate host from the scsi layer, aborting.\n"); 5025 return NULL; 5026 } 5027 5028 /* Clear our data area */ 5029 vha = shost_priv(host); 5030 memset(vha, 0, sizeof(scsi_qla_host_t)); 5031 5032 vha->host = host; 5033 vha->host_no = host->host_no; 5034 vha->hw = ha; 5035 5036 vha->qlini_mode = ql2x_ini_mode; 5037 vha->ql2xexchoffld = ql2xexchoffld; 5038 vha->ql2xiniexchg = ql2xiniexchg; 5039 5040 INIT_LIST_HEAD(&vha->vp_fcports); 5041 INIT_LIST_HEAD(&vha->work_list); 5042 INIT_LIST_HEAD(&vha->list); 5043 INIT_LIST_HEAD(&vha->qla_cmd_list); 5044 INIT_LIST_HEAD(&vha->logo_list); 5045 INIT_LIST_HEAD(&vha->plogi_ack_list); 5046 INIT_LIST_HEAD(&vha->qp_list); 5047 INIT_LIST_HEAD(&vha->gnl.fcports); 5048 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5049 5050 INIT_LIST_HEAD(&vha->purex_list.head); 5051 spin_lock_init(&vha->purex_list.lock); 5052 5053 spin_lock_init(&vha->work_lock); 5054 spin_lock_init(&vha->cmd_list_lock); 5055 init_waitqueue_head(&vha->fcport_waitQ); 5056 init_waitqueue_head(&vha->vref_waitq); 5057 qla_enode_init(vha); 5058 qla_edb_init(vha); 5059 5060 5061 vha->gnl.size = sizeof(struct get_name_list_extended) * 5062 (ha->max_loop_id + 1); 5063 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5064 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5065 if (!vha->gnl.l) { 5066 ql_log(ql_log_fatal, vha, 0xd04a, 5067 "Alloc failed for name list.\n"); 5068 scsi_host_put(vha->host); 5069 return NULL; 5070 } 5071 5072 /* todo: what about ext login? */ 5073 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5074 vha->scan.l = vmalloc(vha->scan.size); 5075 if (!vha->scan.l) { 5076 ql_log(ql_log_fatal, vha, 0xd04a, 5077 "Alloc failed for scan database.\n"); 5078 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5079 vha->gnl.l, vha->gnl.ldma); 5080 vha->gnl.l = NULL; 5081 scsi_host_put(vha->host); 5082 return NULL; 5083 } 5084 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5085 5086 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5087 ql_dbg(ql_dbg_init, vha, 0x0041, 5088 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5089 vha->host, vha->hw, vha, 5090 dev_name(&(ha->pdev->dev))); 5091 5092 return vha; 5093 } 5094 5095 struct qla_work_evt * 5096 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5097 { 5098 struct qla_work_evt *e; 5099 5100 if (test_bit(UNLOADING, &vha->dpc_flags)) 5101 return NULL; 5102 5103 if (qla_vha_mark_busy(vha)) 5104 return NULL; 5105 5106 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5107 if (!e) { 5108 QLA_VHA_MARK_NOT_BUSY(vha); 5109 return NULL; 5110 } 5111 5112 INIT_LIST_HEAD(&e->list); 5113 e->type = type; 5114 e->flags = QLA_EVT_FLAG_FREE; 5115 return e; 5116 } 5117 5118 int 5119 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5120 { 5121 unsigned long flags; 5122 bool q = false; 5123 5124 spin_lock_irqsave(&vha->work_lock, flags); 5125 list_add_tail(&e->list, &vha->work_list); 5126 5127 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5128 q = true; 5129 5130 spin_unlock_irqrestore(&vha->work_lock, flags); 5131 5132 if (q) 5133 queue_work(vha->hw->wq, &vha->iocb_work); 5134 5135 return QLA_SUCCESS; 5136 } 5137 5138 int 5139 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5140 u32 data) 5141 { 5142 struct qla_work_evt *e; 5143 5144 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5145 if (!e) 5146 return QLA_FUNCTION_FAILED; 5147 5148 e->u.aen.code = code; 5149 e->u.aen.data = data; 5150 return qla2x00_post_work(vha, e); 5151 } 5152 5153 int 5154 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5155 { 5156 struct qla_work_evt *e; 5157 5158 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5159 if (!e) 5160 return QLA_FUNCTION_FAILED; 5161 5162 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5163 return qla2x00_post_work(vha, e); 5164 } 5165 5166 #define qla2x00_post_async_work(name, type) \ 5167 int qla2x00_post_async_##name##_work( \ 5168 struct scsi_qla_host *vha, \ 5169 fc_port_t *fcport, uint16_t *data) \ 5170 { \ 5171 struct qla_work_evt *e; \ 5172 \ 5173 e = qla2x00_alloc_work(vha, type); \ 5174 if (!e) \ 5175 return QLA_FUNCTION_FAILED; \ 5176 \ 5177 e->u.logio.fcport = fcport; \ 5178 if (data) { \ 5179 e->u.logio.data[0] = data[0]; \ 5180 e->u.logio.data[1] = data[1]; \ 5181 } \ 5182 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5183 return qla2x00_post_work(vha, e); \ 5184 } 5185 5186 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5187 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5188 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5189 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5190 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5191 5192 int 5193 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5194 { 5195 struct qla_work_evt *e; 5196 5197 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5198 if (!e) 5199 return QLA_FUNCTION_FAILED; 5200 5201 e->u.uevent.code = code; 5202 return qla2x00_post_work(vha, e); 5203 } 5204 5205 static void 5206 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5207 { 5208 char event_string[40]; 5209 char *envp[] = { event_string, NULL }; 5210 5211 switch (code) { 5212 case QLA_UEVENT_CODE_FW_DUMP: 5213 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5214 vha->host_no); 5215 break; 5216 default: 5217 /* do nothing */ 5218 break; 5219 } 5220 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5221 } 5222 5223 int 5224 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5225 uint32_t *data, int cnt) 5226 { 5227 struct qla_work_evt *e; 5228 5229 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5230 if (!e) 5231 return QLA_FUNCTION_FAILED; 5232 5233 e->u.aenfx.evtcode = evtcode; 5234 e->u.aenfx.count = cnt; 5235 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5236 return qla2x00_post_work(vha, e); 5237 } 5238 5239 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5240 { 5241 unsigned long flags; 5242 5243 if (IS_SW_RESV_ADDR(fcport->d_id)) 5244 return; 5245 5246 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5247 if (fcport->disc_state == DSC_UPD_FCPORT) { 5248 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5249 return; 5250 } 5251 fcport->jiffies_at_registration = jiffies; 5252 fcport->sec_since_registration = 0; 5253 fcport->next_disc_state = DSC_DELETED; 5254 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5255 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5256 5257 queue_work(system_unbound_wq, &fcport->reg_work); 5258 } 5259 5260 static 5261 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5262 { 5263 unsigned long flags; 5264 fc_port_t *fcport = NULL, *tfcp; 5265 struct qlt_plogi_ack_t *pla = 5266 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5267 uint8_t free_fcport = 0; 5268 5269 ql_dbg(ql_dbg_disc, vha, 0xffff, 5270 "%s %d %8phC enter\n", 5271 __func__, __LINE__, e->u.new_sess.port_name); 5272 5273 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5274 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5275 if (fcport) { 5276 fcport->d_id = e->u.new_sess.id; 5277 if (pla) { 5278 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5279 memcpy(fcport->node_name, 5280 pla->iocb.u.isp24.u.plogi.node_name, 5281 WWN_SIZE); 5282 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5283 /* we took an extra ref_count to prevent PLOGI ACK when 5284 * fcport/sess has not been created. 5285 */ 5286 pla->ref_count--; 5287 } 5288 } else { 5289 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5290 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5291 if (fcport) { 5292 fcport->d_id = e->u.new_sess.id; 5293 fcport->flags |= FCF_FABRIC_DEVICE; 5294 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5295 fcport->tgt_short_link_down_cnt = 0; 5296 5297 memcpy(fcport->port_name, e->u.new_sess.port_name, 5298 WWN_SIZE); 5299 5300 fcport->fc4_type = e->u.new_sess.fc4_type; 5301 if (NVME_PRIORITY(vha->hw, fcport)) 5302 fcport->do_prli_nvme = 1; 5303 else 5304 fcport->do_prli_nvme = 0; 5305 5306 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5307 fcport->dm_login_expire = jiffies + 5308 QLA_N2N_WAIT_TIME * HZ; 5309 fcport->fc4_type = FS_FC4TYPE_FCP; 5310 fcport->n2n_flag = 1; 5311 if (vha->flags.nvme_enabled) 5312 fcport->fc4_type |= FS_FC4TYPE_NVME; 5313 } 5314 5315 } else { 5316 ql_dbg(ql_dbg_disc, vha, 0xffff, 5317 "%s %8phC mem alloc fail.\n", 5318 __func__, e->u.new_sess.port_name); 5319 5320 if (pla) { 5321 list_del(&pla->list); 5322 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5323 } 5324 return; 5325 } 5326 5327 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5328 /* search again to make sure no one else got ahead */ 5329 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5330 e->u.new_sess.port_name, 1); 5331 if (tfcp) { 5332 /* should rarily happen */ 5333 ql_dbg(ql_dbg_disc, vha, 0xffff, 5334 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5335 __func__, tfcp->port_name, tfcp->disc_state, 5336 tfcp->fw_login_state); 5337 5338 free_fcport = 1; 5339 } else { 5340 list_add_tail(&fcport->list, &vha->vp_fcports); 5341 5342 } 5343 if (pla) { 5344 qlt_plogi_ack_link(vha, pla, fcport, 5345 QLT_PLOGI_LINK_SAME_WWN); 5346 pla->ref_count--; 5347 } 5348 } 5349 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5350 5351 if (fcport) { 5352 fcport->id_changed = 1; 5353 fcport->scan_state = QLA_FCPORT_FOUND; 5354 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5355 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5356 5357 if (pla) { 5358 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5359 u16 wd3_lo; 5360 5361 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5362 fcport->local = 0; 5363 fcport->loop_id = 5364 le16_to_cpu( 5365 pla->iocb.u.isp24.nport_handle); 5366 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5367 wd3_lo = 5368 le16_to_cpu( 5369 pla->iocb.u.isp24.u.prli.wd3_lo); 5370 5371 if (wd3_lo & BIT_7) 5372 fcport->conf_compl_supported = 1; 5373 5374 if ((wd3_lo & BIT_4) == 0) 5375 fcport->port_type = FCT_INITIATOR; 5376 else 5377 fcport->port_type = FCT_TARGET; 5378 } 5379 qlt_plogi_ack_unref(vha, pla); 5380 } else { 5381 fc_port_t *dfcp = NULL; 5382 5383 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5384 tfcp = qla2x00_find_fcport_by_nportid(vha, 5385 &e->u.new_sess.id, 1); 5386 if (tfcp && (tfcp != fcport)) { 5387 /* 5388 * We have a conflict fcport with same NportID. 5389 */ 5390 ql_dbg(ql_dbg_disc, vha, 0xffff, 5391 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5392 __func__, tfcp->port_name, tfcp->disc_state, 5393 tfcp->fw_login_state); 5394 5395 switch (tfcp->disc_state) { 5396 case DSC_DELETED: 5397 break; 5398 case DSC_DELETE_PEND: 5399 fcport->login_pause = 1; 5400 tfcp->conflict = fcport; 5401 break; 5402 default: 5403 fcport->login_pause = 1; 5404 tfcp->conflict = fcport; 5405 dfcp = tfcp; 5406 break; 5407 } 5408 } 5409 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5410 if (dfcp) 5411 qlt_schedule_sess_for_deletion(tfcp); 5412 5413 if (N2N_TOPO(vha->hw)) { 5414 fcport->flags &= ~FCF_FABRIC_DEVICE; 5415 fcport->keep_nport_handle = 1; 5416 if (vha->flags.nvme_enabled) { 5417 fcport->fc4_type = 5418 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5419 fcport->n2n_flag = 1; 5420 } 5421 fcport->fw_login_state = 0; 5422 5423 schedule_delayed_work(&vha->scan.scan_work, 5); 5424 } else { 5425 qla24xx_fcport_handle_login(vha, fcport); 5426 } 5427 } 5428 } 5429 5430 if (free_fcport) { 5431 qla2x00_free_fcport(fcport); 5432 if (pla) { 5433 list_del(&pla->list); 5434 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5435 } 5436 } 5437 } 5438 5439 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5440 { 5441 struct srb *sp = e->u.iosb.sp; 5442 int rval; 5443 5444 rval = qla2x00_start_sp(sp); 5445 if (rval != QLA_SUCCESS) { 5446 ql_dbg(ql_dbg_disc, vha, 0x2043, 5447 "%s: %s: Re-issue IOCB failed (%d).\n", 5448 __func__, sp->name, rval); 5449 qla24xx_sp_unmap(vha, sp); 5450 } 5451 } 5452 5453 void 5454 qla2x00_do_work(struct scsi_qla_host *vha) 5455 { 5456 struct qla_work_evt *e, *tmp; 5457 unsigned long flags; 5458 LIST_HEAD(work); 5459 int rc; 5460 5461 spin_lock_irqsave(&vha->work_lock, flags); 5462 list_splice_init(&vha->work_list, &work); 5463 spin_unlock_irqrestore(&vha->work_lock, flags); 5464 5465 list_for_each_entry_safe(e, tmp, &work, list) { 5466 rc = QLA_SUCCESS; 5467 switch (e->type) { 5468 case QLA_EVT_AEN: 5469 fc_host_post_event(vha->host, fc_get_event_number(), 5470 e->u.aen.code, e->u.aen.data); 5471 break; 5472 case QLA_EVT_IDC_ACK: 5473 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5474 break; 5475 case QLA_EVT_ASYNC_LOGIN: 5476 qla2x00_async_login(vha, e->u.logio.fcport, 5477 e->u.logio.data); 5478 break; 5479 case QLA_EVT_ASYNC_LOGOUT: 5480 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5481 break; 5482 case QLA_EVT_ASYNC_ADISC: 5483 qla2x00_async_adisc(vha, e->u.logio.fcport, 5484 e->u.logio.data); 5485 break; 5486 case QLA_EVT_UEVENT: 5487 qla2x00_uevent_emit(vha, e->u.uevent.code); 5488 break; 5489 case QLA_EVT_AENFX: 5490 qlafx00_process_aen(vha, e); 5491 break; 5492 case QLA_EVT_UNMAP: 5493 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5494 break; 5495 case QLA_EVT_RELOGIN: 5496 qla2x00_relogin(vha); 5497 break; 5498 case QLA_EVT_NEW_SESS: 5499 qla24xx_create_new_sess(vha, e); 5500 break; 5501 case QLA_EVT_GPDB: 5502 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5503 e->u.fcport.opt); 5504 break; 5505 case QLA_EVT_PRLI: 5506 qla24xx_async_prli(vha, e->u.fcport.fcport); 5507 break; 5508 case QLA_EVT_GPSC: 5509 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5510 break; 5511 case QLA_EVT_GNL: 5512 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5513 break; 5514 case QLA_EVT_NACK: 5515 qla24xx_do_nack_work(vha, e); 5516 break; 5517 case QLA_EVT_ASYNC_PRLO: 5518 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5519 break; 5520 case QLA_EVT_ASYNC_PRLO_DONE: 5521 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5522 e->u.logio.data); 5523 break; 5524 case QLA_EVT_GPNFT: 5525 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5526 e->u.gpnft.sp); 5527 break; 5528 case QLA_EVT_GPNFT_DONE: 5529 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5530 break; 5531 case QLA_EVT_GNNFT_DONE: 5532 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5533 break; 5534 case QLA_EVT_GFPNID: 5535 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5536 break; 5537 case QLA_EVT_SP_RETRY: 5538 qla_sp_retry(vha, e); 5539 break; 5540 case QLA_EVT_IIDMA: 5541 qla_do_iidma_work(vha, e->u.fcport.fcport); 5542 break; 5543 case QLA_EVT_ELS_PLOGI: 5544 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5545 e->u.fcport.fcport, false); 5546 break; 5547 case QLA_EVT_SA_REPLACE: 5548 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5549 break; 5550 } 5551 5552 if (rc == EAGAIN) { 5553 /* put 'work' at head of 'vha->work_list' */ 5554 spin_lock_irqsave(&vha->work_lock, flags); 5555 list_splice(&work, &vha->work_list); 5556 spin_unlock_irqrestore(&vha->work_lock, flags); 5557 break; 5558 } 5559 list_del_init(&e->list); 5560 if (e->flags & QLA_EVT_FLAG_FREE) 5561 kfree(e); 5562 5563 /* For each work completed decrement vha ref count */ 5564 QLA_VHA_MARK_NOT_BUSY(vha); 5565 } 5566 } 5567 5568 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5569 { 5570 struct qla_work_evt *e; 5571 5572 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5573 5574 if (!e) { 5575 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5576 return QLA_FUNCTION_FAILED; 5577 } 5578 5579 return qla2x00_post_work(vha, e); 5580 } 5581 5582 /* Relogins all the fcports of a vport 5583 * Context: dpc thread 5584 */ 5585 void qla2x00_relogin(struct scsi_qla_host *vha) 5586 { 5587 fc_port_t *fcport; 5588 int status, relogin_needed = 0; 5589 struct event_arg ea; 5590 5591 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5592 /* 5593 * If the port is not ONLINE then try to login 5594 * to it if we haven't run out of retries. 5595 */ 5596 if (atomic_read(&fcport->state) != FCS_ONLINE && 5597 fcport->login_retry) { 5598 if (fcport->scan_state != QLA_FCPORT_FOUND || 5599 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5600 fcport->disc_state == DSC_LOGIN_COMPLETE) 5601 continue; 5602 5603 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5604 fcport->disc_state == DSC_DELETE_PEND) { 5605 relogin_needed = 1; 5606 } else { 5607 if (vha->hw->current_topology != ISP_CFG_NL) { 5608 memset(&ea, 0, sizeof(ea)); 5609 ea.fcport = fcport; 5610 qla24xx_handle_relogin_event(vha, &ea); 5611 } else if (vha->hw->current_topology == 5612 ISP_CFG_NL && 5613 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5614 (void)qla24xx_fcport_handle_login(vha, 5615 fcport); 5616 } else if (vha->hw->current_topology == 5617 ISP_CFG_NL) { 5618 fcport->login_retry--; 5619 status = 5620 qla2x00_local_device_login(vha, 5621 fcport); 5622 if (status == QLA_SUCCESS) { 5623 fcport->old_loop_id = 5624 fcport->loop_id; 5625 ql_dbg(ql_dbg_disc, vha, 0x2003, 5626 "Port login OK: logged in ID 0x%x.\n", 5627 fcport->loop_id); 5628 qla2x00_update_fcport 5629 (vha, fcport); 5630 } else if (status == 1) { 5631 set_bit(RELOGIN_NEEDED, 5632 &vha->dpc_flags); 5633 /* retry the login again */ 5634 ql_dbg(ql_dbg_disc, vha, 0x2007, 5635 "Retrying %d login again loop_id 0x%x.\n", 5636 fcport->login_retry, 5637 fcport->loop_id); 5638 } else { 5639 fcport->login_retry = 0; 5640 } 5641 5642 if (fcport->login_retry == 0 && 5643 status != QLA_SUCCESS) 5644 qla2x00_clear_loop_id(fcport); 5645 } 5646 } 5647 } 5648 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5649 break; 5650 } 5651 5652 if (relogin_needed) 5653 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5654 5655 ql_dbg(ql_dbg_disc, vha, 0x400e, 5656 "Relogin end.\n"); 5657 } 5658 5659 /* Schedule work on any of the dpc-workqueues */ 5660 void 5661 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5662 { 5663 struct qla_hw_data *ha = base_vha->hw; 5664 5665 switch (work_code) { 5666 case MBA_IDC_AEN: /* 0x8200 */ 5667 if (ha->dpc_lp_wq) 5668 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5669 break; 5670 5671 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5672 if (!ha->flags.nic_core_reset_hdlr_active) { 5673 if (ha->dpc_hp_wq) 5674 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5675 } else 5676 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5677 "NIC Core reset is already active. Skip " 5678 "scheduling it again.\n"); 5679 break; 5680 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5681 if (ha->dpc_hp_wq) 5682 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5683 break; 5684 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5685 if (ha->dpc_hp_wq) 5686 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5687 break; 5688 default: 5689 ql_log(ql_log_warn, base_vha, 0xb05f, 5690 "Unknown work-code=0x%x.\n", work_code); 5691 } 5692 5693 return; 5694 } 5695 5696 /* Work: Perform NIC Core Unrecoverable state handling */ 5697 void 5698 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5699 { 5700 struct qla_hw_data *ha = 5701 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5702 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5703 uint32_t dev_state = 0; 5704 5705 qla83xx_idc_lock(base_vha, 0); 5706 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5707 qla83xx_reset_ownership(base_vha); 5708 if (ha->flags.nic_core_reset_owner) { 5709 ha->flags.nic_core_reset_owner = 0; 5710 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5711 QLA8XXX_DEV_FAILED); 5712 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5713 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5714 } 5715 qla83xx_idc_unlock(base_vha, 0); 5716 } 5717 5718 /* Work: Execute IDC state handler */ 5719 void 5720 qla83xx_idc_state_handler_work(struct work_struct *work) 5721 { 5722 struct qla_hw_data *ha = 5723 container_of(work, struct qla_hw_data, idc_state_handler); 5724 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5725 uint32_t dev_state = 0; 5726 5727 qla83xx_idc_lock(base_vha, 0); 5728 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5729 if (dev_state == QLA8XXX_DEV_FAILED || 5730 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5731 qla83xx_idc_state_handler(base_vha); 5732 qla83xx_idc_unlock(base_vha, 0); 5733 } 5734 5735 static int 5736 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5737 { 5738 int rval = QLA_SUCCESS; 5739 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5740 uint32_t heart_beat_counter1, heart_beat_counter2; 5741 5742 do { 5743 if (time_after(jiffies, heart_beat_wait)) { 5744 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5745 "Nic Core f/w is not alive.\n"); 5746 rval = QLA_FUNCTION_FAILED; 5747 break; 5748 } 5749 5750 qla83xx_idc_lock(base_vha, 0); 5751 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5752 &heart_beat_counter1); 5753 qla83xx_idc_unlock(base_vha, 0); 5754 msleep(100); 5755 qla83xx_idc_lock(base_vha, 0); 5756 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5757 &heart_beat_counter2); 5758 qla83xx_idc_unlock(base_vha, 0); 5759 } while (heart_beat_counter1 == heart_beat_counter2); 5760 5761 return rval; 5762 } 5763 5764 /* Work: Perform NIC Core Reset handling */ 5765 void 5766 qla83xx_nic_core_reset_work(struct work_struct *work) 5767 { 5768 struct qla_hw_data *ha = 5769 container_of(work, struct qla_hw_data, nic_core_reset); 5770 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5771 uint32_t dev_state = 0; 5772 5773 if (IS_QLA2031(ha)) { 5774 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5775 ql_log(ql_log_warn, base_vha, 0xb081, 5776 "Failed to dump mctp\n"); 5777 return; 5778 } 5779 5780 if (!ha->flags.nic_core_reset_hdlr_active) { 5781 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5782 qla83xx_idc_lock(base_vha, 0); 5783 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5784 &dev_state); 5785 qla83xx_idc_unlock(base_vha, 0); 5786 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5787 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5788 "Nic Core f/w is alive.\n"); 5789 return; 5790 } 5791 } 5792 5793 ha->flags.nic_core_reset_hdlr_active = 1; 5794 if (qla83xx_nic_core_reset(base_vha)) { 5795 /* NIC Core reset failed. */ 5796 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5797 "NIC Core reset failed.\n"); 5798 } 5799 ha->flags.nic_core_reset_hdlr_active = 0; 5800 } 5801 } 5802 5803 /* Work: Handle 8200 IDC aens */ 5804 void 5805 qla83xx_service_idc_aen(struct work_struct *work) 5806 { 5807 struct qla_hw_data *ha = 5808 container_of(work, struct qla_hw_data, idc_aen); 5809 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5810 uint32_t dev_state, idc_control; 5811 5812 qla83xx_idc_lock(base_vha, 0); 5813 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5814 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5815 qla83xx_idc_unlock(base_vha, 0); 5816 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5817 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5818 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5819 "Application requested NIC Core Reset.\n"); 5820 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5821 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5822 QLA_SUCCESS) { 5823 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5824 "Other protocol driver requested NIC Core Reset.\n"); 5825 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5826 } 5827 } else if (dev_state == QLA8XXX_DEV_FAILED || 5828 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5829 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5830 } 5831 } 5832 5833 /* 5834 * Control the frequency of IDC lock retries 5835 */ 5836 #define QLA83XX_WAIT_LOGIC_MS 100 5837 5838 static int 5839 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5840 { 5841 int rval; 5842 uint32_t data; 5843 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5844 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5845 struct qla_hw_data *ha = base_vha->hw; 5846 5847 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5848 "Trying force recovery of the IDC lock.\n"); 5849 5850 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5851 if (rval) 5852 return rval; 5853 5854 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5855 return QLA_SUCCESS; 5856 } else { 5857 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5858 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5859 data); 5860 if (rval) 5861 return rval; 5862 5863 msleep(200); 5864 5865 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5866 &data); 5867 if (rval) 5868 return rval; 5869 5870 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5871 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5872 ~(idc_lck_rcvry_stage_mask)); 5873 rval = qla83xx_wr_reg(base_vha, 5874 QLA83XX_IDC_LOCK_RECOVERY, data); 5875 if (rval) 5876 return rval; 5877 5878 /* Forcefully perform IDC UnLock */ 5879 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5880 &data); 5881 if (rval) 5882 return rval; 5883 /* Clear lock-id by setting 0xff */ 5884 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5885 0xff); 5886 if (rval) 5887 return rval; 5888 /* Clear lock-recovery by setting 0x0 */ 5889 rval = qla83xx_wr_reg(base_vha, 5890 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5891 if (rval) 5892 return rval; 5893 } else 5894 return QLA_SUCCESS; 5895 } 5896 5897 return rval; 5898 } 5899 5900 static int 5901 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5902 { 5903 int rval = QLA_SUCCESS; 5904 uint32_t o_drv_lockid, n_drv_lockid; 5905 unsigned long lock_recovery_timeout; 5906 5907 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5908 retry_lockid: 5909 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5910 if (rval) 5911 goto exit; 5912 5913 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5914 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5915 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5916 return QLA_SUCCESS; 5917 else 5918 return QLA_FUNCTION_FAILED; 5919 } 5920 5921 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5922 if (rval) 5923 goto exit; 5924 5925 if (o_drv_lockid == n_drv_lockid) { 5926 msleep(QLA83XX_WAIT_LOGIC_MS); 5927 goto retry_lockid; 5928 } else 5929 return QLA_SUCCESS; 5930 5931 exit: 5932 return rval; 5933 } 5934 5935 /* 5936 * Context: task, can sleep 5937 */ 5938 void 5939 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5940 { 5941 uint32_t data; 5942 uint32_t lock_owner; 5943 struct qla_hw_data *ha = base_vha->hw; 5944 5945 might_sleep(); 5946 5947 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5948 retry_lock: 5949 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5950 == QLA_SUCCESS) { 5951 if (data) { 5952 /* Setting lock-id to our function-number */ 5953 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5954 ha->portnum); 5955 } else { 5956 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5957 &lock_owner); 5958 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5959 "Failed to acquire IDC lock, acquired by %d, " 5960 "retrying...\n", lock_owner); 5961 5962 /* Retry/Perform IDC-Lock recovery */ 5963 if (qla83xx_idc_lock_recovery(base_vha) 5964 == QLA_SUCCESS) { 5965 msleep(QLA83XX_WAIT_LOGIC_MS); 5966 goto retry_lock; 5967 } else 5968 ql_log(ql_log_warn, base_vha, 0xb075, 5969 "IDC Lock recovery FAILED.\n"); 5970 } 5971 5972 } 5973 5974 return; 5975 } 5976 5977 static bool 5978 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5979 struct purex_entry_24xx *purex) 5980 { 5981 char fwstr[16]; 5982 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5983 struct port_database_24xx *pdb; 5984 5985 /* Domain Controller is always logged-out. */ 5986 /* if RDP request is not from Domain Controller: */ 5987 if (sid != 0xfffc01) 5988 return false; 5989 5990 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5991 5992 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5993 if (!pdb) { 5994 ql_dbg(ql_dbg_init, vha, 0x0181, 5995 "%s: Failed allocate pdb\n", __func__); 5996 } else if (qla24xx_get_port_database(vha, 5997 le16_to_cpu(purex->nport_handle), pdb)) { 5998 ql_dbg(ql_dbg_init, vha, 0x0181, 5999 "%s: Failed get pdb sid=%x\n", __func__, sid); 6000 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6001 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6002 ql_dbg(ql_dbg_init, vha, 0x0181, 6003 "%s: Port not logged in sid=%#x\n", __func__, sid); 6004 } else { 6005 /* RDP request is from logged in port */ 6006 kfree(pdb); 6007 return false; 6008 } 6009 kfree(pdb); 6010 6011 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6012 fwstr[strcspn(fwstr, " ")] = 0; 6013 /* if FW version allows RDP response length upto 2048 bytes: */ 6014 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6015 return false; 6016 6017 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6018 6019 /* RDP response length is to be reduced to maximum 256 bytes */ 6020 return true; 6021 } 6022 6023 /* 6024 * Function Name: qla24xx_process_purex_iocb 6025 * 6026 * Description: 6027 * Prepare a RDP response and send to Fabric switch 6028 * 6029 * PARAMETERS: 6030 * vha: SCSI qla host 6031 * purex: RDP request received by HBA 6032 */ 6033 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6034 struct purex_item *item) 6035 { 6036 struct qla_hw_data *ha = vha->hw; 6037 struct purex_entry_24xx *purex = 6038 (struct purex_entry_24xx *)&item->iocb; 6039 dma_addr_t rsp_els_dma; 6040 dma_addr_t rsp_payload_dma; 6041 dma_addr_t stat_dma; 6042 dma_addr_t sfp_dma; 6043 struct els_entry_24xx *rsp_els = NULL; 6044 struct rdp_rsp_payload *rsp_payload = NULL; 6045 struct link_statistics *stat = NULL; 6046 uint8_t *sfp = NULL; 6047 uint16_t sfp_flags = 0; 6048 uint rsp_payload_length = sizeof(*rsp_payload); 6049 int rval; 6050 6051 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6052 "%s: Enter\n", __func__); 6053 6054 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6055 "-------- ELS REQ -------\n"); 6056 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6057 purex, sizeof(*purex)); 6058 6059 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6060 rsp_payload_length = 6061 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6062 ql_dbg(ql_dbg_init, vha, 0x0181, 6063 "Reducing RSP payload length to %u bytes...\n", 6064 rsp_payload_length); 6065 } 6066 6067 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6068 &rsp_els_dma, GFP_KERNEL); 6069 if (!rsp_els) { 6070 ql_log(ql_log_warn, vha, 0x0183, 6071 "Failed allocate dma buffer ELS RSP.\n"); 6072 goto dealloc; 6073 } 6074 6075 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6076 &rsp_payload_dma, GFP_KERNEL); 6077 if (!rsp_payload) { 6078 ql_log(ql_log_warn, vha, 0x0184, 6079 "Failed allocate dma buffer ELS RSP payload.\n"); 6080 goto dealloc; 6081 } 6082 6083 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6084 &sfp_dma, GFP_KERNEL); 6085 6086 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6087 &stat_dma, GFP_KERNEL); 6088 6089 /* Prepare Response IOCB */ 6090 rsp_els->entry_type = ELS_IOCB_TYPE; 6091 rsp_els->entry_count = 1; 6092 rsp_els->sys_define = 0; 6093 rsp_els->entry_status = 0; 6094 rsp_els->handle = 0; 6095 rsp_els->nport_handle = purex->nport_handle; 6096 rsp_els->tx_dsd_count = cpu_to_le16(1); 6097 rsp_els->vp_index = purex->vp_idx; 6098 rsp_els->sof_type = EST_SOFI3; 6099 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6100 rsp_els->rx_dsd_count = 0; 6101 rsp_els->opcode = purex->els_frame_payload[0]; 6102 6103 rsp_els->d_id[0] = purex->s_id[0]; 6104 rsp_els->d_id[1] = purex->s_id[1]; 6105 rsp_els->d_id[2] = purex->s_id[2]; 6106 6107 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6108 rsp_els->rx_byte_count = 0; 6109 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6110 6111 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6112 rsp_els->tx_len = rsp_els->tx_byte_count; 6113 6114 rsp_els->rx_address = 0; 6115 rsp_els->rx_len = 0; 6116 6117 /* Prepare Response Payload */ 6118 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6119 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6120 sizeof(rsp_payload->hdr)); 6121 6122 /* Link service Request Info Descriptor */ 6123 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6124 rsp_payload->ls_req_info_desc.desc_len = 6125 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6126 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6127 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6128 6129 /* Link service Request Info Descriptor 2 */ 6130 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6131 rsp_payload->ls_req_info_desc2.desc_len = 6132 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6133 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6134 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6135 6136 6137 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6138 rsp_payload->sfp_diag_desc.desc_len = 6139 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6140 6141 if (sfp) { 6142 /* SFP Flags */ 6143 memset(sfp, 0, SFP_RTDI_LEN); 6144 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6145 if (!rval) { 6146 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6147 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6148 sfp_flags |= BIT_0; /* short wave */ 6149 else if (sfp[0] & BIT_1) 6150 sfp_flags |= BIT_1; /* long wave 1310nm */ 6151 else if (sfp[1] & BIT_4) 6152 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6153 } 6154 6155 /* SFP Type */ 6156 memset(sfp, 0, SFP_RTDI_LEN); 6157 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6158 if (!rval) { 6159 sfp_flags |= BIT_4; /* optical */ 6160 if (sfp[0] == 0x3) 6161 sfp_flags |= BIT_6; /* sfp+ */ 6162 } 6163 6164 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6165 6166 /* SFP Diagnostics */ 6167 memset(sfp, 0, SFP_RTDI_LEN); 6168 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6169 if (!rval) { 6170 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6171 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6172 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6173 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6174 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6175 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6176 } 6177 } 6178 6179 /* Port Speed Descriptor */ 6180 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6181 rsp_payload->port_speed_desc.desc_len = 6182 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6183 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6184 qla25xx_fdmi_port_speed_capability(ha)); 6185 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6186 qla25xx_fdmi_port_speed_currently(ha)); 6187 6188 /* Link Error Status Descriptor */ 6189 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6190 rsp_payload->ls_err_desc.desc_len = 6191 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6192 6193 if (stat) { 6194 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6195 if (!rval) { 6196 rsp_payload->ls_err_desc.link_fail_cnt = 6197 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6198 rsp_payload->ls_err_desc.loss_sync_cnt = 6199 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6200 rsp_payload->ls_err_desc.loss_sig_cnt = 6201 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6202 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6203 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6204 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6205 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6206 rsp_payload->ls_err_desc.inval_crc_cnt = 6207 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6208 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6209 } 6210 } 6211 6212 /* Portname Descriptor */ 6213 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6214 rsp_payload->port_name_diag_desc.desc_len = 6215 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6216 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6217 vha->node_name, 6218 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6219 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6220 vha->port_name, 6221 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6222 6223 /* F-Port Portname Descriptor */ 6224 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6225 rsp_payload->port_name_direct_desc.desc_len = 6226 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6227 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6228 vha->fabric_node_name, 6229 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6230 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6231 vha->fabric_port_name, 6232 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6233 6234 /* Bufer Credit Descriptor */ 6235 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6236 rsp_payload->buffer_credit_desc.desc_len = 6237 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6238 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6239 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6240 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6241 6242 if (ha->flags.plogi_template_valid) { 6243 uint32_t tmp = 6244 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6245 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6246 } 6247 6248 if (rsp_payload_length < sizeof(*rsp_payload)) 6249 goto send; 6250 6251 /* Optical Element Descriptor, Temperature */ 6252 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6253 rsp_payload->optical_elmt_desc[0].desc_len = 6254 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6255 /* Optical Element Descriptor, Voltage */ 6256 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6257 rsp_payload->optical_elmt_desc[1].desc_len = 6258 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6259 /* Optical Element Descriptor, Tx Bias Current */ 6260 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6261 rsp_payload->optical_elmt_desc[2].desc_len = 6262 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6263 /* Optical Element Descriptor, Tx Power */ 6264 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6265 rsp_payload->optical_elmt_desc[3].desc_len = 6266 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6267 /* Optical Element Descriptor, Rx Power */ 6268 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6269 rsp_payload->optical_elmt_desc[4].desc_len = 6270 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6271 6272 if (sfp) { 6273 memset(sfp, 0, SFP_RTDI_LEN); 6274 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6275 if (!rval) { 6276 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6277 6278 /* Optical Element Descriptor, Temperature */ 6279 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6280 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6281 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6282 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6283 rsp_payload->optical_elmt_desc[0].element_flags = 6284 cpu_to_be32(1 << 28); 6285 6286 /* Optical Element Descriptor, Voltage */ 6287 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6288 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6289 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6290 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6291 rsp_payload->optical_elmt_desc[1].element_flags = 6292 cpu_to_be32(2 << 28); 6293 6294 /* Optical Element Descriptor, Tx Bias Current */ 6295 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6296 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6297 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6298 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6299 rsp_payload->optical_elmt_desc[2].element_flags = 6300 cpu_to_be32(3 << 28); 6301 6302 /* Optical Element Descriptor, Tx Power */ 6303 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6304 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6305 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6306 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6307 rsp_payload->optical_elmt_desc[3].element_flags = 6308 cpu_to_be32(4 << 28); 6309 6310 /* Optical Element Descriptor, Rx Power */ 6311 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6312 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6313 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6314 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6315 rsp_payload->optical_elmt_desc[4].element_flags = 6316 cpu_to_be32(5 << 28); 6317 } 6318 6319 memset(sfp, 0, SFP_RTDI_LEN); 6320 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6321 if (!rval) { 6322 /* Temperature high/low alarm/warning */ 6323 rsp_payload->optical_elmt_desc[0].element_flags |= 6324 cpu_to_be32( 6325 (sfp[0] >> 7 & 1) << 3 | 6326 (sfp[0] >> 6 & 1) << 2 | 6327 (sfp[4] >> 7 & 1) << 1 | 6328 (sfp[4] >> 6 & 1) << 0); 6329 6330 /* Voltage high/low alarm/warning */ 6331 rsp_payload->optical_elmt_desc[1].element_flags |= 6332 cpu_to_be32( 6333 (sfp[0] >> 5 & 1) << 3 | 6334 (sfp[0] >> 4 & 1) << 2 | 6335 (sfp[4] >> 5 & 1) << 1 | 6336 (sfp[4] >> 4 & 1) << 0); 6337 6338 /* Tx Bias Current high/low alarm/warning */ 6339 rsp_payload->optical_elmt_desc[2].element_flags |= 6340 cpu_to_be32( 6341 (sfp[0] >> 3 & 1) << 3 | 6342 (sfp[0] >> 2 & 1) << 2 | 6343 (sfp[4] >> 3 & 1) << 1 | 6344 (sfp[4] >> 2 & 1) << 0); 6345 6346 /* Tx Power high/low alarm/warning */ 6347 rsp_payload->optical_elmt_desc[3].element_flags |= 6348 cpu_to_be32( 6349 (sfp[0] >> 1 & 1) << 3 | 6350 (sfp[0] >> 0 & 1) << 2 | 6351 (sfp[4] >> 1 & 1) << 1 | 6352 (sfp[4] >> 0 & 1) << 0); 6353 6354 /* Rx Power high/low alarm/warning */ 6355 rsp_payload->optical_elmt_desc[4].element_flags |= 6356 cpu_to_be32( 6357 (sfp[1] >> 7 & 1) << 3 | 6358 (sfp[1] >> 6 & 1) << 2 | 6359 (sfp[5] >> 7 & 1) << 1 | 6360 (sfp[5] >> 6 & 1) << 0); 6361 } 6362 } 6363 6364 /* Optical Product Data Descriptor */ 6365 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6366 rsp_payload->optical_prod_desc.desc_len = 6367 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6368 6369 if (sfp) { 6370 memset(sfp, 0, SFP_RTDI_LEN); 6371 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6372 if (!rval) { 6373 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6374 sfp + 0, 6375 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6376 memcpy(rsp_payload->optical_prod_desc.part_number, 6377 sfp + 20, 6378 sizeof(rsp_payload->optical_prod_desc.part_number)); 6379 memcpy(rsp_payload->optical_prod_desc.revision, 6380 sfp + 36, 6381 sizeof(rsp_payload->optical_prod_desc.revision)); 6382 memcpy(rsp_payload->optical_prod_desc.serial_number, 6383 sfp + 48, 6384 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6385 } 6386 6387 memset(sfp, 0, SFP_RTDI_LEN); 6388 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6389 if (!rval) { 6390 memcpy(rsp_payload->optical_prod_desc.date, 6391 sfp + 0, 6392 sizeof(rsp_payload->optical_prod_desc.date)); 6393 } 6394 } 6395 6396 send: 6397 ql_dbg(ql_dbg_init, vha, 0x0183, 6398 "Sending ELS Response to RDP Request...\n"); 6399 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6400 "-------- ELS RSP -------\n"); 6401 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6402 rsp_els, sizeof(*rsp_els)); 6403 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6404 "-------- ELS RSP PAYLOAD -------\n"); 6405 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6406 rsp_payload, rsp_payload_length); 6407 6408 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6409 6410 if (rval) { 6411 ql_log(ql_log_warn, vha, 0x0188, 6412 "%s: iocb failed to execute -> %x\n", __func__, rval); 6413 } else if (rsp_els->comp_status) { 6414 ql_log(ql_log_warn, vha, 0x0189, 6415 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6416 __func__, rsp_els->comp_status, 6417 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6418 } else { 6419 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6420 } 6421 6422 dealloc: 6423 if (stat) 6424 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6425 stat, stat_dma); 6426 if (sfp) 6427 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6428 sfp, sfp_dma); 6429 if (rsp_payload) 6430 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6431 rsp_payload, rsp_payload_dma); 6432 if (rsp_els) 6433 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6434 rsp_els, rsp_els_dma); 6435 } 6436 6437 void 6438 qla24xx_free_purex_item(struct purex_item *item) 6439 { 6440 if (item == &item->vha->default_item) 6441 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6442 else 6443 kfree(item); 6444 } 6445 6446 void qla24xx_process_purex_list(struct purex_list *list) 6447 { 6448 struct list_head head = LIST_HEAD_INIT(head); 6449 struct purex_item *item, *next; 6450 ulong flags; 6451 6452 spin_lock_irqsave(&list->lock, flags); 6453 list_splice_init(&list->head, &head); 6454 spin_unlock_irqrestore(&list->lock, flags); 6455 6456 list_for_each_entry_safe(item, next, &head, list) { 6457 list_del(&item->list); 6458 item->process_item(item->vha, item); 6459 qla24xx_free_purex_item(item); 6460 } 6461 } 6462 6463 /* 6464 * Context: task, can sleep 6465 */ 6466 void 6467 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6468 { 6469 #if 0 6470 uint16_t options = (requester_id << 15) | BIT_7; 6471 #endif 6472 uint16_t retry; 6473 uint32_t data; 6474 struct qla_hw_data *ha = base_vha->hw; 6475 6476 might_sleep(); 6477 6478 /* IDC-unlock implementation using driver-unlock/lock-id 6479 * remote registers 6480 */ 6481 retry = 0; 6482 retry_unlock: 6483 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6484 == QLA_SUCCESS) { 6485 if (data == ha->portnum) { 6486 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6487 /* Clearing lock-id by setting 0xff */ 6488 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6489 } else if (retry < 10) { 6490 /* SV: XXX: IDC unlock retrying needed here? */ 6491 6492 /* Retry for IDC-unlock */ 6493 msleep(QLA83XX_WAIT_LOGIC_MS); 6494 retry++; 6495 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6496 "Failed to release IDC lock, retrying=%d\n", retry); 6497 goto retry_unlock; 6498 } 6499 } else if (retry < 10) { 6500 /* Retry for IDC-unlock */ 6501 msleep(QLA83XX_WAIT_LOGIC_MS); 6502 retry++; 6503 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6504 "Failed to read drv-lockid, retrying=%d\n", retry); 6505 goto retry_unlock; 6506 } 6507 6508 return; 6509 6510 #if 0 6511 /* XXX: IDC-unlock implementation using access-control mbx */ 6512 retry = 0; 6513 retry_unlock2: 6514 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6515 if (retry < 10) { 6516 /* Retry for IDC-unlock */ 6517 msleep(QLA83XX_WAIT_LOGIC_MS); 6518 retry++; 6519 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6520 "Failed to release IDC lock, retrying=%d\n", retry); 6521 goto retry_unlock2; 6522 } 6523 } 6524 6525 return; 6526 #endif 6527 } 6528 6529 int 6530 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6531 { 6532 int rval = QLA_SUCCESS; 6533 struct qla_hw_data *ha = vha->hw; 6534 uint32_t drv_presence; 6535 6536 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6537 if (rval == QLA_SUCCESS) { 6538 drv_presence |= (1 << ha->portnum); 6539 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6540 drv_presence); 6541 } 6542 6543 return rval; 6544 } 6545 6546 int 6547 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6548 { 6549 int rval = QLA_SUCCESS; 6550 6551 qla83xx_idc_lock(vha, 0); 6552 rval = __qla83xx_set_drv_presence(vha); 6553 qla83xx_idc_unlock(vha, 0); 6554 6555 return rval; 6556 } 6557 6558 int 6559 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6560 { 6561 int rval = QLA_SUCCESS; 6562 struct qla_hw_data *ha = vha->hw; 6563 uint32_t drv_presence; 6564 6565 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6566 if (rval == QLA_SUCCESS) { 6567 drv_presence &= ~(1 << ha->portnum); 6568 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6569 drv_presence); 6570 } 6571 6572 return rval; 6573 } 6574 6575 int 6576 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6577 { 6578 int rval = QLA_SUCCESS; 6579 6580 qla83xx_idc_lock(vha, 0); 6581 rval = __qla83xx_clear_drv_presence(vha); 6582 qla83xx_idc_unlock(vha, 0); 6583 6584 return rval; 6585 } 6586 6587 static void 6588 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6589 { 6590 struct qla_hw_data *ha = vha->hw; 6591 uint32_t drv_ack, drv_presence; 6592 unsigned long ack_timeout; 6593 6594 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6595 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6596 while (1) { 6597 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6598 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6599 if ((drv_ack & drv_presence) == drv_presence) 6600 break; 6601 6602 if (time_after_eq(jiffies, ack_timeout)) { 6603 ql_log(ql_log_warn, vha, 0xb067, 6604 "RESET ACK TIMEOUT! drv_presence=0x%x " 6605 "drv_ack=0x%x\n", drv_presence, drv_ack); 6606 /* 6607 * The function(s) which did not ack in time are forced 6608 * to withdraw any further participation in the IDC 6609 * reset. 6610 */ 6611 if (drv_ack != drv_presence) 6612 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6613 drv_ack); 6614 break; 6615 } 6616 6617 qla83xx_idc_unlock(vha, 0); 6618 msleep(1000); 6619 qla83xx_idc_lock(vha, 0); 6620 } 6621 6622 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6623 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6624 } 6625 6626 static int 6627 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6628 { 6629 int rval = QLA_SUCCESS; 6630 uint32_t idc_control; 6631 6632 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6633 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6634 6635 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6636 __qla83xx_get_idc_control(vha, &idc_control); 6637 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6638 __qla83xx_set_idc_control(vha, 0); 6639 6640 qla83xx_idc_unlock(vha, 0); 6641 rval = qla83xx_restart_nic_firmware(vha); 6642 qla83xx_idc_lock(vha, 0); 6643 6644 if (rval != QLA_SUCCESS) { 6645 ql_log(ql_log_fatal, vha, 0xb06a, 6646 "Failed to restart NIC f/w.\n"); 6647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6648 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6649 } else { 6650 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6651 "Success in restarting nic f/w.\n"); 6652 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6653 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6654 } 6655 6656 return rval; 6657 } 6658 6659 /* Assumes idc_lock always held on entry */ 6660 int 6661 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6662 { 6663 struct qla_hw_data *ha = base_vha->hw; 6664 int rval = QLA_SUCCESS; 6665 unsigned long dev_init_timeout; 6666 uint32_t dev_state; 6667 6668 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6669 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6670 6671 while (1) { 6672 6673 if (time_after_eq(jiffies, dev_init_timeout)) { 6674 ql_log(ql_log_warn, base_vha, 0xb06e, 6675 "Initialization TIMEOUT!\n"); 6676 /* Init timeout. Disable further NIC Core 6677 * communication. 6678 */ 6679 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6680 QLA8XXX_DEV_FAILED); 6681 ql_log(ql_log_info, base_vha, 0xb06f, 6682 "HW State: FAILED.\n"); 6683 } 6684 6685 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6686 switch (dev_state) { 6687 case QLA8XXX_DEV_READY: 6688 if (ha->flags.nic_core_reset_owner) 6689 qla83xx_idc_audit(base_vha, 6690 IDC_AUDIT_COMPLETION); 6691 ha->flags.nic_core_reset_owner = 0; 6692 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6693 "Reset_owner reset by 0x%x.\n", 6694 ha->portnum); 6695 goto exit; 6696 case QLA8XXX_DEV_COLD: 6697 if (ha->flags.nic_core_reset_owner) 6698 rval = qla83xx_device_bootstrap(base_vha); 6699 else { 6700 /* Wait for AEN to change device-state */ 6701 qla83xx_idc_unlock(base_vha, 0); 6702 msleep(1000); 6703 qla83xx_idc_lock(base_vha, 0); 6704 } 6705 break; 6706 case QLA8XXX_DEV_INITIALIZING: 6707 /* Wait for AEN to change device-state */ 6708 qla83xx_idc_unlock(base_vha, 0); 6709 msleep(1000); 6710 qla83xx_idc_lock(base_vha, 0); 6711 break; 6712 case QLA8XXX_DEV_NEED_RESET: 6713 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6714 qla83xx_need_reset_handler(base_vha); 6715 else { 6716 /* Wait for AEN to change device-state */ 6717 qla83xx_idc_unlock(base_vha, 0); 6718 msleep(1000); 6719 qla83xx_idc_lock(base_vha, 0); 6720 } 6721 /* reset timeout value after need reset handler */ 6722 dev_init_timeout = jiffies + 6723 (ha->fcoe_dev_init_timeout * HZ); 6724 break; 6725 case QLA8XXX_DEV_NEED_QUIESCENT: 6726 /* XXX: DEBUG for now */ 6727 qla83xx_idc_unlock(base_vha, 0); 6728 msleep(1000); 6729 qla83xx_idc_lock(base_vha, 0); 6730 break; 6731 case QLA8XXX_DEV_QUIESCENT: 6732 /* XXX: DEBUG for now */ 6733 if (ha->flags.quiesce_owner) 6734 goto exit; 6735 6736 qla83xx_idc_unlock(base_vha, 0); 6737 msleep(1000); 6738 qla83xx_idc_lock(base_vha, 0); 6739 dev_init_timeout = jiffies + 6740 (ha->fcoe_dev_init_timeout * HZ); 6741 break; 6742 case QLA8XXX_DEV_FAILED: 6743 if (ha->flags.nic_core_reset_owner) 6744 qla83xx_idc_audit(base_vha, 6745 IDC_AUDIT_COMPLETION); 6746 ha->flags.nic_core_reset_owner = 0; 6747 __qla83xx_clear_drv_presence(base_vha); 6748 qla83xx_idc_unlock(base_vha, 0); 6749 qla8xxx_dev_failed_handler(base_vha); 6750 rval = QLA_FUNCTION_FAILED; 6751 qla83xx_idc_lock(base_vha, 0); 6752 goto exit; 6753 case QLA8XXX_BAD_VALUE: 6754 qla83xx_idc_unlock(base_vha, 0); 6755 msleep(1000); 6756 qla83xx_idc_lock(base_vha, 0); 6757 break; 6758 default: 6759 ql_log(ql_log_warn, base_vha, 0xb071, 6760 "Unknown Device State: %x.\n", dev_state); 6761 qla83xx_idc_unlock(base_vha, 0); 6762 qla8xxx_dev_failed_handler(base_vha); 6763 rval = QLA_FUNCTION_FAILED; 6764 qla83xx_idc_lock(base_vha, 0); 6765 goto exit; 6766 } 6767 } 6768 6769 exit: 6770 return rval; 6771 } 6772 6773 void 6774 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6775 { 6776 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6777 board_disable); 6778 struct pci_dev *pdev = ha->pdev; 6779 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6780 6781 ql_log(ql_log_warn, base_vha, 0x015b, 6782 "Disabling adapter.\n"); 6783 6784 if (!atomic_read(&pdev->enable_cnt)) { 6785 ql_log(ql_log_info, base_vha, 0xfffc, 6786 "PCI device disabled, no action req for PCI error=%lx\n", 6787 base_vha->pci_flags); 6788 return; 6789 } 6790 6791 /* 6792 * if UNLOADING flag is already set, then continue unload, 6793 * where it was set first. 6794 */ 6795 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6796 return; 6797 6798 qla2x00_wait_for_sess_deletion(base_vha); 6799 6800 qla2x00_delete_all_vps(ha, base_vha); 6801 6802 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6803 6804 qla2x00_dfs_remove(base_vha); 6805 6806 qla84xx_put_chip(base_vha); 6807 6808 if (base_vha->timer_active) 6809 qla2x00_stop_timer(base_vha); 6810 6811 base_vha->flags.online = 0; 6812 6813 qla2x00_destroy_deferred_work(ha); 6814 6815 /* 6816 * Do not try to stop beacon blink as it will issue a mailbox 6817 * command. 6818 */ 6819 qla2x00_free_sysfs_attr(base_vha, false); 6820 6821 fc_remove_host(base_vha->host); 6822 6823 scsi_remove_host(base_vha->host); 6824 6825 base_vha->flags.init_done = 0; 6826 qla25xx_delete_queues(base_vha); 6827 qla2x00_free_fcports(base_vha); 6828 qla2x00_free_irqs(base_vha); 6829 qla2x00_mem_free(ha); 6830 qla82xx_md_free(base_vha); 6831 qla2x00_free_queues(ha); 6832 6833 qla2x00_unmap_iobases(ha); 6834 6835 pci_release_selected_regions(ha->pdev, ha->bars); 6836 pci_disable_pcie_error_reporting(pdev); 6837 pci_disable_device(pdev); 6838 6839 /* 6840 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6841 */ 6842 } 6843 6844 /************************************************************************** 6845 * qla2x00_do_dpc 6846 * This kernel thread is a task that is schedule by the interrupt handler 6847 * to perform the background processing for interrupts. 6848 * 6849 * Notes: 6850 * This task always run in the context of a kernel thread. It 6851 * is kick-off by the driver's detect code and starts up 6852 * up one per adapter. It immediately goes to sleep and waits for 6853 * some fibre event. When either the interrupt handler or 6854 * the timer routine detects a event it will one of the task 6855 * bits then wake us up. 6856 **************************************************************************/ 6857 static int 6858 qla2x00_do_dpc(void *data) 6859 { 6860 scsi_qla_host_t *base_vha; 6861 struct qla_hw_data *ha; 6862 uint32_t online; 6863 struct qla_qpair *qpair; 6864 6865 ha = (struct qla_hw_data *)data; 6866 base_vha = pci_get_drvdata(ha->pdev); 6867 6868 set_user_nice(current, MIN_NICE); 6869 6870 set_current_state(TASK_INTERRUPTIBLE); 6871 while (!kthread_should_stop()) { 6872 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6873 "DPC handler sleeping.\n"); 6874 6875 schedule(); 6876 6877 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6878 qla_pci_set_eeh_busy(base_vha); 6879 6880 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6881 goto end_loop; 6882 6883 if (ha->flags.eeh_busy) { 6884 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6885 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6886 goto end_loop; 6887 } 6888 6889 ha->dpc_active = 1; 6890 6891 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6892 "DPC handler waking up, dpc_flags=0x%lx.\n", 6893 base_vha->dpc_flags); 6894 6895 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6896 break; 6897 6898 if (IS_P3P_TYPE(ha)) { 6899 if (IS_QLA8044(ha)) { 6900 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6901 &base_vha->dpc_flags)) { 6902 qla8044_idc_lock(ha); 6903 qla8044_wr_direct(base_vha, 6904 QLA8044_CRB_DEV_STATE_INDEX, 6905 QLA8XXX_DEV_FAILED); 6906 qla8044_idc_unlock(ha); 6907 ql_log(ql_log_info, base_vha, 0x4004, 6908 "HW State: FAILED.\n"); 6909 qla8044_device_state_handler(base_vha); 6910 continue; 6911 } 6912 6913 } else { 6914 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6915 &base_vha->dpc_flags)) { 6916 qla82xx_idc_lock(ha); 6917 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6918 QLA8XXX_DEV_FAILED); 6919 qla82xx_idc_unlock(ha); 6920 ql_log(ql_log_info, base_vha, 0x0151, 6921 "HW State: FAILED.\n"); 6922 qla82xx_device_state_handler(base_vha); 6923 continue; 6924 } 6925 } 6926 6927 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6928 &base_vha->dpc_flags)) { 6929 6930 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6931 "FCoE context reset scheduled.\n"); 6932 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6933 &base_vha->dpc_flags))) { 6934 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6935 /* FCoE-ctx reset failed. 6936 * Escalate to chip-reset 6937 */ 6938 set_bit(ISP_ABORT_NEEDED, 6939 &base_vha->dpc_flags); 6940 } 6941 clear_bit(ABORT_ISP_ACTIVE, 6942 &base_vha->dpc_flags); 6943 } 6944 6945 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6946 "FCoE context reset end.\n"); 6947 } 6948 } else if (IS_QLAFX00(ha)) { 6949 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6950 &base_vha->dpc_flags)) { 6951 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6952 "Firmware Reset Recovery\n"); 6953 if (qlafx00_reset_initialize(base_vha)) { 6954 /* Failed. Abort isp later. */ 6955 if (!test_bit(UNLOADING, 6956 &base_vha->dpc_flags)) { 6957 set_bit(ISP_UNRECOVERABLE, 6958 &base_vha->dpc_flags); 6959 ql_dbg(ql_dbg_dpc, base_vha, 6960 0x4021, 6961 "Reset Recovery Failed\n"); 6962 } 6963 } 6964 } 6965 6966 if (test_and_clear_bit(FX00_TARGET_SCAN, 6967 &base_vha->dpc_flags)) { 6968 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6969 "ISPFx00 Target Scan scheduled\n"); 6970 if (qlafx00_rescan_isp(base_vha)) { 6971 if (!test_bit(UNLOADING, 6972 &base_vha->dpc_flags)) 6973 set_bit(ISP_UNRECOVERABLE, 6974 &base_vha->dpc_flags); 6975 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6976 "ISPFx00 Target Scan Failed\n"); 6977 } 6978 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6979 "ISPFx00 Target Scan End\n"); 6980 } 6981 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6982 &base_vha->dpc_flags)) { 6983 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6984 "ISPFx00 Host Info resend scheduled\n"); 6985 qlafx00_fx_disc(base_vha, 6986 &base_vha->hw->mr.fcport, 6987 FXDISC_REG_HOST_INFO); 6988 } 6989 } 6990 6991 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6992 &base_vha->dpc_flags)) { 6993 /* Semantic: 6994 * - NO-OP -- await next ISP-ABORT. Preferred method 6995 * to minimize disruptions that will occur 6996 * when a forced chip-reset occurs. 6997 * - Force -- ISP-ABORT scheduled. 6998 */ 6999 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7000 } 7001 7002 if (test_and_clear_bit 7003 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7004 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7005 bool do_reset = true; 7006 7007 switch (base_vha->qlini_mode) { 7008 case QLA2XXX_INI_MODE_ENABLED: 7009 break; 7010 case QLA2XXX_INI_MODE_DISABLED: 7011 if (!qla_tgt_mode_enabled(base_vha) && 7012 !ha->flags.fw_started) 7013 do_reset = false; 7014 break; 7015 case QLA2XXX_INI_MODE_DUAL: 7016 if (!qla_dual_mode_enabled(base_vha) && 7017 !ha->flags.fw_started) 7018 do_reset = false; 7019 break; 7020 default: 7021 break; 7022 } 7023 7024 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7025 &base_vha->dpc_flags))) { 7026 base_vha->flags.online = 1; 7027 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7028 "ISP abort scheduled.\n"); 7029 if (ha->isp_ops->abort_isp(base_vha)) { 7030 /* failed. retry later */ 7031 set_bit(ISP_ABORT_NEEDED, 7032 &base_vha->dpc_flags); 7033 } 7034 clear_bit(ABORT_ISP_ACTIVE, 7035 &base_vha->dpc_flags); 7036 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7037 "ISP abort end.\n"); 7038 } 7039 } 7040 7041 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7042 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7043 qla24xx_process_purex_list 7044 (&base_vha->purex_list); 7045 clear_bit(PROCESS_PUREX_IOCB, 7046 &base_vha->dpc_flags); 7047 } 7048 } 7049 7050 if (IS_QLAFX00(ha)) 7051 goto loop_resync_check; 7052 7053 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7054 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7055 "Quiescence mode scheduled.\n"); 7056 if (IS_P3P_TYPE(ha)) { 7057 if (IS_QLA82XX(ha)) 7058 qla82xx_device_state_handler(base_vha); 7059 if (IS_QLA8044(ha)) 7060 qla8044_device_state_handler(base_vha); 7061 clear_bit(ISP_QUIESCE_NEEDED, 7062 &base_vha->dpc_flags); 7063 if (!ha->flags.quiesce_owner) { 7064 qla2x00_perform_loop_resync(base_vha); 7065 if (IS_QLA82XX(ha)) { 7066 qla82xx_idc_lock(ha); 7067 qla82xx_clear_qsnt_ready( 7068 base_vha); 7069 qla82xx_idc_unlock(ha); 7070 } else if (IS_QLA8044(ha)) { 7071 qla8044_idc_lock(ha); 7072 qla8044_clear_qsnt_ready( 7073 base_vha); 7074 qla8044_idc_unlock(ha); 7075 } 7076 } 7077 } else { 7078 clear_bit(ISP_QUIESCE_NEEDED, 7079 &base_vha->dpc_flags); 7080 qla2x00_quiesce_io(base_vha); 7081 } 7082 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7083 "Quiescence mode end.\n"); 7084 } 7085 7086 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7087 &base_vha->dpc_flags) && 7088 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7089 7090 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7091 "Reset marker scheduled.\n"); 7092 qla2x00_rst_aen(base_vha); 7093 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7094 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7095 "Reset marker end.\n"); 7096 } 7097 7098 /* Retry each device up to login retry count */ 7099 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7100 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7101 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7102 7103 if (!base_vha->relogin_jif || 7104 time_after_eq(jiffies, base_vha->relogin_jif)) { 7105 base_vha->relogin_jif = jiffies + HZ; 7106 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7107 7108 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7109 "Relogin scheduled.\n"); 7110 qla24xx_post_relogin_work(base_vha); 7111 } 7112 } 7113 loop_resync_check: 7114 if (!qla2x00_reset_active(base_vha) && 7115 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7116 &base_vha->dpc_flags)) { 7117 /* 7118 * Allow abort_isp to complete before moving on to scanning. 7119 */ 7120 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7121 "Loop resync scheduled.\n"); 7122 7123 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7124 &base_vha->dpc_flags))) { 7125 7126 qla2x00_loop_resync(base_vha); 7127 7128 clear_bit(LOOP_RESYNC_ACTIVE, 7129 &base_vha->dpc_flags); 7130 } 7131 7132 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7133 "Loop resync end.\n"); 7134 } 7135 7136 if (IS_QLAFX00(ha)) 7137 goto intr_on_check; 7138 7139 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7140 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7141 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7142 qla2xxx_flash_npiv_conf(base_vha); 7143 } 7144 7145 intr_on_check: 7146 if (!ha->interrupts_on) 7147 ha->isp_ops->enable_intrs(ha); 7148 7149 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7150 &base_vha->dpc_flags)) { 7151 if (ha->beacon_blink_led == 1) 7152 ha->isp_ops->beacon_blink(base_vha); 7153 } 7154 7155 /* qpair online check */ 7156 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7157 &base_vha->dpc_flags)) { 7158 if (ha->flags.eeh_busy || 7159 ha->flags.pci_channel_io_perm_failure) 7160 online = 0; 7161 else 7162 online = 1; 7163 7164 mutex_lock(&ha->mq_lock); 7165 list_for_each_entry(qpair, &base_vha->qp_list, 7166 qp_list_elem) 7167 qpair->online = online; 7168 mutex_unlock(&ha->mq_lock); 7169 } 7170 7171 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7172 &base_vha->dpc_flags)) { 7173 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7174 7175 if (threshold > ha->orig_fw_xcb_count) 7176 threshold = ha->orig_fw_xcb_count; 7177 7178 ql_log(ql_log_info, base_vha, 0xffffff, 7179 "SET ZIO Activity exchange threshold to %d.\n", 7180 threshold); 7181 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7182 ql_log(ql_log_info, base_vha, 0xffffff, 7183 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7184 threshold); 7185 } 7186 } 7187 7188 if (!IS_QLAFX00(ha)) 7189 qla2x00_do_dpc_all_vps(base_vha); 7190 7191 if (test_and_clear_bit(N2N_LINK_RESET, 7192 &base_vha->dpc_flags)) { 7193 qla2x00_lip_reset(base_vha); 7194 } 7195 7196 ha->dpc_active = 0; 7197 end_loop: 7198 set_current_state(TASK_INTERRUPTIBLE); 7199 } /* End of while(1) */ 7200 __set_current_state(TASK_RUNNING); 7201 7202 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7203 "DPC handler exiting.\n"); 7204 7205 /* 7206 * Make sure that nobody tries to wake us up again. 7207 */ 7208 ha->dpc_active = 0; 7209 7210 /* Cleanup any residual CTX SRBs. */ 7211 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7212 7213 return 0; 7214 } 7215 7216 void 7217 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7218 { 7219 struct qla_hw_data *ha = vha->hw; 7220 struct task_struct *t = ha->dpc_thread; 7221 7222 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7223 wake_up_process(t); 7224 } 7225 7226 /* 7227 * qla2x00_rst_aen 7228 * Processes asynchronous reset. 7229 * 7230 * Input: 7231 * ha = adapter block pointer. 7232 */ 7233 static void 7234 qla2x00_rst_aen(scsi_qla_host_t *vha) 7235 { 7236 if (vha->flags.online && !vha->flags.reset_active && 7237 !atomic_read(&vha->loop_down_timer) && 7238 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7239 do { 7240 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7241 7242 /* 7243 * Issue marker command only when we are going to start 7244 * the I/O. 7245 */ 7246 vha->marker_needed = 1; 7247 } while (!atomic_read(&vha->loop_down_timer) && 7248 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7249 } 7250 } 7251 7252 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7253 { 7254 struct qla_hw_data *ha = vha->hw; 7255 u32 cmpl_cnt; 7256 u16 i; 7257 bool do_heartbeat = false; 7258 7259 /* 7260 * Allow do_heartbeat only if we don’t have any active interrupts, 7261 * but there are still IOs outstanding with firmware. 7262 */ 7263 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7264 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7265 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7266 do_heartbeat = true; 7267 goto skip; 7268 } 7269 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7270 7271 for (i = 0; i < ha->max_qpairs; i++) { 7272 if (ha->queue_pair_map[i]) { 7273 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7274 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7275 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7276 do_heartbeat = true; 7277 break; 7278 } 7279 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7280 } 7281 } 7282 7283 skip: 7284 return do_heartbeat; 7285 } 7286 7287 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7288 { 7289 struct qla_hw_data *ha = vha->hw; 7290 7291 if (vha->vp_idx) 7292 return; 7293 7294 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7295 return; 7296 7297 /* 7298 * dpc thread cannot run if heartbeat is running at the same time. 7299 * We also do not want to starve heartbeat task. Therefore, do 7300 * heartbeat task at least once every 5 seconds. 7301 */ 7302 if (dpc_started && 7303 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7304 return; 7305 7306 if (qla_do_heartbeat(vha)) { 7307 ha->last_heartbeat_run_jiffies = jiffies; 7308 queue_work(ha->wq, &ha->heartbeat_work); 7309 } 7310 } 7311 7312 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7313 { 7314 struct qla_hw_data *ha = vha->hw; 7315 7316 if (!ha->flags.eeh_busy) 7317 return; 7318 if (ha->pci_error_state) 7319 /* system is trying to recover */ 7320 return; 7321 7322 /* 7323 * Current system is not handling PCIE error. At this point, this is 7324 * best effort to wind down the adapter. 7325 */ 7326 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7327 !ha->flags.eeh_flush) { 7328 ql_log(ql_log_info, vha, 0x9009, 7329 "PCI Error detected, attempting to reset hardware.\n"); 7330 7331 ha->isp_ops->reset_chip(vha); 7332 ha->isp_ops->disable_intrs(ha); 7333 7334 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7335 ha->eeh_jif = jiffies; 7336 7337 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7338 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7339 pci_clear_master(ha->pdev); 7340 7341 /* flush all command */ 7342 qla2x00_abort_isp_cleanup(vha); 7343 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7344 7345 ql_log(ql_log_info, vha, 0x900a, 7346 "PCI Error handling complete, all IOs aborted.\n"); 7347 } 7348 } 7349 7350 /************************************************************************** 7351 * qla2x00_timer 7352 * 7353 * Description: 7354 * One second timer 7355 * 7356 * Context: Interrupt 7357 ***************************************************************************/ 7358 void 7359 qla2x00_timer(struct timer_list *t) 7360 { 7361 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7362 unsigned long cpu_flags = 0; 7363 int start_dpc = 0; 7364 int index; 7365 srb_t *sp; 7366 uint16_t w; 7367 struct qla_hw_data *ha = vha->hw; 7368 struct req_que *req; 7369 unsigned long flags; 7370 fc_port_t *fcport = NULL; 7371 7372 if (ha->flags.eeh_busy) { 7373 qla_wind_down_chip(vha); 7374 7375 ql_dbg(ql_dbg_timer, vha, 0x6000, 7376 "EEH = %d, restarting timer.\n", 7377 ha->flags.eeh_busy); 7378 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7379 return; 7380 } 7381 7382 /* 7383 * Hardware read to raise pending EEH errors during mailbox waits. If 7384 * the read returns -1 then disable the board. 7385 */ 7386 if (!pci_channel_offline(ha->pdev)) { 7387 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7388 qla2x00_check_reg16_for_disconnect(vha, w); 7389 } 7390 7391 /* Make sure qla82xx_watchdog is run only for physical port */ 7392 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7393 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7394 start_dpc++; 7395 if (IS_QLA82XX(ha)) 7396 qla82xx_watchdog(vha); 7397 else if (IS_QLA8044(ha)) 7398 qla8044_watchdog(vha); 7399 } 7400 7401 if (!vha->vp_idx && IS_QLAFX00(ha)) 7402 qlafx00_timer_routine(vha); 7403 7404 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7405 vha->link_down_time++; 7406 7407 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7408 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7409 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7410 fcport->tgt_link_down_time++; 7411 } 7412 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7413 7414 /* Loop down handler. */ 7415 if (atomic_read(&vha->loop_down_timer) > 0 && 7416 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7417 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7418 && vha->flags.online) { 7419 7420 if (atomic_read(&vha->loop_down_timer) == 7421 vha->loop_down_abort_time) { 7422 7423 ql_log(ql_log_info, vha, 0x6008, 7424 "Loop down - aborting the queues before time expires.\n"); 7425 7426 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7427 atomic_set(&vha->loop_state, LOOP_DEAD); 7428 7429 /* 7430 * Schedule an ISP abort to return any FCP2-device 7431 * commands. 7432 */ 7433 /* NPIV - scan physical port only */ 7434 if (!vha->vp_idx) { 7435 spin_lock_irqsave(&ha->hardware_lock, 7436 cpu_flags); 7437 req = ha->req_q_map[0]; 7438 for (index = 1; 7439 index < req->num_outstanding_cmds; 7440 index++) { 7441 fc_port_t *sfcp; 7442 7443 sp = req->outstanding_cmds[index]; 7444 if (!sp) 7445 continue; 7446 if (sp->cmd_type != TYPE_SRB) 7447 continue; 7448 if (sp->type != SRB_SCSI_CMD) 7449 continue; 7450 sfcp = sp->fcport; 7451 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7452 continue; 7453 7454 if (IS_QLA82XX(ha)) 7455 set_bit(FCOE_CTX_RESET_NEEDED, 7456 &vha->dpc_flags); 7457 else 7458 set_bit(ISP_ABORT_NEEDED, 7459 &vha->dpc_flags); 7460 break; 7461 } 7462 spin_unlock_irqrestore(&ha->hardware_lock, 7463 cpu_flags); 7464 } 7465 start_dpc++; 7466 } 7467 7468 /* if the loop has been down for 4 minutes, reinit adapter */ 7469 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7470 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7471 ql_log(ql_log_warn, vha, 0x6009, 7472 "Loop down - aborting ISP.\n"); 7473 7474 if (IS_QLA82XX(ha)) 7475 set_bit(FCOE_CTX_RESET_NEEDED, 7476 &vha->dpc_flags); 7477 else 7478 set_bit(ISP_ABORT_NEEDED, 7479 &vha->dpc_flags); 7480 } 7481 } 7482 ql_dbg(ql_dbg_timer, vha, 0x600a, 7483 "Loop down - seconds remaining %d.\n", 7484 atomic_read(&vha->loop_down_timer)); 7485 } 7486 /* Check if beacon LED needs to be blinked for physical host only */ 7487 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7488 /* There is no beacon_blink function for ISP82xx */ 7489 if (!IS_P3P_TYPE(ha)) { 7490 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7491 start_dpc++; 7492 } 7493 } 7494 7495 /* check if edif running */ 7496 if (vha->hw->flags.edif_enabled) 7497 qla_edif_timer(vha); 7498 7499 /* Process any deferred work. */ 7500 if (!list_empty(&vha->work_list)) { 7501 unsigned long flags; 7502 bool q = false; 7503 7504 spin_lock_irqsave(&vha->work_lock, flags); 7505 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7506 q = true; 7507 spin_unlock_irqrestore(&vha->work_lock, flags); 7508 if (q) 7509 queue_work(vha->hw->wq, &vha->iocb_work); 7510 } 7511 7512 /* 7513 * FC-NVME 7514 * see if the active AEN count has changed from what was last reported. 7515 */ 7516 index = atomic_read(&ha->nvme_active_aen_cnt); 7517 if (!vha->vp_idx && 7518 (index != ha->nvme_last_rptd_aen) && 7519 ha->zio_mode == QLA_ZIO_MODE_6 && 7520 !ha->flags.host_shutting_down) { 7521 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7522 ql_log(ql_log_info, vha, 0x3002, 7523 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7524 ha->nvme_last_rptd_aen); 7525 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7526 start_dpc++; 7527 } 7528 7529 if (!vha->vp_idx && 7530 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7531 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7532 ql_log(ql_log_info, vha, 0x3002, 7533 "Sched: Set ZIO exchange threshold to %d.\n", 7534 ha->last_zio_threshold); 7535 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7536 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7537 start_dpc++; 7538 } 7539 qla_adjust_buf(vha); 7540 7541 /* borrowing w to signify dpc will run */ 7542 w = 0; 7543 /* Schedule the DPC routine if needed */ 7544 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7545 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7546 start_dpc || 7547 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7548 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7549 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7550 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7551 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7552 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7553 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7554 ql_dbg(ql_dbg_timer, vha, 0x600b, 7555 "isp_abort_needed=%d loop_resync_needed=%d " 7556 "start_dpc=%d reset_marker_needed=%d", 7557 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7558 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7559 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7560 ql_dbg(ql_dbg_timer, vha, 0x600c, 7561 "beacon_blink_needed=%d isp_unrecoverable=%d " 7562 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7563 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7564 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7565 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7566 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7567 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7568 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7569 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7570 qla2xxx_wake_dpc(vha); 7571 w = 1; 7572 } 7573 7574 qla_heart_beat(vha, w); 7575 7576 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7577 } 7578 7579 /* Firmware interface routines. */ 7580 7581 #define FW_ISP21XX 0 7582 #define FW_ISP22XX 1 7583 #define FW_ISP2300 2 7584 #define FW_ISP2322 3 7585 #define FW_ISP24XX 4 7586 #define FW_ISP25XX 5 7587 #define FW_ISP81XX 6 7588 #define FW_ISP82XX 7 7589 #define FW_ISP2031 8 7590 #define FW_ISP8031 9 7591 #define FW_ISP27XX 10 7592 #define FW_ISP28XX 11 7593 7594 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7595 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7596 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7597 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7598 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7599 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7600 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7601 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7602 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7603 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7604 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7605 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7606 7607 7608 static DEFINE_MUTEX(qla_fw_lock); 7609 7610 static struct fw_blob qla_fw_blobs[] = { 7611 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7612 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7613 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7614 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7615 { .name = FW_FILE_ISP24XX, }, 7616 { .name = FW_FILE_ISP25XX, }, 7617 { .name = FW_FILE_ISP81XX, }, 7618 { .name = FW_FILE_ISP82XX, }, 7619 { .name = FW_FILE_ISP2031, }, 7620 { .name = FW_FILE_ISP8031, }, 7621 { .name = FW_FILE_ISP27XX, }, 7622 { .name = FW_FILE_ISP28XX, }, 7623 { .name = NULL, }, 7624 }; 7625 7626 struct fw_blob * 7627 qla2x00_request_firmware(scsi_qla_host_t *vha) 7628 { 7629 struct qla_hw_data *ha = vha->hw; 7630 struct fw_blob *blob; 7631 7632 if (IS_QLA2100(ha)) { 7633 blob = &qla_fw_blobs[FW_ISP21XX]; 7634 } else if (IS_QLA2200(ha)) { 7635 blob = &qla_fw_blobs[FW_ISP22XX]; 7636 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7637 blob = &qla_fw_blobs[FW_ISP2300]; 7638 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7639 blob = &qla_fw_blobs[FW_ISP2322]; 7640 } else if (IS_QLA24XX_TYPE(ha)) { 7641 blob = &qla_fw_blobs[FW_ISP24XX]; 7642 } else if (IS_QLA25XX(ha)) { 7643 blob = &qla_fw_blobs[FW_ISP25XX]; 7644 } else if (IS_QLA81XX(ha)) { 7645 blob = &qla_fw_blobs[FW_ISP81XX]; 7646 } else if (IS_QLA82XX(ha)) { 7647 blob = &qla_fw_blobs[FW_ISP82XX]; 7648 } else if (IS_QLA2031(ha)) { 7649 blob = &qla_fw_blobs[FW_ISP2031]; 7650 } else if (IS_QLA8031(ha)) { 7651 blob = &qla_fw_blobs[FW_ISP8031]; 7652 } else if (IS_QLA27XX(ha)) { 7653 blob = &qla_fw_blobs[FW_ISP27XX]; 7654 } else if (IS_QLA28XX(ha)) { 7655 blob = &qla_fw_blobs[FW_ISP28XX]; 7656 } else { 7657 return NULL; 7658 } 7659 7660 if (!blob->name) 7661 return NULL; 7662 7663 mutex_lock(&qla_fw_lock); 7664 if (blob->fw) 7665 goto out; 7666 7667 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7668 ql_log(ql_log_warn, vha, 0x0063, 7669 "Failed to load firmware image (%s).\n", blob->name); 7670 blob->fw = NULL; 7671 blob = NULL; 7672 } 7673 7674 out: 7675 mutex_unlock(&qla_fw_lock); 7676 return blob; 7677 } 7678 7679 static void 7680 qla2x00_release_firmware(void) 7681 { 7682 struct fw_blob *blob; 7683 7684 mutex_lock(&qla_fw_lock); 7685 for (blob = qla_fw_blobs; blob->name; blob++) 7686 release_firmware(blob->fw); 7687 mutex_unlock(&qla_fw_lock); 7688 } 7689 7690 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7691 { 7692 struct qla_hw_data *ha = vha->hw; 7693 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7694 struct qla_qpair *qpair = NULL; 7695 struct scsi_qla_host *vp, *tvp; 7696 fc_port_t *fcport; 7697 int i; 7698 unsigned long flags; 7699 7700 ql_dbg(ql_dbg_aer, vha, 0x9000, 7701 "%s\n", __func__); 7702 ha->chip_reset++; 7703 7704 ha->base_qpair->chip_reset = ha->chip_reset; 7705 for (i = 0; i < ha->max_qpairs; i++) { 7706 if (ha->queue_pair_map[i]) 7707 ha->queue_pair_map[i]->chip_reset = 7708 ha->base_qpair->chip_reset; 7709 } 7710 7711 /* 7712 * purge mailbox might take a while. Slot Reset/chip reset 7713 * will take care of the purge 7714 */ 7715 7716 mutex_lock(&ha->mq_lock); 7717 ha->base_qpair->online = 0; 7718 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7719 qpair->online = 0; 7720 wmb(); 7721 mutex_unlock(&ha->mq_lock); 7722 7723 qla2x00_mark_all_devices_lost(vha); 7724 7725 spin_lock_irqsave(&ha->vport_slock, flags); 7726 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7727 atomic_inc(&vp->vref_count); 7728 spin_unlock_irqrestore(&ha->vport_slock, flags); 7729 qla2x00_mark_all_devices_lost(vp); 7730 spin_lock_irqsave(&ha->vport_slock, flags); 7731 atomic_dec(&vp->vref_count); 7732 } 7733 spin_unlock_irqrestore(&ha->vport_slock, flags); 7734 7735 /* Clear all async request states across all VPs. */ 7736 list_for_each_entry(fcport, &vha->vp_fcports, list) 7737 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7738 7739 spin_lock_irqsave(&ha->vport_slock, flags); 7740 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7741 atomic_inc(&vp->vref_count); 7742 spin_unlock_irqrestore(&ha->vport_slock, flags); 7743 list_for_each_entry(fcport, &vp->vp_fcports, list) 7744 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7745 spin_lock_irqsave(&ha->vport_slock, flags); 7746 atomic_dec(&vp->vref_count); 7747 } 7748 spin_unlock_irqrestore(&ha->vport_slock, flags); 7749 } 7750 7751 7752 static pci_ers_result_t 7753 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7754 { 7755 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7756 struct qla_hw_data *ha = vha->hw; 7757 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7758 7759 ql_log(ql_log_warn, vha, 0x9000, 7760 "PCI error detected, state %x.\n", state); 7761 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7762 7763 if (!atomic_read(&pdev->enable_cnt)) { 7764 ql_log(ql_log_info, vha, 0xffff, 7765 "PCI device is disabled,state %x\n", state); 7766 ret = PCI_ERS_RESULT_NEED_RESET; 7767 goto out; 7768 } 7769 7770 switch (state) { 7771 case pci_channel_io_normal: 7772 qla_pci_set_eeh_busy(vha); 7773 if (ql2xmqsupport || ql2xnvmeenable) { 7774 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7775 qla2xxx_wake_dpc(vha); 7776 } 7777 ret = PCI_ERS_RESULT_CAN_RECOVER; 7778 break; 7779 case pci_channel_io_frozen: 7780 qla_pci_set_eeh_busy(vha); 7781 ret = PCI_ERS_RESULT_NEED_RESET; 7782 break; 7783 case pci_channel_io_perm_failure: 7784 ha->flags.pci_channel_io_perm_failure = 1; 7785 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7786 if (ql2xmqsupport || ql2xnvmeenable) { 7787 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7788 qla2xxx_wake_dpc(vha); 7789 } 7790 ret = PCI_ERS_RESULT_DISCONNECT; 7791 } 7792 out: 7793 ql_dbg(ql_dbg_aer, vha, 0x600d, 7794 "PCI error detected returning [%x].\n", ret); 7795 return ret; 7796 } 7797 7798 static pci_ers_result_t 7799 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7800 { 7801 int risc_paused = 0; 7802 uint32_t stat; 7803 unsigned long flags; 7804 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7805 struct qla_hw_data *ha = base_vha->hw; 7806 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7807 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7808 7809 ql_log(ql_log_warn, base_vha, 0x9000, 7810 "mmio enabled\n"); 7811 7812 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7813 7814 if (IS_QLA82XX(ha)) 7815 return PCI_ERS_RESULT_RECOVERED; 7816 7817 if (qla2x00_isp_reg_stat(ha)) { 7818 ql_log(ql_log_info, base_vha, 0x803f, 7819 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7820 goto out; 7821 } 7822 7823 spin_lock_irqsave(&ha->hardware_lock, flags); 7824 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7825 stat = rd_reg_word(®->hccr); 7826 if (stat & HCCR_RISC_PAUSE) 7827 risc_paused = 1; 7828 } else if (IS_QLA23XX(ha)) { 7829 stat = rd_reg_dword(®->u.isp2300.host_status); 7830 if (stat & HSR_RISC_PAUSED) 7831 risc_paused = 1; 7832 } else if (IS_FWI2_CAPABLE(ha)) { 7833 stat = rd_reg_dword(®24->host_status); 7834 if (stat & HSRX_RISC_PAUSED) 7835 risc_paused = 1; 7836 } 7837 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7838 7839 if (risc_paused) { 7840 ql_log(ql_log_info, base_vha, 0x9003, 7841 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7842 qla2xxx_dump_fw(base_vha); 7843 } 7844 out: 7845 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7846 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7847 "mmio enabled returning.\n"); 7848 return PCI_ERS_RESULT_NEED_RESET; 7849 } 7850 7851 static pci_ers_result_t 7852 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7853 { 7854 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7855 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7856 struct qla_hw_data *ha = base_vha->hw; 7857 int rc; 7858 struct qla_qpair *qpair = NULL; 7859 7860 ql_log(ql_log_warn, base_vha, 0x9004, 7861 "Slot Reset.\n"); 7862 7863 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7864 /* Workaround: qla2xxx driver which access hardware earlier 7865 * needs error state to be pci_channel_io_online. 7866 * Otherwise mailbox command timesout. 7867 */ 7868 pdev->error_state = pci_channel_io_normal; 7869 7870 pci_restore_state(pdev); 7871 7872 /* pci_restore_state() clears the saved_state flag of the device 7873 * save restored state which resets saved_state flag 7874 */ 7875 pci_save_state(pdev); 7876 7877 if (ha->mem_only) 7878 rc = pci_enable_device_mem(pdev); 7879 else 7880 rc = pci_enable_device(pdev); 7881 7882 if (rc) { 7883 ql_log(ql_log_warn, base_vha, 0x9005, 7884 "Can't re-enable PCI device after reset.\n"); 7885 goto exit_slot_reset; 7886 } 7887 7888 7889 if (ha->isp_ops->pci_config(base_vha)) 7890 goto exit_slot_reset; 7891 7892 mutex_lock(&ha->mq_lock); 7893 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7894 qpair->online = 1; 7895 mutex_unlock(&ha->mq_lock); 7896 7897 ha->flags.eeh_busy = 0; 7898 base_vha->flags.online = 1; 7899 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7900 ha->isp_ops->abort_isp(base_vha); 7901 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7902 7903 if (qla2x00_isp_reg_stat(ha)) { 7904 ha->flags.eeh_busy = 1; 7905 qla_pci_error_cleanup(base_vha); 7906 ql_log(ql_log_warn, base_vha, 0x9005, 7907 "Device unable to recover from PCI error.\n"); 7908 } else { 7909 ret = PCI_ERS_RESULT_RECOVERED; 7910 } 7911 7912 exit_slot_reset: 7913 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7914 "Slot Reset returning %x.\n", ret); 7915 7916 return ret; 7917 } 7918 7919 static void 7920 qla2xxx_pci_resume(struct pci_dev *pdev) 7921 { 7922 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7923 struct qla_hw_data *ha = base_vha->hw; 7924 int ret; 7925 7926 ql_log(ql_log_warn, base_vha, 0x900f, 7927 "Pci Resume.\n"); 7928 7929 7930 ret = qla2x00_wait_for_hba_online(base_vha); 7931 if (ret != QLA_SUCCESS) { 7932 ql_log(ql_log_fatal, base_vha, 0x9002, 7933 "The device failed to resume I/O from slot/link_reset.\n"); 7934 } 7935 ha->pci_error_state = QLA_PCI_RESUME; 7936 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7937 "Pci Resume returning.\n"); 7938 } 7939 7940 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7941 { 7942 struct qla_hw_data *ha = vha->hw; 7943 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7944 bool do_cleanup = false; 7945 unsigned long flags; 7946 7947 if (ha->flags.eeh_busy) 7948 return; 7949 7950 spin_lock_irqsave(&base_vha->work_lock, flags); 7951 if (!ha->flags.eeh_busy) { 7952 ha->eeh_jif = jiffies; 7953 ha->flags.eeh_flush = 0; 7954 7955 ha->flags.eeh_busy = 1; 7956 do_cleanup = true; 7957 } 7958 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7959 7960 if (do_cleanup) 7961 qla_pci_error_cleanup(base_vha); 7962 } 7963 7964 /* 7965 * this routine will schedule a task to pause IO from interrupt context 7966 * if caller sees a PCIE error event (register read = 0xf's) 7967 */ 7968 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7969 { 7970 struct qla_hw_data *ha = vha->hw; 7971 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7972 7973 if (ha->flags.eeh_busy) 7974 return; 7975 7976 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7977 qla2xxx_wake_dpc(base_vha); 7978 } 7979 7980 static void 7981 qla_pci_reset_prepare(struct pci_dev *pdev) 7982 { 7983 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7984 struct qla_hw_data *ha = base_vha->hw; 7985 struct qla_qpair *qpair; 7986 7987 ql_log(ql_log_warn, base_vha, 0xffff, 7988 "%s.\n", __func__); 7989 7990 /* 7991 * PCI FLR/function reset is about to reset the 7992 * slot. Stop the chip to stop all DMA access. 7993 * It is assumed that pci_reset_done will be called 7994 * after FLR to resume Chip operation. 7995 */ 7996 ha->flags.eeh_busy = 1; 7997 mutex_lock(&ha->mq_lock); 7998 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7999 qpair->online = 0; 8000 mutex_unlock(&ha->mq_lock); 8001 8002 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8003 qla2x00_abort_isp_cleanup(base_vha); 8004 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8005 } 8006 8007 static void 8008 qla_pci_reset_done(struct pci_dev *pdev) 8009 { 8010 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8011 struct qla_hw_data *ha = base_vha->hw; 8012 struct qla_qpair *qpair; 8013 8014 ql_log(ql_log_warn, base_vha, 0xffff, 8015 "%s.\n", __func__); 8016 8017 /* 8018 * FLR just completed by PCI layer. Resume adapter 8019 */ 8020 ha->flags.eeh_busy = 0; 8021 mutex_lock(&ha->mq_lock); 8022 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8023 qpair->online = 1; 8024 mutex_unlock(&ha->mq_lock); 8025 8026 base_vha->flags.online = 1; 8027 ha->isp_ops->abort_isp(base_vha); 8028 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8029 } 8030 8031 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8032 { 8033 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8034 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8035 8036 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8037 blk_mq_map_queues(qmap); 8038 else 8039 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8040 } 8041 8042 struct scsi_host_template qla2xxx_driver_template = { 8043 .module = THIS_MODULE, 8044 .name = QLA2XXX_DRIVER_NAME, 8045 .queuecommand = qla2xxx_queuecommand, 8046 8047 .eh_timed_out = fc_eh_timed_out, 8048 .eh_abort_handler = qla2xxx_eh_abort, 8049 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8050 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8051 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8052 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8053 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8054 8055 .slave_configure = qla2xxx_slave_configure, 8056 8057 .slave_alloc = qla2xxx_slave_alloc, 8058 .slave_destroy = qla2xxx_slave_destroy, 8059 .scan_finished = qla2xxx_scan_finished, 8060 .scan_start = qla2xxx_scan_start, 8061 .change_queue_depth = scsi_change_queue_depth, 8062 .map_queues = qla2xxx_map_queues, 8063 .this_id = -1, 8064 .cmd_per_lun = 3, 8065 .sg_tablesize = SG_ALL, 8066 8067 .max_sectors = 0xFFFF, 8068 .shost_groups = qla2x00_host_groups, 8069 8070 .supported_mode = MODE_INITIATOR, 8071 .track_queue_depth = 1, 8072 .cmd_size = sizeof(srb_t), 8073 }; 8074 8075 static const struct pci_error_handlers qla2xxx_err_handler = { 8076 .error_detected = qla2xxx_pci_error_detected, 8077 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8078 .slot_reset = qla2xxx_pci_slot_reset, 8079 .resume = qla2xxx_pci_resume, 8080 .reset_prepare = qla_pci_reset_prepare, 8081 .reset_done = qla_pci_reset_done, 8082 }; 8083 8084 static struct pci_device_id qla2xxx_pci_tbl[] = { 8085 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8086 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8087 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8088 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8089 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8090 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8091 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8092 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8095 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8096 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8098 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8099 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8100 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8101 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8102 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8112 { 0 }, 8113 }; 8114 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8115 8116 static struct pci_driver qla2xxx_pci_driver = { 8117 .name = QLA2XXX_DRIVER_NAME, 8118 .driver = { 8119 .owner = THIS_MODULE, 8120 }, 8121 .id_table = qla2xxx_pci_tbl, 8122 .probe = qla2x00_probe_one, 8123 .remove = qla2x00_remove_one, 8124 .shutdown = qla2x00_shutdown, 8125 .err_handler = &qla2xxx_err_handler, 8126 }; 8127 8128 static const struct file_operations apidev_fops = { 8129 .owner = THIS_MODULE, 8130 .llseek = noop_llseek, 8131 }; 8132 8133 /** 8134 * qla2x00_module_init - Module initialization. 8135 **/ 8136 static int __init 8137 qla2x00_module_init(void) 8138 { 8139 int ret = 0; 8140 8141 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8142 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8143 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8144 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8145 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8146 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8147 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8148 BUILD_BUG_ON(sizeof(request_t) != 64); 8149 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8150 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8151 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8152 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8153 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8154 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8155 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8156 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8157 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8158 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8159 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8160 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8161 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8162 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8163 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8164 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8165 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8166 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8167 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8168 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8169 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8170 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8171 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8172 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8173 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8174 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8175 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8176 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8177 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8178 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8179 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8180 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8181 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8182 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8183 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8184 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8185 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8186 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8187 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8188 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8189 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8190 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8191 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8192 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8193 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8194 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8195 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8196 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8197 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8198 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8199 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8200 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8201 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8202 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8203 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8204 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8205 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8206 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8207 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8208 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8209 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8210 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8211 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8212 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8213 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8214 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8215 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8216 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8217 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8218 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8219 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8220 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8221 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8222 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8223 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8224 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8225 8226 qla_trace_init(); 8227 8228 /* Allocate cache for SRBs. */ 8229 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8230 SLAB_HWCACHE_ALIGN, NULL); 8231 if (srb_cachep == NULL) { 8232 ql_log(ql_log_fatal, NULL, 0x0001, 8233 "Unable to allocate SRB cache...Failing load!.\n"); 8234 return -ENOMEM; 8235 } 8236 8237 /* Initialize target kmem_cache and mem_pools */ 8238 ret = qlt_init(); 8239 if (ret < 0) { 8240 goto destroy_cache; 8241 } else if (ret > 0) { 8242 /* 8243 * If initiator mode is explictly disabled by qlt_init(), 8244 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8245 * performing scsi_scan_target() during LOOP UP event. 8246 */ 8247 qla2xxx_transport_functions.disable_target_scan = 1; 8248 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8249 } 8250 8251 /* Derive version string. */ 8252 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8253 if (ql2xextended_error_logging) 8254 strcat(qla2x00_version_str, "-debug"); 8255 if (ql2xextended_error_logging == 1) 8256 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8257 8258 qla2xxx_transport_template = 8259 fc_attach_transport(&qla2xxx_transport_functions); 8260 if (!qla2xxx_transport_template) { 8261 ql_log(ql_log_fatal, NULL, 0x0002, 8262 "fc_attach_transport failed...Failing load!.\n"); 8263 ret = -ENODEV; 8264 goto qlt_exit; 8265 } 8266 8267 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8268 if (apidev_major < 0) { 8269 ql_log(ql_log_fatal, NULL, 0x0003, 8270 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8271 } 8272 8273 qla2xxx_transport_vport_template = 8274 fc_attach_transport(&qla2xxx_transport_vport_functions); 8275 if (!qla2xxx_transport_vport_template) { 8276 ql_log(ql_log_fatal, NULL, 0x0004, 8277 "fc_attach_transport vport failed...Failing load!.\n"); 8278 ret = -ENODEV; 8279 goto unreg_chrdev; 8280 } 8281 ql_log(ql_log_info, NULL, 0x0005, 8282 "QLogic Fibre Channel HBA Driver: %s.\n", 8283 qla2x00_version_str); 8284 ret = pci_register_driver(&qla2xxx_pci_driver); 8285 if (ret) { 8286 ql_log(ql_log_fatal, NULL, 0x0006, 8287 "pci_register_driver failed...ret=%d Failing load!.\n", 8288 ret); 8289 goto release_vport_transport; 8290 } 8291 return ret; 8292 8293 release_vport_transport: 8294 fc_release_transport(qla2xxx_transport_vport_template); 8295 8296 unreg_chrdev: 8297 if (apidev_major >= 0) 8298 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8299 fc_release_transport(qla2xxx_transport_template); 8300 8301 qlt_exit: 8302 qlt_exit(); 8303 8304 destroy_cache: 8305 kmem_cache_destroy(srb_cachep); 8306 8307 qla_trace_uninit(); 8308 return ret; 8309 } 8310 8311 /** 8312 * qla2x00_module_exit - Module cleanup. 8313 **/ 8314 static void __exit 8315 qla2x00_module_exit(void) 8316 { 8317 pci_unregister_driver(&qla2xxx_pci_driver); 8318 qla2x00_release_firmware(); 8319 kmem_cache_destroy(ctx_cachep); 8320 fc_release_transport(qla2xxx_transport_vport_template); 8321 if (apidev_major >= 0) 8322 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8323 fc_release_transport(qla2xxx_transport_template); 8324 qlt_exit(); 8325 kmem_cache_destroy(srb_cachep); 8326 qla_trace_uninit(); 8327 } 8328 8329 module_init(qla2x00_module_init); 8330 module_exit(qla2x00_module_exit); 8331 8332 MODULE_AUTHOR("QLogic Corporation"); 8333 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8334 MODULE_LICENSE("GPL"); 8335 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8336 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8337 MODULE_FIRMWARE(FW_FILE_ISP2300); 8338 MODULE_FIRMWARE(FW_FILE_ISP2322); 8339 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8340 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8341