1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) 36 #define SMBUS_BLOCK_READ_MIN_LEN 3 37 38 enum xilinx_i2c_state { 39 STATE_DONE, 40 STATE_ERROR, 41 STATE_START 42 }; 43 44 enum xiic_endian { 45 LITTLE, 46 BIG 47 }; 48 49 enum i2c_scl_freq { 50 REG_VALUES_100KHZ = 0, 51 REG_VALUES_400KHZ = 1, 52 REG_VALUES_1MHZ = 2 53 }; 54 55 /** 56 * struct xiic_i2c - Internal representation of the XIIC I2C bus 57 * @dev: Pointer to device structure 58 * @base: Memory base of the HW registers 59 * @completion: Completion for callers 60 * @adap: Kernel adapter representation 61 * @tx_msg: Messages from above to be sent 62 * @lock: Mutual exclusion 63 * @tx_pos: Current pos in TX message 64 * @nmsgs: Number of messages in tx_msg 65 * @rx_msg: Current RX message 66 * @rx_pos: Position within current RX message 67 * @endianness: big/little-endian byte order 68 * @clk: Pointer to AXI4-lite input clock 69 * @state: See STATE_ 70 * @singlemaster: Indicates bus is single master 71 * @dynamic: Mode of controller 72 * @prev_msg_tx: Previous message is Tx 73 * @quirks: To hold platform specific bug info 74 * @smbus_block_read: Flag to handle block read 75 * @input_clk: Input clock to I2C controller 76 * @i2c_clk: I2C SCL frequency 77 */ 78 struct xiic_i2c { 79 struct device *dev; 80 void __iomem *base; 81 struct completion completion; 82 struct i2c_adapter adap; 83 struct i2c_msg *tx_msg; 84 struct mutex lock; 85 unsigned int tx_pos; 86 unsigned int nmsgs; 87 struct i2c_msg *rx_msg; 88 int rx_pos; 89 enum xiic_endian endianness; 90 struct clk *clk; 91 enum xilinx_i2c_state state; 92 bool singlemaster; 93 bool dynamic; 94 bool prev_msg_tx; 95 u32 quirks; 96 bool smbus_block_read; 97 unsigned long input_clk; 98 unsigned int i2c_clk; 99 }; 100 101 struct xiic_version_data { 102 u32 quirks; 103 }; 104 105 /** 106 * struct timing_regs - AXI I2C timing registers that depend on I2C spec 107 * @tsusta: setup time for a repeated START condition 108 * @tsusto: setup time for a STOP condition 109 * @thdsta: hold time for a repeated START condition 110 * @tsudat: setup time for data 111 * @tbuf: bus free time between STOP and START 112 */ 113 struct timing_regs { 114 unsigned int tsusta; 115 unsigned int tsusto; 116 unsigned int thdsta; 117 unsigned int tsudat; 118 unsigned int tbuf; 119 }; 120 121 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */ 122 static const struct timing_regs timing_reg_values[] = { 123 { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */ 124 { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */ 125 { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */ 126 }; 127 128 #define XIIC_MSB_OFFSET 0 129 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 130 131 /* 132 * Register offsets in bytes from RegisterBase. Three is added to the 133 * base offset to access LSB (IBM style) of the word 134 */ 135 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 136 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 137 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 138 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 139 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 140 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 141 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 142 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 143 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 144 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 145 146 /* 147 * Timing register offsets from RegisterBase. These are used only for 148 * setting i2c clock frequency for the line. 149 */ 150 #define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */ 151 #define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */ 152 #define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */ 153 #define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */ 154 #define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */ 155 #define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */ 156 #define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */ 157 #define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */ 158 159 /* Control Register masks */ 160 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 161 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 162 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 163 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 164 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 165 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 166 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 167 168 /* Status Register masks */ 169 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 170 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 171 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 172 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 173 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 174 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 175 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 176 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 177 178 /* Interrupt Status Register masks Interrupt occurs when... */ 179 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 180 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 181 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 182 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 183 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 184 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 185 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 186 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 187 188 /* The following constants specify the depth of the FIFOs */ 189 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 190 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 191 192 /* The following constants specify groups of interrupts that are typically 193 * enabled or disables at the same time 194 */ 195 #define XIIC_TX_INTERRUPTS \ 196 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 197 198 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 199 200 /* 201 * Tx Fifo upper bit masks. 202 */ 203 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 204 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 205 206 /* Dynamic mode constants */ 207 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ 208 209 /* 210 * The following constants define the register offsets for the Interrupt 211 * registers. There are some holes in the memory map for reserved addresses 212 * to allow other registers to be added and still match the memory map of the 213 * interrupt controller registers 214 */ 215 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 216 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 217 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 218 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 219 220 #define XIIC_RESET_MASK 0xAUL 221 222 #define XIIC_PM_TIMEOUT 1000 /* ms */ 223 /* timeout waiting for the controller to respond */ 224 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 225 /* timeout waiting for the controller finish transfers */ 226 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 227 228 /* 229 * The following constant is used for the device global interrupt enable 230 * register, to enable all interrupts for the device, this is the only bit 231 * in the register 232 */ 233 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 234 235 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 236 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 237 238 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 239 static void __xiic_start_xfer(struct xiic_i2c *i2c); 240 241 /* 242 * For the register read and write functions, a little-endian and big-endian 243 * version are necessary. Endianness is detected during the probe function. 244 * Only the least significant byte [doublet] of the register are ever 245 * accessed. This requires an offset of 3 [2] from the base address for 246 * big-endian systems. 247 */ 248 249 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 250 { 251 if (i2c->endianness == LITTLE) 252 iowrite8(value, i2c->base + reg); 253 else 254 iowrite8(value, i2c->base + reg + 3); 255 } 256 257 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 258 { 259 u8 ret; 260 261 if (i2c->endianness == LITTLE) 262 ret = ioread8(i2c->base + reg); 263 else 264 ret = ioread8(i2c->base + reg + 3); 265 return ret; 266 } 267 268 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 269 { 270 if (i2c->endianness == LITTLE) 271 iowrite16(value, i2c->base + reg); 272 else 273 iowrite16be(value, i2c->base + reg + 2); 274 } 275 276 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 277 { 278 if (i2c->endianness == LITTLE) 279 iowrite32(value, i2c->base + reg); 280 else 281 iowrite32be(value, i2c->base + reg); 282 } 283 284 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 285 { 286 u32 ret; 287 288 if (i2c->endianness == LITTLE) 289 ret = ioread32(i2c->base + reg); 290 else 291 ret = ioread32be(i2c->base + reg); 292 return ret; 293 } 294 295 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 296 { 297 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 298 299 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 300 } 301 302 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 303 { 304 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 305 306 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 307 } 308 309 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 310 { 311 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 312 313 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 314 } 315 316 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 317 { 318 xiic_irq_clr(i2c, mask); 319 xiic_irq_en(i2c, mask); 320 } 321 322 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 323 { 324 u8 sr; 325 unsigned long timeout; 326 327 timeout = jiffies + XIIC_I2C_TIMEOUT; 328 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 329 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 330 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 331 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 332 if (time_after(jiffies, timeout)) { 333 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 334 return -ETIMEDOUT; 335 } 336 } 337 338 return 0; 339 } 340 341 static int xiic_wait_tx_empty(struct xiic_i2c *i2c) 342 { 343 u8 isr; 344 unsigned long timeout; 345 346 timeout = jiffies + XIIC_I2C_TIMEOUT; 347 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 348 !(isr & XIIC_INTR_TX_EMPTY_MASK); 349 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { 350 if (time_after(jiffies, timeout)) { 351 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); 352 return -ETIMEDOUT; 353 } 354 } 355 356 return 0; 357 } 358 359 /** 360 * xiic_setclk - Sets the configured clock rate 361 * @i2c: Pointer to the xiic device structure 362 * 363 * The timing register values are calculated according to the input clock 364 * frequency and configured scl frequency. For details, please refer the 365 * AXI I2C PG and NXP I2C Spec. 366 * Supported frequencies are 100KHz, 400KHz and 1MHz. 367 * 368 * Return: 0 on success (Supported frequency selected or not configurable in SW) 369 * -EINVAL on failure (scl frequency not supported or THIGH is 0) 370 */ 371 static int xiic_setclk(struct xiic_i2c *i2c) 372 { 373 unsigned int clk_in_mhz; 374 unsigned int index = 0; 375 u32 reg_val; 376 377 dev_dbg(i2c->adap.dev.parent, 378 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", 379 __func__, i2c->input_clk, i2c->i2c_clk); 380 381 /* If not specified in DT, do not configure in SW. Rely only on Vivado design */ 382 if (!i2c->i2c_clk || !i2c->input_clk) 383 return 0; 384 385 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000); 386 387 switch (i2c->i2c_clk) { 388 case I2C_MAX_FAST_MODE_PLUS_FREQ: 389 index = REG_VALUES_1MHZ; 390 break; 391 case I2C_MAX_FAST_MODE_FREQ: 392 index = REG_VALUES_400KHZ; 393 break; 394 case I2C_MAX_STANDARD_MODE_FREQ: 395 index = REG_VALUES_100KHZ; 396 break; 397 default: 398 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n"); 399 return -EINVAL; 400 } 401 402 /* 403 * Value to be stored in a register is the number of clock cycles required 404 * for the time duration. So the time is divided by the input clock time 405 * period to get the number of clock cycles required. Refer Xilinx AXI I2C 406 * PG document and I2C specification for further details. 407 */ 408 409 /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */ 410 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7; 411 if (reg_val == 0) 412 return -EINVAL; 413 414 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1); 415 416 /* TLOW - Value same as THIGH */ 417 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1); 418 419 /* TSUSTA */ 420 reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000; 421 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1); 422 423 /* TSUSTO */ 424 reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000; 425 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1); 426 427 /* THDSTA */ 428 reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000; 429 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1); 430 431 /* TSUDAT */ 432 reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000; 433 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1); 434 435 /* TBUF */ 436 reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000; 437 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1); 438 439 /* THDDAT */ 440 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1); 441 442 return 0; 443 } 444 445 static int xiic_reinit(struct xiic_i2c *i2c) 446 { 447 int ret; 448 449 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 450 451 ret = xiic_setclk(i2c); 452 if (ret) 453 return ret; 454 455 /* Set receive Fifo depth to maximum (zero based). */ 456 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 457 458 /* Reset Tx Fifo. */ 459 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 460 461 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 462 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 463 464 /* make sure RX fifo is empty */ 465 ret = xiic_clear_rx_fifo(i2c); 466 if (ret) 467 return ret; 468 469 /* Enable interrupts */ 470 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 471 472 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 473 474 return 0; 475 } 476 477 static void xiic_deinit(struct xiic_i2c *i2c) 478 { 479 u8 cr; 480 481 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 482 483 /* Disable IIC Device. */ 484 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 485 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 486 } 487 488 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) 489 { 490 u8 rxmsg_len, rfd_set = 0; 491 492 /* 493 * Clear the I2C_M_RECV_LEN flag to avoid setting 494 * message length again 495 */ 496 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; 497 498 /* Set smbus_block_read flag to identify in isr */ 499 i2c->smbus_block_read = true; 500 501 /* Read byte from rx fifo and set message length */ 502 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 503 504 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; 505 506 /* Check if received length is valid */ 507 if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { 508 /* Set Receive fifo depth */ 509 if (rxmsg_len > IIC_RX_FIFO_DEPTH) { 510 /* 511 * When Rx msg len greater than or equal to Rx fifo capacity 512 * Receive fifo depth should set to Rx fifo capacity minus 1 513 */ 514 rfd_set = IIC_RX_FIFO_DEPTH - 1; 515 i2c->rx_msg->len = rxmsg_len + 1; 516 } else if ((rxmsg_len == 1) || 517 (rxmsg_len == 0)) { 518 /* 519 * Minimum of 3 bytes required to exit cleanly. 1 byte 520 * already received, Second byte is being received. Have 521 * to set NACK in read_rx before receiving the last byte 522 */ 523 rfd_set = 0; 524 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; 525 } else { 526 /* 527 * When Rx msg len less than Rx fifo capacity 528 * Receive fifo depth should set to Rx msg len minus 2 529 */ 530 rfd_set = rxmsg_len - 2; 531 i2c->rx_msg->len = rxmsg_len + 1; 532 } 533 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 534 535 return; 536 } 537 538 /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */ 539 i2c->tx_msg->len = 3; 540 i2c->smbus_block_read = false; 541 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); 542 } 543 544 static void xiic_read_rx(struct xiic_i2c *i2c) 545 { 546 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; 547 u32 bytes_rem = 0; 548 int i; 549 550 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 551 552 dev_dbg(i2c->adap.dev.parent, 553 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 554 __func__, bytes_in_fifo, xiic_rx_space(i2c), 555 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 556 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 557 558 if (bytes_in_fifo > xiic_rx_space(i2c)) 559 bytes_in_fifo = xiic_rx_space(i2c); 560 561 bytes_to_read = bytes_in_fifo; 562 563 if (!i2c->dynamic) { 564 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; 565 566 /* Set msg length if smbus_block_read */ 567 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { 568 xiic_smbus_block_read_setup(i2c); 569 return; 570 } 571 572 if (bytes_rem > IIC_RX_FIFO_DEPTH) { 573 bytes_to_read = bytes_in_fifo; 574 } else if (bytes_rem > 1) { 575 bytes_to_read = bytes_rem - 1; 576 } else if (bytes_rem == 1) { 577 bytes_to_read = 1; 578 /* Set NACK in CR to indicate slave transmitter */ 579 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 580 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 581 XIIC_CR_NO_ACK_MASK); 582 } else if (bytes_rem == 0) { 583 bytes_to_read = bytes_in_fifo; 584 585 /* Generate stop on the bus if it is last message */ 586 if (i2c->nmsgs == 1) { 587 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 588 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 589 ~XIIC_CR_MSMS_MASK); 590 } 591 592 /* Make TXACK=0, clean up for next transaction */ 593 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 594 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 595 ~XIIC_CR_NO_ACK_MASK); 596 } 597 } 598 599 /* Read the fifo */ 600 for (i = 0; i < bytes_to_read; i++) { 601 i2c->rx_msg->buf[i2c->rx_pos++] = 602 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 603 } 604 605 if (i2c->dynamic) { 606 u8 bytes; 607 608 /* Receive remaining bytes if less than fifo depth */ 609 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); 610 bytes--; 611 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 612 } 613 } 614 615 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 616 { 617 /* return the actual space left in the FIFO */ 618 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 619 } 620 621 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 622 { 623 u8 fifo_space = xiic_tx_fifo_space(i2c); 624 int len = xiic_tx_space(i2c); 625 626 len = (len > fifo_space) ? fifo_space : len; 627 628 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 629 __func__, len, fifo_space); 630 631 while (len--) { 632 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 633 634 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 635 /* last message in transfer -> STOP */ 636 if (i2c->dynamic) { 637 data |= XIIC_TX_DYN_STOP_MASK; 638 } else { 639 u8 cr; 640 int status; 641 642 /* Wait till FIFO is empty so STOP is sent last */ 643 status = xiic_wait_tx_empty(i2c); 644 if (status) 645 return; 646 647 /* Write to CR to stop */ 648 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 649 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 650 ~XIIC_CR_MSMS_MASK); 651 } 652 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 653 } 654 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 655 } 656 } 657 658 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) 659 { 660 i2c->tx_msg = NULL; 661 i2c->rx_msg = NULL; 662 i2c->nmsgs = 0; 663 i2c->state = code; 664 complete(&i2c->completion); 665 } 666 667 static irqreturn_t xiic_process(int irq, void *dev_id) 668 { 669 struct xiic_i2c *i2c = dev_id; 670 u32 pend, isr, ier; 671 u32 clr = 0; 672 int xfer_more = 0; 673 int wakeup_req = 0; 674 enum xilinx_i2c_state wakeup_code = STATE_DONE; 675 int ret; 676 677 /* Get the interrupt Status from the IPIF. There is no clearing of 678 * interrupts in the IPIF. Interrupts must be cleared at the source. 679 * To find which interrupts are pending; AND interrupts pending with 680 * interrupts masked. 681 */ 682 mutex_lock(&i2c->lock); 683 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 684 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 685 pend = isr & ier; 686 687 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 688 __func__, ier, isr, pend); 689 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 690 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 691 i2c->tx_msg, i2c->nmsgs); 692 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", 693 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 694 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 695 696 /* Service requesting interrupt */ 697 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 698 ((pend & XIIC_INTR_TX_ERROR_MASK) && 699 !(pend & XIIC_INTR_RX_FULL_MASK))) { 700 /* bus arbritration lost, or... 701 * Transmit error _OR_ RX completed 702 * if this happens when RX_FULL is not set 703 * this is probably a TX error 704 */ 705 706 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 707 708 /* dynamic mode seem to suffer from problems if we just flushes 709 * fifos and the next message is a TX with len 0 (only addr) 710 * reset the IP instead of just flush fifos 711 */ 712 ret = xiic_reinit(i2c); 713 if (!ret) 714 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 715 716 if (i2c->rx_msg) { 717 wakeup_req = 1; 718 wakeup_code = STATE_ERROR; 719 } 720 if (i2c->tx_msg) { 721 wakeup_req = 1; 722 wakeup_code = STATE_ERROR; 723 } 724 } 725 if (pend & XIIC_INTR_RX_FULL_MASK) { 726 /* Receive register/FIFO is full */ 727 728 clr |= XIIC_INTR_RX_FULL_MASK; 729 if (!i2c->rx_msg) { 730 dev_dbg(i2c->adap.dev.parent, 731 "%s unexpected RX IRQ\n", __func__); 732 xiic_clear_rx_fifo(i2c); 733 goto out; 734 } 735 736 xiic_read_rx(i2c); 737 if (xiic_rx_space(i2c) == 0) { 738 /* this is the last part of the message */ 739 i2c->rx_msg = NULL; 740 741 /* also clear TX error if there (RX complete) */ 742 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 743 744 dev_dbg(i2c->adap.dev.parent, 745 "%s end of message, nmsgs: %d\n", 746 __func__, i2c->nmsgs); 747 748 /* send next message if this wasn't the last, 749 * otherwise the transfer will be finialise when 750 * receiving the bus not busy interrupt 751 */ 752 if (i2c->nmsgs > 1) { 753 i2c->nmsgs--; 754 i2c->tx_msg++; 755 dev_dbg(i2c->adap.dev.parent, 756 "%s will start next...\n", __func__); 757 xfer_more = 1; 758 } 759 } 760 } 761 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 762 /* Transmit register/FIFO is empty or ½ empty */ 763 764 clr |= (pend & 765 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 766 767 if (!i2c->tx_msg) { 768 dev_dbg(i2c->adap.dev.parent, 769 "%s unexpected TX IRQ\n", __func__); 770 goto out; 771 } 772 773 xiic_fill_tx_fifo(i2c); 774 775 /* current message sent and there is space in the fifo */ 776 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 777 dev_dbg(i2c->adap.dev.parent, 778 "%s end of message sent, nmsgs: %d\n", 779 __func__, i2c->nmsgs); 780 if (i2c->nmsgs > 1) { 781 i2c->nmsgs--; 782 i2c->tx_msg++; 783 xfer_more = 1; 784 } else { 785 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 786 787 dev_dbg(i2c->adap.dev.parent, 788 "%s Got TX IRQ but no more to do...\n", 789 __func__); 790 } 791 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 792 /* current frame is sent and is last, 793 * make sure to disable tx half 794 */ 795 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 796 } 797 798 if (pend & XIIC_INTR_BNB_MASK) { 799 /* IIC bus has transitioned to not busy */ 800 clr |= XIIC_INTR_BNB_MASK; 801 802 /* The bus is not busy, disable BusNotBusy interrupt */ 803 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 804 805 if (i2c->tx_msg && i2c->smbus_block_read) { 806 i2c->smbus_block_read = false; 807 /* Set requested message len=1 to indicate STATE_DONE */ 808 i2c->tx_msg->len = 1; 809 } 810 811 if (!i2c->tx_msg) 812 goto out; 813 814 wakeup_req = 1; 815 816 if (i2c->nmsgs == 1 && !i2c->rx_msg && 817 xiic_tx_space(i2c) == 0) 818 wakeup_code = STATE_DONE; 819 else 820 wakeup_code = STATE_ERROR; 821 } 822 823 out: 824 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 825 826 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 827 if (xfer_more) 828 __xiic_start_xfer(i2c); 829 if (wakeup_req) 830 xiic_wakeup(i2c, wakeup_code); 831 832 WARN_ON(xfer_more && wakeup_req); 833 834 mutex_unlock(&i2c->lock); 835 return IRQ_HANDLED; 836 } 837 838 static int xiic_bus_busy(struct xiic_i2c *i2c) 839 { 840 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 841 842 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 843 } 844 845 static int xiic_busy(struct xiic_i2c *i2c) 846 { 847 int tries = 3; 848 int err; 849 850 if (i2c->tx_msg || i2c->rx_msg) 851 return -EBUSY; 852 853 /* In single master mode bus can only be busy, when in use by this 854 * driver. If the register indicates bus being busy for some reason we 855 * should ignore it, since bus will never be released and i2c will be 856 * stuck forever. 857 */ 858 if (i2c->singlemaster) { 859 return 0; 860 } 861 862 /* for instance if previous transfer was terminated due to TX error 863 * it might be that the bus is on it's way to become available 864 * give it at most 3 ms to wake 865 */ 866 err = xiic_bus_busy(i2c); 867 while (err && tries--) { 868 msleep(1); 869 err = xiic_bus_busy(i2c); 870 } 871 872 return err; 873 } 874 875 static void xiic_start_recv(struct xiic_i2c *i2c) 876 { 877 u16 rx_watermark; 878 u8 cr = 0, rfd_set = 0; 879 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 880 881 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 882 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 883 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 884 885 /* Disable Tx interrupts */ 886 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); 887 888 if (i2c->dynamic) { 889 u8 bytes; 890 u16 val; 891 892 /* Clear and enable Rx full interrupt. */ 893 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 894 XIIC_INTR_TX_ERROR_MASK); 895 896 /* 897 * We want to get all but last byte, because the TX_ERROR IRQ 898 * is used to indicate error ACK on the address, and 899 * negative ack on the last received byte, so to not mix 900 * them receive all but last. 901 * In the case where there is only one byte to receive 902 * we can check if ERROR and RX full is set at the same time 903 */ 904 rx_watermark = msg->len; 905 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); 906 907 if (rx_watermark > 0) 908 bytes--; 909 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 910 911 /* write the address */ 912 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 913 i2c_8bit_addr_from_msg(msg) | 914 XIIC_TX_DYN_START_MASK); 915 916 /* If last message, include dynamic stop bit with length */ 917 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; 918 val |= msg->len; 919 920 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); 921 922 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 923 } else { 924 /* 925 * If previous message is Tx, make sure that Tx FIFO is empty 926 * before starting a new transfer as the repeated start in 927 * standard mode can corrupt the transaction if there are 928 * still bytes to be transmitted in FIFO 929 */ 930 if (i2c->prev_msg_tx) { 931 int status; 932 933 status = xiic_wait_tx_empty(i2c); 934 if (status) 935 return; 936 } 937 938 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 939 940 /* Set Receive fifo depth */ 941 rx_watermark = msg->len; 942 if (rx_watermark > IIC_RX_FIFO_DEPTH) { 943 rfd_set = IIC_RX_FIFO_DEPTH - 1; 944 } else if (rx_watermark == 1) { 945 rfd_set = rx_watermark - 1; 946 947 /* Set No_ACK, except for smbus_block_read */ 948 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { 949 /* Handle single byte transfer separately */ 950 cr |= XIIC_CR_NO_ACK_MASK; 951 } 952 } else if (rx_watermark == 0) { 953 rfd_set = rx_watermark; 954 } else { 955 rfd_set = rx_watermark - 2; 956 } 957 /* Check if RSTA should be set */ 958 if (cr & XIIC_CR_MSMS_MASK) { 959 /* Already a master, RSTA should be set */ 960 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 961 XIIC_CR_REPEATED_START_MASK) & 962 ~(XIIC_CR_DIR_IS_TX_MASK)); 963 } 964 965 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 966 967 /* Clear and enable Rx full and transmit complete interrupts */ 968 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 969 XIIC_INTR_TX_ERROR_MASK); 970 971 /* Write the address */ 972 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 973 i2c_8bit_addr_from_msg(msg)); 974 975 /* Write to Control Register,to start transaction in Rx mode */ 976 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 977 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 978 XIIC_CR_MSMS_MASK) 979 & ~(XIIC_CR_DIR_IS_TX_MASK)); 980 } 981 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 982 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 983 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 984 } 985 986 if (i2c->nmsgs == 1) 987 /* very last, enable bus not busy as well */ 988 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 989 990 /* the message is tx:ed */ 991 i2c->tx_pos = msg->len; 992 993 /* Enable interrupts */ 994 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 995 996 i2c->prev_msg_tx = false; 997 } 998 999 static void xiic_start_send(struct xiic_i2c *i2c) 1000 { 1001 u8 cr = 0; 1002 u16 data; 1003 struct i2c_msg *msg = i2c->tx_msg; 1004 1005 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 1006 __func__, msg, msg->len); 1007 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 1008 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 1009 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 1010 1011 if (i2c->dynamic) { 1012 /* write the address */ 1013 data = i2c_8bit_addr_from_msg(msg) | 1014 XIIC_TX_DYN_START_MASK; 1015 1016 if (i2c->nmsgs == 1 && msg->len == 0) 1017 /* no data and last message -> add STOP */ 1018 data |= XIIC_TX_DYN_STOP_MASK; 1019 1020 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 1021 1022 /* Clear any pending Tx empty, Tx Error and then enable them */ 1023 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 1024 XIIC_INTR_TX_ERROR_MASK | 1025 XIIC_INTR_BNB_MASK | 1026 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 1027 XIIC_INTR_TX_HALF_MASK : 0)); 1028 1029 xiic_fill_tx_fifo(i2c); 1030 } else { 1031 /* 1032 * If previous message is Tx, make sure that Tx FIFO is empty 1033 * before starting a new transfer as the repeated start in 1034 * standard mode can corrupt the transaction if there are 1035 * still bytes to be transmitted in FIFO 1036 */ 1037 if (i2c->prev_msg_tx) { 1038 int status; 1039 1040 status = xiic_wait_tx_empty(i2c); 1041 if (status) 1042 return; 1043 } 1044 /* Check if RSTA should be set */ 1045 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 1046 if (cr & XIIC_CR_MSMS_MASK) { 1047 /* Already a master, RSTA should be set */ 1048 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 1049 XIIC_CR_REPEATED_START_MASK | 1050 XIIC_CR_DIR_IS_TX_MASK) & 1051 ~(XIIC_CR_NO_ACK_MASK)); 1052 } 1053 1054 /* Write address to FIFO */ 1055 data = i2c_8bit_addr_from_msg(msg); 1056 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 1057 1058 /* Fill fifo */ 1059 xiic_fill_tx_fifo(i2c); 1060 1061 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 1062 /* Start Tx by writing to CR */ 1063 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 1064 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 1065 XIIC_CR_MSMS_MASK | 1066 XIIC_CR_DIR_IS_TX_MASK); 1067 } 1068 1069 /* Clear any pending Tx empty, Tx Error and then enable them */ 1070 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 1071 XIIC_INTR_TX_ERROR_MASK | 1072 XIIC_INTR_BNB_MASK); 1073 } 1074 i2c->prev_msg_tx = true; 1075 } 1076 1077 static void __xiic_start_xfer(struct xiic_i2c *i2c) 1078 { 1079 int fifo_space = xiic_tx_fifo_space(i2c); 1080 1081 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 1082 __func__, i2c->tx_msg, fifo_space); 1083 1084 if (!i2c->tx_msg) 1085 return; 1086 1087 i2c->rx_pos = 0; 1088 i2c->tx_pos = 0; 1089 i2c->state = STATE_START; 1090 if (i2c->tx_msg->flags & I2C_M_RD) { 1091 /* we dont date putting several reads in the FIFO */ 1092 xiic_start_recv(i2c); 1093 } else { 1094 xiic_start_send(i2c); 1095 } 1096 } 1097 1098 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 1099 { 1100 bool broken_read, max_read_len, smbus_blk_read; 1101 int ret, count; 1102 1103 mutex_lock(&i2c->lock); 1104 1105 ret = xiic_busy(i2c); 1106 if (ret) 1107 goto out; 1108 1109 i2c->tx_msg = msgs; 1110 i2c->rx_msg = NULL; 1111 i2c->nmsgs = num; 1112 init_completion(&i2c->completion); 1113 1114 /* Decide standard mode or Dynamic mode */ 1115 i2c->dynamic = true; 1116 1117 /* Initialize prev message type */ 1118 i2c->prev_msg_tx = false; 1119 1120 /* 1121 * Scan through nmsgs, use dynamic mode when none of the below three 1122 * conditions occur. We need standard mode even if one condition holds 1123 * true in the entire array of messages in a single transfer. 1124 * If read transaction as dynamic mode is broken for delayed reads 1125 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. 1126 * If read length is > 255 bytes. 1127 * If smbus_block_read transaction. 1128 */ 1129 for (count = 0; count < i2c->nmsgs; count++) { 1130 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && 1131 (i2c->tx_msg[count].flags & I2C_M_RD); 1132 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && 1133 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); 1134 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); 1135 1136 if (broken_read || max_read_len || smbus_blk_read) { 1137 i2c->dynamic = false; 1138 break; 1139 } 1140 } 1141 1142 ret = xiic_reinit(i2c); 1143 if (!ret) 1144 __xiic_start_xfer(i2c); 1145 1146 out: 1147 mutex_unlock(&i2c->lock); 1148 1149 return ret; 1150 } 1151 1152 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 1153 { 1154 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 1155 int err; 1156 1157 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 1158 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 1159 1160 err = pm_runtime_resume_and_get(i2c->dev); 1161 if (err < 0) 1162 return err; 1163 1164 err = xiic_start_xfer(i2c, msgs, num); 1165 if (err < 0) { 1166 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 1167 return err; 1168 } 1169 1170 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 1171 mutex_lock(&i2c->lock); 1172 if (err == 0) { /* Timeout */ 1173 i2c->tx_msg = NULL; 1174 i2c->rx_msg = NULL; 1175 i2c->nmsgs = 0; 1176 err = -ETIMEDOUT; 1177 } else { 1178 err = (i2c->state == STATE_DONE) ? num : -EIO; 1179 } 1180 mutex_unlock(&i2c->lock); 1181 pm_runtime_mark_last_busy(i2c->dev); 1182 pm_runtime_put_autosuspend(i2c->dev); 1183 return err; 1184 } 1185 1186 static u32 xiic_func(struct i2c_adapter *adap) 1187 { 1188 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; 1189 } 1190 1191 static const struct i2c_algorithm xiic_algorithm = { 1192 .master_xfer = xiic_xfer, 1193 .functionality = xiic_func, 1194 }; 1195 1196 static const struct i2c_adapter xiic_adapter = { 1197 .owner = THIS_MODULE, 1198 .class = I2C_CLASS_DEPRECATED, 1199 .algo = &xiic_algorithm, 1200 }; 1201 1202 static const struct xiic_version_data xiic_2_00 = { 1203 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, 1204 }; 1205 1206 #if defined(CONFIG_OF) 1207 static const struct of_device_id xiic_of_match[] = { 1208 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, 1209 { .compatible = "xlnx,axi-iic-2.1", }, 1210 {}, 1211 }; 1212 MODULE_DEVICE_TABLE(of, xiic_of_match); 1213 #endif 1214 1215 static int xiic_i2c_probe(struct platform_device *pdev) 1216 { 1217 struct xiic_i2c *i2c; 1218 struct xiic_i2c_platform_data *pdata; 1219 const struct of_device_id *match; 1220 struct resource *res; 1221 int ret, irq; 1222 u8 i; 1223 u32 sr; 1224 1225 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1226 if (!i2c) 1227 return -ENOMEM; 1228 1229 match = of_match_node(xiic_of_match, pdev->dev.of_node); 1230 if (match && match->data) { 1231 const struct xiic_version_data *data = match->data; 1232 1233 i2c->quirks = data->quirks; 1234 } 1235 1236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1237 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1238 if (IS_ERR(i2c->base)) 1239 return PTR_ERR(i2c->base); 1240 1241 irq = platform_get_irq(pdev, 0); 1242 if (irq < 0) 1243 return irq; 1244 1245 pdata = dev_get_platdata(&pdev->dev); 1246 1247 /* hook up driver to tree */ 1248 platform_set_drvdata(pdev, i2c); 1249 i2c->adap = xiic_adapter; 1250 i2c_set_adapdata(&i2c->adap, i2c); 1251 i2c->adap.dev.parent = &pdev->dev; 1252 i2c->adap.dev.of_node = pdev->dev.of_node; 1253 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 1254 DRIVER_NAME " %s", pdev->name); 1255 1256 mutex_init(&i2c->lock); 1257 1258 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1259 if (IS_ERR(i2c->clk)) 1260 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 1261 "input clock not found.\n"); 1262 1263 ret = clk_prepare_enable(i2c->clk); 1264 if (ret) { 1265 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1266 return ret; 1267 } 1268 i2c->dev = &pdev->dev; 1269 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 1270 pm_runtime_use_autosuspend(i2c->dev); 1271 pm_runtime_set_active(i2c->dev); 1272 pm_runtime_enable(i2c->dev); 1273 1274 /* SCL frequency configuration */ 1275 i2c->input_clk = clk_get_rate(i2c->clk); 1276 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1277 &i2c->i2c_clk); 1278 /* If clock-frequency not specified in DT, do not configure in SW */ 1279 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) 1280 i2c->i2c_clk = 0; 1281 1282 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1283 xiic_process, IRQF_ONESHOT, 1284 pdev->name, i2c); 1285 1286 if (ret < 0) { 1287 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 1288 goto err_clk_dis; 1289 } 1290 1291 i2c->singlemaster = 1292 of_property_read_bool(pdev->dev.of_node, "single-master"); 1293 1294 /* 1295 * Detect endianness 1296 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 1297 * set, assume that the endianness was wrong and swap. 1298 */ 1299 i2c->endianness = LITTLE; 1300 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 1301 /* Reset is cleared in xiic_reinit */ 1302 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 1303 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 1304 i2c->endianness = BIG; 1305 1306 ret = xiic_reinit(i2c); 1307 if (ret < 0) { 1308 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 1309 goto err_clk_dis; 1310 } 1311 1312 /* add i2c adapter to i2c tree */ 1313 ret = i2c_add_adapter(&i2c->adap); 1314 if (ret) { 1315 xiic_deinit(i2c); 1316 goto err_clk_dis; 1317 } 1318 1319 if (pdata) { 1320 /* add in known devices to the bus */ 1321 for (i = 0; i < pdata->num_devices; i++) 1322 i2c_new_client_device(&i2c->adap, pdata->devices + i); 1323 } 1324 1325 dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n", 1326 (unsigned long)res->start, irq, i2c->i2c_clk); 1327 1328 return 0; 1329 1330 err_clk_dis: 1331 pm_runtime_set_suspended(&pdev->dev); 1332 pm_runtime_disable(&pdev->dev); 1333 clk_disable_unprepare(i2c->clk); 1334 return ret; 1335 } 1336 1337 static int xiic_i2c_remove(struct platform_device *pdev) 1338 { 1339 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 1340 int ret; 1341 1342 /* remove adapter & data */ 1343 i2c_del_adapter(&i2c->adap); 1344 1345 ret = pm_runtime_get_sync(i2c->dev); 1346 1347 if (ret < 0) 1348 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", 1349 ERR_PTR(ret)); 1350 else 1351 xiic_deinit(i2c); 1352 1353 pm_runtime_put_sync(i2c->dev); 1354 clk_disable_unprepare(i2c->clk); 1355 pm_runtime_disable(&pdev->dev); 1356 pm_runtime_set_suspended(&pdev->dev); 1357 pm_runtime_dont_use_autosuspend(&pdev->dev); 1358 1359 return 0; 1360 } 1361 1362 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 1363 { 1364 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1365 1366 clk_disable(i2c->clk); 1367 1368 return 0; 1369 } 1370 1371 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 1372 { 1373 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1374 int ret; 1375 1376 ret = clk_enable(i2c->clk); 1377 if (ret) { 1378 dev_err(dev, "Cannot enable clock.\n"); 1379 return ret; 1380 } 1381 1382 return 0; 1383 } 1384 1385 static const struct dev_pm_ops xiic_dev_pm_ops = { 1386 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 1387 xiic_i2c_runtime_resume, NULL) 1388 }; 1389 1390 static struct platform_driver xiic_i2c_driver = { 1391 .probe = xiic_i2c_probe, 1392 .remove = xiic_i2c_remove, 1393 .driver = { 1394 .name = DRIVER_NAME, 1395 .of_match_table = of_match_ptr(xiic_of_match), 1396 .pm = &xiic_dev_pm_ops, 1397 }, 1398 }; 1399 1400 module_platform_driver(xiic_i2c_driver); 1401 1402 MODULE_ALIAS("platform:" DRIVER_NAME); 1403 MODULE_AUTHOR("info@mocean-labs.com"); 1404 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 1405 MODULE_LICENSE("GPL v2"); 1406