1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 struct mii_bus *bus = priv->bus; 148 149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 150 151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 152 153 mutex_unlock(&bus->mdio_lock); 154 } 155 156 static void 157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 158 { 159 struct mii_bus *bus = priv->bus; 160 u32 val; 161 162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 163 164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 165 val &= ~mask; 166 val |= set; 167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 168 169 mutex_unlock(&bus->mdio_lock); 170 } 171 172 static void 173 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, 0, val); 176 } 177 178 static void 179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 core_rmw(priv, reg, val, 0); 182 } 183 184 static int 185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 struct mii_bus *bus = priv->bus; 188 u16 page, r, lo, hi; 189 int ret; 190 191 page = (reg >> 6) & 0x3ff; 192 r = (reg >> 2) & 0xf; 193 lo = val & 0xffff; 194 hi = val >> 16; 195 196 /* MT7530 uses 31 as the pseudo port */ 197 ret = bus->write(bus, 0x1f, 0x1f, page); 198 if (ret < 0) 199 goto err; 200 201 ret = bus->write(bus, 0x1f, r, lo); 202 if (ret < 0) 203 goto err; 204 205 ret = bus->write(bus, 0x1f, 0x10, hi); 206 err: 207 if (ret < 0) 208 dev_err(&bus->dev, 209 "failed to write mt7530 register\n"); 210 return ret; 211 } 212 213 static u32 214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 215 { 216 struct mii_bus *bus = priv->bus; 217 u16 page, r, lo, hi; 218 int ret; 219 220 page = (reg >> 6) & 0x3ff; 221 r = (reg >> 2) & 0xf; 222 223 /* MT7530 uses 31 as the pseudo port */ 224 ret = bus->write(bus, 0x1f, 0x1f, page); 225 if (ret < 0) { 226 dev_err(&bus->dev, 227 "failed to read mt7530 register\n"); 228 return ret; 229 } 230 231 lo = bus->read(bus, 0x1f, r); 232 hi = bus->read(bus, 0x1f, 0x10); 233 234 return (hi << 16) | (lo & 0xffff); 235 } 236 237 static void 238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 struct mii_bus *bus = priv->bus; 241 242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 243 244 mt7530_mii_write(priv, reg, val); 245 246 mutex_unlock(&bus->mdio_lock); 247 } 248 249 static u32 250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 251 { 252 return mt7530_mii_read(p->priv, p->reg); 253 } 254 255 static u32 256 _mt7530_read(struct mt7530_dummy_poll *p) 257 { 258 struct mii_bus *bus = p->priv->bus; 259 u32 val; 260 261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 262 263 val = mt7530_mii_read(p->priv, p->reg); 264 265 mutex_unlock(&bus->mdio_lock); 266 267 return val; 268 } 269 270 static u32 271 mt7530_read(struct mt7530_priv *priv, u32 reg) 272 { 273 struct mt7530_dummy_poll p; 274 275 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 276 return _mt7530_read(&p); 277 } 278 279 static void 280 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 281 u32 mask, u32 set) 282 { 283 struct mii_bus *bus = priv->bus; 284 u32 val; 285 286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 287 288 val = mt7530_mii_read(priv, reg); 289 val &= ~mask; 290 val |= set; 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static void 297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, 0, val); 300 } 301 302 static void 303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 304 { 305 mt7530_rmw(priv, reg, val, 0); 306 } 307 308 static int 309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 310 { 311 u32 val; 312 int ret; 313 struct mt7530_dummy_poll p; 314 315 /* Set the command operating upon the MAC address entries */ 316 val = ATC_BUSY | ATC_MAT(0) | cmd; 317 mt7530_write(priv, MT7530_ATC, val); 318 319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 320 ret = readx_poll_timeout(_mt7530_read, &p, val, 321 !(val & ATC_BUSY), 20, 20000); 322 if (ret < 0) { 323 dev_err(priv->dev, "reset timeout\n"); 324 return ret; 325 } 326 327 /* Additional sanity for read command if the specified 328 * entry is invalid 329 */ 330 val = mt7530_read(priv, MT7530_ATC); 331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 332 return -EINVAL; 333 334 if (rsp) 335 *rsp = val; 336 337 return 0; 338 } 339 340 static void 341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 342 { 343 u32 reg[3]; 344 int i; 345 346 /* Read from ARL table into an array */ 347 for (i = 0; i < 3; i++) { 348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 349 350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 351 __func__, __LINE__, i, reg[i]); 352 } 353 354 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 364 } 365 366 static void 367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 368 u8 port_mask, const u8 *mac, 369 u8 aging, u8 type) 370 { 371 u32 reg[3] = { 0 }; 372 int i; 373 374 reg[1] |= vid & CVID_MASK; 375 reg[1] |= ATA2_IVL; 376 reg[1] |= ATA2_FID(FID_BRIDGED); 377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 379 /* STATIC_ENT indicate that entry is static wouldn't 380 * be aged out and STATIC_EMP specified as erasing an 381 * entry 382 */ 383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 384 reg[1] |= mac[5] << MAC_BYTE_5; 385 reg[1] |= mac[4] << MAC_BYTE_4; 386 reg[0] |= mac[3] << MAC_BYTE_3; 387 reg[0] |= mac[2] << MAC_BYTE_2; 388 reg[0] |= mac[1] << MAC_BYTE_1; 389 reg[0] |= mac[0] << MAC_BYTE_0; 390 391 /* Write array into the ARL table */ 392 for (i = 0; i < 3; i++) 393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 394 } 395 396 /* Set up switch core clock for MT7530 */ 397 static void mt7530_pll_setup(struct mt7530_priv *priv) 398 { 399 /* Disable PLL */ 400 core_write(priv, CORE_GSWPLL_GRP1, 0); 401 402 /* Set core clock into 500Mhz */ 403 core_write(priv, CORE_GSWPLL_GRP2, 404 RG_GSWPLL_POSDIV_500M(1) | 405 RG_GSWPLL_FBKDIV_500M(25)); 406 407 /* Enable PLL */ 408 core_write(priv, CORE_GSWPLL_GRP1, 409 RG_GSWPLL_EN_PRE | 410 RG_GSWPLL_POSDIV_200M(2) | 411 RG_GSWPLL_FBKDIV_200M(32)); 412 } 413 414 /* Setup TX circuit including relevant PAD and driving */ 415 static int 416 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 417 { 418 struct mt7530_priv *priv = ds->priv; 419 u32 ncpo1, ssc_delta, trgint, i, xtal; 420 421 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 422 423 if (xtal == HWTRAP_XTAL_20MHZ) { 424 dev_err(priv->dev, 425 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 426 __func__); 427 return -EINVAL; 428 } 429 430 switch (interface) { 431 case PHY_INTERFACE_MODE_RGMII: 432 trgint = 0; 433 /* PLL frequency: 125MHz */ 434 ncpo1 = 0x0c80; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (priv->id == ID_MT7621) { 439 /* PLL frequency: 150MHz: 1.2GBit */ 440 if (xtal == HWTRAP_XTAL_40MHZ) 441 ncpo1 = 0x0780; 442 if (xtal == HWTRAP_XTAL_25MHZ) 443 ncpo1 = 0x0a00; 444 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 445 if (xtal == HWTRAP_XTAL_40MHZ) 446 ncpo1 = 0x0c80; 447 if (xtal == HWTRAP_XTAL_25MHZ) 448 ncpo1 = 0x1400; 449 } 450 break; 451 default: 452 dev_err(priv->dev, "xMII interface %d not supported\n", 453 interface); 454 return -EINVAL; 455 } 456 457 if (xtal == HWTRAP_XTAL_25MHZ) 458 ssc_delta = 0x57; 459 else 460 ssc_delta = 0x87; 461 462 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 463 P6_INTF_MODE(trgint)); 464 465 /* Lower Tx Driving for TRGMII path */ 466 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 467 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 468 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 469 470 /* Disable MT7530 core and TRGMII Tx clocks */ 471 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 472 REG_GSWCK_EN | REG_TRGMIICK_EN); 473 474 /* Setup the MT7530 TRGMII Tx Clock */ 475 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 476 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 477 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 478 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 479 core_write(priv, CORE_PLL_GROUP4, 480 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 481 RG_SYSPLL_BIAS_LPF_EN); 482 core_write(priv, CORE_PLL_GROUP2, 483 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 484 RG_SYSPLL_POSDIV(1)); 485 core_write(priv, CORE_PLL_GROUP7, 486 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 487 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 488 489 /* Enable MT7530 core and TRGMII Tx clocks */ 490 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 491 REG_GSWCK_EN | REG_TRGMIICK_EN); 492 493 if (!trgint) 494 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 495 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 496 RD_TAP_MASK, RD_TAP(16)); 497 return 0; 498 } 499 500 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 501 { 502 u32 val; 503 504 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 505 506 return (val & PAD_DUAL_SGMII_EN) != 0; 507 } 508 509 static int 510 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 511 { 512 return 0; 513 } 514 515 static void 516 mt7531_pll_setup(struct mt7530_priv *priv) 517 { 518 u32 top_sig; 519 u32 hwstrap; 520 u32 xtal; 521 u32 val; 522 523 if (mt7531_dual_sgmii_supported(priv)) 524 return; 525 526 val = mt7530_read(priv, MT7531_CREV); 527 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 528 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 529 if ((val & CHIP_REV_M) > 0) 530 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 531 HWTRAP_XTAL_FSEL_25MHZ; 532 else 533 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 534 535 /* Step 1 : Disable MT7531 COREPLL */ 536 val = mt7530_read(priv, MT7531_PLLGP_EN); 537 val &= ~EN_COREPLL; 538 mt7530_write(priv, MT7531_PLLGP_EN, val); 539 540 /* Step 2: switch to XTAL output */ 541 val = mt7530_read(priv, MT7531_PLLGP_EN); 542 val |= SW_CLKSW; 543 mt7530_write(priv, MT7531_PLLGP_EN, val); 544 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_EN; 547 mt7530_write(priv, MT7531_PLLGP_CR0, val); 548 549 /* Step 3: disable PLLGP and enable program PLLGP */ 550 val = mt7530_read(priv, MT7531_PLLGP_EN); 551 val |= SW_PLLGP; 552 mt7530_write(priv, MT7531_PLLGP_EN, val); 553 554 /* Step 4: program COREPLL output frequency to 500MHz */ 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_POSDIV_M; 557 val |= 2 << RG_COREPLL_POSDIV_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 usleep_range(25, 35); 560 561 switch (xtal) { 562 case HWTRAP_XTAL_FSEL_25MHZ: 563 val = mt7530_read(priv, MT7531_PLLGP_CR0); 564 val &= ~RG_COREPLL_SDM_PCW_M; 565 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 566 mt7530_write(priv, MT7531_PLLGP_CR0, val); 567 break; 568 case HWTRAP_XTAL_FSEL_40MHZ: 569 val = mt7530_read(priv, MT7531_PLLGP_CR0); 570 val &= ~RG_COREPLL_SDM_PCW_M; 571 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 572 mt7530_write(priv, MT7531_PLLGP_CR0, val); 573 break; 574 } 575 576 /* Set feedback divide ratio update signal to high */ 577 val = mt7530_read(priv, MT7531_PLLGP_CR0); 578 val |= RG_COREPLL_SDM_PCW_CHG; 579 mt7530_write(priv, MT7531_PLLGP_CR0, val); 580 /* Wait for at least 16 XTAL clocks */ 581 usleep_range(10, 20); 582 583 /* Step 5: set feedback divide ratio update signal to low */ 584 val = mt7530_read(priv, MT7531_PLLGP_CR0); 585 val &= ~RG_COREPLL_SDM_PCW_CHG; 586 mt7530_write(priv, MT7531_PLLGP_CR0, val); 587 588 /* Enable 325M clock for SGMII */ 589 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 590 591 /* Enable 250SSC clock for RGMII */ 592 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 593 594 /* Step 6: Enable MT7531 PLL */ 595 val = mt7530_read(priv, MT7531_PLLGP_CR0); 596 val |= RG_COREPLL_EN; 597 mt7530_write(priv, MT7531_PLLGP_CR0, val); 598 599 val = mt7530_read(priv, MT7531_PLLGP_EN); 600 val |= EN_COREPLL; 601 mt7530_write(priv, MT7531_PLLGP_EN, val); 602 usleep_range(25, 35); 603 } 604 605 static void 606 mt7530_mib_reset(struct dsa_switch *ds) 607 { 608 struct mt7530_priv *priv = ds->priv; 609 610 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 611 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 612 } 613 614 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 615 { 616 return mdiobus_read_nested(priv->bus, port, regnum); 617 } 618 619 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 620 u16 val) 621 { 622 return mdiobus_write_nested(priv->bus, port, regnum, val); 623 } 624 625 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 626 int devad, int regnum) 627 { 628 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 629 } 630 631 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 632 int regnum, u16 val) 633 { 634 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 635 } 636 637 static int 638 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 639 int regnum) 640 { 641 struct mii_bus *bus = priv->bus; 642 struct mt7530_dummy_poll p; 643 u32 reg, val; 644 int ret; 645 646 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 647 648 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 649 650 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 651 !(val & MT7531_PHY_ACS_ST), 20, 100000); 652 if (ret < 0) { 653 dev_err(priv->dev, "poll timeout\n"); 654 goto out; 655 } 656 657 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 658 MT7531_MDIO_DEV_ADDR(devad) | regnum; 659 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 660 661 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 669 MT7531_MDIO_DEV_ADDR(devad); 670 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 671 672 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 673 !(val & MT7531_PHY_ACS_ST), 20, 100000); 674 if (ret < 0) { 675 dev_err(priv->dev, "poll timeout\n"); 676 goto out; 677 } 678 679 ret = val & MT7531_MDIO_RW_DATA_MASK; 680 out: 681 mutex_unlock(&bus->mdio_lock); 682 683 return ret; 684 } 685 686 static int 687 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 688 int regnum, u16 data) 689 { 690 struct mii_bus *bus = priv->bus; 691 struct mt7530_dummy_poll p; 692 u32 val, reg; 693 int ret; 694 695 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 696 697 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 698 699 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 700 !(val & MT7531_PHY_ACS_ST), 20, 100000); 701 if (ret < 0) { 702 dev_err(priv->dev, "poll timeout\n"); 703 goto out; 704 } 705 706 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 707 MT7531_MDIO_DEV_ADDR(devad) | regnum; 708 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 709 710 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 711 !(val & MT7531_PHY_ACS_ST), 20, 100000); 712 if (ret < 0) { 713 dev_err(priv->dev, "poll timeout\n"); 714 goto out; 715 } 716 717 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 718 MT7531_MDIO_DEV_ADDR(devad) | data; 719 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 720 721 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 722 !(val & MT7531_PHY_ACS_ST), 20, 100000); 723 if (ret < 0) { 724 dev_err(priv->dev, "poll timeout\n"); 725 goto out; 726 } 727 728 out: 729 mutex_unlock(&bus->mdio_lock); 730 731 return ret; 732 } 733 734 static int 735 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 736 { 737 struct mii_bus *bus = priv->bus; 738 struct mt7530_dummy_poll p; 739 int ret; 740 u32 val; 741 742 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 743 744 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 745 746 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 747 !(val & MT7531_PHY_ACS_ST), 20, 100000); 748 if (ret < 0) { 749 dev_err(priv->dev, "poll timeout\n"); 750 goto out; 751 } 752 753 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 754 MT7531_MDIO_REG_ADDR(regnum); 755 756 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 757 758 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 759 !(val & MT7531_PHY_ACS_ST), 20, 100000); 760 if (ret < 0) { 761 dev_err(priv->dev, "poll timeout\n"); 762 goto out; 763 } 764 765 ret = val & MT7531_MDIO_RW_DATA_MASK; 766 out: 767 mutex_unlock(&bus->mdio_lock); 768 769 return ret; 770 } 771 772 static int 773 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 774 u16 data) 775 { 776 struct mii_bus *bus = priv->bus; 777 struct mt7530_dummy_poll p; 778 int ret; 779 u32 reg; 780 781 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 782 783 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 784 785 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 786 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 787 if (ret < 0) { 788 dev_err(priv->dev, "poll timeout\n"); 789 goto out; 790 } 791 792 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 793 MT7531_MDIO_REG_ADDR(regnum) | data; 794 795 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 796 797 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 798 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 799 if (ret < 0) { 800 dev_err(priv->dev, "poll timeout\n"); 801 goto out; 802 } 803 804 out: 805 mutex_unlock(&bus->mdio_lock); 806 807 return ret; 808 } 809 810 static int 811 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 812 { 813 struct mt7530_priv *priv = bus->priv; 814 815 return priv->info->phy_read_c22(priv, port, regnum); 816 } 817 818 static int 819 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 820 { 821 struct mt7530_priv *priv = bus->priv; 822 823 return priv->info->phy_read_c45(priv, port, devad, regnum); 824 } 825 826 static int 827 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 828 { 829 struct mt7530_priv *priv = bus->priv; 830 831 return priv->info->phy_write_c22(priv, port, regnum, val); 832 } 833 834 static int 835 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 836 u16 val) 837 { 838 struct mt7530_priv *priv = bus->priv; 839 840 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 841 } 842 843 static void 844 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 845 uint8_t *data) 846 { 847 int i; 848 849 if (stringset != ETH_SS_STATS) 850 return; 851 852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 853 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 854 ETH_GSTRING_LEN); 855 } 856 857 static void 858 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 859 uint64_t *data) 860 { 861 struct mt7530_priv *priv = ds->priv; 862 const struct mt7530_mib_desc *mib; 863 u32 reg, i; 864 u64 hi; 865 866 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 867 mib = &mt7530_mib[i]; 868 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 869 870 data[i] = mt7530_read(priv, reg); 871 if (mib->size == 2) { 872 hi = mt7530_read(priv, reg + 4); 873 data[i] |= hi << 32; 874 } 875 } 876 } 877 878 static int 879 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 880 { 881 if (sset != ETH_SS_STATS) 882 return 0; 883 884 return ARRAY_SIZE(mt7530_mib); 885 } 886 887 static int 888 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 889 { 890 struct mt7530_priv *priv = ds->priv; 891 unsigned int secs = msecs / 1000; 892 unsigned int tmp_age_count; 893 unsigned int error = -1; 894 unsigned int age_count; 895 unsigned int age_unit; 896 897 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 898 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 899 return -ERANGE; 900 901 /* iterate through all possible age_count to find the closest pair */ 902 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 903 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 904 905 if (tmp_age_unit <= AGE_UNIT_MAX) { 906 unsigned int tmp_error = secs - 907 (tmp_age_count + 1) * (tmp_age_unit + 1); 908 909 /* found a closer pair */ 910 if (error > tmp_error) { 911 error = tmp_error; 912 age_count = tmp_age_count; 913 age_unit = tmp_age_unit; 914 } 915 916 /* found the exact match, so break the loop */ 917 if (!error) 918 break; 919 } 920 } 921 922 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 923 924 return 0; 925 } 926 927 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 928 { 929 struct mt7530_priv *priv = ds->priv; 930 u8 tx_delay = 0; 931 int val; 932 933 mutex_lock(&priv->reg_mutex); 934 935 val = mt7530_read(priv, MT7530_MHWTRAP); 936 937 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 938 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 939 940 switch (priv->p5_intf_sel) { 941 case P5_INTF_SEL_PHY_P0: 942 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 943 val |= MHWTRAP_PHY0_SEL; 944 fallthrough; 945 case P5_INTF_SEL_PHY_P4: 946 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 947 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 948 949 /* Setup the MAC by default for the cpu port */ 950 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 951 break; 952 case P5_INTF_SEL_GMAC5: 953 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 954 val &= ~MHWTRAP_P5_DIS; 955 break; 956 case P5_DISABLED: 957 interface = PHY_INTERFACE_MODE_NA; 958 break; 959 default: 960 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 961 priv->p5_intf_sel); 962 goto unlock_exit; 963 } 964 965 /* Setup RGMII settings */ 966 if (phy_interface_mode_is_rgmii(interface)) { 967 val |= MHWTRAP_P5_RGMII_MODE; 968 969 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 970 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 971 972 /* Don't set delay in DSA mode */ 973 if (!dsa_is_dsa_port(priv->ds, 5) && 974 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 975 interface == PHY_INTERFACE_MODE_RGMII_ID)) 976 tx_delay = 4; /* n * 0.5 ns */ 977 978 /* P5 RGMII TX Clock Control: delay x */ 979 mt7530_write(priv, MT7530_P5RGMIITXCR, 980 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 981 982 /* reduce P5 RGMII Tx driving, 8mA */ 983 mt7530_write(priv, MT7530_IO_DRV_CR, 984 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 985 } 986 987 mt7530_write(priv, MT7530_MHWTRAP, val); 988 989 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 990 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 991 992 priv->p5_interface = interface; 993 994 unlock_exit: 995 mutex_unlock(&priv->reg_mutex); 996 } 997 998 static int 999 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1000 { 1001 struct mt7530_priv *priv = ds->priv; 1002 int ret; 1003 1004 /* Setup max capability of CPU port at first */ 1005 if (priv->info->cpu_port_config) { 1006 ret = priv->info->cpu_port_config(ds, port); 1007 if (ret) 1008 return ret; 1009 } 1010 1011 /* Enable Mediatek header mode on the cpu port */ 1012 mt7530_write(priv, MT7530_PVC_P(port), 1013 PORT_SPEC_TAG); 1014 1015 /* Disable flooding by default */ 1016 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1017 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1018 1019 /* Set CPU port number */ 1020 if (priv->id == ID_MT7621) 1021 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1022 1023 /* CPU port gets connected to all user ports of 1024 * the switch. 1025 */ 1026 mt7530_write(priv, MT7530_PCR_P(port), 1027 PCR_MATRIX(dsa_user_ports(priv->ds))); 1028 1029 /* Set to fallback mode for independent VLAN learning */ 1030 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1031 MT7530_PORT_FALLBACK_MODE); 1032 1033 return 0; 1034 } 1035 1036 static int 1037 mt7530_port_enable(struct dsa_switch *ds, int port, 1038 struct phy_device *phy) 1039 { 1040 struct dsa_port *dp = dsa_to_port(ds, port); 1041 struct mt7530_priv *priv = ds->priv; 1042 1043 mutex_lock(&priv->reg_mutex); 1044 1045 /* Allow the user port gets connected to the cpu port and also 1046 * restore the port matrix if the port is the member of a certain 1047 * bridge. 1048 */ 1049 if (dsa_port_is_user(dp)) { 1050 struct dsa_port *cpu_dp = dp->cpu_dp; 1051 1052 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1053 } 1054 priv->ports[port].enable = true; 1055 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1056 priv->ports[port].pm); 1057 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1058 1059 mutex_unlock(&priv->reg_mutex); 1060 1061 return 0; 1062 } 1063 1064 static void 1065 mt7530_port_disable(struct dsa_switch *ds, int port) 1066 { 1067 struct mt7530_priv *priv = ds->priv; 1068 1069 mutex_lock(&priv->reg_mutex); 1070 1071 /* Clear up all port matrix which could be restored in the next 1072 * enablement for the port. 1073 */ 1074 priv->ports[port].enable = false; 1075 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1076 PCR_MATRIX_CLR); 1077 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1078 1079 mutex_unlock(&priv->reg_mutex); 1080 } 1081 1082 static int 1083 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1084 { 1085 struct mt7530_priv *priv = ds->priv; 1086 struct mii_bus *bus = priv->bus; 1087 int length; 1088 u32 val; 1089 1090 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1091 * largest MTU of the slave ports. Because the switch only has a global 1092 * RX length register, only allowing CPU port here is enough. 1093 */ 1094 if (!dsa_is_cpu_port(ds, port)) 1095 return 0; 1096 1097 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1098 1099 val = mt7530_mii_read(priv, MT7530_GMACCR); 1100 val &= ~MAX_RX_PKT_LEN_MASK; 1101 1102 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1103 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1104 if (length <= 1522) { 1105 val |= MAX_RX_PKT_LEN_1522; 1106 } else if (length <= 1536) { 1107 val |= MAX_RX_PKT_LEN_1536; 1108 } else if (length <= 1552) { 1109 val |= MAX_RX_PKT_LEN_1552; 1110 } else { 1111 val &= ~MAX_RX_JUMBO_MASK; 1112 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1113 val |= MAX_RX_PKT_LEN_JUMBO; 1114 } 1115 1116 mt7530_mii_write(priv, MT7530_GMACCR, val); 1117 1118 mutex_unlock(&bus->mdio_lock); 1119 1120 return 0; 1121 } 1122 1123 static int 1124 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1125 { 1126 return MT7530_MAX_MTU; 1127 } 1128 1129 static void 1130 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1131 { 1132 struct mt7530_priv *priv = ds->priv; 1133 u32 stp_state; 1134 1135 switch (state) { 1136 case BR_STATE_DISABLED: 1137 stp_state = MT7530_STP_DISABLED; 1138 break; 1139 case BR_STATE_BLOCKING: 1140 stp_state = MT7530_STP_BLOCKING; 1141 break; 1142 case BR_STATE_LISTENING: 1143 stp_state = MT7530_STP_LISTENING; 1144 break; 1145 case BR_STATE_LEARNING: 1146 stp_state = MT7530_STP_LEARNING; 1147 break; 1148 case BR_STATE_FORWARDING: 1149 default: 1150 stp_state = MT7530_STP_FORWARDING; 1151 break; 1152 } 1153 1154 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1155 FID_PST(FID_BRIDGED, stp_state)); 1156 } 1157 1158 static int 1159 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1160 struct switchdev_brport_flags flags, 1161 struct netlink_ext_ack *extack) 1162 { 1163 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1164 BR_BCAST_FLOOD)) 1165 return -EINVAL; 1166 1167 return 0; 1168 } 1169 1170 static int 1171 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1172 struct switchdev_brport_flags flags, 1173 struct netlink_ext_ack *extack) 1174 { 1175 struct mt7530_priv *priv = ds->priv; 1176 1177 if (flags.mask & BR_LEARNING) 1178 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1179 flags.val & BR_LEARNING ? 0 : SA_DIS); 1180 1181 if (flags.mask & BR_FLOOD) 1182 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1183 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1184 1185 if (flags.mask & BR_MCAST_FLOOD) 1186 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1187 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1188 1189 if (flags.mask & BR_BCAST_FLOOD) 1190 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1191 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1192 1193 return 0; 1194 } 1195 1196 static int 1197 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1198 struct dsa_bridge bridge, bool *tx_fwd_offload, 1199 struct netlink_ext_ack *extack) 1200 { 1201 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1202 struct dsa_port *cpu_dp = dp->cpu_dp; 1203 u32 port_bitmap = BIT(cpu_dp->index); 1204 struct mt7530_priv *priv = ds->priv; 1205 1206 mutex_lock(&priv->reg_mutex); 1207 1208 dsa_switch_for_each_user_port(other_dp, ds) { 1209 int other_port = other_dp->index; 1210 1211 if (dp == other_dp) 1212 continue; 1213 1214 /* Add this port to the port matrix of the other ports in the 1215 * same bridge. If the port is disabled, port matrix is kept 1216 * and not being setup until the port becomes enabled. 1217 */ 1218 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1219 continue; 1220 1221 if (priv->ports[other_port].enable) 1222 mt7530_set(priv, MT7530_PCR_P(other_port), 1223 PCR_MATRIX(BIT(port))); 1224 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1225 1226 port_bitmap |= BIT(other_port); 1227 } 1228 1229 /* Add the all other ports to this port matrix. */ 1230 if (priv->ports[port].enable) 1231 mt7530_rmw(priv, MT7530_PCR_P(port), 1232 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1233 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1234 1235 /* Set to fallback mode for independent VLAN learning */ 1236 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1237 MT7530_PORT_FALLBACK_MODE); 1238 1239 mutex_unlock(&priv->reg_mutex); 1240 1241 return 0; 1242 } 1243 1244 static void 1245 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1246 { 1247 struct mt7530_priv *priv = ds->priv; 1248 bool all_user_ports_removed = true; 1249 int i; 1250 1251 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1252 * bridge. Don't set standalone ports to fallback mode. 1253 */ 1254 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1255 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1256 MT7530_PORT_FALLBACK_MODE); 1257 1258 mt7530_rmw(priv, MT7530_PVC_P(port), 1259 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1260 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1261 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1262 MT7530_VLAN_ACC_ALL); 1263 1264 /* Set PVID to 0 */ 1265 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1266 G0_PORT_VID_DEF); 1267 1268 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1269 if (dsa_is_user_port(ds, i) && 1270 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1271 all_user_ports_removed = false; 1272 break; 1273 } 1274 } 1275 1276 /* CPU port also does the same thing until all user ports belonging to 1277 * the CPU port get out of VLAN filtering mode. 1278 */ 1279 if (all_user_ports_removed) { 1280 struct dsa_port *dp = dsa_to_port(ds, port); 1281 struct dsa_port *cpu_dp = dp->cpu_dp; 1282 1283 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1284 PCR_MATRIX(dsa_user_ports(priv->ds))); 1285 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1286 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1287 } 1288 } 1289 1290 static void 1291 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1292 { 1293 struct mt7530_priv *priv = ds->priv; 1294 1295 /* Trapped into security mode allows packet forwarding through VLAN 1296 * table lookup. 1297 */ 1298 if (dsa_is_user_port(ds, port)) { 1299 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1300 MT7530_PORT_SECURITY_MODE); 1301 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1302 G0_PORT_VID(priv->ports[port].pvid)); 1303 1304 /* Only accept tagged frames if PVID is not set */ 1305 if (!priv->ports[port].pvid) 1306 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1307 MT7530_VLAN_ACC_TAGGED); 1308 1309 /* Set the port as a user port which is to be able to recognize 1310 * VID from incoming packets before fetching entry within the 1311 * VLAN table. 1312 */ 1313 mt7530_rmw(priv, MT7530_PVC_P(port), 1314 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1315 VLAN_ATTR(MT7530_VLAN_USER) | 1316 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1317 } else { 1318 /* Also set CPU ports to the "user" VLAN port attribute, to 1319 * allow VLAN classification, but keep the EG_TAG attribute as 1320 * "consistent" (i.o.w. don't change its value) for packets 1321 * received by the switch from the CPU, so that tagged packets 1322 * are forwarded to user ports as tagged, and untagged as 1323 * untagged. 1324 */ 1325 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1326 VLAN_ATTR(MT7530_VLAN_USER)); 1327 } 1328 } 1329 1330 static void 1331 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1332 struct dsa_bridge bridge) 1333 { 1334 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1335 struct dsa_port *cpu_dp = dp->cpu_dp; 1336 struct mt7530_priv *priv = ds->priv; 1337 1338 mutex_lock(&priv->reg_mutex); 1339 1340 dsa_switch_for_each_user_port(other_dp, ds) { 1341 int other_port = other_dp->index; 1342 1343 if (dp == other_dp) 1344 continue; 1345 1346 /* Remove this port from the port matrix of the other ports 1347 * in the same bridge. If the port is disabled, port matrix 1348 * is kept and not being setup until the port becomes enabled. 1349 */ 1350 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1351 continue; 1352 1353 if (priv->ports[other_port].enable) 1354 mt7530_clear(priv, MT7530_PCR_P(other_port), 1355 PCR_MATRIX(BIT(port))); 1356 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1357 } 1358 1359 /* Set the cpu port to be the only one in the port matrix of 1360 * this port. 1361 */ 1362 if (priv->ports[port].enable) 1363 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1364 PCR_MATRIX(BIT(cpu_dp->index))); 1365 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1366 1367 /* When a port is removed from the bridge, the port would be set up 1368 * back to the default as is at initial boot which is a VLAN-unaware 1369 * port. 1370 */ 1371 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1372 MT7530_PORT_MATRIX_MODE); 1373 1374 mutex_unlock(&priv->reg_mutex); 1375 } 1376 1377 static int 1378 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1379 const unsigned char *addr, u16 vid, 1380 struct dsa_db db) 1381 { 1382 struct mt7530_priv *priv = ds->priv; 1383 int ret; 1384 u8 port_mask = BIT(port); 1385 1386 mutex_lock(&priv->reg_mutex); 1387 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1388 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1389 mutex_unlock(&priv->reg_mutex); 1390 1391 return ret; 1392 } 1393 1394 static int 1395 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1396 const unsigned char *addr, u16 vid, 1397 struct dsa_db db) 1398 { 1399 struct mt7530_priv *priv = ds->priv; 1400 int ret; 1401 u8 port_mask = BIT(port); 1402 1403 mutex_lock(&priv->reg_mutex); 1404 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1405 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1406 mutex_unlock(&priv->reg_mutex); 1407 1408 return ret; 1409 } 1410 1411 static int 1412 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1413 dsa_fdb_dump_cb_t *cb, void *data) 1414 { 1415 struct mt7530_priv *priv = ds->priv; 1416 struct mt7530_fdb _fdb = { 0 }; 1417 int cnt = MT7530_NUM_FDB_RECORDS; 1418 int ret = 0; 1419 u32 rsp = 0; 1420 1421 mutex_lock(&priv->reg_mutex); 1422 1423 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1424 if (ret < 0) 1425 goto err; 1426 1427 do { 1428 if (rsp & ATC_SRCH_HIT) { 1429 mt7530_fdb_read(priv, &_fdb); 1430 if (_fdb.port_mask & BIT(port)) { 1431 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1432 data); 1433 if (ret < 0) 1434 break; 1435 } 1436 } 1437 } while (--cnt && 1438 !(rsp & ATC_SRCH_END) && 1439 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1440 err: 1441 mutex_unlock(&priv->reg_mutex); 1442 1443 return 0; 1444 } 1445 1446 static int 1447 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1448 const struct switchdev_obj_port_mdb *mdb, 1449 struct dsa_db db) 1450 { 1451 struct mt7530_priv *priv = ds->priv; 1452 const u8 *addr = mdb->addr; 1453 u16 vid = mdb->vid; 1454 u8 port_mask = 0; 1455 int ret; 1456 1457 mutex_lock(&priv->reg_mutex); 1458 1459 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1460 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1461 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1462 & PORT_MAP_MASK; 1463 1464 port_mask |= BIT(port); 1465 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1466 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1467 1468 mutex_unlock(&priv->reg_mutex); 1469 1470 return ret; 1471 } 1472 1473 static int 1474 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1475 const struct switchdev_obj_port_mdb *mdb, 1476 struct dsa_db db) 1477 { 1478 struct mt7530_priv *priv = ds->priv; 1479 const u8 *addr = mdb->addr; 1480 u16 vid = mdb->vid; 1481 u8 port_mask = 0; 1482 int ret; 1483 1484 mutex_lock(&priv->reg_mutex); 1485 1486 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1487 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1488 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1489 & PORT_MAP_MASK; 1490 1491 port_mask &= ~BIT(port); 1492 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1493 port_mask ? STATIC_ENT : STATIC_EMP); 1494 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1495 1496 mutex_unlock(&priv->reg_mutex); 1497 1498 return ret; 1499 } 1500 1501 static int 1502 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1503 { 1504 struct mt7530_dummy_poll p; 1505 u32 val; 1506 int ret; 1507 1508 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1509 mt7530_write(priv, MT7530_VTCR, val); 1510 1511 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1512 ret = readx_poll_timeout(_mt7530_read, &p, val, 1513 !(val & VTCR_BUSY), 20, 20000); 1514 if (ret < 0) { 1515 dev_err(priv->dev, "poll timeout\n"); 1516 return ret; 1517 } 1518 1519 val = mt7530_read(priv, MT7530_VTCR); 1520 if (val & VTCR_INVALID) { 1521 dev_err(priv->dev, "read VTCR invalid\n"); 1522 return -EINVAL; 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int 1529 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1530 struct netlink_ext_ack *extack) 1531 { 1532 struct dsa_port *dp = dsa_to_port(ds, port); 1533 struct dsa_port *cpu_dp = dp->cpu_dp; 1534 1535 if (vlan_filtering) { 1536 /* The port is being kept as VLAN-unaware port when bridge is 1537 * set up with vlan_filtering not being set, Otherwise, the 1538 * port and the corresponding CPU port is required the setup 1539 * for becoming a VLAN-aware port. 1540 */ 1541 mt7530_port_set_vlan_aware(ds, port); 1542 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1543 } else { 1544 mt7530_port_set_vlan_unaware(ds, port); 1545 } 1546 1547 return 0; 1548 } 1549 1550 static void 1551 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1552 struct mt7530_hw_vlan_entry *entry) 1553 { 1554 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1555 u8 new_members; 1556 u32 val; 1557 1558 new_members = entry->old_members | BIT(entry->port); 1559 1560 /* Validate the entry with independent learning, create egress tag per 1561 * VLAN and joining the port as one of the port members. 1562 */ 1563 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1564 VLAN_VALID; 1565 mt7530_write(priv, MT7530_VAWD1, val); 1566 1567 /* Decide whether adding tag or not for those outgoing packets from the 1568 * port inside the VLAN. 1569 * CPU port is always taken as a tagged port for serving more than one 1570 * VLANs across and also being applied with egress type stack mode for 1571 * that VLAN tags would be appended after hardware special tag used as 1572 * DSA tag. 1573 */ 1574 if (dsa_port_is_cpu(dp)) 1575 val = MT7530_VLAN_EGRESS_STACK; 1576 else if (entry->untagged) 1577 val = MT7530_VLAN_EGRESS_UNTAG; 1578 else 1579 val = MT7530_VLAN_EGRESS_TAG; 1580 mt7530_rmw(priv, MT7530_VAWD2, 1581 ETAG_CTRL_P_MASK(entry->port), 1582 ETAG_CTRL_P(entry->port, val)); 1583 } 1584 1585 static void 1586 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1587 struct mt7530_hw_vlan_entry *entry) 1588 { 1589 u8 new_members; 1590 u32 val; 1591 1592 new_members = entry->old_members & ~BIT(entry->port); 1593 1594 val = mt7530_read(priv, MT7530_VAWD1); 1595 if (!(val & VLAN_VALID)) { 1596 dev_err(priv->dev, 1597 "Cannot be deleted due to invalid entry\n"); 1598 return; 1599 } 1600 1601 if (new_members) { 1602 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1603 VLAN_VALID; 1604 mt7530_write(priv, MT7530_VAWD1, val); 1605 } else { 1606 mt7530_write(priv, MT7530_VAWD1, 0); 1607 mt7530_write(priv, MT7530_VAWD2, 0); 1608 } 1609 } 1610 1611 static void 1612 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1613 struct mt7530_hw_vlan_entry *entry, 1614 mt7530_vlan_op vlan_op) 1615 { 1616 u32 val; 1617 1618 /* Fetch entry */ 1619 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1620 1621 val = mt7530_read(priv, MT7530_VAWD1); 1622 1623 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1624 1625 /* Manipulate entry */ 1626 vlan_op(priv, entry); 1627 1628 /* Flush result to hardware */ 1629 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1630 } 1631 1632 static int 1633 mt7530_setup_vlan0(struct mt7530_priv *priv) 1634 { 1635 u32 val; 1636 1637 /* Validate the entry with independent learning, keep the original 1638 * ingress tag attribute. 1639 */ 1640 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1641 VLAN_VALID; 1642 mt7530_write(priv, MT7530_VAWD1, val); 1643 1644 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1645 } 1646 1647 static int 1648 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1649 const struct switchdev_obj_port_vlan *vlan, 1650 struct netlink_ext_ack *extack) 1651 { 1652 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1653 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1654 struct mt7530_hw_vlan_entry new_entry; 1655 struct mt7530_priv *priv = ds->priv; 1656 1657 mutex_lock(&priv->reg_mutex); 1658 1659 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1660 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1661 1662 if (pvid) { 1663 priv->ports[port].pvid = vlan->vid; 1664 1665 /* Accept all frames if PVID is set */ 1666 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1667 MT7530_VLAN_ACC_ALL); 1668 1669 /* Only configure PVID if VLAN filtering is enabled */ 1670 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1671 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1672 G0_PORT_VID_MASK, 1673 G0_PORT_VID(vlan->vid)); 1674 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1675 /* This VLAN is overwritten without PVID, so unset it */ 1676 priv->ports[port].pvid = G0_PORT_VID_DEF; 1677 1678 /* Only accept tagged frames if the port is VLAN-aware */ 1679 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1680 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1681 MT7530_VLAN_ACC_TAGGED); 1682 1683 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1684 G0_PORT_VID_DEF); 1685 } 1686 1687 mutex_unlock(&priv->reg_mutex); 1688 1689 return 0; 1690 } 1691 1692 static int 1693 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1694 const struct switchdev_obj_port_vlan *vlan) 1695 { 1696 struct mt7530_hw_vlan_entry target_entry; 1697 struct mt7530_priv *priv = ds->priv; 1698 1699 mutex_lock(&priv->reg_mutex); 1700 1701 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1702 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1703 mt7530_hw_vlan_del); 1704 1705 /* PVID is being restored to the default whenever the PVID port 1706 * is being removed from the VLAN. 1707 */ 1708 if (priv->ports[port].pvid == vlan->vid) { 1709 priv->ports[port].pvid = G0_PORT_VID_DEF; 1710 1711 /* Only accept tagged frames if the port is VLAN-aware */ 1712 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1713 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1714 MT7530_VLAN_ACC_TAGGED); 1715 1716 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1717 G0_PORT_VID_DEF); 1718 } 1719 1720 1721 mutex_unlock(&priv->reg_mutex); 1722 1723 return 0; 1724 } 1725 1726 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1727 { 1728 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1729 MIRROR_PORT(val); 1730 } 1731 1732 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1733 { 1734 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1735 MIRROR_PORT(val); 1736 } 1737 1738 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1739 struct dsa_mall_mirror_tc_entry *mirror, 1740 bool ingress, struct netlink_ext_ack *extack) 1741 { 1742 struct mt7530_priv *priv = ds->priv; 1743 int monitor_port; 1744 u32 val; 1745 1746 /* Check for existent entry */ 1747 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1748 return -EEXIST; 1749 1750 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1751 1752 /* MT7530 only supports one monitor port */ 1753 monitor_port = mt753x_mirror_port_get(priv->id, val); 1754 if (val & MT753X_MIRROR_EN(priv->id) && 1755 monitor_port != mirror->to_local_port) 1756 return -EEXIST; 1757 1758 val |= MT753X_MIRROR_EN(priv->id); 1759 val &= ~MT753X_MIRROR_MASK(priv->id); 1760 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1761 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1762 1763 val = mt7530_read(priv, MT7530_PCR_P(port)); 1764 if (ingress) { 1765 val |= PORT_RX_MIR; 1766 priv->mirror_rx |= BIT(port); 1767 } else { 1768 val |= PORT_TX_MIR; 1769 priv->mirror_tx |= BIT(port); 1770 } 1771 mt7530_write(priv, MT7530_PCR_P(port), val); 1772 1773 return 0; 1774 } 1775 1776 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1777 struct dsa_mall_mirror_tc_entry *mirror) 1778 { 1779 struct mt7530_priv *priv = ds->priv; 1780 u32 val; 1781 1782 val = mt7530_read(priv, MT7530_PCR_P(port)); 1783 if (mirror->ingress) { 1784 val &= ~PORT_RX_MIR; 1785 priv->mirror_rx &= ~BIT(port); 1786 } else { 1787 val &= ~PORT_TX_MIR; 1788 priv->mirror_tx &= ~BIT(port); 1789 } 1790 mt7530_write(priv, MT7530_PCR_P(port), val); 1791 1792 if (!priv->mirror_rx && !priv->mirror_tx) { 1793 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1794 val &= ~MT753X_MIRROR_EN(priv->id); 1795 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1796 } 1797 } 1798 1799 static enum dsa_tag_protocol 1800 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1801 enum dsa_tag_protocol mp) 1802 { 1803 return DSA_TAG_PROTO_MTK; 1804 } 1805 1806 #ifdef CONFIG_GPIOLIB 1807 static inline u32 1808 mt7530_gpio_to_bit(unsigned int offset) 1809 { 1810 /* Map GPIO offset to register bit 1811 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1812 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1813 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1814 * [14:12] port 3 LED 0..2 as GPIO 9..11 1815 * [18:16] port 4 LED 0..2 as GPIO 12..14 1816 */ 1817 return BIT(offset + offset / 3); 1818 } 1819 1820 static int 1821 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1822 { 1823 struct mt7530_priv *priv = gpiochip_get_data(gc); 1824 u32 bit = mt7530_gpio_to_bit(offset); 1825 1826 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1827 } 1828 1829 static void 1830 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1831 { 1832 struct mt7530_priv *priv = gpiochip_get_data(gc); 1833 u32 bit = mt7530_gpio_to_bit(offset); 1834 1835 if (value) 1836 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1837 else 1838 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1839 } 1840 1841 static int 1842 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1843 { 1844 struct mt7530_priv *priv = gpiochip_get_data(gc); 1845 u32 bit = mt7530_gpio_to_bit(offset); 1846 1847 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1848 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1849 } 1850 1851 static int 1852 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1853 { 1854 struct mt7530_priv *priv = gpiochip_get_data(gc); 1855 u32 bit = mt7530_gpio_to_bit(offset); 1856 1857 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1858 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1859 1860 return 0; 1861 } 1862 1863 static int 1864 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1865 { 1866 struct mt7530_priv *priv = gpiochip_get_data(gc); 1867 u32 bit = mt7530_gpio_to_bit(offset); 1868 1869 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1870 1871 if (value) 1872 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1873 else 1874 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1875 1876 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1877 1878 return 0; 1879 } 1880 1881 static int 1882 mt7530_setup_gpio(struct mt7530_priv *priv) 1883 { 1884 struct device *dev = priv->dev; 1885 struct gpio_chip *gc; 1886 1887 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1888 if (!gc) 1889 return -ENOMEM; 1890 1891 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1892 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1893 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1894 1895 gc->label = "mt7530"; 1896 gc->parent = dev; 1897 gc->owner = THIS_MODULE; 1898 gc->get_direction = mt7530_gpio_get_direction; 1899 gc->direction_input = mt7530_gpio_direction_input; 1900 gc->direction_output = mt7530_gpio_direction_output; 1901 gc->get = mt7530_gpio_get; 1902 gc->set = mt7530_gpio_set; 1903 gc->base = -1; 1904 gc->ngpio = 15; 1905 gc->can_sleep = true; 1906 1907 return devm_gpiochip_add_data(dev, gc, priv); 1908 } 1909 #endif /* CONFIG_GPIOLIB */ 1910 1911 static irqreturn_t 1912 mt7530_irq_thread_fn(int irq, void *dev_id) 1913 { 1914 struct mt7530_priv *priv = dev_id; 1915 bool handled = false; 1916 u32 val; 1917 int p; 1918 1919 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1920 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1921 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1922 mutex_unlock(&priv->bus->mdio_lock); 1923 1924 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1925 if (BIT(p) & val) { 1926 unsigned int irq; 1927 1928 irq = irq_find_mapping(priv->irq_domain, p); 1929 handle_nested_irq(irq); 1930 handled = true; 1931 } 1932 } 1933 1934 return IRQ_RETVAL(handled); 1935 } 1936 1937 static void 1938 mt7530_irq_mask(struct irq_data *d) 1939 { 1940 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1941 1942 priv->irq_enable &= ~BIT(d->hwirq); 1943 } 1944 1945 static void 1946 mt7530_irq_unmask(struct irq_data *d) 1947 { 1948 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1949 1950 priv->irq_enable |= BIT(d->hwirq); 1951 } 1952 1953 static void 1954 mt7530_irq_bus_lock(struct irq_data *d) 1955 { 1956 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1957 1958 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1959 } 1960 1961 static void 1962 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1963 { 1964 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1965 1966 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1967 mutex_unlock(&priv->bus->mdio_lock); 1968 } 1969 1970 static struct irq_chip mt7530_irq_chip = { 1971 .name = KBUILD_MODNAME, 1972 .irq_mask = mt7530_irq_mask, 1973 .irq_unmask = mt7530_irq_unmask, 1974 .irq_bus_lock = mt7530_irq_bus_lock, 1975 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1976 }; 1977 1978 static int 1979 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1980 irq_hw_number_t hwirq) 1981 { 1982 irq_set_chip_data(irq, domain->host_data); 1983 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1984 irq_set_nested_thread(irq, true); 1985 irq_set_noprobe(irq); 1986 1987 return 0; 1988 } 1989 1990 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1991 .map = mt7530_irq_map, 1992 .xlate = irq_domain_xlate_onecell, 1993 }; 1994 1995 static void 1996 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1997 { 1998 struct dsa_switch *ds = priv->ds; 1999 int p; 2000 2001 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2002 if (BIT(p) & ds->phys_mii_mask) { 2003 unsigned int irq; 2004 2005 irq = irq_create_mapping(priv->irq_domain, p); 2006 ds->slave_mii_bus->irq[p] = irq; 2007 } 2008 } 2009 } 2010 2011 static int 2012 mt7530_setup_irq(struct mt7530_priv *priv) 2013 { 2014 struct device *dev = priv->dev; 2015 struct device_node *np = dev->of_node; 2016 int ret; 2017 2018 if (!of_property_read_bool(np, "interrupt-controller")) { 2019 dev_info(dev, "no interrupt support\n"); 2020 return 0; 2021 } 2022 2023 priv->irq = of_irq_get(np, 0); 2024 if (priv->irq <= 0) { 2025 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2026 return priv->irq ? : -EINVAL; 2027 } 2028 2029 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2030 &mt7530_irq_domain_ops, priv); 2031 if (!priv->irq_domain) { 2032 dev_err(dev, "failed to create IRQ domain\n"); 2033 return -ENOMEM; 2034 } 2035 2036 /* This register must be set for MT7530 to properly fire interrupts */ 2037 if (priv->id != ID_MT7531) 2038 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2039 2040 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2041 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2042 if (ret) { 2043 irq_domain_remove(priv->irq_domain); 2044 dev_err(dev, "failed to request IRQ: %d\n", ret); 2045 return ret; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static void 2052 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2053 { 2054 int p; 2055 2056 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2057 if (BIT(p) & priv->ds->phys_mii_mask) { 2058 unsigned int irq; 2059 2060 irq = irq_find_mapping(priv->irq_domain, p); 2061 irq_dispose_mapping(irq); 2062 } 2063 } 2064 } 2065 2066 static void 2067 mt7530_free_irq_common(struct mt7530_priv *priv) 2068 { 2069 free_irq(priv->irq, priv); 2070 irq_domain_remove(priv->irq_domain); 2071 } 2072 2073 static void 2074 mt7530_free_irq(struct mt7530_priv *priv) 2075 { 2076 mt7530_free_mdio_irq(priv); 2077 mt7530_free_irq_common(priv); 2078 } 2079 2080 static int 2081 mt7530_setup_mdio(struct mt7530_priv *priv) 2082 { 2083 struct dsa_switch *ds = priv->ds; 2084 struct device *dev = priv->dev; 2085 struct mii_bus *bus; 2086 static int idx; 2087 int ret; 2088 2089 bus = devm_mdiobus_alloc(dev); 2090 if (!bus) 2091 return -ENOMEM; 2092 2093 ds->slave_mii_bus = bus; 2094 bus->priv = priv; 2095 bus->name = KBUILD_MODNAME "-mii"; 2096 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2097 bus->read = mt753x_phy_read_c22; 2098 bus->write = mt753x_phy_write_c22; 2099 bus->read_c45 = mt753x_phy_read_c45; 2100 bus->write_c45 = mt753x_phy_write_c45; 2101 bus->parent = dev; 2102 bus->phy_mask = ~ds->phys_mii_mask; 2103 2104 if (priv->irq) 2105 mt7530_setup_mdio_irq(priv); 2106 2107 ret = devm_mdiobus_register(dev, bus); 2108 if (ret) { 2109 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2110 if (priv->irq) 2111 mt7530_free_mdio_irq(priv); 2112 } 2113 2114 return ret; 2115 } 2116 2117 static int 2118 mt7530_setup(struct dsa_switch *ds) 2119 { 2120 struct mt7530_priv *priv = ds->priv; 2121 struct device_node *dn = NULL; 2122 struct device_node *phy_node; 2123 struct device_node *mac_np; 2124 struct mt7530_dummy_poll p; 2125 phy_interface_t interface; 2126 struct dsa_port *cpu_dp; 2127 u32 id, val; 2128 int ret, i; 2129 2130 /* The parent node of master netdev which holds the common system 2131 * controller also is the container for two GMACs nodes representing 2132 * as two netdev instances. 2133 */ 2134 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2135 dn = cpu_dp->master->dev.of_node->parent; 2136 /* It doesn't matter which CPU port is found first, 2137 * their masters should share the same parent OF node 2138 */ 2139 break; 2140 } 2141 2142 if (!dn) { 2143 dev_err(ds->dev, "parent OF node of DSA master not found"); 2144 return -EINVAL; 2145 } 2146 2147 ds->assisted_learning_on_cpu_port = true; 2148 ds->mtu_enforcement_ingress = true; 2149 2150 if (priv->id == ID_MT7530) { 2151 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2152 ret = regulator_enable(priv->core_pwr); 2153 if (ret < 0) { 2154 dev_err(priv->dev, 2155 "Failed to enable core power: %d\n", ret); 2156 return ret; 2157 } 2158 2159 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2160 ret = regulator_enable(priv->io_pwr); 2161 if (ret < 0) { 2162 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2163 ret); 2164 return ret; 2165 } 2166 } 2167 2168 /* Reset whole chip through gpio pin or memory-mapped registers for 2169 * different type of hardware 2170 */ 2171 if (priv->mcm) { 2172 reset_control_assert(priv->rstc); 2173 usleep_range(1000, 1100); 2174 reset_control_deassert(priv->rstc); 2175 } else { 2176 gpiod_set_value_cansleep(priv->reset, 0); 2177 usleep_range(1000, 1100); 2178 gpiod_set_value_cansleep(priv->reset, 1); 2179 } 2180 2181 /* Waiting for MT7530 got to stable */ 2182 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2183 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2184 20, 1000000); 2185 if (ret < 0) { 2186 dev_err(priv->dev, "reset timeout\n"); 2187 return ret; 2188 } 2189 2190 id = mt7530_read(priv, MT7530_CREV); 2191 id >>= CHIP_NAME_SHIFT; 2192 if (id != MT7530_ID) { 2193 dev_err(priv->dev, "chip %x can't be supported\n", id); 2194 return -ENODEV; 2195 } 2196 2197 /* Reset the switch through internal reset */ 2198 mt7530_write(priv, MT7530_SYS_CTRL, 2199 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2200 SYS_CTRL_REG_RST); 2201 2202 mt7530_pll_setup(priv); 2203 2204 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2205 val = mt7530_read(priv, MT7530_MHWTRAP); 2206 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2207 val |= MHWTRAP_MANUAL; 2208 mt7530_write(priv, MT7530_MHWTRAP, val); 2209 2210 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2211 2212 /* Enable and reset MIB counters */ 2213 mt7530_mib_reset(ds); 2214 2215 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2216 /* Disable forwarding by default on all ports */ 2217 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2218 PCR_MATRIX_CLR); 2219 2220 /* Disable learning by default on all ports */ 2221 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2222 2223 if (dsa_is_cpu_port(ds, i)) { 2224 ret = mt753x_cpu_port_enable(ds, i); 2225 if (ret) 2226 return ret; 2227 } else { 2228 mt7530_port_disable(ds, i); 2229 2230 /* Set default PVID to 0 on all user ports */ 2231 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2232 G0_PORT_VID_DEF); 2233 } 2234 /* Enable consistent egress tag */ 2235 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2236 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2237 } 2238 2239 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2240 ret = mt7530_setup_vlan0(priv); 2241 if (ret) 2242 return ret; 2243 2244 /* Setup port 5 */ 2245 priv->p5_intf_sel = P5_DISABLED; 2246 interface = PHY_INTERFACE_MODE_NA; 2247 2248 if (!dsa_is_unused_port(ds, 5)) { 2249 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2250 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2251 if (ret && ret != -ENODEV) 2252 return ret; 2253 } else { 2254 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2255 for_each_child_of_node(dn, mac_np) { 2256 if (!of_device_is_compatible(mac_np, 2257 "mediatek,eth-mac")) 2258 continue; 2259 2260 ret = of_property_read_u32(mac_np, "reg", &id); 2261 if (ret < 0 || id != 1) 2262 continue; 2263 2264 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2265 if (!phy_node) 2266 continue; 2267 2268 if (phy_node->parent == priv->dev->of_node->parent) { 2269 ret = of_get_phy_mode(mac_np, &interface); 2270 if (ret && ret != -ENODEV) { 2271 of_node_put(mac_np); 2272 of_node_put(phy_node); 2273 return ret; 2274 } 2275 id = of_mdio_parse_addr(ds->dev, phy_node); 2276 if (id == 0) 2277 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2278 if (id == 4) 2279 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2280 } 2281 of_node_put(mac_np); 2282 of_node_put(phy_node); 2283 break; 2284 } 2285 } 2286 2287 #ifdef CONFIG_GPIOLIB 2288 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2289 ret = mt7530_setup_gpio(priv); 2290 if (ret) 2291 return ret; 2292 } 2293 #endif /* CONFIG_GPIOLIB */ 2294 2295 mt7530_setup_port5(ds, interface); 2296 2297 /* Flush the FDB table */ 2298 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2299 if (ret < 0) 2300 return ret; 2301 2302 return 0; 2303 } 2304 2305 static int 2306 mt7531_setup(struct dsa_switch *ds) 2307 { 2308 struct mt7530_priv *priv = ds->priv; 2309 struct mt7530_dummy_poll p; 2310 struct dsa_port *cpu_dp; 2311 u32 val, id; 2312 int ret, i; 2313 2314 /* Reset whole chip through gpio pin or memory-mapped registers for 2315 * different type of hardware 2316 */ 2317 if (priv->mcm) { 2318 reset_control_assert(priv->rstc); 2319 usleep_range(1000, 1100); 2320 reset_control_deassert(priv->rstc); 2321 } else { 2322 gpiod_set_value_cansleep(priv->reset, 0); 2323 usleep_range(1000, 1100); 2324 gpiod_set_value_cansleep(priv->reset, 1); 2325 } 2326 2327 /* Waiting for MT7530 got to stable */ 2328 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2329 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2330 20, 1000000); 2331 if (ret < 0) { 2332 dev_err(priv->dev, "reset timeout\n"); 2333 return ret; 2334 } 2335 2336 id = mt7530_read(priv, MT7531_CREV); 2337 id >>= CHIP_NAME_SHIFT; 2338 2339 if (id != MT7531_ID) { 2340 dev_err(priv->dev, "chip %x can't be supported\n", id); 2341 return -ENODEV; 2342 } 2343 2344 /* all MACs must be forced link-down before sw reset */ 2345 for (i = 0; i < MT7530_NUM_PORTS; i++) 2346 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2347 2348 /* Reset the switch through internal reset */ 2349 mt7530_write(priv, MT7530_SYS_CTRL, 2350 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2351 SYS_CTRL_REG_RST); 2352 2353 mt7531_pll_setup(priv); 2354 2355 if (mt7531_dual_sgmii_supported(priv)) { 2356 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2357 2358 /* Let ds->slave_mii_bus be able to access external phy. */ 2359 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2360 MT7531_EXT_P_MDC_11); 2361 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2362 MT7531_EXT_P_MDIO_12); 2363 } else { 2364 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2365 } 2366 dev_dbg(ds->dev, "P5 support %s interface\n", 2367 p5_intf_modes(priv->p5_intf_sel)); 2368 2369 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2370 MT7531_GPIO0_INTERRUPT); 2371 2372 /* Let phylink decide the interface later. */ 2373 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2374 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2375 2376 /* Enable PHY core PLL, since phy_device has not yet been created 2377 * provided for phy_[read,write]_mmd_indirect is called, we provide 2378 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2379 * function. 2380 */ 2381 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2382 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2383 val |= MT7531_PHY_PLL_BYPASS_MODE; 2384 val &= ~MT7531_PHY_PLL_OFF; 2385 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2386 CORE_PLL_GROUP4, val); 2387 2388 /* BPDU to CPU port */ 2389 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2390 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2391 BIT(cpu_dp->index)); 2392 break; 2393 } 2394 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2395 MT753X_BPDU_CPU_ONLY); 2396 2397 /* Enable and reset MIB counters */ 2398 mt7530_mib_reset(ds); 2399 2400 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2401 /* Disable forwarding by default on all ports */ 2402 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2403 PCR_MATRIX_CLR); 2404 2405 /* Disable learning by default on all ports */ 2406 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2407 2408 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2409 2410 if (dsa_is_cpu_port(ds, i)) { 2411 ret = mt753x_cpu_port_enable(ds, i); 2412 if (ret) 2413 return ret; 2414 } else { 2415 mt7530_port_disable(ds, i); 2416 2417 /* Set default PVID to 0 on all user ports */ 2418 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2419 G0_PORT_VID_DEF); 2420 } 2421 2422 /* Enable consistent egress tag */ 2423 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2424 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2425 } 2426 2427 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2428 ret = mt7530_setup_vlan0(priv); 2429 if (ret) 2430 return ret; 2431 2432 ds->assisted_learning_on_cpu_port = true; 2433 ds->mtu_enforcement_ingress = true; 2434 2435 /* Flush the FDB table */ 2436 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2437 if (ret < 0) 2438 return ret; 2439 2440 return 0; 2441 } 2442 2443 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2444 struct phylink_config *config) 2445 { 2446 switch (port) { 2447 case 0 ... 4: /* Internal phy */ 2448 __set_bit(PHY_INTERFACE_MODE_GMII, 2449 config->supported_interfaces); 2450 break; 2451 2452 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2453 phy_interface_set_rgmii(config->supported_interfaces); 2454 __set_bit(PHY_INTERFACE_MODE_MII, 2455 config->supported_interfaces); 2456 __set_bit(PHY_INTERFACE_MODE_GMII, 2457 config->supported_interfaces); 2458 break; 2459 2460 case 6: /* 1st cpu port */ 2461 __set_bit(PHY_INTERFACE_MODE_RGMII, 2462 config->supported_interfaces); 2463 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2464 config->supported_interfaces); 2465 break; 2466 } 2467 } 2468 2469 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2470 { 2471 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2472 } 2473 2474 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2475 struct phylink_config *config) 2476 { 2477 struct mt7530_priv *priv = ds->priv; 2478 2479 switch (port) { 2480 case 0 ... 4: /* Internal phy */ 2481 __set_bit(PHY_INTERFACE_MODE_GMII, 2482 config->supported_interfaces); 2483 break; 2484 2485 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2486 if (mt7531_is_rgmii_port(priv, port)) { 2487 phy_interface_set_rgmii(config->supported_interfaces); 2488 break; 2489 } 2490 fallthrough; 2491 2492 case 6: /* 1st cpu port supports sgmii/8023z only */ 2493 __set_bit(PHY_INTERFACE_MODE_SGMII, 2494 config->supported_interfaces); 2495 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2496 config->supported_interfaces); 2497 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2498 config->supported_interfaces); 2499 2500 config->mac_capabilities |= MAC_2500FD; 2501 break; 2502 } 2503 } 2504 2505 static int 2506 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2507 { 2508 struct mt7530_priv *priv = ds->priv; 2509 2510 return priv->info->pad_setup(ds, state->interface); 2511 } 2512 2513 static int 2514 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2515 phy_interface_t interface) 2516 { 2517 struct mt7530_priv *priv = ds->priv; 2518 2519 /* Only need to setup port5. */ 2520 if (port != 5) 2521 return 0; 2522 2523 mt7530_setup_port5(priv->ds, interface); 2524 2525 return 0; 2526 } 2527 2528 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2529 phy_interface_t interface, 2530 struct phy_device *phydev) 2531 { 2532 u32 val; 2533 2534 if (!mt7531_is_rgmii_port(priv, port)) { 2535 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2536 port); 2537 return -EINVAL; 2538 } 2539 2540 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2541 val |= GP_CLK_EN; 2542 val &= ~GP_MODE_MASK; 2543 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2544 val &= ~CLK_SKEW_IN_MASK; 2545 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2546 val &= ~CLK_SKEW_OUT_MASK; 2547 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2548 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2549 2550 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2551 if (!phydev || phy_driver_is_genphy(phydev)) { 2552 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2553 switch (interface) { 2554 case PHY_INTERFACE_MODE_RGMII: 2555 val |= TXCLK_NO_REVERSE; 2556 val |= RXCLK_NO_DELAY; 2557 break; 2558 case PHY_INTERFACE_MODE_RGMII_RXID: 2559 val |= TXCLK_NO_REVERSE; 2560 break; 2561 case PHY_INTERFACE_MODE_RGMII_TXID: 2562 val |= RXCLK_NO_DELAY; 2563 break; 2564 case PHY_INTERFACE_MODE_RGMII_ID: 2565 break; 2566 default: 2567 return -EINVAL; 2568 } 2569 } 2570 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2571 2572 return 0; 2573 } 2574 2575 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 2576 phy_interface_t interface, int speed, int duplex) 2577 { 2578 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2579 int port = pcs_to_mt753x_pcs(pcs)->port; 2580 unsigned int val; 2581 2582 /* For adjusting speed and duplex of SGMII force mode. */ 2583 if (interface != PHY_INTERFACE_MODE_SGMII || 2584 phylink_autoneg_inband(mode)) 2585 return; 2586 2587 /* SGMII force mode setting */ 2588 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2589 val &= ~MT7531_SGMII_IF_MODE_MASK; 2590 2591 switch (speed) { 2592 case SPEED_10: 2593 val |= MT7531_SGMII_FORCE_SPEED_10; 2594 break; 2595 case SPEED_100: 2596 val |= MT7531_SGMII_FORCE_SPEED_100; 2597 break; 2598 case SPEED_1000: 2599 val |= MT7531_SGMII_FORCE_SPEED_1000; 2600 break; 2601 } 2602 2603 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2604 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2605 * 2606 * The speed check is unnecessary as the MAC capabilities apply 2607 * this restriction. --rmk 2608 */ 2609 if ((speed == SPEED_10 || speed == SPEED_100) && 2610 duplex != DUPLEX_FULL) 2611 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2612 2613 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2614 } 2615 2616 static bool mt753x_is_mac_port(u32 port) 2617 { 2618 return (port == 5 || port == 6); 2619 } 2620 2621 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2622 phy_interface_t interface) 2623 { 2624 u32 val; 2625 2626 if (!mt753x_is_mac_port(port)) 2627 return -EINVAL; 2628 2629 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2630 MT7531_SGMII_PHYA_PWD); 2631 2632 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2633 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2634 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2635 * encoding. 2636 */ 2637 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2638 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2639 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2640 2641 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2642 2643 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2644 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2645 */ 2646 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2647 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2648 MT7531_SGMII_FORCE_SPEED_1000); 2649 2650 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2651 2652 return 0; 2653 } 2654 2655 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2656 phy_interface_t interface) 2657 { 2658 if (!mt753x_is_mac_port(port)) 2659 return -EINVAL; 2660 2661 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2662 MT7531_SGMII_PHYA_PWD); 2663 2664 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2665 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2666 2667 mt7530_set(priv, MT7531_SGMII_MODE(port), 2668 MT7531_SGMII_REMOTE_FAULT_DIS | 2669 MT7531_SGMII_SPEED_DUPLEX_AN); 2670 2671 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2672 MT7531_SGMII_TX_CONFIG_MASK, 1); 2673 2674 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2675 2676 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2677 2678 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2679 2680 return 0; 2681 } 2682 2683 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) 2684 { 2685 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2686 int port = pcs_to_mt753x_pcs(pcs)->port; 2687 u32 val; 2688 2689 /* Only restart AN when AN is enabled */ 2690 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2691 if (val & MT7531_SGMII_AN_ENABLE) { 2692 val |= MT7531_SGMII_AN_RESTART; 2693 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2694 } 2695 } 2696 2697 static int 2698 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2699 phy_interface_t interface) 2700 { 2701 struct mt7530_priv *priv = ds->priv; 2702 struct phy_device *phydev; 2703 struct dsa_port *dp; 2704 2705 if (!mt753x_is_mac_port(port)) { 2706 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2707 return -EINVAL; 2708 } 2709 2710 switch (interface) { 2711 case PHY_INTERFACE_MODE_RGMII: 2712 case PHY_INTERFACE_MODE_RGMII_ID: 2713 case PHY_INTERFACE_MODE_RGMII_RXID: 2714 case PHY_INTERFACE_MODE_RGMII_TXID: 2715 dp = dsa_to_port(ds, port); 2716 phydev = dp->slave->phydev; 2717 return mt7531_rgmii_setup(priv, port, interface, phydev); 2718 case PHY_INTERFACE_MODE_SGMII: 2719 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2720 case PHY_INTERFACE_MODE_NA: 2721 case PHY_INTERFACE_MODE_1000BASEX: 2722 case PHY_INTERFACE_MODE_2500BASEX: 2723 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2724 default: 2725 return -EINVAL; 2726 } 2727 2728 return -EINVAL; 2729 } 2730 2731 static int 2732 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2733 const struct phylink_link_state *state) 2734 { 2735 struct mt7530_priv *priv = ds->priv; 2736 2737 return priv->info->mac_port_config(ds, port, mode, state->interface); 2738 } 2739 2740 static struct phylink_pcs * 2741 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2742 phy_interface_t interface) 2743 { 2744 struct mt7530_priv *priv = ds->priv; 2745 2746 switch (interface) { 2747 case PHY_INTERFACE_MODE_TRGMII: 2748 case PHY_INTERFACE_MODE_SGMII: 2749 case PHY_INTERFACE_MODE_1000BASEX: 2750 case PHY_INTERFACE_MODE_2500BASEX: 2751 return &priv->pcs[port].pcs; 2752 2753 default: 2754 return NULL; 2755 } 2756 } 2757 2758 static void 2759 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2760 const struct phylink_link_state *state) 2761 { 2762 struct mt7530_priv *priv = ds->priv; 2763 u32 mcr_cur, mcr_new; 2764 2765 switch (port) { 2766 case 0 ... 4: /* Internal phy */ 2767 if (state->interface != PHY_INTERFACE_MODE_GMII) 2768 goto unsupported; 2769 break; 2770 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2771 if (priv->p5_interface == state->interface) 2772 break; 2773 2774 if (mt753x_mac_config(ds, port, mode, state) < 0) 2775 goto unsupported; 2776 2777 if (priv->p5_intf_sel != P5_DISABLED) 2778 priv->p5_interface = state->interface; 2779 break; 2780 case 6: /* 1st cpu port */ 2781 if (priv->p6_interface == state->interface) 2782 break; 2783 2784 mt753x_pad_setup(ds, state); 2785 2786 if (mt753x_mac_config(ds, port, mode, state) < 0) 2787 goto unsupported; 2788 2789 priv->p6_interface = state->interface; 2790 break; 2791 default: 2792 unsupported: 2793 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2794 __func__, phy_modes(state->interface), port); 2795 return; 2796 } 2797 2798 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2799 mcr_new = mcr_cur; 2800 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2801 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2802 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2803 2804 /* Are we connected to external phy */ 2805 if (port == 5 && dsa_is_user_port(ds, 5)) 2806 mcr_new |= PMCR_EXT_PHY; 2807 2808 if (mcr_new != mcr_cur) 2809 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2810 } 2811 2812 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2813 unsigned int mode, 2814 phy_interface_t interface) 2815 { 2816 struct mt7530_priv *priv = ds->priv; 2817 2818 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2819 } 2820 2821 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2822 unsigned int mode, 2823 phy_interface_t interface, 2824 int speed, int duplex) 2825 { 2826 if (pcs->ops->pcs_link_up) 2827 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2828 } 2829 2830 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2831 unsigned int mode, 2832 phy_interface_t interface, 2833 struct phy_device *phydev, 2834 int speed, int duplex, 2835 bool tx_pause, bool rx_pause) 2836 { 2837 struct mt7530_priv *priv = ds->priv; 2838 u32 mcr; 2839 2840 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2841 2842 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2843 * variants. 2844 */ 2845 if (interface == PHY_INTERFACE_MODE_TRGMII || 2846 (phy_interface_mode_is_8023z(interface))) { 2847 speed = SPEED_1000; 2848 duplex = DUPLEX_FULL; 2849 } 2850 2851 switch (speed) { 2852 case SPEED_1000: 2853 mcr |= PMCR_FORCE_SPEED_1000; 2854 break; 2855 case SPEED_100: 2856 mcr |= PMCR_FORCE_SPEED_100; 2857 break; 2858 } 2859 if (duplex == DUPLEX_FULL) { 2860 mcr |= PMCR_FORCE_FDX; 2861 if (tx_pause) 2862 mcr |= PMCR_TX_FC_EN; 2863 if (rx_pause) 2864 mcr |= PMCR_RX_FC_EN; 2865 } 2866 2867 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2868 switch (speed) { 2869 case SPEED_1000: 2870 mcr |= PMCR_FORCE_EEE1G; 2871 break; 2872 case SPEED_100: 2873 mcr |= PMCR_FORCE_EEE100; 2874 break; 2875 } 2876 } 2877 2878 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2879 } 2880 2881 static int 2882 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2883 { 2884 struct mt7530_priv *priv = ds->priv; 2885 phy_interface_t interface; 2886 int speed; 2887 int ret; 2888 2889 switch (port) { 2890 case 5: 2891 if (mt7531_is_rgmii_port(priv, port)) 2892 interface = PHY_INTERFACE_MODE_RGMII; 2893 else 2894 interface = PHY_INTERFACE_MODE_2500BASEX; 2895 2896 priv->p5_interface = interface; 2897 break; 2898 case 6: 2899 interface = PHY_INTERFACE_MODE_2500BASEX; 2900 2901 priv->p6_interface = interface; 2902 break; 2903 default: 2904 return -EINVAL; 2905 } 2906 2907 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2908 speed = SPEED_2500; 2909 else 2910 speed = SPEED_1000; 2911 2912 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2913 if (ret) 2914 return ret; 2915 mt7530_write(priv, MT7530_PMCR_P(port), 2916 PMCR_CPU_PORT_SETTING(priv->id)); 2917 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2918 interface, speed, DUPLEX_FULL); 2919 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2920 speed, DUPLEX_FULL, true, true); 2921 2922 return 0; 2923 } 2924 2925 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2926 struct phylink_config *config) 2927 { 2928 struct mt7530_priv *priv = ds->priv; 2929 2930 /* This switch only supports full-duplex at 1Gbps */ 2931 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2932 MAC_10 | MAC_100 | MAC_1000FD; 2933 2934 /* This driver does not make use of the speed, duplex, pause or the 2935 * advertisement in its mac_config, so it is safe to mark this driver 2936 * as non-legacy. 2937 */ 2938 config->legacy_pre_march2020 = false; 2939 2940 priv->info->mac_port_get_caps(ds, port, config); 2941 } 2942 2943 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2944 unsigned long *supported, 2945 const struct phylink_link_state *state) 2946 { 2947 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2948 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2949 phy_interface_mode_is_8023z(state->interface)) 2950 phylink_clear(supported, Autoneg); 2951 2952 return 0; 2953 } 2954 2955 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2956 struct phylink_link_state *state) 2957 { 2958 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2959 int port = pcs_to_mt753x_pcs(pcs)->port; 2960 u32 pmsr; 2961 2962 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2963 2964 state->link = (pmsr & PMSR_LINK); 2965 state->an_complete = state->link; 2966 state->duplex = !!(pmsr & PMSR_DPX); 2967 2968 switch (pmsr & PMSR_SPEED_MASK) { 2969 case PMSR_SPEED_10: 2970 state->speed = SPEED_10; 2971 break; 2972 case PMSR_SPEED_100: 2973 state->speed = SPEED_100; 2974 break; 2975 case PMSR_SPEED_1000: 2976 state->speed = SPEED_1000; 2977 break; 2978 default: 2979 state->speed = SPEED_UNKNOWN; 2980 break; 2981 } 2982 2983 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2984 if (pmsr & PMSR_RX_FC) 2985 state->pause |= MLO_PAUSE_RX; 2986 if (pmsr & PMSR_TX_FC) 2987 state->pause |= MLO_PAUSE_TX; 2988 } 2989 2990 static int 2991 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2992 struct phylink_link_state *state) 2993 { 2994 u32 status, val; 2995 u16 config_reg; 2996 2997 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2998 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2999 state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE); 3000 if (state->interface == PHY_INTERFACE_MODE_SGMII && 3001 (status & MT7531_SGMII_AN_ENABLE)) { 3002 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 3003 config_reg = val >> 16; 3004 3005 switch (config_reg & LPA_SGMII_SPD_MASK) { 3006 case LPA_SGMII_1000: 3007 state->speed = SPEED_1000; 3008 break; 3009 case LPA_SGMII_100: 3010 state->speed = SPEED_100; 3011 break; 3012 case LPA_SGMII_10: 3013 state->speed = SPEED_10; 3014 break; 3015 default: 3016 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3017 state->link = false; 3018 return -EINVAL; 3019 } 3020 3021 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3022 state->duplex = DUPLEX_FULL; 3023 else 3024 state->duplex = DUPLEX_HALF; 3025 } 3026 3027 return 0; 3028 } 3029 3030 static void 3031 mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port, 3032 struct phylink_link_state *state) 3033 { 3034 unsigned int val; 3035 3036 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3037 state->link = !!(val & MT7531_SGMII_LINK_STATUS); 3038 if (!state->link) 3039 return; 3040 3041 state->an_complete = state->link; 3042 3043 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3044 state->speed = SPEED_2500; 3045 else 3046 state->speed = SPEED_1000; 3047 3048 state->duplex = DUPLEX_FULL; 3049 state->pause = MLO_PAUSE_NONE; 3050 } 3051 3052 static void mt7531_pcs_get_state(struct phylink_pcs *pcs, 3053 struct phylink_link_state *state) 3054 { 3055 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3056 int port = pcs_to_mt753x_pcs(pcs)->port; 3057 3058 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3059 mt7531_sgmii_pcs_get_state_an(priv, port, state); 3060 return; 3061 } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) || 3062 (state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3063 mt7531_sgmii_pcs_get_state_inband(priv, port, state); 3064 return; 3065 } 3066 3067 state->link = false; 3068 } 3069 3070 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3071 phy_interface_t interface, 3072 const unsigned long *advertising, 3073 bool permit_pause_to_mac) 3074 { 3075 return 0; 3076 } 3077 3078 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3079 { 3080 } 3081 3082 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3083 .pcs_validate = mt753x_pcs_validate, 3084 .pcs_get_state = mt7530_pcs_get_state, 3085 .pcs_config = mt753x_pcs_config, 3086 .pcs_an_restart = mt7530_pcs_an_restart, 3087 }; 3088 3089 static const struct phylink_pcs_ops mt7531_pcs_ops = { 3090 .pcs_validate = mt753x_pcs_validate, 3091 .pcs_get_state = mt7531_pcs_get_state, 3092 .pcs_config = mt753x_pcs_config, 3093 .pcs_an_restart = mt7531_pcs_an_restart, 3094 .pcs_link_up = mt7531_pcs_link_up, 3095 }; 3096 3097 static int 3098 mt753x_setup(struct dsa_switch *ds) 3099 { 3100 struct mt7530_priv *priv = ds->priv; 3101 int i, ret; 3102 3103 /* Initialise the PCS devices */ 3104 for (i = 0; i < priv->ds->num_ports; i++) { 3105 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3106 priv->pcs[i].priv = priv; 3107 priv->pcs[i].port = i; 3108 if (mt753x_is_mac_port(i)) 3109 priv->pcs[i].pcs.poll = 1; 3110 } 3111 3112 ret = priv->info->sw_setup(ds); 3113 if (ret) 3114 return ret; 3115 3116 ret = mt7530_setup_irq(priv); 3117 if (ret) 3118 return ret; 3119 3120 ret = mt7530_setup_mdio(priv); 3121 if (ret && priv->irq) 3122 mt7530_free_irq_common(priv); 3123 3124 return ret; 3125 } 3126 3127 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3128 struct ethtool_eee *e) 3129 { 3130 struct mt7530_priv *priv = ds->priv; 3131 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3132 3133 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3134 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3135 3136 return 0; 3137 } 3138 3139 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3140 struct ethtool_eee *e) 3141 { 3142 struct mt7530_priv *priv = ds->priv; 3143 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3144 3145 if (e->tx_lpi_timer > 0xFFF) 3146 return -EINVAL; 3147 3148 set = SET_LPI_THRESH(e->tx_lpi_timer); 3149 if (!e->tx_lpi_enabled) 3150 /* Force LPI Mode without a delay */ 3151 set |= LPI_MODE_EN; 3152 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3153 3154 return 0; 3155 } 3156 3157 static const struct dsa_switch_ops mt7530_switch_ops = { 3158 .get_tag_protocol = mtk_get_tag_protocol, 3159 .setup = mt753x_setup, 3160 .get_strings = mt7530_get_strings, 3161 .get_ethtool_stats = mt7530_get_ethtool_stats, 3162 .get_sset_count = mt7530_get_sset_count, 3163 .set_ageing_time = mt7530_set_ageing_time, 3164 .port_enable = mt7530_port_enable, 3165 .port_disable = mt7530_port_disable, 3166 .port_change_mtu = mt7530_port_change_mtu, 3167 .port_max_mtu = mt7530_port_max_mtu, 3168 .port_stp_state_set = mt7530_stp_state_set, 3169 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3170 .port_bridge_flags = mt7530_port_bridge_flags, 3171 .port_bridge_join = mt7530_port_bridge_join, 3172 .port_bridge_leave = mt7530_port_bridge_leave, 3173 .port_fdb_add = mt7530_port_fdb_add, 3174 .port_fdb_del = mt7530_port_fdb_del, 3175 .port_fdb_dump = mt7530_port_fdb_dump, 3176 .port_mdb_add = mt7530_port_mdb_add, 3177 .port_mdb_del = mt7530_port_mdb_del, 3178 .port_vlan_filtering = mt7530_port_vlan_filtering, 3179 .port_vlan_add = mt7530_port_vlan_add, 3180 .port_vlan_del = mt7530_port_vlan_del, 3181 .port_mirror_add = mt753x_port_mirror_add, 3182 .port_mirror_del = mt753x_port_mirror_del, 3183 .phylink_get_caps = mt753x_phylink_get_caps, 3184 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3185 .phylink_mac_config = mt753x_phylink_mac_config, 3186 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3187 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3188 .get_mac_eee = mt753x_get_mac_eee, 3189 .set_mac_eee = mt753x_set_mac_eee, 3190 }; 3191 3192 static const struct mt753x_info mt753x_table[] = { 3193 [ID_MT7621] = { 3194 .id = ID_MT7621, 3195 .pcs_ops = &mt7530_pcs_ops, 3196 .sw_setup = mt7530_setup, 3197 .phy_read_c22 = mt7530_phy_read_c22, 3198 .phy_write_c22 = mt7530_phy_write_c22, 3199 .phy_read_c45 = mt7530_phy_read_c45, 3200 .phy_write_c45 = mt7530_phy_write_c45, 3201 .pad_setup = mt7530_pad_clk_setup, 3202 .mac_port_get_caps = mt7530_mac_port_get_caps, 3203 .mac_port_config = mt7530_mac_config, 3204 }, 3205 [ID_MT7530] = { 3206 .id = ID_MT7530, 3207 .pcs_ops = &mt7530_pcs_ops, 3208 .sw_setup = mt7530_setup, 3209 .phy_read_c22 = mt7530_phy_read_c22, 3210 .phy_write_c22 = mt7530_phy_write_c22, 3211 .phy_read_c45 = mt7530_phy_read_c45, 3212 .phy_write_c45 = mt7530_phy_write_c45, 3213 .pad_setup = mt7530_pad_clk_setup, 3214 .mac_port_get_caps = mt7530_mac_port_get_caps, 3215 .mac_port_config = mt7530_mac_config, 3216 }, 3217 [ID_MT7531] = { 3218 .id = ID_MT7531, 3219 .pcs_ops = &mt7531_pcs_ops, 3220 .sw_setup = mt7531_setup, 3221 .phy_read_c22 = mt7531_ind_c22_phy_read, 3222 .phy_write_c22 = mt7531_ind_c22_phy_write, 3223 .phy_read_c45 = mt7531_ind_c45_phy_read, 3224 .phy_write_c45 = mt7531_ind_c45_phy_write, 3225 .pad_setup = mt7531_pad_setup, 3226 .cpu_port_config = mt7531_cpu_port_config, 3227 .mac_port_get_caps = mt7531_mac_port_get_caps, 3228 .mac_port_config = mt7531_mac_config, 3229 }, 3230 }; 3231 3232 static const struct of_device_id mt7530_of_match[] = { 3233 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3234 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3235 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3236 { /* sentinel */ }, 3237 }; 3238 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3239 3240 static int 3241 mt7530_probe(struct mdio_device *mdiodev) 3242 { 3243 struct mt7530_priv *priv; 3244 struct device_node *dn; 3245 3246 dn = mdiodev->dev.of_node; 3247 3248 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3249 if (!priv) 3250 return -ENOMEM; 3251 3252 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3253 if (!priv->ds) 3254 return -ENOMEM; 3255 3256 priv->ds->dev = &mdiodev->dev; 3257 priv->ds->num_ports = MT7530_NUM_PORTS; 3258 3259 /* Use medatek,mcm property to distinguish hardware type that would 3260 * casues a little bit differences on power-on sequence. 3261 */ 3262 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3263 if (priv->mcm) { 3264 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3265 3266 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3267 if (IS_ERR(priv->rstc)) { 3268 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3269 return PTR_ERR(priv->rstc); 3270 } 3271 } 3272 3273 /* Get the hardware identifier from the devicetree node. 3274 * We will need it for some of the clock and regulator setup. 3275 */ 3276 priv->info = of_device_get_match_data(&mdiodev->dev); 3277 if (!priv->info) 3278 return -EINVAL; 3279 3280 /* Sanity check if these required device operations are filled 3281 * properly. 3282 */ 3283 if (!priv->info->sw_setup || !priv->info->pad_setup || 3284 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3285 !priv->info->mac_port_get_caps || 3286 !priv->info->mac_port_config) 3287 return -EINVAL; 3288 3289 priv->id = priv->info->id; 3290 3291 if (priv->id == ID_MT7530) { 3292 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3293 if (IS_ERR(priv->core_pwr)) 3294 return PTR_ERR(priv->core_pwr); 3295 3296 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3297 if (IS_ERR(priv->io_pwr)) 3298 return PTR_ERR(priv->io_pwr); 3299 } 3300 3301 /* Not MCM that indicates switch works as the remote standalone 3302 * integrated circuit so the GPIO pin would be used to complete 3303 * the reset, otherwise memory-mapped register accessing used 3304 * through syscon provides in the case of MCM. 3305 */ 3306 if (!priv->mcm) { 3307 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3308 GPIOD_OUT_LOW); 3309 if (IS_ERR(priv->reset)) { 3310 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3311 return PTR_ERR(priv->reset); 3312 } 3313 } 3314 3315 priv->bus = mdiodev->bus; 3316 priv->dev = &mdiodev->dev; 3317 priv->ds->priv = priv; 3318 priv->ds->ops = &mt7530_switch_ops; 3319 mutex_init(&priv->reg_mutex); 3320 dev_set_drvdata(&mdiodev->dev, priv); 3321 3322 return dsa_register_switch(priv->ds); 3323 } 3324 3325 static void 3326 mt7530_remove(struct mdio_device *mdiodev) 3327 { 3328 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3329 int ret = 0; 3330 3331 if (!priv) 3332 return; 3333 3334 ret = regulator_disable(priv->core_pwr); 3335 if (ret < 0) 3336 dev_err(priv->dev, 3337 "Failed to disable core power: %d\n", ret); 3338 3339 ret = regulator_disable(priv->io_pwr); 3340 if (ret < 0) 3341 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3342 ret); 3343 3344 if (priv->irq) 3345 mt7530_free_irq(priv); 3346 3347 dsa_unregister_switch(priv->ds); 3348 mutex_destroy(&priv->reg_mutex); 3349 } 3350 3351 static void mt7530_shutdown(struct mdio_device *mdiodev) 3352 { 3353 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3354 3355 if (!priv) 3356 return; 3357 3358 dsa_switch_shutdown(priv->ds); 3359 3360 dev_set_drvdata(&mdiodev->dev, NULL); 3361 } 3362 3363 static struct mdio_driver mt7530_mdio_driver = { 3364 .probe = mt7530_probe, 3365 .remove = mt7530_remove, 3366 .shutdown = mt7530_shutdown, 3367 .mdiodrv.driver = { 3368 .name = "mt7530", 3369 .of_match_table = mt7530_of_match, 3370 }, 3371 }; 3372 3373 mdio_module_driver(mt7530_mdio_driver); 3374 3375 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3376 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3377 MODULE_LICENSE("GPL"); 3378