xref: /linux/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml (revision 69bfec7548f4c1595bac0e3ddfc0458a5af31f4c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip AXI PCIe Root Port Bridge Host
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-bus.yaml#
14  - $ref: rockchip,rk3399-pcie-common.yaml#
15
16properties:
17  compatible:
18    const: rockchip,rk3399-pcie
19
20  reg: true
21
22  reg-names:
23    items:
24      - const: axi-base
25      - const: apb-base
26
27  interrupts:
28    maxItems: 3
29
30  interrupt-names:
31    items:
32      - const: sys
33      - const: legacy
34      - const: client
35
36  aspm-no-l0s:
37    description: This property is needed if using 24MHz OSC for RC's PHY.
38
39  ep-gpios:
40    description: pre-reset GPIO
41
42  vpcie12v-supply:
43    description: The 12v regulator to use for PCIe.
44
45  vpcie3v3-supply:
46    description: The 3.3v regulator to use for PCIe.
47
48  vpcie1v8-supply:
49    description: The 1.8v regulator to use for PCIe.
50
51  vpcie0v9-supply:
52    description: The 0.9v regulator to use for PCIe.
53
54  interrupt-controller:
55    type: object
56    additionalProperties: false
57
58    properties:
59      '#address-cells':
60        const: 0
61
62      '#interrupt-cells':
63        const: 1
64
65      interrupt-controller: true
66
67required:
68  - ranges
69  - "#interrupt-cells"
70  - interrupts
71  - interrupt-controller
72  - interrupt-map
73  - interrupt-map-mask
74  - msi-map
75
76unevaluatedProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/gpio/gpio.h>
82    #include <dt-bindings/clock/rk3399-cru.h>
83
84    bus {
85        #address-cells = <2>;
86        #size-cells = <2>;
87
88        pcie@f8000000 {
89            compatible = "rockchip,rk3399-pcie";
90            device_type = "pci";
91            #address-cells = <3>;
92            #size-cells = <2>;
93            clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
94              <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
95            clock-names = "aclk", "aclk-perf",
96                    "hclk", "pm";
97            interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
98                  <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
99                  <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
100            interrupt-names = "sys", "legacy", "client";
101            ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
102            ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
103                0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
104            num-lanes = <4>;
105            msi-map = <0x0 &its 0x0 0x1000>;
106            reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
107            reg-names = "axi-base", "apb-base";
108            resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
109              <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
110              <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
111            reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
112                    "pm", "pclk", "aclk";
113            /* deprecated legacy PHY model */
114            phys = <&pcie_phy>;
115            phy-names = "pcie-phy";
116            pinctrl-names = "default";
117            pinctrl-0 = <&pcie_clkreq>;
118            #interrupt-cells = <1>;
119            interrupt-map-mask = <0 0 0 7>;
120            interrupt-map = <0 0 0 1 &pcie0_intc 0>,
121                <0 0 0 2 &pcie0_intc 1>,
122                <0 0 0 3 &pcie0_intc 2>,
123                <0 0 0 4 &pcie0_intc 3>;
124
125            pcie0_intc: interrupt-controller {
126                interrupt-controller;
127                #address-cells = <0>;
128                #interrupt-cells = <1>;
129            };
130        };
131    };
132...
133