1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "EventCode": "0xc8", 5 "EventName": "HLE_RETIRED.ABORTED", 6 "PEBS": "1", 7 "PublicDescription": "Number of times HLE abort was triggered.", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x4" 10 }, 11 { 12 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 13 "EventCode": "0xc8", 14 "EventName": "HLE_RETIRED.ABORTED_MISC1", 15 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 16 "SampleAfterValue": "2000003", 17 "UMask": "0x8" 18 }, 19 { 20 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 21 "EventCode": "0xc8", 22 "EventName": "HLE_RETIRED.ABORTED_MISC2", 23 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 24 "SampleAfterValue": "2000003", 25 "UMask": "0x10" 26 }, 27 { 28 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 29 "EventCode": "0xc8", 30 "EventName": "HLE_RETIRED.ABORTED_MISC3", 31 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 32 "SampleAfterValue": "2000003", 33 "UMask": "0x20" 34 }, 35 { 36 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC4", 39 "PublicDescription": "Number of times HLE caused a fault.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x40" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 45 "EventCode": "0xc8", 46 "EventName": "HLE_RETIRED.ABORTED_MISC5", 47 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x80" 50 }, 51 { 52 "BriefDescription": "Number of times HLE commit succeeded", 53 "EventCode": "0xc8", 54 "EventName": "HLE_RETIRED.COMMIT", 55 "PublicDescription": "Number of times HLE commit succeeded.", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 61 "EventCode": "0xc8", 62 "EventName": "HLE_RETIRED.START", 63 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x1" 66 }, 67 { 68 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 69 "EventCode": "0xC3", 70 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 71 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 72 "SampleAfterValue": "100003", 73 "UMask": "0x2" 74 }, 75 { 76 "BriefDescription": "Randomly selected loads with latency value being above 128", 77 "Data_LA": "1", 78 "Errata": "BDM100, BDM35", 79 "EventCode": "0xcd", 80 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 81 "MSRIndex": "0x3F6", 82 "MSRValue": "0x80", 83 "PEBS": "2", 84 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 85 "SampleAfterValue": "1009", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Randomly selected loads with latency value being above 16", 90 "Data_LA": "1", 91 "Errata": "BDM100, BDM35", 92 "EventCode": "0xcd", 93 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 94 "MSRIndex": "0x3F6", 95 "MSRValue": "0x10", 96 "PEBS": "2", 97 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 98 "SampleAfterValue": "20011", 99 "UMask": "0x1" 100 }, 101 { 102 "BriefDescription": "Randomly selected loads with latency value being above 256", 103 "Data_LA": "1", 104 "Errata": "BDM100, BDM35", 105 "EventCode": "0xcd", 106 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 107 "MSRIndex": "0x3F6", 108 "MSRValue": "0x100", 109 "PEBS": "2", 110 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 111 "SampleAfterValue": "503", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "Randomly selected loads with latency value being above 32", 116 "Data_LA": "1", 117 "Errata": "BDM100, BDM35", 118 "EventCode": "0xcd", 119 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 120 "MSRIndex": "0x3F6", 121 "MSRValue": "0x20", 122 "PEBS": "2", 123 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 124 "SampleAfterValue": "100007", 125 "UMask": "0x1" 126 }, 127 { 128 "BriefDescription": "Randomly selected loads with latency value being above 4", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x4", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 137 "SampleAfterValue": "100003", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Randomly selected loads with latency value being above 512", 142 "Data_LA": "1", 143 "Errata": "BDM100, BDM35", 144 "EventCode": "0xcd", 145 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 146 "MSRIndex": "0x3F6", 147 "MSRValue": "0x200", 148 "PEBS": "2", 149 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 150 "SampleAfterValue": "101", 151 "UMask": "0x1" 152 }, 153 { 154 "BriefDescription": "Randomly selected loads with latency value being above 64", 155 "Data_LA": "1", 156 "Errata": "BDM100, BDM35", 157 "EventCode": "0xcd", 158 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 159 "MSRIndex": "0x3F6", 160 "MSRValue": "0x40", 161 "PEBS": "2", 162 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 163 "SampleAfterValue": "2003", 164 "UMask": "0x1" 165 }, 166 { 167 "BriefDescription": "Randomly selected loads with latency value being above 8", 168 "Data_LA": "1", 169 "Errata": "BDM100, BDM35", 170 "EventCode": "0xcd", 171 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 172 "MSRIndex": "0x3F6", 173 "MSRValue": "0x8", 174 "PEBS": "2", 175 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 176 "SampleAfterValue": "50021", 177 "UMask": "0x1" 178 }, 179 { 180 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 181 "EventCode": "0x05", 182 "EventName": "MISALIGN_MEM_REF.LOADS", 183 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 184 "SampleAfterValue": "2000003", 185 "UMask": "0x1" 186 }, 187 { 188 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 189 "EventCode": "0x05", 190 "EventName": "MISALIGN_MEM_REF.STORES", 191 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 192 "SampleAfterValue": "2000003", 193 "UMask": "0x2" 194 }, 195 { 196 "BriefDescription": "Counts all demand & prefetch data reads", 197 "EventCode": "0xB7, 0xBB", 198 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 199 "MSRIndex": "0x1a6,0x1a7", 200 "MSRValue": "0x20003C0091", 201 "SampleAfterValue": "100003", 202 "UMask": "0x1" 203 }, 204 { 205 "BriefDescription": "Counts all demand & prefetch data reads", 206 "EventCode": "0xB7, 0xBB", 207 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 208 "MSRIndex": "0x1a6,0x1a7", 209 "MSRValue": "0x43C000091", 210 "SampleAfterValue": "100003", 211 "UMask": "0x1" 212 }, 213 { 214 "BriefDescription": "Counts all demand & prefetch data reads", 215 "EventCode": "0xB7, 0xBB", 216 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 217 "MSRIndex": "0x1a6,0x1a7", 218 "MSRValue": "0x23C000091", 219 "SampleAfterValue": "100003", 220 "UMask": "0x1" 221 }, 222 { 223 "BriefDescription": "Counts all demand & prefetch data reads", 224 "EventCode": "0xB7, 0xBB", 225 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 226 "MSRIndex": "0x1a6,0x1a7", 227 "MSRValue": "0xBC000091", 228 "SampleAfterValue": "100003", 229 "UMask": "0x1" 230 }, 231 { 232 "BriefDescription": "Counts all demand & prefetch data reads", 233 "EventCode": "0xB7, 0xBB", 234 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 235 "MSRIndex": "0x1a6,0x1a7", 236 "MSRValue": "0x13C000091", 237 "SampleAfterValue": "100003", 238 "UMask": "0x1" 239 }, 240 { 241 "BriefDescription": "Counts all demand & prefetch data reads", 242 "EventCode": "0xB7, 0xBB", 243 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 244 "MSRIndex": "0x1a6,0x1a7", 245 "MSRValue": "0x3F84000091", 246 "SampleAfterValue": "100003", 247 "UMask": "0x1" 248 }, 249 { 250 "BriefDescription": "Counts all demand & prefetch data reads", 251 "EventCode": "0xB7, 0xBB", 252 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 253 "MSRIndex": "0x1a6,0x1a7", 254 "MSRValue": "0x1004000091", 255 "SampleAfterValue": "100003", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "Counts all demand & prefetch data reads", 260 "EventCode": "0xB7, 0xBB", 261 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 262 "MSRIndex": "0x1a6,0x1a7", 263 "MSRValue": "0x404000091", 264 "SampleAfterValue": "100003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "Counts all demand & prefetch data reads", 269 "EventCode": "0xB7, 0xBB", 270 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x204000091", 273 "SampleAfterValue": "100003", 274 "UMask": "0x1" 275 }, 276 { 277 "BriefDescription": "Counts all demand & prefetch data reads", 278 "EventCode": "0xB7, 0xBB", 279 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 280 "MSRIndex": "0x1a6,0x1a7", 281 "MSRValue": "0x84000091", 282 "SampleAfterValue": "100003", 283 "UMask": "0x1" 284 }, 285 { 286 "BriefDescription": "Counts all demand & prefetch data reads", 287 "EventCode": "0xB7, 0xBB", 288 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 289 "MSRIndex": "0x1a6,0x1a7", 290 "MSRValue": "0x2004000091", 291 "SampleAfterValue": "100003", 292 "UMask": "0x1" 293 }, 294 { 295 "BriefDescription": "Counts all demand & prefetch data reads", 296 "EventCode": "0xB7, 0xBB", 297 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 298 "MSRIndex": "0x1a6,0x1a7", 299 "MSRValue": "0x104000091", 300 "SampleAfterValue": "100003", 301 "UMask": "0x1" 302 }, 303 { 304 "BriefDescription": "Counts all demand & prefetch data reads", 305 "EventCode": "0xB7, 0xBB", 306 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 307 "MSRIndex": "0x1a6,0x1a7", 308 "MSRValue": "0x2000020091", 309 "SampleAfterValue": "100003", 310 "UMask": "0x1" 311 }, 312 { 313 "BriefDescription": "Counts all prefetch code reads", 314 "EventCode": "0xB7, 0xBB", 315 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 316 "MSRIndex": "0x1a6,0x1a7", 317 "MSRValue": "0x20003C0240", 318 "SampleAfterValue": "100003", 319 "UMask": "0x1" 320 }, 321 { 322 "BriefDescription": "Counts all prefetch code reads", 323 "EventCode": "0xB7, 0xBB", 324 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x43C000240", 327 "SampleAfterValue": "100003", 328 "UMask": "0x1" 329 }, 330 { 331 "BriefDescription": "Counts all prefetch code reads", 332 "EventCode": "0xB7, 0xBB", 333 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", 334 "MSRIndex": "0x1a6,0x1a7", 335 "MSRValue": "0x23C000240", 336 "SampleAfterValue": "100003", 337 "UMask": "0x1" 338 }, 339 { 340 "BriefDescription": "Counts all prefetch code reads", 341 "EventCode": "0xB7, 0xBB", 342 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", 343 "MSRIndex": "0x1a6,0x1a7", 344 "MSRValue": "0xBC000240", 345 "SampleAfterValue": "100003", 346 "UMask": "0x1" 347 }, 348 { 349 "BriefDescription": "Counts all prefetch code reads", 350 "EventCode": "0xB7, 0xBB", 351 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 352 "MSRIndex": "0x1a6,0x1a7", 353 "MSRValue": "0x13C000240", 354 "SampleAfterValue": "100003", 355 "UMask": "0x1" 356 }, 357 { 358 "BriefDescription": "Counts all prefetch code reads", 359 "EventCode": "0xB7, 0xBB", 360 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 361 "MSRIndex": "0x1a6,0x1a7", 362 "MSRValue": "0x3F84000240", 363 "SampleAfterValue": "100003", 364 "UMask": "0x1" 365 }, 366 { 367 "BriefDescription": "Counts all prefetch code reads", 368 "EventCode": "0xB7, 0xBB", 369 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 370 "MSRIndex": "0x1a6,0x1a7", 371 "MSRValue": "0x1004000240", 372 "SampleAfterValue": "100003", 373 "UMask": "0x1" 374 }, 375 { 376 "BriefDescription": "Counts all prefetch code reads", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0x404000240", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts all prefetch code reads", 386 "EventCode": "0xB7, 0xBB", 387 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 388 "MSRIndex": "0x1a6,0x1a7", 389 "MSRValue": "0x204000240", 390 "SampleAfterValue": "100003", 391 "UMask": "0x1" 392 }, 393 { 394 "BriefDescription": "Counts all prefetch code reads", 395 "EventCode": "0xB7, 0xBB", 396 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 397 "MSRIndex": "0x1a6,0x1a7", 398 "MSRValue": "0x84000240", 399 "SampleAfterValue": "100003", 400 "UMask": "0x1" 401 }, 402 { 403 "BriefDescription": "Counts all prefetch code reads", 404 "EventCode": "0xB7, 0xBB", 405 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 406 "MSRIndex": "0x1a6,0x1a7", 407 "MSRValue": "0x2004000240", 408 "SampleAfterValue": "100003", 409 "UMask": "0x1" 410 }, 411 { 412 "BriefDescription": "Counts all prefetch code reads", 413 "EventCode": "0xB7, 0xBB", 414 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 415 "MSRIndex": "0x1a6,0x1a7", 416 "MSRValue": "0x104000240", 417 "SampleAfterValue": "100003", 418 "UMask": "0x1" 419 }, 420 { 421 "BriefDescription": "Counts all prefetch code reads", 422 "EventCode": "0xB7, 0xBB", 423 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 424 "MSRIndex": "0x1a6,0x1a7", 425 "MSRValue": "0x2000020240", 426 "SampleAfterValue": "100003", 427 "UMask": "0x1" 428 }, 429 { 430 "BriefDescription": "Counts all prefetch data reads", 431 "EventCode": "0xB7, 0xBB", 432 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 433 "MSRIndex": "0x1a6,0x1a7", 434 "MSRValue": "0x20003C0090", 435 "SampleAfterValue": "100003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "Counts all prefetch data reads", 440 "EventCode": "0xB7, 0xBB", 441 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 442 "MSRIndex": "0x1a6,0x1a7", 443 "MSRValue": "0x43C000090", 444 "SampleAfterValue": "100003", 445 "UMask": "0x1" 446 }, 447 { 448 "BriefDescription": "Counts all prefetch data reads", 449 "EventCode": "0xB7, 0xBB", 450 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 451 "MSRIndex": "0x1a6,0x1a7", 452 "MSRValue": "0x23C000090", 453 "SampleAfterValue": "100003", 454 "UMask": "0x1" 455 }, 456 { 457 "BriefDescription": "Counts all prefetch data reads", 458 "EventCode": "0xB7, 0xBB", 459 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 460 "MSRIndex": "0x1a6,0x1a7", 461 "MSRValue": "0xBC000090", 462 "SampleAfterValue": "100003", 463 "UMask": "0x1" 464 }, 465 { 466 "BriefDescription": "Counts all prefetch data reads", 467 "EventCode": "0xB7, 0xBB", 468 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 469 "MSRIndex": "0x1a6,0x1a7", 470 "MSRValue": "0x13C000090", 471 "SampleAfterValue": "100003", 472 "UMask": "0x1" 473 }, 474 { 475 "BriefDescription": "Counts all prefetch data reads", 476 "EventCode": "0xB7, 0xBB", 477 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 478 "MSRIndex": "0x1a6,0x1a7", 479 "MSRValue": "0x3F84000090", 480 "SampleAfterValue": "100003", 481 "UMask": "0x1" 482 }, 483 { 484 "BriefDescription": "Counts all prefetch data reads", 485 "EventCode": "0xB7, 0xBB", 486 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 487 "MSRIndex": "0x1a6,0x1a7", 488 "MSRValue": "0x1004000090", 489 "SampleAfterValue": "100003", 490 "UMask": "0x1" 491 }, 492 { 493 "BriefDescription": "Counts all prefetch data reads", 494 "EventCode": "0xB7, 0xBB", 495 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 496 "MSRIndex": "0x1a6,0x1a7", 497 "MSRValue": "0x404000090", 498 "SampleAfterValue": "100003", 499 "UMask": "0x1" 500 }, 501 { 502 "BriefDescription": "Counts all prefetch data reads", 503 "EventCode": "0xB7, 0xBB", 504 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 505 "MSRIndex": "0x1a6,0x1a7", 506 "MSRValue": "0x204000090", 507 "SampleAfterValue": "100003", 508 "UMask": "0x1" 509 }, 510 { 511 "BriefDescription": "Counts all prefetch data reads", 512 "EventCode": "0xB7, 0xBB", 513 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 514 "MSRIndex": "0x1a6,0x1a7", 515 "MSRValue": "0x84000090", 516 "SampleAfterValue": "100003", 517 "UMask": "0x1" 518 }, 519 { 520 "BriefDescription": "Counts all prefetch data reads", 521 "EventCode": "0xB7, 0xBB", 522 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 523 "MSRIndex": "0x1a6,0x1a7", 524 "MSRValue": "0x2004000090", 525 "SampleAfterValue": "100003", 526 "UMask": "0x1" 527 }, 528 { 529 "BriefDescription": "Counts all prefetch data reads", 530 "EventCode": "0xB7, 0xBB", 531 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 532 "MSRIndex": "0x1a6,0x1a7", 533 "MSRValue": "0x104000090", 534 "SampleAfterValue": "100003", 535 "UMask": "0x1" 536 }, 537 { 538 "BriefDescription": "Counts all prefetch data reads", 539 "EventCode": "0xB7, 0xBB", 540 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 541 "MSRIndex": "0x1a6,0x1a7", 542 "MSRValue": "0x2000020090", 543 "SampleAfterValue": "100003", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "Counts prefetch RFOs", 548 "EventCode": "0xB7, 0xBB", 549 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM", 550 "MSRIndex": "0x1a6,0x1a7", 551 "MSRValue": "0x20003C0120", 552 "SampleAfterValue": "100003", 553 "UMask": "0x1" 554 }, 555 { 556 "BriefDescription": "Counts prefetch RFOs", 557 "EventCode": "0xB7, 0xBB", 558 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 559 "MSRIndex": "0x1a6,0x1a7", 560 "MSRValue": "0x43C000120", 561 "SampleAfterValue": "100003", 562 "UMask": "0x1" 563 }, 564 { 565 "BriefDescription": "Counts prefetch RFOs", 566 "EventCode": "0xB7, 0xBB", 567 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 568 "MSRIndex": "0x1a6,0x1a7", 569 "MSRValue": "0x23C000120", 570 "SampleAfterValue": "100003", 571 "UMask": "0x1" 572 }, 573 { 574 "BriefDescription": "Counts prefetch RFOs", 575 "EventCode": "0xB7, 0xBB", 576 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 577 "MSRIndex": "0x1a6,0x1a7", 578 "MSRValue": "0xBC000120", 579 "SampleAfterValue": "100003", 580 "UMask": "0x1" 581 }, 582 { 583 "BriefDescription": "Counts prefetch RFOs", 584 "EventCode": "0xB7, 0xBB", 585 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED", 586 "MSRIndex": "0x1a6,0x1a7", 587 "MSRValue": "0x13C000120", 588 "SampleAfterValue": "100003", 589 "UMask": "0x1" 590 }, 591 { 592 "BriefDescription": "Counts prefetch RFOs", 593 "EventCode": "0xB7, 0xBB", 594 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 595 "MSRIndex": "0x1a6,0x1a7", 596 "MSRValue": "0x3F84000120", 597 "SampleAfterValue": "100003", 598 "UMask": "0x1" 599 }, 600 { 601 "BriefDescription": "Counts prefetch RFOs", 602 "EventCode": "0xB7, 0xBB", 603 "EventName": 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"EventCode": "0xB7, 0xBB", 666 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM", 667 "MSRIndex": "0x1a6,0x1a7", 668 "MSRValue": "0x20003C0122", 669 "SampleAfterValue": "100003", 670 "UMask": "0x1" 671 }, 672 { 673 "BriefDescription": "Counts all demand & prefetch RFOs", 674 "EventCode": "0xB7, 0xBB", 675 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 676 "MSRIndex": "0x1a6,0x1a7", 677 "MSRValue": "0x43C000122", 678 "SampleAfterValue": "100003", 679 "UMask": "0x1" 680 }, 681 { 682 "BriefDescription": "Counts all demand & prefetch RFOs", 683 "EventCode": "0xB7, 0xBB", 684 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", 685 "MSRIndex": "0x1a6,0x1a7", 686 "MSRValue": "0x23C000122", 687 "SampleAfterValue": "100003", 688 "UMask": "0x1" 689 }, 690 { 691 "BriefDescription": "Counts all demand & prefetch RFOs", 692 "EventCode": "0xB7, 0xBB", 693 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", 694 "MSRIndex": "0x1a6,0x1a7", 695 "MSRValue": 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demand & prefetch RFOs", 728 "EventCode": "0xB7, 0xBB", 729 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 730 "MSRIndex": "0x1a6,0x1a7", 731 "MSRValue": "0x404000122", 732 "SampleAfterValue": "100003", 733 "UMask": "0x1" 734 }, 735 { 736 "BriefDescription": "Counts all demand & prefetch RFOs", 737 "EventCode": "0xB7, 0xBB", 738 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 739 "MSRIndex": "0x1a6,0x1a7", 740 "MSRValue": "0x204000122", 741 "SampleAfterValue": "100003", 742 "UMask": "0x1" 743 }, 744 { 745 "BriefDescription": "Counts all demand & prefetch RFOs", 746 "EventCode": "0xB7, 0xBB", 747 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 748 "MSRIndex": "0x1a6,0x1a7", 749 "MSRValue": "0x84000122", 750 "SampleAfterValue": "100003", 751 "UMask": "0x1" 752 }, 753 { 754 "BriefDescription": "Counts all demand & prefetch RFOs", 755 "EventCode": "0xB7, 0xBB", 756 "EventName": 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writebacks (modified to exclusive)", 818 "EventCode": "0xB7, 0xBB", 819 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", 820 "MSRIndex": "0x1a6,0x1a7", 821 "MSRValue": "0x13C000008", 822 "SampleAfterValue": "100003", 823 "UMask": "0x1" 824 }, 825 { 826 "BriefDescription": "Counts writebacks (modified to exclusive)", 827 "EventCode": "0xB7, 0xBB", 828 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 829 "MSRIndex": "0x1a6,0x1a7", 830 "MSRValue": "0x3F84000008", 831 "SampleAfterValue": "100003", 832 "UMask": "0x1" 833 }, 834 { 835 "BriefDescription": "Counts writebacks (modified to exclusive)", 836 "EventCode": "0xB7, 0xBB", 837 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 838 "MSRIndex": "0x1a6,0x1a7", 839 "MSRValue": "0x1004000008", 840 "SampleAfterValue": "100003", 841 "UMask": "0x1" 842 }, 843 { 844 "BriefDescription": "Counts writebacks (modified to exclusive)", 845 "EventCode": "0xB7, 0xBB", 846 "EventName": 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1087 "BriefDescription": "Counts demand data reads", 1088 "EventCode": "0xB7, 0xBB", 1089 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1090 "MSRIndex": "0x1a6,0x1a7", 1091 "MSRValue": "0x204000001", 1092 "SampleAfterValue": "100003", 1093 "UMask": "0x1" 1094 }, 1095 { 1096 "BriefDescription": "Counts demand data reads", 1097 "EventCode": "0xB7, 0xBB", 1098 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "MSRValue": "0x84000001", 1101 "SampleAfterValue": "100003", 1102 "UMask": "0x1" 1103 }, 1104 { 1105 "BriefDescription": "Counts demand data reads", 1106 "EventCode": "0xB7, 0xBB", 1107 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1108 "MSRIndex": "0x1a6,0x1a7", 1109 "MSRValue": "0x2004000001", 1110 "SampleAfterValue": "100003", 1111 "UMask": "0x1" 1112 }, 1113 { 1114 "BriefDescription": "Counts demand data reads", 1115 "EventCode": "0xB7, 0xBB", 1116 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1117 "MSRIndex": "0x1a6,0x1a7", 1118 "MSRValue": "0x104000001", 1119 "SampleAfterValue": "100003", 1120 "UMask": "0x1" 1121 }, 1122 { 1123 "BriefDescription": "Counts demand data reads", 1124 "EventCode": "0xB7, 0xBB", 1125 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1126 "MSRIndex": "0x1a6,0x1a7", 1127 "MSRValue": "0x2000020001", 1128 "SampleAfterValue": "100003", 1129 "UMask": "0x1" 1130 }, 1131 { 1132 "BriefDescription": "Counts all demand data writes (RFOs)", 1133 "EventCode": "0xB7, 0xBB", 1134 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", 1135 "MSRIndex": "0x1a6,0x1a7", 1136 "MSRValue": "0x20003C0002", 1137 "SampleAfterValue": "100003", 1138 "UMask": "0x1" 1139 }, 1140 { 1141 "BriefDescription": "Counts all demand data writes (RFOs)", 1142 "EventCode": "0xB7, 0xBB", 1143 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1144 "MSRIndex": "0x1a6,0x1a7", 1145 "MSRValue": "0x43C000002", 1146 "SampleAfterValue": "100003", 1147 "UMask": "0x1" 1148 }, 1149 { 1150 "BriefDescription": "Counts all demand data writes (RFOs)", 1151 "EventCode": "0xB7, 0xBB", 1152 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 1153 "MSRIndex": "0x1a6,0x1a7", 1154 "MSRValue": "0x23C000002", 1155 "SampleAfterValue": "100003", 1156 "UMask": "0x1" 1157 }, 1158 { 1159 "BriefDescription": "Counts all demand data writes (RFOs)", 1160 "EventCode": "0xB7, 0xBB", 1161 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 1162 "MSRIndex": "0x1a6,0x1a7", 1163 "MSRValue": "0xBC000002", 1164 "SampleAfterValue": "100003", 1165 "UMask": "0x1" 1166 }, 1167 { 1168 "BriefDescription": "Counts all demand data writes (RFOs)", 1169 "EventCode": "0xB7, 0xBB", 1170 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1171 "MSRIndex": "0x1a6,0x1a7", 1172 "MSRValue": "0x13C000002", 1173 "SampleAfterValue": "100003", 1174 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0xBB", 1206 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 1207 "MSRIndex": "0x1a6,0x1a7", 1208 "MSRValue": "0x23C008000", 1209 "SampleAfterValue": "100003", 1210 "UMask": "0x1" 1211 }, 1212 { 1213 "BriefDescription": "Counts any other requests", 1214 "EventCode": "0xB7, 0xBB", 1215 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 1216 "MSRIndex": "0x1a6,0x1a7", 1217 "MSRValue": "0xBC008000", 1218 "SampleAfterValue": "100003", 1219 "UMask": "0x1" 1220 }, 1221 { 1222 "BriefDescription": "Counts any other requests", 1223 "EventCode": "0xB7, 0xBB", 1224 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 1225 "MSRIndex": "0x1a6,0x1a7", 1226 "MSRValue": "0x13C008000", 1227 "SampleAfterValue": "100003", 1228 "UMask": "0x1" 1229 }, 1230 { 1231 "BriefDescription": "Counts any other requests", 1232 "EventCode": "0xB7, 0xBB", 1233 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1234 "MSRIndex": "0x1a6,0x1a7", 1235 "MSRValue": "0x3F84008000", 1236 "SampleAfterValue": "100003", 1237 "UMask": "0x1" 1238 }, 1239 { 1240 "BriefDescription": "Counts any other requests", 1241 "EventCode": "0xB7, 0xBB", 1242 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1243 "MSRIndex": "0x1a6,0x1a7", 1244 "MSRValue": "0x1004008000", 1245 "SampleAfterValue": "100003", 1246 "UMask": "0x1" 1247 }, 1248 { 1249 "BriefDescription": "Counts any other requests", 1250 "EventCode": "0xB7, 0xBB", 1251 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1252 "MSRIndex": "0x1a6,0x1a7", 1253 "MSRValue": "0x404008000", 1254 "SampleAfterValue": "100003", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "Counts any other requests", 1259 "EventCode": "0xB7, 0xBB", 1260 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1261 "MSRIndex": "0x1a6,0x1a7", 1262 "MSRValue": "0x204008000", 1263 "SampleAfterValue": "100003", 1264 "UMask": "0x1" 1265 }, 1266 { 1267 "BriefDescription": "Counts any other requests", 1268 "EventCode": "0xB7, 0xBB", 1269 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1270 "MSRIndex": "0x1a6,0x1a7", 1271 "MSRValue": "0x84008000", 1272 "SampleAfterValue": "100003", 1273 "UMask": "0x1" 1274 }, 1275 { 1276 "BriefDescription": "Counts any other requests", 1277 "EventCode": "0xB7, 0xBB", 1278 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1279 "MSRIndex": "0x1a6,0x1a7", 1280 "MSRValue": "0x2004008000", 1281 "SampleAfterValue": "100003", 1282 "UMask": "0x1" 1283 }, 1284 { 1285 "BriefDescription": "Counts any other requests", 1286 "EventCode": "0xB7, 0xBB", 1287 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1288 "MSRIndex": "0x1a6,0x1a7", 1289 "MSRValue": "0x104008000", 1290 "SampleAfterValue": "100003", 1291 "UMask": "0x1" 1292 }, 1293 { 1294 "BriefDescription": "Counts any other requests", 1295 "EventCode": "0xB7, 0xBB", 1296 "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", 1297 "MSRIndex": "0x1a6,0x1a7", 1298 "MSRValue": "0x2000028000", 1299 "SampleAfterValue": "100003", 1300 "UMask": "0x1" 1301 }, 1302 { 1303 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1304 "EventCode": "0xB7, 0xBB", 1305 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 1306 "MSRIndex": "0x1a6,0x1a7", 1307 "MSRValue": "0x20003C0040", 1308 "SampleAfterValue": "100003", 1309 "UMask": "0x1" 1310 }, 1311 { 1312 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1313 "EventCode": "0xB7, 0xBB", 1314 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1315 "MSRIndex": "0x1a6,0x1a7", 1316 "MSRValue": "0x43C000040", 1317 "SampleAfterValue": "100003", 1318 "UMask": "0x1" 1319 }, 1320 { 1321 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1322 "EventCode": "0xB7, 0xBB", 1323 "EventName": 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"OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1351 "MSRIndex": "0x1a6,0x1a7", 1352 "MSRValue": "0x3F84000040", 1353 "SampleAfterValue": "100003", 1354 "UMask": "0x1" 1355 }, 1356 { 1357 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1358 "EventCode": "0xB7, 0xBB", 1359 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1360 "MSRIndex": "0x1a6,0x1a7", 1361 "MSRValue": "0x1004000040", 1362 "SampleAfterValue": "100003", 1363 "UMask": "0x1" 1364 }, 1365 { 1366 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1367 "EventCode": "0xB7, 0xBB", 1368 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1369 "MSRIndex": "0x1a6,0x1a7", 1370 "MSRValue": "0x404000040", 1371 "SampleAfterValue": "100003", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1376 "EventCode": "0xB7, 0xBB", 1377 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1378 "MSRIndex": "0x1a6,0x1a7", 1379 "MSRValue": "0x204000040", 1380 "SampleAfterValue": "100003", 1381 "UMask": "0x1" 1382 }, 1383 { 1384 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1385 "EventCode": "0xB7, 0xBB", 1386 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1387 "MSRIndex": "0x1a6,0x1a7", 1388 "MSRValue": "0x84000040", 1389 "SampleAfterValue": "100003", 1390 "UMask": "0x1" 1391 }, 1392 { 1393 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1394 "EventCode": "0xB7, 0xBB", 1395 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1396 "MSRIndex": "0x1a6,0x1a7", 1397 "MSRValue": "0x2004000040", 1398 "SampleAfterValue": "100003", 1399 "UMask": "0x1" 1400 }, 1401 { 1402 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1403 "EventCode": "0xB7, 0xBB", 1404 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1405 "MSRIndex": "0x1a6,0x1a7", 1406 "MSRValue": "0x104000040", 1407 "SampleAfterValue": "100003", 1408 "UMask": "0x1" 1409 }, 1410 { 1411 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1412 "EventCode": "0xB7, 0xBB", 1413 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1414 "MSRIndex": "0x1a6,0x1a7", 1415 "MSRValue": "0x2000020040", 1416 "SampleAfterValue": "100003", 1417 "UMask": "0x1" 1418 }, 1419 { 1420 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1421 "EventCode": "0xB7, 0xBB", 1422 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1423 "MSRIndex": "0x1a6,0x1a7", 1424 "MSRValue": "0x20003C0010", 1425 "SampleAfterValue": "100003", 1426 "UMask": "0x1" 1427 }, 1428 { 1429 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1430 "EventCode": "0xB7, 0xBB", 1431 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1432 "MSRIndex": "0x1a6,0x1a7", 1433 "MSRValue": "0x43C000010", 1434 "SampleAfterValue": "100003", 1435 "UMask": "0x1" 1436 }, 1437 { 1438 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1439 "EventCode": "0xB7, 0xBB", 1440 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 1441 "MSRIndex": "0x1a6,0x1a7", 1442 "MSRValue": "0x23C000010", 1443 "SampleAfterValue": "100003", 1444 "UMask": "0x1" 1445 }, 1446 { 1447 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1448 "EventCode": "0xB7, 0xBB", 1449 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 1450 "MSRIndex": "0x1a6,0x1a7", 1451 "MSRValue": "0xBC000010", 1452 "SampleAfterValue": "100003", 1453 "UMask": "0x1" 1454 }, 1455 { 1456 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1457 "EventCode": "0xB7, 0xBB", 1458 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1459 "MSRIndex": "0x1a6,0x1a7", 1460 "MSRValue": "0x13C000010", 1461 "SampleAfterValue": "100003", 1462 "UMask": "0x1" 1463 }, 1464 { 1465 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1466 "EventCode": "0xB7, 0xBB", 1467 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1468 "MSRIndex": "0x1a6,0x1a7", 1469 "MSRValue": "0x3F84000010", 1470 "SampleAfterValue": "100003", 1471 "UMask": "0x1" 1472 }, 1473 { 1474 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1475 "EventCode": "0xB7, 0xBB", 1476 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1477 "MSRIndex": "0x1a6,0x1a7", 1478 "MSRValue": "0x1004000010", 1479 "SampleAfterValue": "100003", 1480 "UMask": "0x1" 1481 }, 1482 { 1483 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1484 "EventCode": "0xB7, 0xBB", 1485 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1486 "MSRIndex": "0x1a6,0x1a7", 1487 "MSRValue": "0x404000010", 1488 "SampleAfterValue": "100003", 1489 "UMask": "0x1" 1490 }, 1491 { 1492 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1493 "EventCode": "0xB7, 0xBB", 1494 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1495 "MSRIndex": "0x1a6,0x1a7", 1496 "MSRValue": "0x204000010", 1497 "SampleAfterValue": "100003", 1498 "UMask": "0x1" 1499 }, 1500 { 1501 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1502 "EventCode": "0xB7, 0xBB", 1503 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1504 "MSRIndex": "0x1a6,0x1a7", 1505 "MSRValue": "0x84000010", 1506 "SampleAfterValue": "100003", 1507 "UMask": "0x1" 1508 }, 1509 { 1510 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1511 "EventCode": "0xB7, 0xBB", 1512 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1513 "MSRIndex": "0x1a6,0x1a7", 1514 "MSRValue": "0x2004000010", 1515 "SampleAfterValue": "100003", 1516 "UMask": "0x1" 1517 }, 1518 { 1519 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1520 "EventCode": "0xB7, 0xBB", 1521 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1522 "MSRIndex": "0x1a6,0x1a7", 1523 "MSRValue": "0x104000010", 1524 "SampleAfterValue": "100003", 1525 "UMask": "0x1" 1526 }, 1527 { 1528 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1529 "EventCode": "0xB7, 0xBB", 1530 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1531 "MSRIndex": "0x1a6,0x1a7", 1532 "MSRValue": "0x2000020010", 1533 "SampleAfterValue": "100003", 1534 "UMask": "0x1" 1535 }, 1536 { 1537 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1538 "EventCode": "0xB7, 0xBB", 1539 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM", 1540 "MSRIndex": "0x1a6,0x1a7", 1541 "MSRValue": "0x20003C0020", 1542 "SampleAfterValue": "100003", 1543 "UMask": "0x1" 1544 }, 1545 { 1546 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1547 "EventCode": "0xB7, 0xBB", 1548 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1549 "MSRIndex": "0x1a6,0x1a7", 1550 "MSRValue": "0x43C000020", 1551 "SampleAfterValue": "100003", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1556 "EventCode": "0xB7, 0xBB", 1557 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", 1558 "MSRIndex": "0x1a6,0x1a7", 1559 "MSRValue": "0x23C000020", 1560 "SampleAfterValue": "100003", 1561 "UMask": "0x1" 1562 }, 1563 { 1564 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1565 "EventCode": "0xB7, 0xBB", 1566 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", 1567 "MSRIndex": "0x1a6,0x1a7", 1568 "MSRValue": "0xBC000020", 1569 "SampleAfterValue": "100003", 1570 "UMask": "0x1" 1571 }, 1572 { 1573 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1574 "EventCode": "0xB7, 0xBB", 1575 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1576 "MSRIndex": "0x1a6,0x1a7", 1577 "MSRValue": "0x13C000020", 1578 "SampleAfterValue": "100003", 1579 "UMask": "0x1" 1580 }, 1581 { 1582 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1583 "EventCode": "0xB7, 0xBB", 1584 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1585 "MSRIndex": "0x1a6,0x1a7", 1586 "MSRValue": "0x3F84000020", 1587 "SampleAfterValue": "100003", 1588 "UMask": "0x1" 1589 }, 1590 { 1591 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1592 "EventCode": "0xB7, 0xBB", 1593 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1594 "MSRIndex": "0x1a6,0x1a7", 1595 "MSRValue": "0x1004000020", 1596 "SampleAfterValue": "100003", 1597 "UMask": "0x1" 1598 }, 1599 { 1600 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1601 "EventCode": "0xB7, 0xBB", 1602 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1603 "MSRIndex": "0x1a6,0x1a7", 1604 "MSRValue": "0x404000020", 1605 "SampleAfterValue": "100003", 1606 "UMask": "0x1" 1607 }, 1608 { 1609 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1610 "EventCode": "0xB7, 0xBB", 1611 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1612 "MSRIndex": "0x1a6,0x1a7", 1613 "MSRValue": "0x204000020", 1614 "SampleAfterValue": "100003", 1615 "UMask": "0x1" 1616 }, 1617 { 1618 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1619 "EventCode": "0xB7, 0xBB", 1620 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1621 "MSRIndex": "0x1a6,0x1a7", 1622 "MSRValue": "0x84000020", 1623 "SampleAfterValue": "100003", 1624 "UMask": "0x1" 1625 }, 1626 { 1627 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1628 "EventCode": "0xB7, 0xBB", 1629 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1630 "MSRIndex": "0x1a6,0x1a7", 1631 "MSRValue": "0x2004000020", 1632 "SampleAfterValue": "100003", 1633 "UMask": "0x1" 1634 }, 1635 { 1636 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1637 "EventCode": "0xB7, 0xBB", 1638 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1639 "MSRIndex": "0x1a6,0x1a7", 1640 "MSRValue": "0x104000020", 1641 "SampleAfterValue": "100003", 1642 "UMask": "0x1" 1643 }, 1644 { 1645 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1646 "EventCode": "0xB7, 0xBB", 1647 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 1648 "MSRIndex": "0x1a6,0x1a7", 1649 "MSRValue": "0x2000020020", 1650 "SampleAfterValue": "100003", 1651 "UMask": "0x1" 1652 }, 1653 { 1654 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1655 "EventCode": "0xB7, 0xBB", 1656 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 1657 "MSRIndex": "0x1a6,0x1a7", 1658 "MSRValue": "0x20003C0200", 1659 "SampleAfterValue": "100003", 1660 "UMask": "0x1" 1661 }, 1662 { 1663 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1664 "EventCode": "0xB7, 0xBB", 1665 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1666 "MSRIndex": "0x1a6,0x1a7", 1667 "MSRValue": "0x43C000200", 1668 "SampleAfterValue": "100003", 1669 "UMask": "0x1" 1670 }, 1671 { 1672 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1673 "EventCode": "0xB7, 0xBB", 1674 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", 1675 "MSRIndex": "0x1a6,0x1a7", 1676 "MSRValue": "0x23C000200", 1677 "SampleAfterValue": "100003", 1678 "UMask": "0x1" 1679 }, 1680 { 1681 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1682 "EventCode": "0xB7, 0xBB", 1683 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", 1684 "MSRIndex": "0x1a6,0x1a7", 1685 "MSRValue": "0xBC000200", 1686 "SampleAfterValue": "100003", 1687 "UMask": "0x1" 1688 }, 1689 { 1690 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1691 "EventCode": "0xB7, 0xBB", 1692 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 1693 "MSRIndex": "0x1a6,0x1a7", 1694 "MSRValue": "0x13C000200", 1695 "SampleAfterValue": "100003", 1696 "UMask": "0x1" 1697 }, 1698 { 1699 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1700 "EventCode": "0xB7, 0xBB", 1701 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1702 "MSRIndex": "0x1a6,0x1a7", 1703 "MSRValue": "0x3F84000200", 1704 "SampleAfterValue": "100003", 1705 "UMask": "0x1" 1706 }, 1707 { 1708 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1709 "EventCode": "0xB7, 0xBB", 1710 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1711 "MSRIndex": "0x1a6,0x1a7", 1712 "MSRValue": "0x1004000200", 1713 "SampleAfterValue": "100003", 1714 "UMask": "0x1" 1715 }, 1716 { 1717 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1718 "EventCode": "0xB7, 0xBB", 1719 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1720 "MSRIndex": "0x1a6,0x1a7", 1721 "MSRValue": "0x404000200", 1722 "SampleAfterValue": "100003", 1723 "UMask": "0x1" 1724 }, 1725 { 1726 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1727 "EventCode": "0xB7, 0xBB", 1728 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1729 "MSRIndex": "0x1a6,0x1a7", 1730 "MSRValue": "0x204000200", 1731 "SampleAfterValue": "100003", 1732 "UMask": "0x1" 1733 }, 1734 { 1735 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1736 "EventCode": "0xB7, 0xBB", 1737 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1738 "MSRIndex": "0x1a6,0x1a7", 1739 "MSRValue": "0x84000200", 1740 "SampleAfterValue": "100003", 1741 "UMask": "0x1" 1742 }, 1743 { 1744 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1745 "EventCode": "0xB7, 0xBB", 1746 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1747 "MSRIndex": "0x1a6,0x1a7", 1748 "MSRValue": "0x2004000200", 1749 "SampleAfterValue": "100003", 1750 "UMask": "0x1" 1751 }, 1752 { 1753 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1754 "EventCode": "0xB7, 0xBB", 1755 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1756 "MSRIndex": "0x1a6,0x1a7", 1757 "MSRValue": "0x104000200", 1758 "SampleAfterValue": "100003", 1759 "UMask": "0x1" 1760 }, 1761 { 1762 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1763 "EventCode": "0xB7, 0xBB", 1764 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1765 "MSRIndex": "0x1a6,0x1a7", 1766 "MSRValue": "0x2000020200", 1767 "SampleAfterValue": "100003", 1768 "UMask": "0x1" 1769 }, 1770 { 1771 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1772 "EventCode": "0xB7, 0xBB", 1773 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1774 "MSRIndex": "0x1a6,0x1a7", 1775 "MSRValue": "0x20003C0080", 1776 "SampleAfterValue": "100003", 1777 "UMask": "0x1" 1778 }, 1779 { 1780 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1781 "EventCode": "0xB7, 0xBB", 1782 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1783 "MSRIndex": "0x1a6,0x1a7", 1784 "MSRValue": "0x43C000080", 1785 "SampleAfterValue": "100003", 1786 "UMask": "0x1" 1787 }, 1788 { 1789 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1790 "EventCode": "0xB7, 0xBB", 1791 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 1792 "MSRIndex": "0x1a6,0x1a7", 1793 "MSRValue": "0x23C000080", 1794 "SampleAfterValue": "100003", 1795 "UMask": "0x1" 1796 }, 1797 { 1798 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1799 "EventCode": "0xB7, 0xBB", 1800 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 1801 "MSRIndex": "0x1a6,0x1a7", 1802 "MSRValue": "0xBC000080", 1803 "SampleAfterValue": "100003", 1804 "UMask": "0x1" 1805 }, 1806 { 1807 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1808 "EventCode": "0xB7, 0xBB", 1809 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1810 "MSRIndex": "0x1a6,0x1a7", 1811 "MSRValue": "0x13C000080", 1812 "SampleAfterValue": "100003", 1813 "UMask": "0x1" 1814 }, 1815 { 1816 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1817 "EventCode": "0xB7, 0xBB", 1818 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1819 "MSRIndex": "0x1a6,0x1a7", 1820 "MSRValue": "0x3F84000080", 1821 "SampleAfterValue": "100003", 1822 "UMask": "0x1" 1823 }, 1824 { 1825 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1826 "EventCode": "0xB7, 0xBB", 1827 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1828 "MSRIndex": "0x1a6,0x1a7", 1829 "MSRValue": "0x1004000080", 1830 "SampleAfterValue": "100003", 1831 "UMask": "0x1" 1832 }, 1833 { 1834 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1835 "EventCode": "0xB7, 0xBB", 1836 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1837 "MSRIndex": "0x1a6,0x1a7", 1838 "MSRValue": "0x404000080", 1839 "SampleAfterValue": "100003", 1840 "UMask": "0x1" 1841 }, 1842 { 1843 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1844 "EventCode": "0xB7, 0xBB", 1845 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1846 "MSRIndex": "0x1a6,0x1a7", 1847 "MSRValue": "0x204000080", 1848 "SampleAfterValue": "100003", 1849 "UMask": "0x1" 1850 }, 1851 { 1852 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1853 "EventCode": "0xB7, 0xBB", 1854 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1855 "MSRIndex": "0x1a6,0x1a7", 1856 "MSRValue": "0x84000080", 1857 "SampleAfterValue": "100003", 1858 "UMask": "0x1" 1859 }, 1860 { 1861 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1862 "EventCode": "0xB7, 0xBB", 1863 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1864 "MSRIndex": "0x1a6,0x1a7", 1865 "MSRValue": "0x2004000080", 1866 "SampleAfterValue": "100003", 1867 "UMask": "0x1" 1868 }, 1869 { 1870 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1871 "EventCode": "0xB7, 0xBB", 1872 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1873 "MSRIndex": "0x1a6,0x1a7", 1874 "MSRValue": "0x104000080", 1875 "SampleAfterValue": "100003", 1876 "UMask": "0x1" 1877 }, 1878 { 1879 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1880 "EventCode": "0xB7, 0xBB", 1881 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1882 "MSRIndex": "0x1a6,0x1a7", 1883 "MSRValue": "0x2000020080", 1884 "SampleAfterValue": "100003", 1885 "UMask": "0x1" 1886 }, 1887 { 1888 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1889 "EventCode": "0xB7, 0xBB", 1890 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", 1891 "MSRIndex": "0x1a6,0x1a7", 1892 "MSRValue": "0x20003C0100", 1893 "SampleAfterValue": "100003", 1894 "UMask": "0x1" 1895 }, 1896 { 1897 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1898 "EventCode": "0xB7, 0xBB", 1899 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1900 "MSRIndex": "0x1a6,0x1a7", 1901 "MSRValue": "0x43C000100", 1902 "SampleAfterValue": "100003", 1903 "UMask": "0x1" 1904 }, 1905 { 1906 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1907 "EventCode": "0xB7, 0xBB", 1908 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", 1909 "MSRIndex": "0x1a6,0x1a7", 1910 "MSRValue": "0x23C000100", 1911 "SampleAfterValue": "100003", 1912 "UMask": "0x1" 1913 }, 1914 { 1915 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1916 "EventCode": "0xB7, 0xBB", 1917 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", 1918 "MSRIndex": "0x1a6,0x1a7", 1919 "MSRValue": "0xBC000100", 1920 "SampleAfterValue": "100003", 1921 "UMask": "0x1" 1922 }, 1923 { 1924 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1925 "EventCode": "0xB7, 0xBB", 1926 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1927 "MSRIndex": "0x1a6,0x1a7", 1928 "MSRValue": "0x13C000100", 1929 "SampleAfterValue": "100003", 1930 "UMask": "0x1" 1931 }, 1932 { 1933 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1934 "EventCode": "0xB7, 0xBB", 1935 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1936 "MSRIndex": "0x1a6,0x1a7", 1937 "MSRValue": "0x3F84000100", 1938 "SampleAfterValue": "100003", 1939 "UMask": "0x1" 1940 }, 1941 { 1942 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1943 "EventCode": "0xB7, 0xBB", 1944 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1945 "MSRIndex": "0x1a6,0x1a7", 1946 "MSRValue": "0x1004000100", 1947 "SampleAfterValue": "100003", 1948 "UMask": "0x1" 1949 }, 1950 { 1951 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1952 "EventCode": "0xB7, 0xBB", 1953 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1954 "MSRIndex": "0x1a6,0x1a7", 1955 "MSRValue": "0x404000100", 1956 "SampleAfterValue": "100003", 1957 "UMask": "0x1" 1958 }, 1959 { 1960 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1961 "EventCode": "0xB7, 0xBB", 1962 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1963 "MSRIndex": "0x1a6,0x1a7", 1964 "MSRValue": "0x204000100", 1965 "SampleAfterValue": "100003", 1966 "UMask": "0x1" 1967 }, 1968 { 1969 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1970 "EventCode": "0xB7, 0xBB", 1971 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1972 "MSRIndex": "0x1a6,0x1a7", 1973 "MSRValue": "0x84000100", 1974 "SampleAfterValue": "100003", 1975 "UMask": "0x1" 1976 }, 1977 { 1978 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1979 "EventCode": "0xB7, 0xBB", 1980 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1981 "MSRIndex": "0x1a6,0x1a7", 1982 "MSRValue": "0x2004000100", 1983 "SampleAfterValue": "100003", 1984 "UMask": "0x1" 1985 }, 1986 { 1987 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1988 "EventCode": "0xB7, 0xBB", 1989 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1990 "MSRIndex": "0x1a6,0x1a7", 1991 "MSRValue": "0x104000100", 1992 "SampleAfterValue": "100003", 1993 "UMask": "0x1" 1994 }, 1995 { 1996 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 1997 "EventCode": "0xB7, 0xBB", 1998 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 1999 "MSRIndex": "0x1a6,0x1a7", 2000 "MSRValue": "0x2000020100", 2001 "SampleAfterValue": "100003", 2002 "UMask": "0x1" 2003 }, 2004 { 2005 "BriefDescription": "Number of times RTM abort was triggered", 2006 "EventCode": "0xc9", 2007 "EventName": "RTM_RETIRED.ABORTED", 2008 "PEBS": "1", 2009 "PublicDescription": "Number of times RTM abort was triggered .", 2010 "SampleAfterValue": "2000003", 2011 "UMask": "0x4" 2012 }, 2013 { 2014 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 2015 "EventCode": "0xc9", 2016 "EventName": "RTM_RETIRED.ABORTED_MISC1", 2017 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 2018 "SampleAfterValue": "2000003", 2019 "UMask": "0x8" 2020 }, 2021 { 2022 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 2023 "EventCode": "0xc9", 2024 "EventName": "RTM_RETIRED.ABORTED_MISC2", 2025 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 2026 "SampleAfterValue": "2000003", 2027 "UMask": "0x10" 2028 }, 2029 { 2030 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 2031 "EventCode": "0xc9", 2032 "EventName": "RTM_RETIRED.ABORTED_MISC3", 2033 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 2034 "SampleAfterValue": "2000003", 2035 "UMask": "0x20" 2036 }, 2037 { 2038 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 2039 "EventCode": "0xc9", 2040 "EventName": "RTM_RETIRED.ABORTED_MISC4", 2041 "PublicDescription": "Number of times a RTM caused a fault.", 2042 "SampleAfterValue": "2000003", 2043 "UMask": "0x40" 2044 }, 2045 { 2046 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 2047 "EventCode": "0xc9", 2048 "EventName": "RTM_RETIRED.ABORTED_MISC5", 2049 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 2050 "SampleAfterValue": "2000003", 2051 "UMask": "0x80" 2052 }, 2053 { 2054 "BriefDescription": "Number of times RTM commit succeeded", 2055 "EventCode": "0xc9", 2056 "EventName": "RTM_RETIRED.COMMIT", 2057 "PublicDescription": "Number of times RTM commit succeeded.", 2058 "SampleAfterValue": "2000003", 2059 "UMask": "0x2" 2060 }, 2061 { 2062 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 2063 "EventCode": "0xc9", 2064 "EventName": "RTM_RETIRED.START", 2065 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 2066 "SampleAfterValue": "2000003", 2067 "UMask": "0x1" 2068 }, 2069 { 2070 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 2071 "EventCode": "0x5d", 2072 "EventName": "TX_EXEC.MISC1", 2073 "SampleAfterValue": "2000003", 2074 "UMask": "0x1" 2075 }, 2076 { 2077 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 2078 "EventCode": "0x5d", 2079 "EventName": "TX_EXEC.MISC2", 2080 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 2081 "SampleAfterValue": "2000003", 2082 "UMask": "0x2" 2083 }, 2084 { 2085 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 2086 "EventCode": "0x5d", 2087 "EventName": "TX_EXEC.MISC3", 2088 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 2089 "SampleAfterValue": "2000003", 2090 "UMask": "0x4" 2091 }, 2092 { 2093 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 2094 "EventCode": "0x5d", 2095 "EventName": "TX_EXEC.MISC4", 2096 "PublicDescription": "RTM region detected inside HLE.", 2097 "SampleAfterValue": "2000003", 2098 "UMask": "0x8" 2099 }, 2100 { 2101 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 2102 "EventCode": "0x5d", 2103 "EventName": "TX_EXEC.MISC5", 2104 "SampleAfterValue": "2000003", 2105 "UMask": "0x10" 2106 }, 2107 { 2108 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 2109 "EventCode": "0x54", 2110 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 2111 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 2112 "SampleAfterValue": "2000003", 2113 "UMask": "0x2" 2114 }, 2115 { 2116 "BriefDescription": "Number of times a TSX line had a cache conflict", 2117 "EventCode": "0x54", 2118 "EventName": "TX_MEM.ABORT_CONFLICT", 2119 "PublicDescription": "Number of times a TSX line had a cache conflict.", 2120 "SampleAfterValue": "2000003", 2121 "UMask": "0x1" 2122 }, 2123 { 2124 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 2125 "EventCode": "0x54", 2126 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 2127 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 2128 "SampleAfterValue": "2000003", 2129 "UMask": "0x10" 2130 }, 2131 { 2132 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 2133 "EventCode": "0x54", 2134 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 2135 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 2136 "SampleAfterValue": "2000003", 2137 "UMask": "0x8" 2138 }, 2139 { 2140 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 2141 "EventCode": "0x54", 2142 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 2143 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 2144 "SampleAfterValue": "2000003", 2145 "UMask": "0x20" 2146 }, 2147 { 2148 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 2149 "EventCode": "0x54", 2150 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 2151 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 2152 "SampleAfterValue": "2000003", 2153 "UMask": "0x4" 2154 }, 2155 { 2156 "BriefDescription": "Number of times we could not allocate Lock Buffer", 2157 "EventCode": "0x54", 2158 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 2159 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 2160 "SampleAfterValue": "2000003", 2161 "UMask": "0x40" 2162 } 2163] 2164