1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra20 Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 const: nvidia,tegra20-pinmux 16 17 reg: 18 items: 19 - description: tri-state registers 20 - description: mux register 21 - description: pull-up/down registers 22 - description: pad control registers 23 24patternProperties: 25 "^pinmux(-[a-z0-9-_]+)?$": 26 type: object 27 properties: 28 phandle: true 29 30 # pin groups 31 additionalProperties: 32 $ref: nvidia,tegra-pinmux-common.yaml 33 additionalProperties: false 34 properties: 35 nvidia,pins: 36 items: 37 enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, 38 dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma, 39 gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx, 40 irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1, 41 ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, 42 ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, 43 lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck, 44 lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb, 45 sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia, 46 spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, 47 uad, uca, ucb, uda, 48 # tristate groups 49 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, 50 lc, ld17_0, ld19_18, ld21_20, ld23_22, 51 # drive groups 52 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, 53 drive_cdev2, drive_csus, drive_dap1, drive_dap2, 54 drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2, 55 drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, 56 drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, 57 drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk, 58 drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb, 59 drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ] 60 61 nvidia,function: 62 enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, 63 dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, 64 gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, 65 mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1, 66 pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr, 67 pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2, 68 sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3, 69 spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi, 70 vi, vi_sensor_clk, xio ] 71 72 nvidia,pull: true 73 nvidia,tristate: true 74 nvidia,schmitt: true 75 nvidia,pull-down-strength: true 76 nvidia,pull-up-strength: true 77 nvidia,high-speed-mode: true 78 nvidia,low-power-mode: true 79 nvidia,slew-rate-rising: true 80 nvidia,slew-rate-falling: true 81 82 required: 83 - nvidia,pins 84 85additionalProperties: false 86 87required: 88 - compatible 89 - reg 90 91examples: 92 - | 93 #include <dt-bindings/clock/tegra20-car.h> 94 #include <dt-bindings/interrupt-controller/arm-gic.h> 95 96 pinctrl@70000000 { 97 compatible = "nvidia,tegra20-pinmux"; 98 reg = <0x70000014 0x10>, /* Tri-state registers */ 99 <0x70000080 0x20>, /* Mux registers */ 100 <0x700000a0 0x14>, /* Pull-up/down registers */ 101 <0x70000868 0xa8>; /* Pad control registers */ 102 103 pinmux { 104 atb { 105 nvidia,pins = "atb", "gma", "gme"; 106 nvidia,function = "sdio4"; 107 nvidia,pull = <0>; 108 nvidia,tristate = <0>; 109 }; 110 }; 111 }; 112... 113