xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso (revision 69bfec7548f4c1595bac0e3ddfc0458a5af31f4c)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 *
5 * GW72xx RS422 (RS485 full duplex):
6 *  - GPIO1_0 rs485_term selects on-chip termination
7 *  - GPIO4_0 rs485_en needs to be driven high (active)
8 *  - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 *  - UART4_TX is DE for RS485 transmitter
10 *  - RS485_EN needs to be pulled high
11 *  - RS485_HALF needs to be low
12 */
13
14#include <dt-bindings/gpio/gpio.h>
15
16#include "imx8mm-pinfunc.h"
17
18/dts-v1/;
19/plugin/;
20
21&{/} {
22	compatible = "gw,imx8mm-gw72xx-0x";
23};
24
25&gpio4 {
26	rs485_en {
27		gpio-hog;
28		gpios = <0 GPIO_ACTIVE_HIGH>;
29		output-high;
30		line-name = "rs485_en";
31	};
32
33	rs485_hd {
34		gpio-hog;
35		gpios = <2 GPIO_ACTIVE_HIGH>;
36		output-low;
37		line-name = "rs485_hd";
38	};
39};
40
41&uart2 {
42	pinctrl-names = "default";
43	pinctrl-0 = <&pinctrl_uart2>;
44	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
45	linux,rs485-enabled-at-boot-time;
46	status = "okay";
47};
48
49&uart4 {
50	status = "disabled";
51};
52
53&iomuxc {
54	pinctrl_uart2: uart2grp {
55		fsl,pins = <
56			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
57			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
58			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
59		>;
60	};
61};
62