| be0e82b8 | 10-Jun-2026 |
Alexandre MINETTE <contact@alex-min.fr> |
drm/msm/a3xx: Drain VBIF before GPU suspend
A3xx hangs after every runtime suspend on the Samsung Galaxy S4
GT-I9505. Even simple GPU workloads, such as drawing a single triangle,
hang reliably once
drm/msm/a3xx: Drain VBIF before GPU suspend
A3xx hangs after every runtime suspend on the Samsung Galaxy S4
GT-I9505. Even simple GPU workloads, such as drawing a single triangle,
hang reliably once the GPU has been suspended by runtime PM.
The generic MSM GPU suspend path disables clocks/power, but A3xx also
needs to ensure that pending VBIF transactions are drained before that
happens.
Add an A3xx-specific pm_suspend callback. Wait for the GPU to become
idle, halt all VBIF XIN clients, wait for the corresponding
acknowledgment, and only then enter the generic MSM GPU suspend path.
This fixes reliable A3xx GPU hangs observed after runtime PM on the
Samsung Galaxy S4 GT-I9505, codename jflte. The failure is reported as:
mdp4 5100000.display-controller: [drm:hangcheck_handler] *ERROR* 3.2.0.2: hangcheck detected gpu lockup rb 0!
mdp4 5100000.display-controller: [drm:hangcheck_handler] *ERROR* 3.2.0.2: completed fence: 4294967041
mdp4 5100000.display-controller: [drm:hangcheck_handler] *ERROR* 3.2.0.2: submitted fence: 4294967049
mdp4 5100000.display-controller: [drm:recover_worker] *ERROR* 3.2.0.2: hangcheck recover!
Link: https://github.com/freedreno-zz/freedreno/issues/12
Signed-off-by: Alexandre MINETTE <contact@alex-min.fr>
Patchwork: https://patchwork.freedesktop.org/patch/731919/
Message-ID: <20260610-mainline-fix-a3xx-gpu-hang-sending-v1-1-9282182840b5@alex-min.fr>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| 510fad8a | 26-May-2026 |
Rob Clark <robin.clark@oss.qualcomm.com> |
drm/msm/registers: Sync gen_header.py from mesa
Update gen_header.py to bring in support for generating perfcntr tables.
Sync from mesa commit 96c5179c02d1 ("freedreno/registers: Skip deprecated
wa
drm/msm/registers: Sync gen_header.py from mesa
Update gen_header.py to bring in support for generating perfcntr tables.
Sync from mesa commit 96c5179c02d1 ("freedreno/registers: Skip deprecated
warns for kernel")
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728203/
Message-ID: <20260526145137.160554-5-robin.clark@oss.qualcomm.com>
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| cfc8b486 | 27-Mar-2026 |
Akhil P Oommen <akhilpo@oss.qualcomm.com> |
drm/msm/a8xx: Fix the ticks used in submit traces
GMU_ALWAYS_ON_COUNTER_* registers got moved in A8x, but currently, A6x
register offsets are used in the submit traces instead of A8x offsets.
To fix
drm/msm/a8xx: Fix the ticks used in submit traces
GMU_ALWAYS_ON_COUNTER_* registers got moved in A8x, but currently, A6x
register offsets are used in the submit traces instead of A8x offsets.
To fix this, refactor a bit and use adreno_gpu->funcs->get_timestamp()
everywhere.
While we are at it, update a8xx_gmu_get_timestamp() to use the GMU AO
counter.
Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714655/
Message-ID: <20260327-a8xx-gpu-batch2-v2-2-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| 288a9320 | 18-Nov-2025 |
Akhil P Oommen <akhilpo@oss.qualcomm.com> |
drm/msm/adreno: Introduce A8x GPU Support
A8x is the next generation of Adreno GPUs, featuring a significant
hardware design change. A major update to the design is the introduction
of Slice archite
drm/msm/adreno: Introduce A8x GPU Support
A8x is the next generation of Adreno GPUs, featuring a significant
hardware design change. A major update to the design is the introduction
of Slice architecture. Slices are sort of mini-GPUs within the GPU which
are more independent in processing Graphics and compute workloads. Also,
in addition to the BV and BR pipe we saw in A7x, CP has more concurrency
with additional pipes.
From a software interface perspective, these changes have a significant
impact on the KMD side. First, the GPU register space has been extensively
reorganized. Second, to avoid a register space explosion caused by the
new slice architecture and additional pipes, many registers are now
virtualized, instead of duplicated as in A7x. KMD must configure an
aperture register with the appropriate slice and pipe ID before accessing
these virtualized registers.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689019/
Message-ID: <20251118-kaana-gpu-support-v4-14-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| 50e8a557 | 18-Nov-2025 |
Akhil P Oommen <akhilpo@oss.qualcomm.com> |
drm/msm/a8xx: Add support for A8x GMU
A8x GMU configurations are very similar to A7x. Unfortunately, there are
minor shuffling in the register offsets in the GMU CX register region.
So, update the d
drm/msm/a8xx: Add support for A8x GMU
A8x GMU configurations are very similar to A7x. Unfortunately, there are
minor shuffling in the register offsets in the GMU CX register region.
So, update the driver to use the correct register offsets on A8x hw.
Some A8x GPUs have more than 16 powerlevels on GX domain and 4 on CX
domain. To accommodate this, increase the arrays' sizes which hold gx and
cx power levels.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689013/
Message-ID: <20251118-kaana-gpu-support-v4-11-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| 188db3d7 | 18-Nov-2025 |
Akhil P Oommen <akhilpo@oss.qualcomm.com> |
drm/msm/a6xx: Rebase GMU register offsets
GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x famil
drm/msm/a6xx: Rebase GMU register offsets
GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x family, the base address of the GMU has changed, but the offsets
of the gmu registers remain largely the same. To enable reuse of the gmu
code for A8x chipsets, update the gmu register offsets to be relative
to the GPU's base address instead of GMU's.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689010/
Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| f5232d63 | 18-Nov-2025 |
Akhil P Oommen <akhilpo@oss.qualcomm.com> |
drm/msm/adreno: Common-ize PIPE definitions
Newer gen's introduce pipe enums which do not exist on older gens, but
the numeric values do not conflict. IOW, they are backward compatible.
So move its
drm/msm/adreno: Common-ize PIPE definitions
Newer gen's introduce pipe enums which do not exist on older gens, but
the numeric values do not conflict. IOW, they are backward compatible.
So move its definition to adreno_common.xml.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689001/
Message-ID: <20251118-kaana-gpu-support-v4-5-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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| b5bad77e | 08-Sep-2025 |
Rob Clark <robin.clark@oss.qualcomm.com> |
drm/msm/registers: Sync GPU registers from mesa
In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.
Sync from mesa commit 15ee3873aa4d ("freedreno/registers
drm/msm/registers: Sync GPU registers from mesa
In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.
Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU
register xml").
Cc: Karmjit Mahil <karmjit.mahil@igalia.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673558/
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| 60e9f776 | 08-Sep-2025 |
Rob Clark <robin.clark@oss.qualcomm.com> |
drm/msm/registers: Generate _HI/LO builders for reg64
The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's. This works better with the "new-
drm/msm/registers: Generate _HI/LO builders for reg64
The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's. This works better with the "new-
style" c++ builders that mesa has been migrating to for a6xx+ (to better
handle register shuffling between gens), but it leaves the C builders
with missing _HI/LO builders.
So handle the special case of reg64, automatically generating the
missing _HI/LO builders.
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673559/
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| 90528176 | 08-Sep-2025 |
Rob Clark <robin.clark@oss.qualcomm.com> |
drm/msm/registers: Sync gen_header.py from mesa
Sync from mesa commit 04e2140d8be7 ("freedreno/registers: remove python
3.9 dependency for compiling msm").
Signed-off-by: Rob Clark <robin.clark@oss
drm/msm/registers: Sync gen_header.py from mesa
Sync from mesa commit 04e2140d8be7 ("freedreno/registers: remove python
3.9 dependency for compiling msm").
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673556/
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| f03464c6 | 08-Sep-2025 |
Rob Clark <robin.clark@oss.qualcomm.com> |
drm/msm/registers: Remove license/etc from generated headers
Since these generated files are no longer checked in, either in mesa or
in the linux kernel, simplify things by dropping the verbose gene
drm/msm/registers: Remove license/etc from generated headers
Since these generated files are no longer checked in, either in mesa or
in the linux kernel, simplify things by dropping the verbose generated
comment.
These were semi-nerf'd on the kernel side, in the name of build
reproducibility, by commit ba64c6737f86 ("drivers: gpu: drm: msm:
registers: improve reproducibility"), but in a way that was semi-
kernel specific. We can just reduce the divergence between kernel
and mesa by just dropping all of this.
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673551/
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| 494045c5 | 30-Jul-2025 |
Ayushi Makhija <quic_amakhija@quicinc.com> |
drm/msm: update the high bitfield of certain DSI registers
Currently, the high bitfield of certain DSI registers
do not align with the configuration of the SWI registers
description. This can lead t
drm/msm: update the high bitfield of certain DSI registers
Currently, the high bitfield of certain DSI registers
do not align with the configuration of the SWI registers
description. This can lead to wrong programming these DSI
registers, for example for 4k resloution where H_TOTAL is
taking 13 bits but software is programming only 12 bits
because of the incorrect bitmask for H_TOTAL bitfeild,
this is causing DSI FIFO errors. To resolve this issue,
increase the high bitfield of the DSI registers from 12 bits
to 16 bits in dsi.xml to match the SWI register configuration.
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Fixes: 4f52f5e63b62 ("drm/msm: import XML display registers database")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/666229/
Link: https://lore.kernel.org/r/20250730123938.1038640-1-quic_amakhija@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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