1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include <dt-bindings/leds/leds-pca9532.h> 11#include <dt-bindings/pwm/pwm.h> 12#include "imx8mp-phycore-som.dtsi" 13 14/ { 15 model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 16 compatible = "phytec,imx8mp-phyboard-pollux-rdk", 17 "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart1; 21 }; 22 23 backlight_lvds: backlight { 24 compatible = "pwm-backlight"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_lvds1>; 27 brightness-levels = <0 4 8 16 32 64 128 255>; 28 default-brightness-level = <11>; 29 enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; 30 num-interpolated-steps = <2>; 31 power-supply = <®_lvds1_reg_en>; 32 pwms = <&pwm3 0 50000 0>; 33 }; 34 35 panel1_lvds: panel-lvds { 36 compatible = "edt,etml1010g3dra"; 37 backlight = <&backlight_lvds>; 38 power-supply = <®_vcc_3v3_sw>; 39 40 port { 41 panel1_in: endpoint { 42 remote-endpoint = <&ldb_lvds_ch1>; 43 }; 44 }; 45 }; 46 47 reg_vcc_5v_sw: regulator-vcc-5v-sw { 48 compatible = "regulator-fixed"; 49 regulator-always-on; 50 regulator-boot-on; 51 regulator-max-microvolt = <5000000>; 52 regulator-min-microvolt = <5000000>; 53 regulator-name = "VCC_5V_SW"; 54 }; 55 56 reg_can1_stby: regulator-can1-stby { 57 compatible = "regulator-fixed"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_flexcan1_reg>; 60 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 61 regulator-max-microvolt = <3300000>; 62 regulator-min-microvolt = <3300000>; 63 regulator-name = "can1-stby"; 64 }; 65 66 reg_can2_stby: regulator-can2-stby { 67 compatible = "regulator-fixed"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_flexcan2_reg>; 70 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; 71 regulator-max-microvolt = <3300000>; 72 regulator-min-microvolt = <3300000>; 73 regulator-name = "can2-stby"; 74 }; 75 76 reg_lvds1_reg_en: regulator-lvds1 { 77 compatible = "regulator-fixed"; 78 enable-active-high; 79 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 80 regulator-max-microvolt = <1200000>; 81 regulator-min-microvolt = <1200000>; 82 regulator-name = "lvds1_reg_en"; 83 }; 84 85 reg_usb1_vbus: regulator-usb1-vbus { 86 compatible = "regulator-fixed"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_usb1_vbus>; 89 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; 90 regulator-max-microvolt = <5000000>; 91 regulator-min-microvolt = <5000000>; 92 regulator-name = "usb1_host_vbus"; 93 }; 94 95 reg_usdhc2_vmmc: regulator-usdhc2 { 96 compatible = "regulator-fixed"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 99 regulator-name = "VSD_3V3"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 103 enable-active-high; 104 startup-delay-us = <100>; 105 off-on-delay-us = <12000>; 106 }; 107 108 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { 109 compatible = "regulator-fixed"; 110 regulator-name = "VCC_3V3_SW"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 }; 114}; 115 116/* TPM */ 117&ecspi1 { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_ecspi1>; 123 status = "okay"; 124 125 tpm: tpm@0 { 126 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 127 reg = <0>; 128 spi-max-frequency = <38000000>; 129 }; 130}; 131 132&eqos { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_eqos>; 135 phy-mode = "rgmii-id"; 136 phy-handle = <ðphy0>; 137 status = "okay"; 138 139 mdio { 140 compatible = "snps,dwmac-mdio"; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 ethphy0: ethernet-phy@1 { 145 compatible = "ethernet-phy-ieee802.3-c22"; 146 reg = <0x1>; 147 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 148 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 149 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 150 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 151 enet-phy-lane-no-swap; 152 }; 153 }; 154}; 155 156/* CAN FD */ 157&flexcan1 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_flexcan1>; 160 xceiver-supply = <®_can1_stby>; 161 status = "okay"; 162}; 163 164&flexcan2 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_flexcan2>; 167 xceiver-supply = <®_can2_stby>; 168 status = "okay"; 169}; 170 171&i2c2 { 172 clock-frequency = <400000>; 173 pinctrl-names = "default", "gpio"; 174 pinctrl-0 = <&pinctrl_i2c2>; 175 pinctrl-1 = <&pinctrl_i2c2_gpio>; 176 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 177 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 status = "okay"; 179 180 eeprom@51 { 181 compatible = "atmel,24c02"; 182 reg = <0x51>; 183 pagesize = <16>; 184 vcc-supply = <®_vcc_3v3_sw>; 185 }; 186 187 leds@62 { 188 compatible = "nxp,pca9533"; 189 reg = <0x62>; 190 191 led-1 { 192 type = <PCA9532_TYPE_LED>; 193 }; 194 195 led-2 { 196 type = <PCA9532_TYPE_LED>; 197 }; 198 199 led-3 { 200 type = <PCA9532_TYPE_LED>; 201 }; 202 }; 203}; 204 205&lcdif2 { 206 status = "okay"; 207}; 208 209&lvds_bridge { 210 status = "okay"; 211 212 ports { 213 port@2 { 214 ldb_lvds_ch1: endpoint { 215 remote-endpoint = <&panel1_in>; 216 }; 217 }; 218 }; 219}; 220 221&snvs_pwrkey { 222 status = "okay"; 223}; 224 225&pcie_phy { 226 clocks = <&hsio_blk_ctrl>; 227 clock-names = "ref"; 228 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 229 fsl,clkreq-unsupported; 230 status = "okay"; 231}; 232 233/* Mini PCIe */ 234&pcie { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_pcie0>; 237 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; 238 vpcie-supply = <®_vcc_3v3_sw>; 239 status = "okay"; 240}; 241 242&pwm3 { 243 status = "okay"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_pwm3>; 246}; 247 248&rv3028 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_rtc>; 251 interrupt-parent = <&gpio4>; 252 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 253 aux-voltage-chargeable = <1>; 254 wakeup-source; 255 trickle-resistor-ohms = <3000>; 256}; 257 258/* debug console */ 259&uart1 { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_uart1>; 262 status = "okay"; 263}; 264 265/* USB1 Host mode Type-A */ 266&usb3_phy0 { 267 vbus-supply = <®_usb1_vbus>; 268 status = "okay"; 269}; 270 271&usb3_0 { 272 status = "okay"; 273}; 274 275&usb_dwc3_0 { 276 dr_mode = "host"; 277 status = "okay"; 278}; 279 280/* USB2 4-port USB3.0 HUB */ 281&usb3_phy1 { 282 vbus-supply = <®_vcc_5v_sw>; 283 status = "okay"; 284}; 285 286&usb3_1 { 287 fsl,permanently-attached; 288 fsl,disable-port-power-control; 289 status = "okay"; 290}; 291 292&usb_dwc3_1 { 293 dr_mode = "host"; 294 status = "okay"; 295}; 296 297/* RS232/RS485 */ 298&uart2 { 299 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 300 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_uart2>; 303 uart-has-rtscts; 304 status = "okay"; 305}; 306 307/* SD-Card */ 308&usdhc2 { 309 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 310 assigned-clock-rates = <200000000>; 311 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 312 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 313 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; 314 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; 315 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 316 disable-wp; 317 vmmc-supply = <®_usdhc2_vmmc>; 318 vqmmc-supply = <&ldo5>; 319 bus-width = <4>; 320 status = "okay"; 321}; 322 323&gpio1 { 324 gpio-line-names = "", "", "X_PMIC_WDOG_B", "", 325 "PMIC_SD_VSEL", "", "", "", "", "", 326 "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; 327}; 328 329&gpio2 { 330 gpio-line-names = "", "", "", "", 331 "", "", "", "", "", "", 332 "", "", "X_SD2_CD_B", "", "", "", 333 "", "", "", "SD2_RESET_B"; 334}; 335 336&gpio3 { 337 gpio-line-names = "", "", "", "", 338 "", "", "", "", "", "", 339 "", "", "", "", "", "", 340 "", "", "", "", "nCAN1_EN", "nCAN2_EN"; 341}; 342 343&gpio4 { 344 gpio-line-names = "", "", "", "", 345 "", "", "", "", "", "", 346 "", "", "", "", "", "", 347 "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; 348}; 349 350&iomuxc { 351 pinctrl_ecspi1: ecspi1grp { 352 fsl,pins = < 353 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80 354 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80 355 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80 356 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00 357 >; 358 }; 359 360 pinctrl_eqos: eqosgrp { 361 fsl,pins = < 362 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 363 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 364 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 365 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 366 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 367 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 368 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 369 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 370 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 371 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 372 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 373 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 374 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 375 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 376 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 377 >; 378 }; 379 380 pinctrl_flexcan1: flexcan1grp { 381 fsl,pins = < 382 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 383 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 384 >; 385 }; 386 387 pinctrl_flexcan2: flexcan2grp { 388 fsl,pins = < 389 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 390 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 391 >; 392 }; 393 394 pinctrl_flexcan1_reg: flexcan1reggrp { 395 fsl,pins = < 396 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 397 >; 398 }; 399 400 pinctrl_flexcan2_reg: flexcan2reggrp { 401 fsl,pins = < 402 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 403 >; 404 }; 405 406 pinctrl_i2c2: i2c2grp { 407 fsl,pins = < 408 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 409 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 410 >; 411 }; 412 413 pinctrl_i2c2_gpio: i2c2gpiogrp { 414 fsl,pins = < 415 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 416 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 417 >; 418 }; 419 420 pinctrl_lvds1: lvds1grp { 421 fsl,pins = < 422 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 423 >; 424 }; 425 426 pinctrl_pcie0: pcie0grp { 427 fsl,pins = < 428 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 429 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60 430 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ 431 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 432 >; 433 }; 434 435 pinctrl_pwm3: pwm3grp { 436 fsl,pins = < 437 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 438 >; 439 }; 440 441 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 442 fsl,pins = < 443 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 444 >; 445 }; 446 447 pinctrl_rtc: rtcgrp { 448 fsl,pins = < 449 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 450 >; 451 }; 452 453 pinctrl_uart1: uart1grp { 454 fsl,pins = < 455 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 456 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 457 >; 458 }; 459 460 pinctrl_usb1_vbus: usb1vbusgrp { 461 fsl,pins = < 462 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 463 >; 464 }; 465 466 pinctrl_uart2: uart2grp { 467 fsl,pins = < 468 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 469 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 470 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 471 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 472 >; 473 }; 474 475 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 476 fsl,pins = < 477 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40 478 >; 479 }; 480 481 pinctrl_usdhc2: usdhc2grp { 482 fsl,pins = < 483 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 484 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 485 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 486 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 487 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 488 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 489 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 490 >; 491 }; 492 493 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 494 fsl,pins = < 495 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 496 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 497 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 498 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 499 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 500 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 501 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 502 >; 503 }; 504 505 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 506 fsl,pins = < 507 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 508 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 509 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 510 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 511 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 512 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 513 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 514 >; 515 }; 516}; 517