1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __UMC_V12_0_H__ 24 #define __UMC_V12_0_H__ 25 26 #include "soc15_common.h" 27 #include "amdgpu.h" 28 29 #define UMC_V12_0_NODE_DIST 0x40000000 30 #define UMC_V12_0_INST_DIST 0x40000 31 32 /* UMC register per channel offset */ 33 #define UMC_V12_0_PER_CHANNEL_OFFSET 0x400 34 35 /* UMC cross node offset */ 36 #define UMC_V12_0_CROSS_NODE_OFFSET 0x100000000 37 38 /* OdEccErrCnt max value */ 39 #define UMC_V12_0_CE_CNT_MAX 0xffff 40 /* umc ce interrupt threshold */ 41 #define UMC_V12_0_CE_INT_THRESHOLD 0xffff 42 /* umc ce count initial value */ 43 #define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD) 44 45 /* number of umc channel instance with memory map register access */ 46 #define UMC_V12_0_CHANNEL_INSTANCE_NUM 8 47 /* number of umc instance with memory map register access */ 48 #define UMC_V12_0_UMC_INSTANCE_NUM 4 49 50 /* Total channel instances for all available umc nodes */ 51 #define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \ 52 (UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc) 53 54 /* one piece of normalized address is mapped to 8 pieces of physical address */ 55 #define UMC_V12_0_NA_MAP_PA_NUM 8 56 /* R13 bit shift should be considered, double the number */ 57 #define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2) 58 59 /* column bits in SOC physical address */ 60 #define UMC_V12_0_PA_C2_BIT 15 61 #define UMC_V12_0_PA_C4_BIT 21 62 /* row bits in SOC physical address */ 63 #define UMC_V12_0_PA_R13_BIT 35 64 65 #define MCA_UMC_HWID_V12_0 0x96 66 #define MCA_UMC_MCATYPE_V12_0 0x0 67 68 #define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \ 69 (((_ipid_lo) >> 12) & 0xF)) 70 #define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7) 71 72 #define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03) 73 74 #define MCA_IPID_2_UMC_CH(ipid) \ 75 (MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) 76 77 #define MCA_IPID_2_UMC_INST(ipid) \ 78 (MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) 79 80 #define MCA_IPID_2_SOCKET_ID(ipid) \ 81 (((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \ 82 (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03)) 83 84 #define UMC_V12_ADDR_MASK_BAD_COLS(addr) \ 85 ((addr) & ~((0x3ULL << UMC_V12_0_PA_C2_BIT) | \ 86 (0x1ULL << UMC_V12_0_PA_C4_BIT) | \ 87 (0x1ULL << UMC_V12_0_PA_R13_BIT))) 88 89 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status); 90 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); 91 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); 92 93 typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status); 94 95 extern struct amdgpu_umc_ras umc_v12_0_ras; 96 97 #endif 98