1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq5018-dwc3 18 - qcom,ipq5332-dwc3 19 - qcom,ipq6018-dwc3 20 - qcom,ipq8064-dwc3 21 - qcom,ipq8074-dwc3 22 - qcom,ipq9574-dwc3 23 - qcom,msm8953-dwc3 24 - qcom,msm8994-dwc3 25 - qcom,msm8996-dwc3 26 - qcom,msm8998-dwc3 27 - qcom,qcm2290-dwc3 28 - qcom,qcs404-dwc3 29 - qcom,qdu1000-dwc3 30 - qcom,sa8775p-dwc3 31 - qcom,sc7180-dwc3 32 - qcom,sc7280-dwc3 33 - qcom,sc8180x-dwc3 34 - qcom,sc8180x-dwc3-mp 35 - qcom,sc8280xp-dwc3 36 - qcom,sc8280xp-dwc3-mp 37 - qcom,sdm660-dwc3 38 - qcom,sdm670-dwc3 39 - qcom,sdm845-dwc3 40 - qcom,sdx55-dwc3 41 - qcom,sdx65-dwc3 42 - qcom,sdx75-dwc3 43 - qcom,sm4250-dwc3 44 - qcom,sm6115-dwc3 45 - qcom,sm6125-dwc3 46 - qcom,sm6350-dwc3 47 - qcom,sm6375-dwc3 48 - qcom,sm8150-dwc3 49 - qcom,sm8250-dwc3 50 - qcom,sm8350-dwc3 51 - qcom,sm8450-dwc3 52 - qcom,sm8550-dwc3 53 - qcom,sm8650-dwc3 54 - qcom,x1e80100-dwc3 55 - qcom,x1e80100-dwc3-mp 56 - const: qcom,dwc3 57 58 reg: 59 description: Offset and length of register set for QSCRATCH wrapper 60 maxItems: 1 61 62 "#address-cells": 63 enum: [ 1, 2 ] 64 65 "#size-cells": 66 enum: [ 1, 2 ] 67 68 ranges: true 69 70 power-domains: 71 description: specifies a phandle to PM domain provider node 72 maxItems: 1 73 74 required-opps: 75 maxItems: 1 76 77 clocks: 78 description: | 79 Several clocks are used, depending on the variant. Typical ones are:: 80 - cfg_noc:: System Config NOC clock. 81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 82 60MHz for HS operation. 83 - iface:: System bus AXI clock. 84 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 85 power mode (U3). 86 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 87 mode. Its frequency should be 19.2MHz. 88 minItems: 1 89 maxItems: 9 90 91 clock-names: 92 minItems: 1 93 maxItems: 9 94 95 resets: 96 maxItems: 1 97 98 interconnects: 99 maxItems: 2 100 101 interconnect-names: 102 items: 103 - const: usb-ddr 104 - const: apps-usb 105 106 interrupts: 107 description: | 108 Different types of interrupts are used based on HS PHY used on target: 109 - pwr_event: Used for wakeup based on other power events. 110 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 111 hs_phy_irq which is not triggered by default and its 112 functionality is mutually exclusive to that of 113 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 114 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 115 expose only a single IRQ whose behavior can be modified 116 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 117 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 118 of PHY address space. 119 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 120 DM pads of the SoC. These are used for wakeup 121 only on SoCs with non-QUSB2 targets with 122 exception of SDM670/SDM845/SM6350. 123 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 124 minItems: 2 125 maxItems: 18 126 127 interrupt-names: 128 minItems: 2 129 maxItems: 18 130 131 qcom,select-utmi-as-pipe-clk: 132 description: 133 If present, disable USB3 pipe_clk requirement. 134 Used when dwc3 operates without SSPHY and only 135 HS/FS/LS modes are supported. 136 type: boolean 137 138 wakeup-source: true 139 140# Required child node: 141 142patternProperties: 143 "^usb@[0-9a-f]+$": 144 $ref: snps,dwc3.yaml# 145 unevaluatedProperties: false 146 147 properties: 148 wakeup-source: false 149 150required: 151 - compatible 152 - reg 153 - "#address-cells" 154 - "#size-cells" 155 - ranges 156 - clocks 157 - clock-names 158 - interrupts 159 - interrupt-names 160 161allOf: 162 - if: 163 properties: 164 compatible: 165 contains: 166 enum: 167 - qcom,ipq4019-dwc3 168 - qcom,ipq5332-dwc3 169 then: 170 properties: 171 clocks: 172 maxItems: 3 173 clock-names: 174 items: 175 - const: core 176 - const: sleep 177 - const: mock_utmi 178 179 - if: 180 properties: 181 compatible: 182 contains: 183 enum: 184 - qcom,ipq8064-dwc3 185 then: 186 properties: 187 clocks: 188 items: 189 - description: Master/Core clock, has to be >= 125 MHz 190 for SS operation and >= 60MHz for HS operation. 191 clock-names: 192 items: 193 - const: core 194 195 - if: 196 properties: 197 compatible: 198 contains: 199 enum: 200 - qcom,ipq9574-dwc3 201 - qcom,msm8953-dwc3 202 - qcom,msm8996-dwc3 203 - qcom,msm8998-dwc3 204 - qcom,sa8775p-dwc3 205 - qcom,sc7180-dwc3 206 - qcom,sc7280-dwc3 207 - qcom,sdm670-dwc3 208 - qcom,sdm845-dwc3 209 - qcom,sdx55-dwc3 210 - qcom,sdx65-dwc3 211 - qcom,sdx75-dwc3 212 - qcom,sm6350-dwc3 213 then: 214 properties: 215 clocks: 216 maxItems: 5 217 clock-names: 218 items: 219 - const: cfg_noc 220 - const: core 221 - const: iface 222 - const: sleep 223 - const: mock_utmi 224 225 - if: 226 properties: 227 compatible: 228 contains: 229 enum: 230 - qcom,ipq6018-dwc3 231 then: 232 properties: 233 clocks: 234 minItems: 3 235 maxItems: 4 236 clock-names: 237 oneOf: 238 - items: 239 - const: core 240 - const: sleep 241 - const: mock_utmi 242 - items: 243 - const: cfg_noc 244 - const: core 245 - const: sleep 246 - const: mock_utmi 247 248 - if: 249 properties: 250 compatible: 251 contains: 252 enum: 253 - qcom,ipq8074-dwc3 254 - qcom,qdu1000-dwc3 255 then: 256 properties: 257 clocks: 258 maxItems: 4 259 clock-names: 260 items: 261 - const: cfg_noc 262 - const: core 263 - const: sleep 264 - const: mock_utmi 265 266 - if: 267 properties: 268 compatible: 269 contains: 270 enum: 271 - qcom,ipq5018-dwc3 272 - qcom,msm8994-dwc3 273 - qcom,qcs404-dwc3 274 then: 275 properties: 276 clocks: 277 maxItems: 4 278 clock-names: 279 items: 280 - const: core 281 - const: iface 282 - const: sleep 283 - const: mock_utmi 284 285 - if: 286 properties: 287 compatible: 288 contains: 289 enum: 290 - qcom,sc8280xp-dwc3 291 - qcom,sc8280xp-dwc3-mp 292 - qcom,x1e80100-dwc3 293 - qcom,x1e80100-dwc3-mp 294 then: 295 properties: 296 clocks: 297 maxItems: 9 298 clock-names: 299 items: 300 - const: cfg_noc 301 - const: core 302 - const: iface 303 - const: sleep 304 - const: mock_utmi 305 - const: noc_aggr 306 - const: noc_aggr_north 307 - const: noc_aggr_south 308 - const: noc_sys 309 310 - if: 311 properties: 312 compatible: 313 contains: 314 enum: 315 - qcom,sdm660-dwc3 316 then: 317 properties: 318 clocks: 319 minItems: 4 320 maxItems: 5 321 clock-names: 322 oneOf: 323 - items: 324 - const: cfg_noc 325 - const: core 326 - const: iface 327 - const: sleep 328 - const: mock_utmi 329 - items: 330 - const: cfg_noc 331 - const: core 332 - const: sleep 333 - const: mock_utmi 334 335 - if: 336 properties: 337 compatible: 338 contains: 339 enum: 340 - qcom,qcm2290-dwc3 341 - qcom,sc8180x-dwc3 342 - qcom,sc8180x-dwc3-mp 343 - qcom,sm6115-dwc3 344 - qcom,sm6125-dwc3 345 - qcom,sm8150-dwc3 346 - qcom,sm8250-dwc3 347 - qcom,sm8450-dwc3 348 - qcom,sm8550-dwc3 349 - qcom,sm8650-dwc3 350 then: 351 properties: 352 clocks: 353 minItems: 6 354 clock-names: 355 items: 356 - const: cfg_noc 357 - const: core 358 - const: iface 359 - const: sleep 360 - const: mock_utmi 361 - const: xo 362 363 - if: 364 properties: 365 compatible: 366 contains: 367 enum: 368 - qcom,sm8350-dwc3 369 then: 370 properties: 371 clocks: 372 minItems: 5 373 maxItems: 6 374 clock-names: 375 minItems: 5 376 items: 377 - const: cfg_noc 378 - const: core 379 - const: iface 380 - const: sleep 381 - const: mock_utmi 382 - const: xo 383 384 - if: 385 properties: 386 compatible: 387 contains: 388 enum: 389 - qcom,ipq5018-dwc3 390 - qcom,ipq6018-dwc3 391 - qcom,ipq8074-dwc3 392 - qcom,msm8953-dwc3 393 - qcom,msm8998-dwc3 394 then: 395 properties: 396 interrupts: 397 minItems: 2 398 maxItems: 3 399 interrupt-names: 400 items: 401 - const: pwr_event 402 - const: qusb2_phy 403 - const: ss_phy_irq 404 405 - if: 406 properties: 407 compatible: 408 contains: 409 enum: 410 - qcom,msm8996-dwc3 411 - qcom,qcs404-dwc3 412 - qcom,sdm660-dwc3 413 - qcom,sm6115-dwc3 414 - qcom,sm6125-dwc3 415 then: 416 properties: 417 interrupts: 418 minItems: 3 419 maxItems: 4 420 interrupt-names: 421 items: 422 - const: pwr_event 423 - const: qusb2_phy 424 - const: hs_phy_irq 425 - const: ss_phy_irq 426 427 - if: 428 properties: 429 compatible: 430 contains: 431 enum: 432 - qcom,ipq5332-dwc3 433 then: 434 properties: 435 interrupts: 436 maxItems: 3 437 interrupt-names: 438 items: 439 - const: pwr_event 440 - const: dp_hs_phy_irq 441 - const: dm_hs_phy_irq 442 443 - if: 444 properties: 445 compatible: 446 contains: 447 enum: 448 - qcom,x1e80100-dwc3 449 then: 450 properties: 451 interrupts: 452 maxItems: 4 453 interrupt-names: 454 items: 455 - const: pwr_event 456 - const: dp_hs_phy_irq 457 - const: dm_hs_phy_irq 458 - const: ss_phy_irq 459 460 - if: 461 properties: 462 compatible: 463 contains: 464 enum: 465 - qcom,ipq4019-dwc3 466 - qcom,ipq8064-dwc3 467 - qcom,msm8994-dwc3 468 - qcom,qdu1000-dwc3 469 - qcom,sa8775p-dwc3 470 - qcom,sc7180-dwc3 471 - qcom,sc7280-dwc3 472 - qcom,sc8180x-dwc3 473 - qcom,sc8280xp-dwc3 474 - qcom,sdm670-dwc3 475 - qcom,sdm845-dwc3 476 - qcom,sdx55-dwc3 477 - qcom,sdx65-dwc3 478 - qcom,sdx75-dwc3 479 - qcom,sm4250-dwc3 480 - qcom,sm6350-dwc3 481 - qcom,sm8150-dwc3 482 - qcom,sm8250-dwc3 483 - qcom,sm8350-dwc3 484 - qcom,sm8450-dwc3 485 - qcom,sm8550-dwc3 486 - qcom,sm8650-dwc3 487 then: 488 properties: 489 interrupts: 490 minItems: 4 491 maxItems: 5 492 interrupt-names: 493 items: 494 - const: pwr_event 495 - const: hs_phy_irq 496 - const: dp_hs_phy_irq 497 - const: dm_hs_phy_irq 498 - const: ss_phy_irq 499 500 - if: 501 properties: 502 compatible: 503 contains: 504 enum: 505 - qcom,sc8180x-dwc3-mp 506 - qcom,x1e80100-dwc3-mp 507 then: 508 properties: 509 interrupts: 510 minItems: 10 511 maxItems: 10 512 interrupt-names: 513 items: 514 - const: pwr_event_1 515 - const: pwr_event_2 516 - const: hs_phy_1 517 - const: hs_phy_2 518 - const: dp_hs_phy_1 519 - const: dm_hs_phy_1 520 - const: dp_hs_phy_2 521 - const: dm_hs_phy_2 522 - const: ss_phy_1 523 - const: ss_phy_2 524 525 - if: 526 properties: 527 compatible: 528 contains: 529 enum: 530 - qcom,sc8280xp-dwc3-mp 531 then: 532 properties: 533 interrupts: 534 minItems: 18 535 maxItems: 18 536 interrupt-names: 537 items: 538 - const: pwr_event_1 539 - const: pwr_event_2 540 - const: pwr_event_3 541 - const: pwr_event_4 542 - const: hs_phy_1 543 - const: hs_phy_2 544 - const: hs_phy_3 545 - const: hs_phy_4 546 - const: dp_hs_phy_1 547 - const: dm_hs_phy_1 548 - const: dp_hs_phy_2 549 - const: dm_hs_phy_2 550 - const: dp_hs_phy_3 551 - const: dm_hs_phy_3 552 - const: dp_hs_phy_4 553 - const: dm_hs_phy_4 554 - const: ss_phy_1 555 - const: ss_phy_2 556 557additionalProperties: false 558 559examples: 560 - | 561 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 562 #include <dt-bindings/interrupt-controller/arm-gic.h> 563 #include <dt-bindings/interrupt-controller/irq.h> 564 soc { 565 #address-cells = <2>; 566 #size-cells = <2>; 567 568 usb@a6f8800 { 569 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 570 reg = <0 0x0a6f8800 0 0x400>; 571 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges; 575 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 576 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 577 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 578 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 579 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 580 clock-names = "cfg_noc", 581 "core", 582 "iface", 583 "sleep", 584 "mock_utmi"; 585 586 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 587 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 588 assigned-clock-rates = <19200000>, <150000000>; 589 590 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 593 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 594 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 595 interrupt-names = "pwr_event", "hs_phy_irq", 596 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 597 598 power-domains = <&gcc USB30_PRIM_GDSC>; 599 600 resets = <&gcc GCC_USB30_PRIM_BCR>; 601 602 usb@a600000 { 603 compatible = "snps,dwc3"; 604 reg = <0 0x0a600000 0 0xcd00>; 605 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 606 iommus = <&apps_smmu 0x740 0>; 607 snps,dis_u2_susphy_quirk; 608 snps,dis_enblslpm_quirk; 609 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 610 phy-names = "usb2-phy", "usb3-phy"; 611 }; 612 }; 613 }; 614