1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "unused", 103 "SET_DEBUG_VMID", 104 "MISC", 105 "UPDATE_ROOT_PAGE_TABLE", 106 "AMD_LOG", 107 "SET_SE_MODE", 108 "SET_GANG_SUBMIT", 109 "SET_HW_RSRC_1", 110 }; 111 112 static const char *mes_v12_0_misc_opcodes[] = { 113 "WRITE_REG", 114 "INV_GART", 115 "QUERY_STATUS", 116 "READ_REG", 117 "WAIT_REG_MEM", 118 "SET_SHADER_DEBUGGER", 119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 120 "NOTIFY_TO_UNMAP_PROCESSES", 121 }; 122 123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 124 { 125 const char *op_str = NULL; 126 127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 129 130 return op_str; 131 } 132 133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 134 { 135 const char *op_str = NULL; 136 137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 140 141 return op_str; 142 } 143 144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 145 int pipe, void *pkt, int size, 146 int api_status_off) 147 { 148 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 149 signed long timeout = 3000000; /* 3000 ms */ 150 struct amdgpu_device *adev = mes->adev; 151 struct amdgpu_ring *ring = &mes->ring[pipe]; 152 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 153 struct MES_API_STATUS *api_status; 154 union MESAPI__MISC *x_pkt = pkt; 155 const char *op_str, *misc_op_str; 156 unsigned long flags; 157 u64 status_gpu_addr; 158 u32 seq, status_offset; 159 u64 *status_ptr; 160 signed long r; 161 int ret; 162 163 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 164 return -EINVAL; 165 166 if (amdgpu_emu_mode) { 167 timeout *= 100; 168 } else if (amdgpu_sriov_vf(adev)) { 169 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 170 timeout = 15 * 600 * 1000; 171 } 172 173 ret = amdgpu_device_wb_get(adev, &status_offset); 174 if (ret) 175 return ret; 176 177 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 178 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 179 *status_ptr = 0; 180 181 spin_lock_irqsave(ring_lock, flags); 182 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 183 if (r) 184 goto error_unlock_free; 185 186 seq = ++ring->fence_drv.sync_seq; 187 r = amdgpu_fence_wait_polling(ring, 188 seq - ring->fence_drv.num_fences_mask, 189 timeout); 190 if (r < 1) 191 goto error_undo; 192 193 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 194 api_status->api_completion_fence_addr = status_gpu_addr; 195 api_status->api_completion_fence_value = 1; 196 197 amdgpu_ring_write_multiple(ring, pkt, size / 4); 198 199 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 200 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 201 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 202 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 203 mes_status_pkt.api_status.api_completion_fence_addr = 204 ring->fence_drv.gpu_addr; 205 mes_status_pkt.api_status.api_completion_fence_value = seq; 206 207 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 208 sizeof(mes_status_pkt) / 4); 209 210 amdgpu_ring_commit(ring); 211 spin_unlock_irqrestore(ring_lock, flags); 212 213 op_str = mes_v12_0_get_op_string(x_pkt); 214 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 215 216 if (misc_op_str) 217 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 218 pipe, op_str, misc_op_str); 219 else if (op_str) 220 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 221 pipe, op_str); 222 else 223 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 224 pipe, x_pkt->header.opcode); 225 226 r = amdgpu_fence_wait_polling(ring, seq, timeout); 227 if (r < 1 || !*status_ptr) { 228 229 if (misc_op_str) 230 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 231 pipe, op_str, misc_op_str); 232 else if (op_str) 233 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 234 pipe, op_str); 235 else 236 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 237 pipe, x_pkt->header.opcode); 238 239 while (halt_if_hws_hang) 240 schedule(); 241 242 r = -ETIMEDOUT; 243 goto error_wb_free; 244 } 245 246 amdgpu_device_wb_free(adev, status_offset); 247 return 0; 248 249 error_undo: 250 dev_err(adev->dev, "MES ring buffer is full.\n"); 251 amdgpu_ring_undo(ring); 252 253 error_unlock_free: 254 spin_unlock_irqrestore(ring_lock, flags); 255 256 error_wb_free: 257 amdgpu_device_wb_free(adev, status_offset); 258 return r; 259 } 260 261 static int convert_to_mes_queue_type(int queue_type) 262 { 263 if (queue_type == AMDGPU_RING_TYPE_GFX) 264 return MES_QUEUE_TYPE_GFX; 265 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 266 return MES_QUEUE_TYPE_COMPUTE; 267 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 268 return MES_QUEUE_TYPE_SDMA; 269 else if (queue_type == AMDGPU_RING_TYPE_MES) 270 return MES_QUEUE_TYPE_SCHQ; 271 else 272 BUG(); 273 return -1; 274 } 275 276 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 277 struct mes_add_queue_input *input) 278 { 279 struct amdgpu_device *adev = mes->adev; 280 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 281 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 282 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 283 284 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 285 286 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 287 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 288 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 289 290 mes_add_queue_pkt.process_id = input->process_id; 291 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 292 mes_add_queue_pkt.process_va_start = input->process_va_start; 293 mes_add_queue_pkt.process_va_end = input->process_va_end; 294 mes_add_queue_pkt.process_quantum = input->process_quantum; 295 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 296 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 297 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 298 mes_add_queue_pkt.inprocess_gang_priority = 299 input->inprocess_gang_priority; 300 mes_add_queue_pkt.gang_global_priority_level = 301 input->gang_global_priority_level; 302 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 303 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 304 305 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 306 307 mes_add_queue_pkt.queue_type = 308 convert_to_mes_queue_type(input->queue_type); 309 mes_add_queue_pkt.paging = input->paging; 310 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 311 mes_add_queue_pkt.gws_base = input->gws_base; 312 mes_add_queue_pkt.gws_size = input->gws_size; 313 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 314 mes_add_queue_pkt.tma_addr = input->tma_addr; 315 mes_add_queue_pkt.trap_en = input->trap_en; 316 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 317 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 318 319 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 320 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 321 mes_add_queue_pkt.gds_size = input->queue_size; 322 323 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 324 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 325 mes_add_queue_pkt.gds_size = input->queue_size; 326 327 return mes_v12_0_submit_pkt_and_poll_completion(mes, 328 AMDGPU_MES_SCHED_PIPE, 329 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 330 offsetof(union MESAPI__ADD_QUEUE, api_status)); 331 } 332 333 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 334 struct mes_remove_queue_input *input) 335 { 336 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 337 338 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 339 340 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 341 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 342 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 343 344 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 345 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 346 347 return mes_v12_0_submit_pkt_and_poll_completion(mes, 348 AMDGPU_MES_SCHED_PIPE, 349 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 350 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 351 } 352 353 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 354 struct mes_reset_queue_input *input) 355 { 356 union MESAPI__RESET mes_reset_queue_pkt; 357 int pipe; 358 359 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 360 361 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 362 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 363 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 364 365 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 366 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 367 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 368 369 if (mes->adev->enable_uni_mes) 370 pipe = AMDGPU_MES_KIQ_PIPE; 371 else 372 pipe = AMDGPU_MES_SCHED_PIPE; 373 374 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 375 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 376 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 377 } 378 379 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 380 struct mes_map_legacy_queue_input *input) 381 { 382 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 383 int pipe; 384 385 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 386 387 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 388 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 389 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 390 391 mes_add_queue_pkt.pipe_id = input->pipe_id; 392 mes_add_queue_pkt.queue_id = input->queue_id; 393 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 394 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 395 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 396 mes_add_queue_pkt.queue_type = 397 convert_to_mes_queue_type(input->queue_type); 398 mes_add_queue_pkt.map_legacy_kq = 1; 399 400 if (mes->adev->enable_uni_mes) 401 pipe = AMDGPU_MES_KIQ_PIPE; 402 else 403 pipe = AMDGPU_MES_SCHED_PIPE; 404 405 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 406 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 407 offsetof(union MESAPI__ADD_QUEUE, api_status)); 408 } 409 410 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 411 struct mes_unmap_legacy_queue_input *input) 412 { 413 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 414 int pipe; 415 416 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 417 418 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 419 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 420 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 421 422 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 423 mes_remove_queue_pkt.gang_context_addr = 0; 424 425 mes_remove_queue_pkt.pipe_id = input->pipe_id; 426 mes_remove_queue_pkt.queue_id = input->queue_id; 427 428 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 429 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 430 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 431 mes_remove_queue_pkt.tf_data = 432 lower_32_bits(input->trail_fence_data); 433 } else { 434 mes_remove_queue_pkt.unmap_legacy_queue = 1; 435 mes_remove_queue_pkt.queue_type = 436 convert_to_mes_queue_type(input->queue_type); 437 } 438 439 if (mes->adev->enable_uni_mes) 440 pipe = AMDGPU_MES_KIQ_PIPE; 441 else 442 pipe = AMDGPU_MES_SCHED_PIPE; 443 444 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 445 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 446 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 447 } 448 449 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 450 struct mes_suspend_gang_input *input) 451 { 452 return 0; 453 } 454 455 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 456 struct mes_resume_gang_input *input) 457 { 458 return 0; 459 } 460 461 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 462 { 463 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 464 465 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 466 467 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 468 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 469 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 470 471 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 472 &mes_status_pkt, sizeof(mes_status_pkt), 473 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 474 } 475 476 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 477 struct mes_misc_op_input *input) 478 { 479 union MESAPI__MISC misc_pkt; 480 int pipe; 481 482 memset(&misc_pkt, 0, sizeof(misc_pkt)); 483 484 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 485 misc_pkt.header.opcode = MES_SCH_API_MISC; 486 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 487 488 switch (input->op) { 489 case MES_MISC_OP_READ_REG: 490 misc_pkt.opcode = MESAPI_MISC__READ_REG; 491 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 492 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 493 break; 494 case MES_MISC_OP_WRITE_REG: 495 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 496 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 497 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 498 break; 499 case MES_MISC_OP_WRM_REG_WAIT: 500 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 501 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 502 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 503 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 504 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 505 misc_pkt.wait_reg_mem.reg_offset2 = 0; 506 break; 507 case MES_MISC_OP_WRM_REG_WR_WAIT: 508 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 509 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 510 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 511 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 512 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 513 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 514 break; 515 case MES_MISC_OP_SET_SHADER_DEBUGGER: 516 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 517 misc_pkt.set_shader_debugger.process_context_addr = 518 input->set_shader_debugger.process_context_addr; 519 misc_pkt.set_shader_debugger.flags.u32all = 520 input->set_shader_debugger.flags.u32all; 521 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 522 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 523 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 524 input->set_shader_debugger.tcp_watch_cntl, 525 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 526 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 527 break; 528 default: 529 DRM_ERROR("unsupported misc op (%d) \n", input->op); 530 return -EINVAL; 531 } 532 533 if (mes->adev->enable_uni_mes) 534 pipe = AMDGPU_MES_KIQ_PIPE; 535 else 536 pipe = AMDGPU_MES_SCHED_PIPE; 537 538 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 539 &misc_pkt, sizeof(misc_pkt), 540 offsetof(union MESAPI__MISC, api_status)); 541 } 542 543 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 544 { 545 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 546 547 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 548 549 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 550 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 551 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 552 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 553 554 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 555 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 556 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 557 } 558 559 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 560 { 561 int i; 562 struct amdgpu_device *adev = mes->adev; 563 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 564 565 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 566 567 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 568 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 569 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 570 571 if (pipe == AMDGPU_MES_SCHED_PIPE) { 572 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 573 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 574 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 575 mes_set_hw_res_pkt.paging_vmid = 0; 576 577 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 578 mes_set_hw_res_pkt.compute_hqd_mask[i] = 579 mes->compute_hqd_mask[i]; 580 581 for (i = 0; i < MAX_GFX_PIPES; i++) 582 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 583 mes->gfx_hqd_mask[i]; 584 585 for (i = 0; i < MAX_SDMA_PIPES; i++) 586 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 587 mes->sdma_hqd_mask[i]; 588 589 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 590 mes_set_hw_res_pkt.aggregated_doorbells[i] = 591 mes->aggregated_doorbells[i]; 592 } 593 594 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 595 mes->sch_ctx_gpu_addr[pipe]; 596 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 597 mes->query_status_fence_gpu_addr[pipe]; 598 599 for (i = 0; i < 5; i++) { 600 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 601 mes_set_hw_res_pkt.mmhub_base[i] = 602 adev->reg_offset[MMHUB_HWIP][0][i]; 603 mes_set_hw_res_pkt.osssys_base[i] = 604 adev->reg_offset[OSSSYS_HWIP][0][i]; 605 } 606 607 mes_set_hw_res_pkt.disable_reset = 1; 608 mes_set_hw_res_pkt.disable_mes_log = 1; 609 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 610 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 611 612 /* 613 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 614 * handling support, other queue will not use the oversubscribe timer. 615 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 616 */ 617 mes_set_hw_res_pkt.oversubscription_timer = 50; 618 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 619 620 if (amdgpu_mes_log_enable) { 621 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 622 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 623 } 624 625 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 626 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 627 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 628 } 629 630 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 631 { 632 struct amdgpu_device *adev = mes->adev; 633 uint32_t data; 634 635 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 636 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 637 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 638 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 639 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 640 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 641 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 642 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 643 644 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 645 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 646 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 647 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 648 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 649 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 650 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 651 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 652 653 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 654 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 655 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 656 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 657 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 658 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 659 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 660 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 661 662 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 663 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 664 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 665 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 666 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 667 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 668 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 669 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 670 671 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 672 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 673 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 674 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 675 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 676 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 677 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 678 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 679 680 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 681 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 682 } 683 684 685 static void mes_v12_0_enable_unmapped_doorbell_handling( 686 struct amdgpu_mes *mes, bool enable) 687 { 688 struct amdgpu_device *adev = mes->adev; 689 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 690 691 /* 692 * The default PROC_LSB settng is 0xc which means doorbell 693 * addr[16:12] gives the doorbell page number. For kfd, each 694 * process will use 2 pages of doorbell, we need to change the 695 * setting to 0xd 696 */ 697 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 698 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 699 700 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 701 702 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 703 } 704 705 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes, 706 struct mes_reset_legacy_queue_input *input) 707 { 708 union MESAPI__RESET mes_reset_queue_pkt; 709 int pipe; 710 711 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 712 713 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 714 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 715 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 716 717 mes_reset_queue_pkt.queue_type = 718 convert_to_mes_queue_type(input->queue_type); 719 720 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 721 mes_reset_queue_pkt.reset_legacy_gfx = 1; 722 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 723 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 724 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 725 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 726 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 727 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 728 } else { 729 mes_reset_queue_pkt.reset_queue_only = 1; 730 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 731 } 732 733 if (mes->adev->enable_uni_mes) 734 pipe = AMDGPU_MES_KIQ_PIPE; 735 else 736 pipe = AMDGPU_MES_SCHED_PIPE; 737 738 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 739 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 740 offsetof(union MESAPI__RESET, api_status)); 741 } 742 743 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 744 .add_hw_queue = mes_v12_0_add_hw_queue, 745 .remove_hw_queue = mes_v12_0_remove_hw_queue, 746 .map_legacy_queue = mes_v12_0_map_legacy_queue, 747 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 748 .suspend_gang = mes_v12_0_suspend_gang, 749 .resume_gang = mes_v12_0_resume_gang, 750 .misc_op = mes_v12_0_misc_op, 751 .reset_legacy_queue = mes_v12_0_reset_legacy_queue, 752 .reset_hw_queue = mes_v12_0_reset_hw_queue, 753 }; 754 755 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 756 enum admgpu_mes_pipe pipe) 757 { 758 int r; 759 const struct mes_firmware_header_v1_0 *mes_hdr; 760 const __le32 *fw_data; 761 unsigned fw_size; 762 763 mes_hdr = (const struct mes_firmware_header_v1_0 *) 764 adev->mes.fw[pipe]->data; 765 766 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 767 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 768 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 769 770 r = amdgpu_bo_create_reserved(adev, fw_size, 771 PAGE_SIZE, 772 AMDGPU_GEM_DOMAIN_VRAM, 773 &adev->mes.ucode_fw_obj[pipe], 774 &adev->mes.ucode_fw_gpu_addr[pipe], 775 (void **)&adev->mes.ucode_fw_ptr[pipe]); 776 if (r) { 777 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 778 return r; 779 } 780 781 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 782 783 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 784 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 785 786 return 0; 787 } 788 789 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 790 enum admgpu_mes_pipe pipe) 791 { 792 int r; 793 const struct mes_firmware_header_v1_0 *mes_hdr; 794 const __le32 *fw_data; 795 unsigned fw_size; 796 797 mes_hdr = (const struct mes_firmware_header_v1_0 *) 798 adev->mes.fw[pipe]->data; 799 800 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 801 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 802 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 803 804 r = amdgpu_bo_create_reserved(adev, fw_size, 805 64 * 1024, 806 AMDGPU_GEM_DOMAIN_VRAM, 807 &adev->mes.data_fw_obj[pipe], 808 &adev->mes.data_fw_gpu_addr[pipe], 809 (void **)&adev->mes.data_fw_ptr[pipe]); 810 if (r) { 811 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 812 return r; 813 } 814 815 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 816 817 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 818 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 819 820 return 0; 821 } 822 823 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 824 enum admgpu_mes_pipe pipe) 825 { 826 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 827 &adev->mes.data_fw_gpu_addr[pipe], 828 (void **)&adev->mes.data_fw_ptr[pipe]); 829 830 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 831 &adev->mes.ucode_fw_gpu_addr[pipe], 832 (void **)&adev->mes.ucode_fw_ptr[pipe]); 833 } 834 835 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 836 { 837 uint64_t ucode_addr; 838 uint32_t pipe, data = 0; 839 840 if (enable) { 841 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 842 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 843 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 844 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 845 846 mutex_lock(&adev->srbm_mutex); 847 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 848 soc21_grbm_select(adev, 3, pipe, 0, 0); 849 850 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 851 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 852 lower_32_bits(ucode_addr)); 853 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 854 upper_32_bits(ucode_addr)); 855 } 856 soc21_grbm_select(adev, 0, 0, 0, 0); 857 mutex_unlock(&adev->srbm_mutex); 858 859 /* unhalt MES and activate pipe0 */ 860 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 861 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 862 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 863 864 if (amdgpu_emu_mode) 865 msleep(100); 866 else if (adev->enable_uni_mes) 867 udelay(500); 868 else 869 udelay(50); 870 } else { 871 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 872 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 873 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 874 data = REG_SET_FIELD(data, CP_MES_CNTL, 875 MES_INVALIDATE_ICACHE, 1); 876 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 877 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 878 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 879 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 880 } 881 } 882 883 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 884 { 885 uint64_t ucode_addr; 886 int pipe; 887 888 mes_v12_0_enable(adev, false); 889 890 mutex_lock(&adev->srbm_mutex); 891 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 892 /* me=3, queue=0 */ 893 soc21_grbm_select(adev, 3, pipe, 0, 0); 894 895 /* set ucode start address */ 896 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 897 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 898 lower_32_bits(ucode_addr)); 899 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 900 upper_32_bits(ucode_addr)); 901 902 soc21_grbm_select(adev, 0, 0, 0, 0); 903 } 904 mutex_unlock(&adev->srbm_mutex); 905 } 906 907 /* This function is for backdoor MES firmware */ 908 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 909 enum admgpu_mes_pipe pipe, bool prime_icache) 910 { 911 int r; 912 uint32_t data; 913 914 mes_v12_0_enable(adev, false); 915 916 if (!adev->mes.fw[pipe]) 917 return -EINVAL; 918 919 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 920 if (r) 921 return r; 922 923 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 924 if (r) { 925 mes_v12_0_free_ucode_buffers(adev, pipe); 926 return r; 927 } 928 929 mutex_lock(&adev->srbm_mutex); 930 /* me=3, pipe=0, queue=0 */ 931 soc21_grbm_select(adev, 3, pipe, 0, 0); 932 933 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 934 935 /* set ucode fimrware address */ 936 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 937 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 938 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 939 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 940 941 /* set ucode instruction cache boundary to 2M-1 */ 942 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 943 944 /* set ucode data firmware address */ 945 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 946 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 947 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 948 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 949 950 /* Set data cache boundary CP_MES_MDBOUND_LO */ 951 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 952 953 if (prime_icache) { 954 /* invalidate ICACHE */ 955 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 956 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 957 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 958 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 959 960 /* prime the ICACHE. */ 961 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 962 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 963 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 964 } 965 966 soc21_grbm_select(adev, 0, 0, 0, 0); 967 mutex_unlock(&adev->srbm_mutex); 968 969 return 0; 970 } 971 972 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 973 enum admgpu_mes_pipe pipe) 974 { 975 int r; 976 u32 *eop; 977 978 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 979 AMDGPU_GEM_DOMAIN_GTT, 980 &adev->mes.eop_gpu_obj[pipe], 981 &adev->mes.eop_gpu_addr[pipe], 982 (void **)&eop); 983 if (r) { 984 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 985 return r; 986 } 987 988 memset(eop, 0, 989 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 990 991 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 992 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 993 994 return 0; 995 } 996 997 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 998 { 999 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1000 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1001 uint32_t tmp; 1002 1003 mqd->header = 0xC0310800; 1004 mqd->compute_pipelinestat_enable = 0x00000001; 1005 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1006 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1007 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1008 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1009 mqd->compute_misc_reserved = 0x00000007; 1010 1011 eop_base_addr = ring->eop_gpu_addr >> 8; 1012 1013 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1014 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1015 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1016 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1017 1018 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1019 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1020 mqd->cp_hqd_eop_control = tmp; 1021 1022 /* disable the queue if it's active */ 1023 ring->wptr = 0; 1024 mqd->cp_hqd_pq_rptr = 0; 1025 mqd->cp_hqd_pq_wptr_lo = 0; 1026 mqd->cp_hqd_pq_wptr_hi = 0; 1027 1028 /* set the pointer to the MQD */ 1029 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1030 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1031 1032 /* set MQD vmid to 0 */ 1033 tmp = regCP_MQD_CONTROL_DEFAULT; 1034 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1035 mqd->cp_mqd_control = tmp; 1036 1037 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1038 hqd_gpu_addr = ring->gpu_addr >> 8; 1039 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1040 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1041 1042 /* set the wb address whether it's enabled or not */ 1043 wb_gpu_addr = ring->rptr_gpu_addr; 1044 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1045 mqd->cp_hqd_pq_rptr_report_addr_hi = 1046 upper_32_bits(wb_gpu_addr) & 0xffff; 1047 1048 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1049 wb_gpu_addr = ring->wptr_gpu_addr; 1050 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1051 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1052 1053 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1054 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1055 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1056 (order_base_2(ring->ring_size / 4) - 1)); 1057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1058 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1064 mqd->cp_hqd_pq_control = tmp; 1065 1066 /* enable doorbell */ 1067 tmp = 0; 1068 if (ring->use_doorbell) { 1069 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1070 DOORBELL_OFFSET, ring->doorbell_index); 1071 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1072 DOORBELL_EN, 1); 1073 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1074 DOORBELL_SOURCE, 0); 1075 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1076 DOORBELL_HIT, 0); 1077 } else { 1078 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1079 DOORBELL_EN, 0); 1080 } 1081 mqd->cp_hqd_pq_doorbell_control = tmp; 1082 1083 mqd->cp_hqd_vmid = 0; 1084 /* activate the queue */ 1085 mqd->cp_hqd_active = 1; 1086 1087 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1088 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1089 PRELOAD_SIZE, 0x55); 1090 mqd->cp_hqd_persistent_state = tmp; 1091 1092 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1093 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1094 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1095 1096 /* 1097 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1098 * doorbell handling. This is a reserved CP internal register can 1099 * not be accesss by others 1100 */ 1101 mqd->reserved_184 = BIT(15); 1102 1103 return 0; 1104 } 1105 1106 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1107 { 1108 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1109 struct amdgpu_device *adev = ring->adev; 1110 uint32_t data = 0; 1111 1112 mutex_lock(&adev->srbm_mutex); 1113 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1114 1115 /* set CP_HQD_VMID.VMID = 0. */ 1116 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1117 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1118 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1119 1120 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1121 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1122 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1123 DOORBELL_EN, 0); 1124 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1125 1126 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1127 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1128 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1129 1130 /* set CP_MQD_CONTROL.VMID=0 */ 1131 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1132 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1133 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1134 1135 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1136 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1137 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1138 1139 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1140 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1141 mqd->cp_hqd_pq_rptr_report_addr_lo); 1142 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1143 mqd->cp_hqd_pq_rptr_report_addr_hi); 1144 1145 /* set CP_HQD_PQ_CONTROL */ 1146 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1147 1148 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1149 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1150 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1151 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1152 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1153 1154 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1155 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1156 mqd->cp_hqd_pq_doorbell_control); 1157 1158 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1159 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1160 1161 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1162 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1163 1164 soc21_grbm_select(adev, 0, 0, 0, 0); 1165 mutex_unlock(&adev->srbm_mutex); 1166 } 1167 1168 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1169 { 1170 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1171 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1172 int r; 1173 1174 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1175 return -EINVAL; 1176 1177 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1178 if (r) { 1179 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1180 return r; 1181 } 1182 1183 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1184 1185 r = amdgpu_ring_test_ring(kiq_ring); 1186 if (r) { 1187 DRM_ERROR("kfq enable failed\n"); 1188 kiq_ring->sched.ready = false; 1189 } 1190 return r; 1191 } 1192 1193 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1194 enum admgpu_mes_pipe pipe) 1195 { 1196 struct amdgpu_ring *ring; 1197 int r; 1198 1199 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1200 ring = &adev->gfx.kiq[0].ring; 1201 else 1202 ring = &adev->mes.ring[pipe]; 1203 1204 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1205 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1206 *(ring->wptr_cpu_addr) = 0; 1207 *(ring->rptr_cpu_addr) = 0; 1208 amdgpu_ring_clear_ring(ring); 1209 } 1210 1211 r = mes_v12_0_mqd_init(ring); 1212 if (r) 1213 return r; 1214 1215 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1216 if (adev->enable_uni_mes) 1217 r = amdgpu_mes_map_legacy_queue(adev, ring); 1218 else 1219 r = mes_v12_0_kiq_enable_queue(adev); 1220 if (r) 1221 return r; 1222 } else { 1223 mes_v12_0_queue_init_register(ring); 1224 } 1225 1226 /* get MES scheduler/KIQ versions */ 1227 mutex_lock(&adev->srbm_mutex); 1228 soc21_grbm_select(adev, 3, pipe, 0, 0); 1229 1230 if (pipe == AMDGPU_MES_SCHED_PIPE) 1231 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1232 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1233 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1234 1235 soc21_grbm_select(adev, 0, 0, 0, 0); 1236 mutex_unlock(&adev->srbm_mutex); 1237 1238 return 0; 1239 } 1240 1241 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1242 { 1243 struct amdgpu_ring *ring; 1244 1245 ring = &adev->mes.ring[pipe]; 1246 1247 ring->funcs = &mes_v12_0_ring_funcs; 1248 1249 ring->me = 3; 1250 ring->pipe = pipe; 1251 ring->queue = 0; 1252 1253 ring->ring_obj = NULL; 1254 ring->use_doorbell = true; 1255 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1256 ring->no_scheduler = true; 1257 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1258 1259 if (pipe == AMDGPU_MES_SCHED_PIPE) 1260 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1261 else 1262 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1263 1264 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1265 AMDGPU_RING_PRIO_DEFAULT, NULL); 1266 } 1267 1268 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1269 { 1270 struct amdgpu_ring *ring; 1271 1272 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1273 1274 ring = &adev->gfx.kiq[0].ring; 1275 1276 ring->me = 3; 1277 ring->pipe = 1; 1278 ring->queue = 0; 1279 1280 ring->adev = NULL; 1281 ring->ring_obj = NULL; 1282 ring->use_doorbell = true; 1283 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1284 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1285 ring->no_scheduler = true; 1286 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1287 ring->me, ring->pipe, ring->queue); 1288 1289 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1290 AMDGPU_RING_PRIO_DEFAULT, NULL); 1291 } 1292 1293 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1294 enum admgpu_mes_pipe pipe) 1295 { 1296 int r, mqd_size = sizeof(struct v12_compute_mqd); 1297 struct amdgpu_ring *ring; 1298 1299 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1300 ring = &adev->gfx.kiq[0].ring; 1301 else 1302 ring = &adev->mes.ring[pipe]; 1303 1304 if (ring->mqd_obj) 1305 return 0; 1306 1307 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1308 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1309 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1310 if (r) { 1311 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1312 return r; 1313 } 1314 1315 memset(ring->mqd_ptr, 0, mqd_size); 1316 1317 /* prepare MQD backup */ 1318 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1319 if (!adev->mes.mqd_backup[pipe]) 1320 dev_warn(adev->dev, 1321 "no memory to create MQD backup for ring %s\n", 1322 ring->name); 1323 1324 return 0; 1325 } 1326 1327 static int mes_v12_0_sw_init(void *handle) 1328 { 1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1330 int pipe, r; 1331 1332 adev->mes.funcs = &mes_v12_0_funcs; 1333 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1334 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1335 1336 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1337 1338 r = amdgpu_mes_init(adev); 1339 if (r) 1340 return r; 1341 1342 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1343 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1344 if (r) 1345 return r; 1346 1347 r = mes_v12_0_mqd_sw_init(adev, pipe); 1348 if (r) 1349 return r; 1350 1351 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1352 r = mes_v12_0_kiq_ring_init(adev); 1353 else 1354 r = mes_v12_0_ring_init(adev, pipe); 1355 if (r) 1356 return r; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static int mes_v12_0_sw_fini(void *handle) 1363 { 1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1365 int pipe; 1366 1367 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1368 kfree(adev->mes.mqd_backup[pipe]); 1369 1370 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1371 &adev->mes.eop_gpu_addr[pipe], 1372 NULL); 1373 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1374 1375 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1376 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1377 &adev->mes.ring[pipe].mqd_gpu_addr, 1378 &adev->mes.ring[pipe].mqd_ptr); 1379 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1380 } 1381 } 1382 1383 if (!adev->enable_uni_mes) { 1384 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1385 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1386 &adev->gfx.kiq[0].ring.mqd_ptr); 1387 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1388 } 1389 1390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1391 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1392 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1393 } 1394 1395 amdgpu_mes_fini(adev); 1396 return 0; 1397 } 1398 1399 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1400 { 1401 uint32_t data; 1402 int i; 1403 1404 mutex_lock(&adev->srbm_mutex); 1405 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1406 1407 /* disable the queue if it's active */ 1408 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1409 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1410 for (i = 0; i < adev->usec_timeout; i++) { 1411 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1412 break; 1413 udelay(1); 1414 } 1415 } 1416 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1417 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1418 DOORBELL_EN, 0); 1419 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1420 DOORBELL_HIT, 1); 1421 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1422 1423 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1424 1425 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1426 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1427 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1428 1429 soc21_grbm_select(adev, 0, 0, 0, 0); 1430 mutex_unlock(&adev->srbm_mutex); 1431 1432 adev->mes.ring[0].sched.ready = false; 1433 } 1434 1435 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1436 { 1437 uint32_t tmp; 1438 struct amdgpu_device *adev = ring->adev; 1439 1440 /* tell RLC which is KIQ queue */ 1441 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1442 tmp &= 0xffffff00; 1443 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1444 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1445 tmp |= 0x80; 1446 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1447 } 1448 1449 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1450 { 1451 int r = 0; 1452 1453 if (adev->enable_uni_mes) 1454 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1455 else 1456 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1457 1458 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1459 1460 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1461 if (r) { 1462 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1463 return r; 1464 } 1465 1466 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1467 if (r) { 1468 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1469 return r; 1470 } 1471 1472 mes_v12_0_set_ucode_start_addr(adev); 1473 1474 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1475 mes_v12_0_set_ucode_start_addr(adev); 1476 1477 mes_v12_0_enable(adev, true); 1478 1479 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1480 if (r) 1481 goto failure; 1482 1483 if (adev->enable_uni_mes) { 1484 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1485 if (r) 1486 goto failure; 1487 1488 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1489 } 1490 1491 r = mes_v12_0_hw_init(adev); 1492 if (r) 1493 goto failure; 1494 1495 return r; 1496 1497 failure: 1498 mes_v12_0_hw_fini(adev); 1499 return r; 1500 } 1501 1502 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1503 { 1504 if (adev->mes.ring[0].sched.ready) { 1505 if (adev->enable_uni_mes) 1506 amdgpu_mes_unmap_legacy_queue(adev, 1507 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1508 RESET_QUEUES, 0, 0); 1509 else 1510 mes_v12_0_kiq_dequeue_sched(adev); 1511 1512 adev->mes.ring[0].sched.ready = false; 1513 } 1514 1515 mes_v12_0_enable(adev, false); 1516 1517 return 0; 1518 } 1519 1520 static int mes_v12_0_hw_init(void *handle) 1521 { 1522 int r; 1523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1524 1525 if (adev->mes.ring[0].sched.ready) 1526 goto out; 1527 1528 if (!adev->enable_mes_kiq) { 1529 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1530 r = mes_v12_0_load_microcode(adev, 1531 AMDGPU_MES_SCHED_PIPE, true); 1532 if (r) { 1533 DRM_ERROR("failed to MES fw, r=%d\n", r); 1534 return r; 1535 } 1536 1537 mes_v12_0_set_ucode_start_addr(adev); 1538 1539 } else if (adev->firmware.load_type == 1540 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1541 1542 mes_v12_0_set_ucode_start_addr(adev); 1543 } 1544 1545 mes_v12_0_enable(adev, true); 1546 } 1547 1548 /* Enable the MES to handle doorbell ring on unmapped queue */ 1549 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1550 1551 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1552 if (r) 1553 goto failure; 1554 1555 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1556 if (r) 1557 goto failure; 1558 1559 if (adev->enable_uni_mes) 1560 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1561 1562 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1563 1564 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1565 if (r) { 1566 DRM_ERROR("MES is busy\n"); 1567 goto failure; 1568 } 1569 1570 out: 1571 /* 1572 * Disable KIQ ring usage from the driver once MES is enabled. 1573 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1574 * with MES enabled. 1575 */ 1576 adev->gfx.kiq[0].ring.sched.ready = false; 1577 adev->mes.ring[0].sched.ready = true; 1578 1579 return 0; 1580 1581 failure: 1582 mes_v12_0_hw_fini(adev); 1583 return r; 1584 } 1585 1586 static int mes_v12_0_hw_fini(void *handle) 1587 { 1588 return 0; 1589 } 1590 1591 static int mes_v12_0_suspend(void *handle) 1592 { 1593 int r; 1594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1595 1596 r = amdgpu_mes_suspend(adev); 1597 if (r) 1598 return r; 1599 1600 return mes_v12_0_hw_fini(adev); 1601 } 1602 1603 static int mes_v12_0_resume(void *handle) 1604 { 1605 int r; 1606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1607 1608 r = mes_v12_0_hw_init(adev); 1609 if (r) 1610 return r; 1611 1612 return amdgpu_mes_resume(adev); 1613 } 1614 1615 static int mes_v12_0_early_init(void *handle) 1616 { 1617 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1618 int pipe, r; 1619 1620 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1621 r = amdgpu_mes_init_microcode(adev, pipe); 1622 if (r) 1623 return r; 1624 } 1625 1626 return 0; 1627 } 1628 1629 static int mes_v12_0_late_init(void *handle) 1630 { 1631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1632 1633 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1634 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1635 amdgpu_mes_self_test(adev); 1636 1637 return 0; 1638 } 1639 1640 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1641 .name = "mes_v12_0", 1642 .early_init = mes_v12_0_early_init, 1643 .late_init = mes_v12_0_late_init, 1644 .sw_init = mes_v12_0_sw_init, 1645 .sw_fini = mes_v12_0_sw_fini, 1646 .hw_init = mes_v12_0_hw_init, 1647 .hw_fini = mes_v12_0_hw_fini, 1648 .suspend = mes_v12_0_suspend, 1649 .resume = mes_v12_0_resume, 1650 }; 1651 1652 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1653 .type = AMD_IP_BLOCK_TYPE_MES, 1654 .major = 12, 1655 .minor = 0, 1656 .rev = 0, 1657 .funcs = &mes_v12_0_ip_funcs, 1658 }; 1659