1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 #include "fw.h" 20 21 unsigned int ath11k_debug_mask; 22 EXPORT_SYMBOL(ath11k_debug_mask); 23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 24 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 25 26 static unsigned int ath11k_crypto_mode; 27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 29 30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 33 MODULE_PARM_DESC(frame_mode, 34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 35 36 bool ath11k_ftm_mode; 37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 39 40 static const struct ath11k_hw_params ath11k_hw_params[] = { 41 { 42 .hw_rev = ATH11K_HW_IPQ8074, 43 .name = "ipq8074 hw2.0", 44 .fw = { 45 .dir = "IPQ8074/hw2.0", 46 .board_size = 256 * 1024, 47 .cal_offset = 128 * 1024, 48 }, 49 .max_radios = 3, 50 .bdf_addr = 0x4B0C0000, 51 .hw_ops = &ipq8074_ops, 52 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 53 .internal_sleep_clock = false, 54 .regs = &ipq8074_regs, 55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 56 .host_ce_config = ath11k_host_ce_config_ipq8074, 57 .ce_count = 12, 58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 59 .target_ce_count = 11, 60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 61 .svc_to_ce_map_len = 21, 62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 63 .single_pdev_only = false, 64 .rxdma1_enable = true, 65 .num_rxdma_per_pdev = 1, 66 .rx_mac_buf_ring = false, 67 .vdev_start_delay = false, 68 .htt_peer_map_v2 = true, 69 70 .spectral = { 71 .fft_sz = 2, 72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 73 * so added pad size as 2 bytes to compensate the BIN size 74 */ 75 .fft_pad_sz = 2, 76 .summary_pad_sz = 0, 77 .fft_hdr_len = 16, 78 .max_fft_bins = 512, 79 .fragment_160mhz = true, 80 }, 81 82 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 83 BIT(NL80211_IFTYPE_AP) | 84 BIT(NL80211_IFTYPE_MESH_POINT), 85 .supports_monitor = true, 86 .full_monitor_mode = false, 87 .supports_shadow_regs = false, 88 .idle_ps = false, 89 .supports_sta_ps = false, 90 .coldboot_cal_mm = true, 91 .coldboot_cal_ftm = true, 92 .cbcal_restart_fw = true, 93 .fw_mem_mode = 0, 94 .num_vdevs = 16 + 1, 95 .num_peers = 512, 96 .supports_suspend = false, 97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 98 .supports_regdb = false, 99 .fix_l1ss = true, 100 .credit_flow = false, 101 .max_tx_ring = DP_TCL_NUM_RING_MAX, 102 .hal_params = &ath11k_hw_hal_params_ipq8074, 103 .supports_dynamic_smps_6ghz = false, 104 .alloc_cacheable_memory = true, 105 .supports_rssi_stats = false, 106 .fw_wmi_diag_event = false, 107 .current_cc_support = false, 108 .dbr_debug_support = true, 109 .global_reset = false, 110 .bios_sar_capa = NULL, 111 .m3_fw_support = false, 112 .fixed_bdf_addr = true, 113 .fixed_mem_region = true, 114 .static_window_map = false, 115 .hybrid_bus_type = false, 116 .fixed_fw_mem = false, 117 .support_off_channel_tx = false, 118 .supports_multi_bssid = false, 119 120 .sram_dump = {}, 121 122 .tcl_ring_retry = true, 123 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 124 .smp2p_wow_exit = false, 125 .support_dual_stations = false, 126 }, 127 { 128 .hw_rev = ATH11K_HW_IPQ6018_HW10, 129 .name = "ipq6018 hw1.0", 130 .fw = { 131 .dir = "IPQ6018/hw1.0", 132 .board_size = 256 * 1024, 133 .cal_offset = 128 * 1024, 134 }, 135 .max_radios = 2, 136 .bdf_addr = 0x4ABC0000, 137 .hw_ops = &ipq6018_ops, 138 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 139 .internal_sleep_clock = false, 140 .regs = &ipq8074_regs, 141 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 142 .host_ce_config = ath11k_host_ce_config_ipq8074, 143 .ce_count = 12, 144 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 145 .target_ce_count = 11, 146 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 147 .svc_to_ce_map_len = 19, 148 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 149 .single_pdev_only = false, 150 .rxdma1_enable = true, 151 .num_rxdma_per_pdev = 1, 152 .rx_mac_buf_ring = false, 153 .vdev_start_delay = false, 154 .htt_peer_map_v2 = true, 155 156 .spectral = { 157 .fft_sz = 4, 158 .fft_pad_sz = 0, 159 .summary_pad_sz = 0, 160 .fft_hdr_len = 16, 161 .max_fft_bins = 512, 162 .fragment_160mhz = true, 163 }, 164 165 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 166 BIT(NL80211_IFTYPE_AP) | 167 BIT(NL80211_IFTYPE_MESH_POINT), 168 .supports_monitor = true, 169 .full_monitor_mode = false, 170 .supports_shadow_regs = false, 171 .idle_ps = false, 172 .supports_sta_ps = false, 173 .coldboot_cal_mm = true, 174 .coldboot_cal_ftm = true, 175 .cbcal_restart_fw = true, 176 .fw_mem_mode = 0, 177 .num_vdevs = 16 + 1, 178 .num_peers = 512, 179 .supports_suspend = false, 180 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 181 .supports_regdb = false, 182 .fix_l1ss = true, 183 .credit_flow = false, 184 .max_tx_ring = DP_TCL_NUM_RING_MAX, 185 .hal_params = &ath11k_hw_hal_params_ipq8074, 186 .supports_dynamic_smps_6ghz = false, 187 .alloc_cacheable_memory = true, 188 .supports_rssi_stats = false, 189 .fw_wmi_diag_event = false, 190 .current_cc_support = false, 191 .dbr_debug_support = true, 192 .global_reset = false, 193 .bios_sar_capa = NULL, 194 .m3_fw_support = false, 195 .fixed_bdf_addr = true, 196 .fixed_mem_region = true, 197 .static_window_map = false, 198 .hybrid_bus_type = false, 199 .fixed_fw_mem = false, 200 .support_off_channel_tx = false, 201 .supports_multi_bssid = false, 202 203 .sram_dump = {}, 204 205 .tcl_ring_retry = true, 206 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 207 .smp2p_wow_exit = false, 208 .support_fw_mac_sequence = false, 209 .support_dual_stations = false, 210 }, 211 { 212 .name = "qca6390 hw2.0", 213 .hw_rev = ATH11K_HW_QCA6390_HW20, 214 .fw = { 215 .dir = "QCA6390/hw2.0", 216 .board_size = 256 * 1024, 217 .cal_offset = 128 * 1024, 218 }, 219 .max_radios = 3, 220 .bdf_addr = 0x4B0C0000, 221 .hw_ops = &qca6390_ops, 222 .ring_mask = &ath11k_hw_ring_mask_qca6390, 223 .internal_sleep_clock = true, 224 .regs = &qca6390_regs, 225 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 226 .host_ce_config = ath11k_host_ce_config_qca6390, 227 .ce_count = 9, 228 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 229 .target_ce_count = 9, 230 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 231 .svc_to_ce_map_len = 14, 232 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 233 .single_pdev_only = true, 234 .rxdma1_enable = false, 235 .num_rxdma_per_pdev = 2, 236 .rx_mac_buf_ring = true, 237 .vdev_start_delay = true, 238 .htt_peer_map_v2 = false, 239 240 .spectral = { 241 .fft_sz = 0, 242 .fft_pad_sz = 0, 243 .summary_pad_sz = 0, 244 .fft_hdr_len = 0, 245 .max_fft_bins = 0, 246 .fragment_160mhz = false, 247 }, 248 249 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 250 BIT(NL80211_IFTYPE_AP) | 251 BIT(NL80211_IFTYPE_P2P_DEVICE) | 252 BIT(NL80211_IFTYPE_P2P_CLIENT) | 253 BIT(NL80211_IFTYPE_P2P_GO), 254 .supports_monitor = false, 255 .full_monitor_mode = false, 256 .supports_shadow_regs = true, 257 .idle_ps = true, 258 .supports_sta_ps = true, 259 .coldboot_cal_mm = false, 260 .coldboot_cal_ftm = false, 261 .cbcal_restart_fw = false, 262 .fw_mem_mode = 0, 263 .num_vdevs = 2 + 1, 264 .num_peers = 512, 265 .supports_suspend = true, 266 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 267 .supports_regdb = false, 268 .fix_l1ss = true, 269 .credit_flow = true, 270 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 271 .hal_params = &ath11k_hw_hal_params_qca6390, 272 .supports_dynamic_smps_6ghz = false, 273 .alloc_cacheable_memory = false, 274 .supports_rssi_stats = true, 275 .fw_wmi_diag_event = true, 276 .current_cc_support = true, 277 .dbr_debug_support = false, 278 .global_reset = true, 279 .bios_sar_capa = NULL, 280 .m3_fw_support = true, 281 .fixed_bdf_addr = false, 282 .fixed_mem_region = false, 283 .static_window_map = false, 284 .hybrid_bus_type = false, 285 .fixed_fw_mem = false, 286 .support_off_channel_tx = true, 287 .supports_multi_bssid = true, 288 289 .sram_dump = { 290 .start = 0x01400000, 291 .end = 0x0171ffff, 292 }, 293 294 .tcl_ring_retry = true, 295 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 296 .smp2p_wow_exit = false, 297 .support_fw_mac_sequence = true, 298 .support_dual_stations = true, 299 }, 300 { 301 .name = "qcn9074 hw1.0", 302 .hw_rev = ATH11K_HW_QCN9074_HW10, 303 .fw = { 304 .dir = "QCN9074/hw1.0", 305 .board_size = 256 * 1024, 306 .cal_offset = 128 * 1024, 307 }, 308 .max_radios = 1, 309 .single_pdev_only = false, 310 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 311 .hw_ops = &qcn9074_ops, 312 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 313 .internal_sleep_clock = false, 314 .regs = &qcn9074_regs, 315 .host_ce_config = ath11k_host_ce_config_qcn9074, 316 .ce_count = 6, 317 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 318 .target_ce_count = 9, 319 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 320 .svc_to_ce_map_len = 18, 321 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 322 .rxdma1_enable = true, 323 .num_rxdma_per_pdev = 1, 324 .rx_mac_buf_ring = false, 325 .vdev_start_delay = false, 326 .htt_peer_map_v2 = true, 327 328 .spectral = { 329 .fft_sz = 2, 330 .fft_pad_sz = 0, 331 .summary_pad_sz = 16, 332 .fft_hdr_len = 24, 333 .max_fft_bins = 1024, 334 .fragment_160mhz = false, 335 }, 336 337 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 338 BIT(NL80211_IFTYPE_AP) | 339 BIT(NL80211_IFTYPE_MESH_POINT), 340 .supports_monitor = true, 341 .full_monitor_mode = true, 342 .supports_shadow_regs = false, 343 .idle_ps = false, 344 .supports_sta_ps = false, 345 .coldboot_cal_mm = false, 346 .coldboot_cal_ftm = true, 347 .cbcal_restart_fw = true, 348 .fw_mem_mode = 2, 349 .num_vdevs = 8, 350 .num_peers = 128, 351 .supports_suspend = false, 352 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 353 .supports_regdb = false, 354 .fix_l1ss = true, 355 .credit_flow = false, 356 .max_tx_ring = DP_TCL_NUM_RING_MAX, 357 .hal_params = &ath11k_hw_hal_params_ipq8074, 358 .supports_dynamic_smps_6ghz = true, 359 .alloc_cacheable_memory = true, 360 .supports_rssi_stats = false, 361 .fw_wmi_diag_event = false, 362 .current_cc_support = false, 363 .dbr_debug_support = true, 364 .global_reset = false, 365 .bios_sar_capa = NULL, 366 .m3_fw_support = true, 367 .fixed_bdf_addr = false, 368 .fixed_mem_region = false, 369 .static_window_map = true, 370 .hybrid_bus_type = false, 371 .fixed_fw_mem = false, 372 .support_off_channel_tx = false, 373 .supports_multi_bssid = false, 374 375 .sram_dump = {}, 376 377 .tcl_ring_retry = true, 378 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 379 .smp2p_wow_exit = false, 380 .support_fw_mac_sequence = false, 381 .support_dual_stations = false, 382 }, 383 { 384 .name = "wcn6855 hw2.0", 385 .hw_rev = ATH11K_HW_WCN6855_HW20, 386 .fw = { 387 .dir = "WCN6855/hw2.0", 388 .board_size = 256 * 1024, 389 .cal_offset = 128 * 1024, 390 }, 391 .max_radios = 3, 392 .bdf_addr = 0x4B0C0000, 393 .hw_ops = &wcn6855_ops, 394 .ring_mask = &ath11k_hw_ring_mask_qca6390, 395 .internal_sleep_clock = true, 396 .regs = &wcn6855_regs, 397 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 398 .host_ce_config = ath11k_host_ce_config_qca6390, 399 .ce_count = 9, 400 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 401 .target_ce_count = 9, 402 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 403 .svc_to_ce_map_len = 14, 404 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 405 .single_pdev_only = true, 406 .rxdma1_enable = false, 407 .num_rxdma_per_pdev = 2, 408 .rx_mac_buf_ring = true, 409 .vdev_start_delay = true, 410 .htt_peer_map_v2 = false, 411 412 .spectral = { 413 .fft_sz = 0, 414 .fft_pad_sz = 0, 415 .summary_pad_sz = 0, 416 .fft_hdr_len = 0, 417 .max_fft_bins = 0, 418 .fragment_160mhz = false, 419 }, 420 421 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 422 BIT(NL80211_IFTYPE_AP) | 423 BIT(NL80211_IFTYPE_P2P_DEVICE) | 424 BIT(NL80211_IFTYPE_P2P_CLIENT) | 425 BIT(NL80211_IFTYPE_P2P_GO), 426 .supports_monitor = false, 427 .full_monitor_mode = false, 428 .supports_shadow_regs = true, 429 .idle_ps = true, 430 .supports_sta_ps = true, 431 .coldboot_cal_mm = false, 432 .coldboot_cal_ftm = false, 433 .cbcal_restart_fw = false, 434 .fw_mem_mode = 0, 435 .num_vdevs = 2 + 1, 436 .num_peers = 512, 437 .supports_suspend = true, 438 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 439 .supports_regdb = true, 440 .fix_l1ss = false, 441 .credit_flow = true, 442 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 443 .hal_params = &ath11k_hw_hal_params_qca6390, 444 .supports_dynamic_smps_6ghz = false, 445 .alloc_cacheable_memory = false, 446 .supports_rssi_stats = true, 447 .fw_wmi_diag_event = true, 448 .current_cc_support = true, 449 .dbr_debug_support = false, 450 .global_reset = true, 451 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 452 .m3_fw_support = true, 453 .fixed_bdf_addr = false, 454 .fixed_mem_region = false, 455 .static_window_map = false, 456 .hybrid_bus_type = false, 457 .fixed_fw_mem = false, 458 .support_off_channel_tx = true, 459 .supports_multi_bssid = true, 460 461 .sram_dump = { 462 .start = 0x01400000, 463 .end = 0x0177ffff, 464 }, 465 466 .tcl_ring_retry = true, 467 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 468 .smp2p_wow_exit = false, 469 .support_fw_mac_sequence = true, 470 .support_dual_stations = true, 471 }, 472 { 473 .name = "wcn6855 hw2.1", 474 .hw_rev = ATH11K_HW_WCN6855_HW21, 475 .fw = { 476 .dir = "WCN6855/hw2.1", 477 .board_size = 256 * 1024, 478 .cal_offset = 128 * 1024, 479 }, 480 .max_radios = 3, 481 .bdf_addr = 0x4B0C0000, 482 .hw_ops = &wcn6855_ops, 483 .ring_mask = &ath11k_hw_ring_mask_qca6390, 484 .internal_sleep_clock = true, 485 .regs = &wcn6855_regs, 486 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 487 .host_ce_config = ath11k_host_ce_config_qca6390, 488 .ce_count = 9, 489 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 490 .target_ce_count = 9, 491 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 492 .svc_to_ce_map_len = 14, 493 .single_pdev_only = true, 494 .rxdma1_enable = false, 495 .num_rxdma_per_pdev = 2, 496 .rx_mac_buf_ring = true, 497 .vdev_start_delay = true, 498 .htt_peer_map_v2 = false, 499 500 .spectral = { 501 .fft_sz = 0, 502 .fft_pad_sz = 0, 503 .summary_pad_sz = 0, 504 .fft_hdr_len = 0, 505 .max_fft_bins = 0, 506 .fragment_160mhz = false, 507 }, 508 509 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 510 BIT(NL80211_IFTYPE_AP) | 511 BIT(NL80211_IFTYPE_P2P_DEVICE) | 512 BIT(NL80211_IFTYPE_P2P_CLIENT) | 513 BIT(NL80211_IFTYPE_P2P_GO), 514 .supports_monitor = false, 515 .supports_shadow_regs = true, 516 .idle_ps = true, 517 .supports_sta_ps = true, 518 .coldboot_cal_mm = false, 519 .coldboot_cal_ftm = false, 520 .cbcal_restart_fw = false, 521 .fw_mem_mode = 0, 522 .num_vdevs = 2 + 1, 523 .num_peers = 512, 524 .supports_suspend = true, 525 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 526 .supports_regdb = true, 527 .fix_l1ss = false, 528 .credit_flow = true, 529 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 530 .hal_params = &ath11k_hw_hal_params_qca6390, 531 .supports_dynamic_smps_6ghz = false, 532 .alloc_cacheable_memory = false, 533 .supports_rssi_stats = true, 534 .fw_wmi_diag_event = true, 535 .current_cc_support = true, 536 .dbr_debug_support = false, 537 .global_reset = true, 538 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 539 .m3_fw_support = true, 540 .fixed_bdf_addr = false, 541 .fixed_mem_region = false, 542 .static_window_map = false, 543 .hybrid_bus_type = false, 544 .fixed_fw_mem = false, 545 .support_off_channel_tx = true, 546 .supports_multi_bssid = true, 547 548 .sram_dump = { 549 .start = 0x01400000, 550 .end = 0x0177ffff, 551 }, 552 553 .tcl_ring_retry = true, 554 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 555 .smp2p_wow_exit = false, 556 .support_fw_mac_sequence = true, 557 .support_dual_stations = true, 558 }, 559 { 560 .name = "wcn6750 hw1.0", 561 .hw_rev = ATH11K_HW_WCN6750_HW10, 562 .fw = { 563 .dir = "WCN6750/hw1.0", 564 .board_size = 256 * 1024, 565 .cal_offset = 128 * 1024, 566 }, 567 .max_radios = 1, 568 .bdf_addr = 0x4B0C0000, 569 .hw_ops = &wcn6750_ops, 570 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 571 .internal_sleep_clock = false, 572 .regs = &wcn6750_regs, 573 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 574 .host_ce_config = ath11k_host_ce_config_qca6390, 575 .ce_count = 9, 576 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 577 .target_ce_count = 9, 578 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 579 .svc_to_ce_map_len = 14, 580 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 581 .single_pdev_only = true, 582 .rxdma1_enable = false, 583 .num_rxdma_per_pdev = 1, 584 .rx_mac_buf_ring = true, 585 .vdev_start_delay = true, 586 .htt_peer_map_v2 = false, 587 588 .spectral = { 589 .fft_sz = 0, 590 .fft_pad_sz = 0, 591 .summary_pad_sz = 0, 592 .fft_hdr_len = 0, 593 .max_fft_bins = 0, 594 .fragment_160mhz = false, 595 }, 596 597 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 598 BIT(NL80211_IFTYPE_AP), 599 .supports_monitor = false, 600 .supports_shadow_regs = true, 601 .idle_ps = true, 602 .supports_sta_ps = true, 603 .coldboot_cal_mm = true, 604 .coldboot_cal_ftm = true, 605 .cbcal_restart_fw = false, 606 .fw_mem_mode = 0, 607 .num_vdevs = 3, 608 .num_peers = 512, 609 .supports_suspend = false, 610 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 611 .supports_regdb = true, 612 .fix_l1ss = false, 613 .credit_flow = true, 614 .max_tx_ring = DP_TCL_NUM_RING_MAX, 615 .hal_params = &ath11k_hw_hal_params_wcn6750, 616 .supports_dynamic_smps_6ghz = false, 617 .alloc_cacheable_memory = false, 618 .supports_rssi_stats = true, 619 .fw_wmi_diag_event = false, 620 .current_cc_support = true, 621 .dbr_debug_support = false, 622 .global_reset = false, 623 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 624 .m3_fw_support = false, 625 .fixed_bdf_addr = false, 626 .fixed_mem_region = false, 627 .static_window_map = true, 628 .hybrid_bus_type = true, 629 .fixed_fw_mem = true, 630 .support_off_channel_tx = true, 631 .supports_multi_bssid = true, 632 633 .sram_dump = {}, 634 635 .tcl_ring_retry = false, 636 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 637 .smp2p_wow_exit = true, 638 .support_fw_mac_sequence = true, 639 .support_dual_stations = false, 640 }, 641 { 642 .hw_rev = ATH11K_HW_IPQ5018_HW10, 643 .name = "ipq5018 hw1.0", 644 .fw = { 645 .dir = "IPQ5018/hw1.0", 646 .board_size = 256 * 1024, 647 .cal_offset = 128 * 1024, 648 }, 649 .max_radios = MAX_RADIOS_5018, 650 .bdf_addr = 0x4BA00000, 651 /* hal_desc_sz and hw ops are similar to qcn9074 */ 652 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 653 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 654 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 655 .credit_flow = false, 656 .max_tx_ring = 1, 657 .spectral = { 658 .fft_sz = 2, 659 .fft_pad_sz = 0, 660 .summary_pad_sz = 16, 661 .fft_hdr_len = 24, 662 .max_fft_bins = 1024, 663 }, 664 .internal_sleep_clock = false, 665 .regs = &ipq5018_regs, 666 .hw_ops = &ipq5018_ops, 667 .host_ce_config = ath11k_host_ce_config_qcn9074, 668 .ce_count = CE_CNT_5018, 669 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 670 .target_ce_count = TARGET_CE_CNT_5018, 671 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 672 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 673 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 674 .ce_remap = &ath11k_ce_remap_ipq5018, 675 .rxdma1_enable = true, 676 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018, 677 .rx_mac_buf_ring = false, 678 .vdev_start_delay = false, 679 .htt_peer_map_v2 = true, 680 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 681 BIT(NL80211_IFTYPE_AP) | 682 BIT(NL80211_IFTYPE_MESH_POINT), 683 .supports_monitor = false, 684 .supports_sta_ps = false, 685 .supports_shadow_regs = false, 686 .fw_mem_mode = 0, 687 .num_vdevs = 16 + 1, 688 .num_peers = 512, 689 .supports_regdb = false, 690 .idle_ps = false, 691 .supports_suspend = false, 692 .hal_params = &ath11k_hw_hal_params_ipq8074, 693 .single_pdev_only = false, 694 .coldboot_cal_mm = true, 695 .coldboot_cal_ftm = true, 696 .cbcal_restart_fw = true, 697 .fix_l1ss = true, 698 .supports_dynamic_smps_6ghz = false, 699 .alloc_cacheable_memory = true, 700 .supports_rssi_stats = false, 701 .fw_wmi_diag_event = false, 702 .current_cc_support = false, 703 .dbr_debug_support = true, 704 .global_reset = false, 705 .bios_sar_capa = NULL, 706 .m3_fw_support = false, 707 .fixed_bdf_addr = true, 708 .fixed_mem_region = true, 709 .static_window_map = false, 710 .hybrid_bus_type = false, 711 .fixed_fw_mem = false, 712 .support_off_channel_tx = false, 713 .supports_multi_bssid = false, 714 715 .sram_dump = {}, 716 717 .tcl_ring_retry = true, 718 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 719 .smp2p_wow_exit = false, 720 .support_fw_mac_sequence = false, 721 .support_dual_stations = false, 722 }, 723 { 724 .name = "qca2066 hw2.1", 725 .hw_rev = ATH11K_HW_QCA2066_HW21, 726 .fw = { 727 .dir = "QCA2066/hw2.1", 728 .board_size = 256 * 1024, 729 .cal_offset = 128 * 1024, 730 }, 731 .max_radios = 3, 732 .bdf_addr = 0x4B0C0000, 733 .hw_ops = &wcn6855_ops, 734 .ring_mask = &ath11k_hw_ring_mask_qca6390, 735 .internal_sleep_clock = true, 736 .regs = &wcn6855_regs, 737 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 738 .host_ce_config = ath11k_host_ce_config_qca6390, 739 .ce_count = 9, 740 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 741 .target_ce_count = 9, 742 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 743 .svc_to_ce_map_len = 14, 744 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 745 .single_pdev_only = true, 746 .rxdma1_enable = false, 747 .num_rxdma_per_pdev = 2, 748 .rx_mac_buf_ring = true, 749 .vdev_start_delay = true, 750 .htt_peer_map_v2 = false, 751 752 .spectral = { 753 .fft_sz = 0, 754 .fft_pad_sz = 0, 755 .summary_pad_sz = 0, 756 .fft_hdr_len = 0, 757 .max_fft_bins = 0, 758 .fragment_160mhz = false, 759 }, 760 761 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 762 BIT(NL80211_IFTYPE_AP) | 763 BIT(NL80211_IFTYPE_P2P_DEVICE) | 764 BIT(NL80211_IFTYPE_P2P_CLIENT) | 765 BIT(NL80211_IFTYPE_P2P_GO), 766 .supports_monitor = false, 767 .full_monitor_mode = false, 768 .supports_shadow_regs = true, 769 .idle_ps = true, 770 .supports_sta_ps = true, 771 .coldboot_cal_mm = false, 772 .coldboot_cal_ftm = false, 773 .cbcal_restart_fw = false, 774 .fw_mem_mode = 0, 775 .num_vdevs = 2 + 1, 776 .num_peers = 512, 777 .supports_suspend = true, 778 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 779 .supports_regdb = true, 780 .fix_l1ss = false, 781 .credit_flow = true, 782 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 783 .hal_params = &ath11k_hw_hal_params_qca6390, 784 .supports_dynamic_smps_6ghz = false, 785 .alloc_cacheable_memory = false, 786 .supports_rssi_stats = true, 787 .fw_wmi_diag_event = true, 788 .current_cc_support = true, 789 .dbr_debug_support = false, 790 .global_reset = true, 791 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 792 .m3_fw_support = true, 793 .fixed_bdf_addr = false, 794 .fixed_mem_region = false, 795 .static_window_map = false, 796 .hybrid_bus_type = false, 797 .fixed_fw_mem = false, 798 .support_off_channel_tx = true, 799 .supports_multi_bssid = true, 800 801 .sram_dump = { 802 .start = 0x01400000, 803 .end = 0x0177ffff, 804 }, 805 806 .tcl_ring_retry = true, 807 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 808 .smp2p_wow_exit = false, 809 .support_fw_mac_sequence = true, 810 .support_dual_stations = true, 811 }, 812 }; 813 814 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 815 { 816 WARN_ON(!ab->hw_params.single_pdev_only); 817 818 return &ab->pdevs[0]; 819 } 820 821 void ath11k_fw_stats_pdevs_free(struct list_head *head) 822 { 823 struct ath11k_fw_stats_pdev *i, *tmp; 824 825 list_for_each_entry_safe(i, tmp, head, list) { 826 list_del(&i->list); 827 kfree(i); 828 } 829 } 830 831 void ath11k_fw_stats_vdevs_free(struct list_head *head) 832 { 833 struct ath11k_fw_stats_vdev *i, *tmp; 834 835 list_for_each_entry_safe(i, tmp, head, list) { 836 list_del(&i->list); 837 kfree(i); 838 } 839 } 840 841 void ath11k_fw_stats_bcn_free(struct list_head *head) 842 { 843 struct ath11k_fw_stats_bcn *i, *tmp; 844 845 list_for_each_entry_safe(i, tmp, head, list) { 846 list_del(&i->list); 847 kfree(i); 848 } 849 } 850 851 void ath11k_fw_stats_init(struct ath11k *ar) 852 { 853 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 854 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 855 INIT_LIST_HEAD(&ar->fw_stats.bcn); 856 857 init_completion(&ar->fw_stats_complete); 858 } 859 860 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 861 { 862 ath11k_fw_stats_pdevs_free(&stats->pdevs); 863 ath11k_fw_stats_vdevs_free(&stats->vdevs); 864 ath11k_fw_stats_bcn_free(&stats->bcn); 865 } 866 867 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) 868 { 869 if (!ath11k_cold_boot_cal) 870 return false; 871 872 if (ath11k_ftm_mode) 873 return ab->hw_params.coldboot_cal_ftm; 874 875 else 876 return ab->hw_params.coldboot_cal_mm; 877 } 878 879 int ath11k_core_suspend(struct ath11k_base *ab) 880 { 881 int ret; 882 struct ath11k_pdev *pdev; 883 struct ath11k *ar; 884 885 if (!ab->hw_params.supports_suspend) 886 return -EOPNOTSUPP; 887 888 /* so far single_pdev_only chips have supports_suspend as true 889 * and only the first pdev is valid. 890 */ 891 pdev = ath11k_core_get_single_pdev(ab); 892 ar = pdev->ar; 893 if (!ar || ar->state != ATH11K_STATE_OFF) 894 return 0; 895 896 ret = ath11k_dp_rx_pktlog_stop(ab, true); 897 if (ret) { 898 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 899 ret); 900 return ret; 901 } 902 903 ret = ath11k_mac_wait_tx_complete(ar); 904 if (ret) { 905 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 906 return ret; 907 } 908 909 ret = ath11k_dp_rx_pktlog_stop(ab, false); 910 if (ret) { 911 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 912 ret); 913 return ret; 914 } 915 916 ath11k_ce_stop_shadow_timers(ab); 917 ath11k_dp_stop_shadow_timers(ab); 918 919 /* PM framework skips suspend_late/resume_early callbacks 920 * if other devices report errors in their suspend callbacks. 921 * However ath11k_core_resume() would still be called because 922 * here we return success thus kernel put us on dpm_suspended_list. 923 * Since we won't go through a power down/up cycle, there is 924 * no chance to call complete(&ab->restart_completed) in 925 * ath11k_core_restart(), making ath11k_core_resume() timeout. 926 * So call it here to avoid this issue. This also works in case 927 * no error happens thus suspend_late/resume_early get called, 928 * because it will be reinitialized in ath11k_core_resume_early(). 929 */ 930 complete(&ab->restart_completed); 931 932 return 0; 933 } 934 EXPORT_SYMBOL(ath11k_core_suspend); 935 936 int ath11k_core_suspend_late(struct ath11k_base *ab) 937 { 938 struct ath11k_pdev *pdev; 939 struct ath11k *ar; 940 941 if (!ab->hw_params.supports_suspend) 942 return -EOPNOTSUPP; 943 944 /* so far single_pdev_only chips have supports_suspend as true 945 * and only the first pdev is valid. 946 */ 947 pdev = ath11k_core_get_single_pdev(ab); 948 ar = pdev->ar; 949 if (!ar || ar->state != ATH11K_STATE_OFF) 950 return 0; 951 952 ath11k_hif_irq_disable(ab); 953 ath11k_hif_ce_irq_disable(ab); 954 955 ath11k_hif_power_down(ab, true); 956 957 return 0; 958 } 959 EXPORT_SYMBOL(ath11k_core_suspend_late); 960 961 int ath11k_core_resume_early(struct ath11k_base *ab) 962 { 963 int ret; 964 struct ath11k_pdev *pdev; 965 struct ath11k *ar; 966 967 if (!ab->hw_params.supports_suspend) 968 return -EOPNOTSUPP; 969 970 /* so far single_pdev_only chips have supports_suspend as true 971 * and only the first pdev is valid. 972 */ 973 pdev = ath11k_core_get_single_pdev(ab); 974 ar = pdev->ar; 975 if (!ar || ar->state != ATH11K_STATE_OFF) 976 return 0; 977 978 reinit_completion(&ab->restart_completed); 979 ret = ath11k_hif_power_up(ab); 980 if (ret) 981 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret); 982 983 return ret; 984 } 985 EXPORT_SYMBOL(ath11k_core_resume_early); 986 987 int ath11k_core_resume(struct ath11k_base *ab) 988 { 989 int ret; 990 struct ath11k_pdev *pdev; 991 struct ath11k *ar; 992 long time_left; 993 994 if (!ab->hw_params.supports_suspend) 995 return -EOPNOTSUPP; 996 997 /* so far single_pdev_only chips have supports_suspend as true 998 * and only the first pdev is valid. 999 */ 1000 pdev = ath11k_core_get_single_pdev(ab); 1001 ar = pdev->ar; 1002 if (!ar || ar->state != ATH11K_STATE_OFF) 1003 return 0; 1004 1005 time_left = wait_for_completion_timeout(&ab->restart_completed, 1006 ATH11K_RESET_TIMEOUT_HZ); 1007 if (time_left == 0) { 1008 ath11k_warn(ab, "timeout while waiting for restart complete"); 1009 return -ETIMEDOUT; 1010 } 1011 1012 if (ab->hw_params.current_cc_support && 1013 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) { 1014 ret = ath11k_reg_set_cc(ar); 1015 if (ret) { 1016 ath11k_warn(ab, "failed to set country code during resume: %d\n", 1017 ret); 1018 return ret; 1019 } 1020 } 1021 1022 ret = ath11k_dp_rx_pktlog_start(ab); 1023 if (ret) 1024 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1025 ret); 1026 1027 return ret; 1028 } 1029 EXPORT_SYMBOL(ath11k_core_resume); 1030 1031 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 1032 { 1033 struct ath11k_base *ab = data; 1034 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 1035 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 1036 ssize_t copied; 1037 size_t len; 1038 int i; 1039 1040 if (ab->qmi.target.bdf_ext[0] != '\0') 1041 return; 1042 1043 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 1044 return; 1045 1046 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 1047 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1048 "wrong smbios bdf ext type length (%d).\n", 1049 hdr->length); 1050 return; 1051 } 1052 1053 spin_lock_bh(&ab->base_lock); 1054 1055 switch (smbios->country_code_flag) { 1056 case ATH11K_SMBIOS_CC_ISO: 1057 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 1058 ab->new_alpha2[1] = smbios->cc_code & 0xff; 1059 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 1060 ab->new_alpha2[0], ab->new_alpha2[1]); 1061 break; 1062 case ATH11K_SMBIOS_CC_WW: 1063 ab->new_alpha2[0] = '0'; 1064 ab->new_alpha2[1] = '0'; 1065 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 1066 break; 1067 default: 1068 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 1069 smbios->country_code_flag); 1070 break; 1071 } 1072 1073 spin_unlock_bh(&ab->base_lock); 1074 1075 if (!smbios->bdf_enabled) { 1076 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 1077 return; 1078 } 1079 1080 /* Only one string exists (per spec) */ 1081 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 1082 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1083 "bdf variant magic does not match.\n"); 1084 return; 1085 } 1086 1087 len = min_t(size_t, 1088 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 1089 for (i = 0; i < len; i++) { 1090 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 1091 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1092 "bdf variant name contains non ascii chars.\n"); 1093 return; 1094 } 1095 } 1096 1097 /* Copy extension name without magic prefix */ 1098 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 1099 sizeof(ab->qmi.target.bdf_ext)); 1100 if (copied < 0) { 1101 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1102 "bdf variant string is longer than the buffer can accommodate\n"); 1103 return; 1104 } 1105 1106 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1107 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1108 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 1109 } 1110 1111 int ath11k_core_check_smbios(struct ath11k_base *ab) 1112 { 1113 ab->qmi.target.bdf_ext[0] = '\0'; 1114 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 1115 1116 if (ab->qmi.target.bdf_ext[0] == '\0') 1117 return -ENODATA; 1118 1119 return 0; 1120 } 1121 1122 int ath11k_core_check_dt(struct ath11k_base *ab) 1123 { 1124 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 1125 const char *variant = NULL; 1126 struct device_node *node; 1127 1128 node = ab->dev->of_node; 1129 if (!node) 1130 return -ENOENT; 1131 1132 of_property_read_string(node, "qcom,ath11k-calibration-variant", 1133 &variant); 1134 if (!variant) 1135 return -ENODATA; 1136 1137 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 1138 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1139 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1140 variant); 1141 1142 return 0; 1143 } 1144 1145 enum ath11k_bdf_name_type { 1146 ATH11K_BDF_NAME_FULL, 1147 ATH11K_BDF_NAME_BUS_NAME, 1148 ATH11K_BDF_NAME_CHIP_ID, 1149 }; 1150 1151 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1152 size_t name_len, bool with_variant, 1153 enum ath11k_bdf_name_type name_type) 1154 { 1155 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 1156 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 1157 1158 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 1159 scnprintf(variant, sizeof(variant), ",variant=%s", 1160 ab->qmi.target.bdf_ext); 1161 1162 switch (ab->id.bdf_search) { 1163 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 1164 switch (name_type) { 1165 case ATH11K_BDF_NAME_FULL: 1166 scnprintf(name, name_len, 1167 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 1168 ath11k_bus_str(ab->hif.bus), 1169 ab->id.vendor, ab->id.device, 1170 ab->id.subsystem_vendor, 1171 ab->id.subsystem_device, 1172 ab->qmi.target.chip_id, 1173 ab->qmi.target.board_id, 1174 variant); 1175 break; 1176 case ATH11K_BDF_NAME_BUS_NAME: 1177 scnprintf(name, name_len, 1178 "bus=%s", 1179 ath11k_bus_str(ab->hif.bus)); 1180 break; 1181 case ATH11K_BDF_NAME_CHIP_ID: 1182 scnprintf(name, name_len, 1183 "bus=%s,qmi-chip-id=%d", 1184 ath11k_bus_str(ab->hif.bus), 1185 ab->qmi.target.chip_id); 1186 break; 1187 } 1188 break; 1189 default: 1190 scnprintf(name, name_len, 1191 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 1192 ath11k_bus_str(ab->hif.bus), 1193 ab->qmi.target.chip_id, 1194 ab->qmi.target.board_id, variant); 1195 break; 1196 } 1197 1198 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1199 1200 return 0; 1201 } 1202 1203 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1204 size_t name_len) 1205 { 1206 return __ath11k_core_create_board_name(ab, name, name_len, true, 1207 ATH11K_BDF_NAME_FULL); 1208 } 1209 1210 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1211 size_t name_len) 1212 { 1213 return __ath11k_core_create_board_name(ab, name, name_len, false, 1214 ATH11K_BDF_NAME_FULL); 1215 } 1216 1217 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1218 size_t name_len) 1219 { 1220 return __ath11k_core_create_board_name(ab, name, name_len, false, 1221 ATH11K_BDF_NAME_BUS_NAME); 1222 } 1223 1224 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, 1225 size_t name_len) 1226 { 1227 return __ath11k_core_create_board_name(ab, name, name_len, false, 1228 ATH11K_BDF_NAME_CHIP_ID); 1229 } 1230 1231 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1232 const char *file) 1233 { 1234 const struct firmware *fw; 1235 char path[100]; 1236 int ret; 1237 1238 if (file == NULL) 1239 return ERR_PTR(-ENOENT); 1240 1241 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1242 1243 ret = firmware_request_nowarn(&fw, path, ab->dev); 1244 if (ret) 1245 return ERR_PTR(ret); 1246 1247 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1248 path, fw->size); 1249 1250 return fw; 1251 } 1252 1253 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1254 { 1255 if (!IS_ERR(bd->fw)) 1256 release_firmware(bd->fw); 1257 1258 memset(bd, 0, sizeof(*bd)); 1259 } 1260 1261 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1262 struct ath11k_board_data *bd, 1263 const void *buf, size_t buf_len, 1264 const char *boardname, 1265 int ie_id, 1266 int name_id, 1267 int data_id) 1268 { 1269 const struct ath11k_fw_ie *hdr; 1270 bool name_match_found; 1271 int ret, board_ie_id; 1272 size_t board_ie_len; 1273 const void *board_ie_data; 1274 1275 name_match_found = false; 1276 1277 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1278 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1279 hdr = buf; 1280 board_ie_id = le32_to_cpu(hdr->id); 1281 board_ie_len = le32_to_cpu(hdr->len); 1282 board_ie_data = hdr->data; 1283 1284 buf_len -= sizeof(*hdr); 1285 buf += sizeof(*hdr); 1286 1287 if (buf_len < ALIGN(board_ie_len, 4)) { 1288 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1289 ath11k_bd_ie_type_str(ie_id), 1290 buf_len, ALIGN(board_ie_len, 4)); 1291 ret = -EINVAL; 1292 goto out; 1293 } 1294 1295 if (board_ie_id == name_id) { 1296 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1297 board_ie_data, board_ie_len); 1298 1299 if (board_ie_len != strlen(boardname)) 1300 goto next; 1301 1302 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1303 if (ret) 1304 goto next; 1305 1306 name_match_found = true; 1307 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1308 "found match %s for name '%s'", 1309 ath11k_bd_ie_type_str(ie_id), 1310 boardname); 1311 } else if (board_ie_id == data_id) { 1312 if (!name_match_found) 1313 /* no match found */ 1314 goto next; 1315 1316 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1317 "found %s for '%s'", 1318 ath11k_bd_ie_type_str(ie_id), 1319 boardname); 1320 1321 bd->data = board_ie_data; 1322 bd->len = board_ie_len; 1323 1324 ret = 0; 1325 goto out; 1326 } else { 1327 ath11k_warn(ab, "unknown %s id found: %d\n", 1328 ath11k_bd_ie_type_str(ie_id), 1329 board_ie_id); 1330 } 1331 next: 1332 /* jump over the padding */ 1333 board_ie_len = ALIGN(board_ie_len, 4); 1334 1335 buf_len -= board_ie_len; 1336 buf += board_ie_len; 1337 } 1338 1339 /* no match found */ 1340 ret = -ENOENT; 1341 1342 out: 1343 return ret; 1344 } 1345 1346 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1347 struct ath11k_board_data *bd, 1348 const char *boardname, 1349 int ie_id_match, 1350 int name_id, 1351 int data_id) 1352 { 1353 size_t len, magic_len; 1354 const u8 *data; 1355 char *filename, filepath[100]; 1356 size_t ie_len; 1357 struct ath11k_fw_ie *hdr; 1358 int ret, ie_id; 1359 1360 filename = ATH11K_BOARD_API2_FILE; 1361 1362 if (!bd->fw) 1363 bd->fw = ath11k_core_firmware_request(ab, filename); 1364 1365 if (IS_ERR(bd->fw)) 1366 return PTR_ERR(bd->fw); 1367 1368 data = bd->fw->data; 1369 len = bd->fw->size; 1370 1371 ath11k_core_create_firmware_path(ab, filename, 1372 filepath, sizeof(filepath)); 1373 1374 /* magic has extra null byte padded */ 1375 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1376 if (len < magic_len) { 1377 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1378 filepath, len); 1379 ret = -EINVAL; 1380 goto err; 1381 } 1382 1383 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1384 ath11k_err(ab, "found invalid board magic\n"); 1385 ret = -EINVAL; 1386 goto err; 1387 } 1388 1389 /* magic is padded to 4 bytes */ 1390 magic_len = ALIGN(magic_len, 4); 1391 if (len < magic_len) { 1392 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1393 filepath, len); 1394 ret = -EINVAL; 1395 goto err; 1396 } 1397 1398 data += magic_len; 1399 len -= magic_len; 1400 1401 while (len > sizeof(struct ath11k_fw_ie)) { 1402 hdr = (struct ath11k_fw_ie *)data; 1403 ie_id = le32_to_cpu(hdr->id); 1404 ie_len = le32_to_cpu(hdr->len); 1405 1406 len -= sizeof(*hdr); 1407 data = hdr->data; 1408 1409 if (len < ALIGN(ie_len, 4)) { 1410 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1411 ie_id, ie_len, len); 1412 ret = -EINVAL; 1413 goto err; 1414 } 1415 1416 if (ie_id == ie_id_match) { 1417 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1418 ie_len, 1419 boardname, 1420 ie_id_match, 1421 name_id, 1422 data_id); 1423 if (ret == -ENOENT) 1424 /* no match found, continue */ 1425 goto next; 1426 else if (ret) 1427 /* there was an error, bail out */ 1428 goto err; 1429 /* either found or error, so stop searching */ 1430 goto out; 1431 } 1432 next: 1433 /* jump over the padding */ 1434 ie_len = ALIGN(ie_len, 4); 1435 1436 len -= ie_len; 1437 data += ie_len; 1438 } 1439 1440 out: 1441 if (!bd->data || !bd->len) { 1442 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1443 "failed to fetch %s for %s from %s\n", 1444 ath11k_bd_ie_type_str(ie_id_match), 1445 boardname, filepath); 1446 ret = -ENODATA; 1447 goto err; 1448 } 1449 1450 return 0; 1451 1452 err: 1453 ath11k_core_free_bdf(ab, bd); 1454 return ret; 1455 } 1456 1457 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1458 struct ath11k_board_data *bd, 1459 const char *name) 1460 { 1461 bd->fw = ath11k_core_firmware_request(ab, name); 1462 1463 if (IS_ERR(bd->fw)) 1464 return PTR_ERR(bd->fw); 1465 1466 bd->data = bd->fw->data; 1467 bd->len = bd->fw->size; 1468 1469 return 0; 1470 } 1471 1472 #define BOARD_NAME_SIZE 200 1473 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1474 { 1475 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; 1476 char *filename, filepath[100]; 1477 int bd_api; 1478 int ret = 0; 1479 1480 filename = ATH11K_BOARD_API2_FILE; 1481 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1482 if (!boardname) { 1483 ret = -ENOMEM; 1484 goto exit; 1485 } 1486 1487 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1488 if (ret) { 1489 ath11k_err(ab, "failed to create board name: %d", ret); 1490 goto exit; 1491 } 1492 1493 bd_api = 2; 1494 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1495 ATH11K_BD_IE_BOARD, 1496 ATH11K_BD_IE_BOARD_NAME, 1497 ATH11K_BD_IE_BOARD_DATA); 1498 if (!ret) 1499 goto exit; 1500 1501 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1502 if (!fallback_boardname) { 1503 ret = -ENOMEM; 1504 goto exit; 1505 } 1506 1507 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1508 BOARD_NAME_SIZE); 1509 if (ret) { 1510 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1511 goto exit; 1512 } 1513 1514 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1515 ATH11K_BD_IE_BOARD, 1516 ATH11K_BD_IE_BOARD_NAME, 1517 ATH11K_BD_IE_BOARD_DATA); 1518 if (!ret) 1519 goto exit; 1520 1521 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1522 if (!chip_id_boardname) { 1523 ret = -ENOMEM; 1524 goto exit; 1525 } 1526 1527 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, 1528 BOARD_NAME_SIZE); 1529 if (ret) { 1530 ath11k_err(ab, "failed to create chip id board name: %d", ret); 1531 goto exit; 1532 } 1533 1534 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, 1535 ATH11K_BD_IE_BOARD, 1536 ATH11K_BD_IE_BOARD_NAME, 1537 ATH11K_BD_IE_BOARD_DATA); 1538 1539 if (!ret) 1540 goto exit; 1541 1542 bd_api = 1; 1543 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1544 if (ret) { 1545 ath11k_core_create_firmware_path(ab, filename, 1546 filepath, sizeof(filepath)); 1547 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1548 boardname, filepath); 1549 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1550 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1551 fallback_boardname, filepath); 1552 1553 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1554 chip_id_boardname, filepath); 1555 1556 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1557 ab->hw_params.fw.dir); 1558 } 1559 1560 exit: 1561 kfree(boardname); 1562 kfree(fallback_boardname); 1563 kfree(chip_id_boardname); 1564 1565 if (!ret) 1566 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api); 1567 1568 return ret; 1569 } 1570 1571 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1572 { 1573 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1574 int ret; 1575 1576 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1577 if (ret) { 1578 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1579 "failed to create board name for regdb: %d", ret); 1580 goto exit; 1581 } 1582 1583 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1584 ATH11K_BD_IE_REGDB, 1585 ATH11K_BD_IE_REGDB_NAME, 1586 ATH11K_BD_IE_REGDB_DATA); 1587 if (!ret) 1588 goto exit; 1589 1590 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1591 BOARD_NAME_SIZE); 1592 if (ret) { 1593 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1594 "failed to create default board name for regdb: %d", ret); 1595 goto exit; 1596 } 1597 1598 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1599 ATH11K_BD_IE_REGDB, 1600 ATH11K_BD_IE_REGDB_NAME, 1601 ATH11K_BD_IE_REGDB_DATA); 1602 if (!ret) 1603 goto exit; 1604 1605 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1606 if (ret) 1607 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1608 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1609 1610 exit: 1611 if (!ret) 1612 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1613 1614 return ret; 1615 } 1616 1617 static void ath11k_core_stop(struct ath11k_base *ab) 1618 { 1619 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1620 ath11k_qmi_firmware_stop(ab); 1621 1622 ath11k_hif_stop(ab); 1623 ath11k_wmi_detach(ab); 1624 ath11k_dp_pdev_reo_cleanup(ab); 1625 1626 /* De-Init of components as needed */ 1627 } 1628 1629 static int ath11k_core_soc_create(struct ath11k_base *ab) 1630 { 1631 int ret; 1632 1633 if (ath11k_ftm_mode) { 1634 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1635 ath11k_info(ab, "Booting in factory test mode\n"); 1636 } 1637 1638 ret = ath11k_qmi_init_service(ab); 1639 if (ret) { 1640 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1641 return ret; 1642 } 1643 1644 ret = ath11k_debugfs_soc_create(ab); 1645 if (ret) { 1646 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1647 goto err_qmi_deinit; 1648 } 1649 1650 ret = ath11k_hif_power_up(ab); 1651 if (ret) { 1652 ath11k_err(ab, "failed to power up :%d\n", ret); 1653 goto err_debugfs_reg; 1654 } 1655 1656 return 0; 1657 1658 err_debugfs_reg: 1659 ath11k_debugfs_soc_destroy(ab); 1660 err_qmi_deinit: 1661 ath11k_qmi_deinit_service(ab); 1662 return ret; 1663 } 1664 1665 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1666 { 1667 ath11k_debugfs_soc_destroy(ab); 1668 ath11k_dp_free(ab); 1669 ath11k_reg_free(ab); 1670 ath11k_qmi_deinit_service(ab); 1671 } 1672 1673 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1674 { 1675 int ret; 1676 1677 ret = ath11k_debugfs_pdev_create(ab); 1678 if (ret) { 1679 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1680 return ret; 1681 } 1682 1683 ret = ath11k_dp_pdev_alloc(ab); 1684 if (ret) { 1685 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1686 goto err_pdev_debug; 1687 } 1688 1689 ret = ath11k_mac_register(ab); 1690 if (ret) { 1691 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1692 goto err_dp_pdev_free; 1693 } 1694 1695 ret = ath11k_thermal_register(ab); 1696 if (ret) { 1697 ath11k_err(ab, "could not register thermal device: %d\n", 1698 ret); 1699 goto err_mac_unregister; 1700 } 1701 1702 ret = ath11k_spectral_init(ab); 1703 if (ret) { 1704 ath11k_err(ab, "failed to init spectral %d\n", ret); 1705 goto err_thermal_unregister; 1706 } 1707 1708 return 0; 1709 1710 err_thermal_unregister: 1711 ath11k_thermal_unregister(ab); 1712 err_mac_unregister: 1713 ath11k_mac_unregister(ab); 1714 err_dp_pdev_free: 1715 ath11k_dp_pdev_free(ab); 1716 err_pdev_debug: 1717 ath11k_debugfs_pdev_destroy(ab); 1718 1719 return ret; 1720 } 1721 1722 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1723 { 1724 ath11k_spectral_deinit(ab); 1725 ath11k_thermal_unregister(ab); 1726 ath11k_mac_unregister(ab); 1727 ath11k_hif_irq_disable(ab); 1728 ath11k_dp_pdev_free(ab); 1729 ath11k_debugfs_pdev_destroy(ab); 1730 } 1731 1732 static int ath11k_core_start(struct ath11k_base *ab) 1733 { 1734 int ret; 1735 1736 ret = ath11k_wmi_attach(ab); 1737 if (ret) { 1738 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1739 return ret; 1740 } 1741 1742 ret = ath11k_htc_init(ab); 1743 if (ret) { 1744 ath11k_err(ab, "failed to init htc: %d\n", ret); 1745 goto err_wmi_detach; 1746 } 1747 1748 ret = ath11k_hif_start(ab); 1749 if (ret) { 1750 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1751 goto err_wmi_detach; 1752 } 1753 1754 ret = ath11k_htc_wait_target(&ab->htc); 1755 if (ret) { 1756 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1757 goto err_hif_stop; 1758 } 1759 1760 ret = ath11k_dp_htt_connect(&ab->dp); 1761 if (ret) { 1762 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1763 goto err_hif_stop; 1764 } 1765 1766 ret = ath11k_wmi_connect(ab); 1767 if (ret) { 1768 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1769 goto err_hif_stop; 1770 } 1771 1772 ret = ath11k_htc_start(&ab->htc); 1773 if (ret) { 1774 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1775 goto err_hif_stop; 1776 } 1777 1778 ret = ath11k_wmi_wait_for_service_ready(ab); 1779 if (ret) { 1780 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1781 ret); 1782 goto err_hif_stop; 1783 } 1784 1785 ret = ath11k_mac_allocate(ab); 1786 if (ret) { 1787 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1788 ret); 1789 goto err_hif_stop; 1790 } 1791 1792 ath11k_dp_pdev_pre_alloc(ab); 1793 1794 ret = ath11k_dp_pdev_reo_setup(ab); 1795 if (ret) { 1796 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1797 goto err_mac_destroy; 1798 } 1799 1800 ret = ath11k_wmi_cmd_init(ab); 1801 if (ret) { 1802 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1803 goto err_reo_cleanup; 1804 } 1805 1806 ret = ath11k_wmi_wait_for_unified_ready(ab); 1807 if (ret) { 1808 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1809 ret); 1810 goto err_reo_cleanup; 1811 } 1812 1813 /* put hardware to DBS mode */ 1814 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) { 1815 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1816 if (ret) { 1817 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1818 goto err_hif_stop; 1819 } 1820 } 1821 1822 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1823 if (ret) { 1824 ath11k_err(ab, "failed to send htt version request message: %d\n", 1825 ret); 1826 goto err_reo_cleanup; 1827 } 1828 1829 return 0; 1830 1831 err_reo_cleanup: 1832 ath11k_dp_pdev_reo_cleanup(ab); 1833 err_mac_destroy: 1834 ath11k_mac_destroy(ab); 1835 err_hif_stop: 1836 ath11k_hif_stop(ab); 1837 err_wmi_detach: 1838 ath11k_wmi_detach(ab); 1839 1840 return ret; 1841 } 1842 1843 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1844 enum ath11k_firmware_mode mode) 1845 { 1846 int ret; 1847 1848 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1849 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1850 1851 ret = ath11k_qmi_firmware_start(ab, mode); 1852 if (ret) { 1853 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1854 return ret; 1855 } 1856 1857 return ret; 1858 } 1859 1860 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1861 { 1862 int ret; 1863 1864 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 1865 if (ret) { 1866 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1867 return ret; 1868 } 1869 1870 ret = ath11k_ce_init_pipes(ab); 1871 if (ret) { 1872 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1873 goto err_firmware_stop; 1874 } 1875 1876 ret = ath11k_dp_alloc(ab); 1877 if (ret) { 1878 ath11k_err(ab, "failed to init DP: %d\n", ret); 1879 goto err_firmware_stop; 1880 } 1881 1882 switch (ath11k_crypto_mode) { 1883 case ATH11K_CRYPT_MODE_SW: 1884 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1885 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1886 break; 1887 case ATH11K_CRYPT_MODE_HW: 1888 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1889 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1890 break; 1891 default: 1892 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1893 return -EINVAL; 1894 } 1895 1896 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1897 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1898 1899 mutex_lock(&ab->core_lock); 1900 ret = ath11k_core_start(ab); 1901 if (ret) { 1902 ath11k_err(ab, "failed to start core: %d\n", ret); 1903 goto err_dp_free; 1904 } 1905 1906 ret = ath11k_core_pdev_create(ab); 1907 if (ret) { 1908 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1909 goto err_core_stop; 1910 } 1911 ath11k_hif_irq_enable(ab); 1912 mutex_unlock(&ab->core_lock); 1913 1914 return 0; 1915 1916 err_core_stop: 1917 ath11k_core_stop(ab); 1918 ath11k_mac_destroy(ab); 1919 err_dp_free: 1920 ath11k_dp_free(ab); 1921 mutex_unlock(&ab->core_lock); 1922 err_firmware_stop: 1923 ath11k_qmi_firmware_stop(ab); 1924 1925 return ret; 1926 } 1927 1928 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1929 { 1930 int ret; 1931 1932 mutex_lock(&ab->core_lock); 1933 ath11k_thermal_unregister(ab); 1934 ath11k_dp_pdev_free(ab); 1935 ath11k_spectral_deinit(ab); 1936 ath11k_ce_cleanup_pipes(ab); 1937 ath11k_wmi_detach(ab); 1938 ath11k_dp_pdev_reo_cleanup(ab); 1939 mutex_unlock(&ab->core_lock); 1940 1941 ath11k_dp_free(ab); 1942 ath11k_hal_srng_deinit(ab); 1943 1944 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1945 1946 ret = ath11k_hal_srng_init(ab); 1947 if (ret) 1948 return ret; 1949 1950 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1951 1952 ret = ath11k_core_qmi_firmware_ready(ab); 1953 if (ret) 1954 goto err_hal_srng_deinit; 1955 1956 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1957 1958 return 0; 1959 1960 err_hal_srng_deinit: 1961 ath11k_hal_srng_deinit(ab); 1962 return ret; 1963 } 1964 1965 void ath11k_core_halt(struct ath11k *ar) 1966 { 1967 struct ath11k_base *ab = ar->ab; 1968 1969 lockdep_assert_held(&ar->conf_mutex); 1970 1971 ar->num_created_vdevs = 0; 1972 ar->allocated_vdev_map = 0; 1973 1974 ath11k_mac_scan_finish(ar); 1975 ath11k_mac_peer_cleanup_all(ar); 1976 cancel_delayed_work_sync(&ar->scan.timeout); 1977 cancel_work_sync(&ar->regd_update_work); 1978 cancel_work_sync(&ab->update_11d_work); 1979 1980 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1981 synchronize_rcu(); 1982 INIT_LIST_HEAD(&ar->arvifs); 1983 idr_init(&ar->txmgmt_idr); 1984 } 1985 1986 static void ath11k_update_11d(struct work_struct *work) 1987 { 1988 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1989 struct ath11k *ar; 1990 struct ath11k_pdev *pdev; 1991 int ret, i; 1992 1993 for (i = 0; i < ab->num_radios; i++) { 1994 pdev = &ab->pdevs[i]; 1995 ar = pdev->ar; 1996 1997 spin_lock_bh(&ab->base_lock); 1998 memcpy(&ar->alpha2, &ab->new_alpha2, 2); 1999 spin_unlock_bh(&ab->base_lock); 2000 2001 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n", 2002 ar->alpha2[0], ar->alpha2[1], i); 2003 2004 ret = ath11k_reg_set_cc(ar); 2005 if (ret) 2006 ath11k_warn(ar->ab, 2007 "pdev id %d failed set current country code: %d\n", 2008 i, ret); 2009 } 2010 } 2011 2012 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 2013 { 2014 struct ath11k *ar; 2015 struct ath11k_pdev *pdev; 2016 int i; 2017 2018 spin_lock_bh(&ab->base_lock); 2019 ab->stats.fw_crash_counter++; 2020 spin_unlock_bh(&ab->base_lock); 2021 2022 for (i = 0; i < ab->num_radios; i++) { 2023 pdev = &ab->pdevs[i]; 2024 ar = pdev->ar; 2025 if (!ar || ar->state == ATH11K_STATE_OFF || 2026 ar->state == ATH11K_STATE_FTM) 2027 continue; 2028 2029 ieee80211_stop_queues(ar->hw); 2030 ath11k_mac_drain_tx(ar); 2031 ar->state_11d = ATH11K_11D_IDLE; 2032 complete(&ar->completed_11d_scan); 2033 complete(&ar->scan.started); 2034 complete_all(&ar->scan.completed); 2035 complete(&ar->scan.on_channel); 2036 complete(&ar->peer_assoc_done); 2037 complete(&ar->peer_delete_done); 2038 complete(&ar->install_key_done); 2039 complete(&ar->vdev_setup_done); 2040 complete(&ar->vdev_delete_done); 2041 complete(&ar->bss_survey_done); 2042 complete(&ar->thermal.wmi_sync); 2043 2044 wake_up(&ar->dp.tx_empty_waitq); 2045 idr_for_each(&ar->txmgmt_idr, 2046 ath11k_mac_tx_mgmt_pending_free, ar); 2047 idr_destroy(&ar->txmgmt_idr); 2048 wake_up(&ar->txmgmt_empty_waitq); 2049 2050 ar->monitor_vdev_id = -1; 2051 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 2052 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 2053 } 2054 2055 wake_up(&ab->wmi_ab.tx_credits_wq); 2056 wake_up(&ab->peer_mapping_wq); 2057 2058 reinit_completion(&ab->driver_recovery); 2059 } 2060 2061 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 2062 { 2063 struct ath11k *ar; 2064 struct ath11k_pdev *pdev; 2065 int i; 2066 2067 for (i = 0; i < ab->num_radios; i++) { 2068 pdev = &ab->pdevs[i]; 2069 ar = pdev->ar; 2070 if (!ar || ar->state == ATH11K_STATE_OFF) 2071 continue; 2072 2073 mutex_lock(&ar->conf_mutex); 2074 2075 switch (ar->state) { 2076 case ATH11K_STATE_ON: 2077 ar->state = ATH11K_STATE_RESTARTING; 2078 ath11k_core_halt(ar); 2079 ieee80211_restart_hw(ar->hw); 2080 break; 2081 case ATH11K_STATE_OFF: 2082 ath11k_warn(ab, 2083 "cannot restart radio %d that hasn't been started\n", 2084 i); 2085 break; 2086 case ATH11K_STATE_RESTARTING: 2087 break; 2088 case ATH11K_STATE_RESTARTED: 2089 ar->state = ATH11K_STATE_WEDGED; 2090 fallthrough; 2091 case ATH11K_STATE_WEDGED: 2092 ath11k_warn(ab, 2093 "device is wedged, will not restart radio %d\n", i); 2094 break; 2095 case ATH11K_STATE_FTM: 2096 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 2097 "fw mode reset done radio %d\n", i); 2098 break; 2099 } 2100 2101 mutex_unlock(&ar->conf_mutex); 2102 } 2103 complete(&ab->driver_recovery); 2104 } 2105 2106 static void ath11k_core_restart(struct work_struct *work) 2107 { 2108 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 2109 int ret; 2110 2111 ret = ath11k_core_reconfigure_on_crash(ab); 2112 if (ret) { 2113 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 2114 return; 2115 } 2116 2117 if (ab->is_reset) 2118 complete_all(&ab->reconfigure_complete); 2119 2120 if (!ab->is_reset) 2121 ath11k_core_post_reconfigure_recovery(ab); 2122 2123 complete(&ab->restart_completed); 2124 } 2125 2126 static void ath11k_core_reset(struct work_struct *work) 2127 { 2128 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 2129 int reset_count, fail_cont_count; 2130 long time_left; 2131 2132 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 2133 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 2134 return; 2135 } 2136 2137 /* Sometimes the recovery will fail and then the next all recovery fail, 2138 * this is to avoid infinite recovery since it can not recovery success. 2139 */ 2140 fail_cont_count = atomic_read(&ab->fail_cont_count); 2141 2142 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 2143 return; 2144 2145 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 2146 time_before(jiffies, ab->reset_fail_timeout)) 2147 return; 2148 2149 reset_count = atomic_inc_return(&ab->reset_count); 2150 2151 if (reset_count > 1) { 2152 /* Sometimes it happened another reset worker before the previous one 2153 * completed, then the second reset worker will destroy the previous one, 2154 * thus below is to avoid that. 2155 */ 2156 ath11k_warn(ab, "already resetting count %d\n", reset_count); 2157 2158 reinit_completion(&ab->reset_complete); 2159 time_left = wait_for_completion_timeout(&ab->reset_complete, 2160 ATH11K_RESET_TIMEOUT_HZ); 2161 2162 if (time_left) { 2163 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 2164 atomic_dec(&ab->reset_count); 2165 return; 2166 } 2167 2168 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 2169 /* Record the continuous recovery fail count when recovery failed*/ 2170 atomic_inc(&ab->fail_cont_count); 2171 } 2172 2173 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 2174 2175 ab->is_reset = true; 2176 atomic_set(&ab->recovery_count, 0); 2177 reinit_completion(&ab->recovery_start); 2178 atomic_set(&ab->recovery_start_count, 0); 2179 2180 ath11k_core_pre_reconfigure_recovery(ab); 2181 2182 reinit_completion(&ab->reconfigure_complete); 2183 ath11k_core_post_reconfigure_recovery(ab); 2184 2185 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 2186 2187 time_left = wait_for_completion_timeout(&ab->recovery_start, 2188 ATH11K_RECOVER_START_TIMEOUT_HZ); 2189 2190 ath11k_hif_irq_disable(ab); 2191 ath11k_hif_ce_irq_disable(ab); 2192 2193 ath11k_hif_power_down(ab, false); 2194 ath11k_hif_power_up(ab); 2195 2196 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 2197 } 2198 2199 static int ath11k_init_hw_params(struct ath11k_base *ab) 2200 { 2201 const struct ath11k_hw_params *hw_params = NULL; 2202 int i; 2203 2204 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 2205 hw_params = &ath11k_hw_params[i]; 2206 2207 if (hw_params->hw_rev == ab->hw_rev) 2208 break; 2209 } 2210 2211 if (i == ARRAY_SIZE(ath11k_hw_params)) { 2212 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 2213 return -EINVAL; 2214 } 2215 2216 ab->hw_params = *hw_params; 2217 2218 ath11k_info(ab, "%s\n", ab->hw_params.name); 2219 2220 return 0; 2221 } 2222 2223 int ath11k_core_pre_init(struct ath11k_base *ab) 2224 { 2225 int ret; 2226 2227 ret = ath11k_init_hw_params(ab); 2228 if (ret) { 2229 ath11k_err(ab, "failed to get hw params: %d\n", ret); 2230 return ret; 2231 } 2232 2233 ret = ath11k_fw_pre_init(ab); 2234 if (ret) { 2235 ath11k_err(ab, "failed to pre init firmware: %d", ret); 2236 return ret; 2237 } 2238 2239 return 0; 2240 } 2241 EXPORT_SYMBOL(ath11k_core_pre_init); 2242 2243 int ath11k_core_init(struct ath11k_base *ab) 2244 { 2245 int ret; 2246 2247 ret = ath11k_core_soc_create(ab); 2248 if (ret) { 2249 ath11k_err(ab, "failed to create soc core: %d\n", ret); 2250 return ret; 2251 } 2252 2253 return 0; 2254 } 2255 EXPORT_SYMBOL(ath11k_core_init); 2256 2257 void ath11k_core_deinit(struct ath11k_base *ab) 2258 { 2259 mutex_lock(&ab->core_lock); 2260 2261 ath11k_core_pdev_destroy(ab); 2262 ath11k_core_stop(ab); 2263 2264 mutex_unlock(&ab->core_lock); 2265 2266 ath11k_hif_power_down(ab, false); 2267 ath11k_mac_destroy(ab); 2268 ath11k_core_soc_destroy(ab); 2269 ath11k_fw_destroy(ab); 2270 } 2271 EXPORT_SYMBOL(ath11k_core_deinit); 2272 2273 void ath11k_core_free(struct ath11k_base *ab) 2274 { 2275 destroy_workqueue(ab->workqueue_aux); 2276 destroy_workqueue(ab->workqueue); 2277 2278 kfree(ab); 2279 } 2280 EXPORT_SYMBOL(ath11k_core_free); 2281 2282 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2283 enum ath11k_bus bus) 2284 { 2285 struct ath11k_base *ab; 2286 2287 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2288 if (!ab) 2289 return NULL; 2290 2291 init_completion(&ab->driver_recovery); 2292 2293 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2294 if (!ab->workqueue) 2295 goto err_sc_free; 2296 2297 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2298 if (!ab->workqueue_aux) 2299 goto err_free_wq; 2300 2301 mutex_init(&ab->core_lock); 2302 mutex_init(&ab->tbl_mtx_lock); 2303 spin_lock_init(&ab->base_lock); 2304 mutex_init(&ab->vdev_id_11d_lock); 2305 init_completion(&ab->reset_complete); 2306 init_completion(&ab->reconfigure_complete); 2307 init_completion(&ab->recovery_start); 2308 2309 INIT_LIST_HEAD(&ab->peers); 2310 init_waitqueue_head(&ab->peer_mapping_wq); 2311 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2312 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2313 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2314 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2315 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2316 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2317 init_completion(&ab->htc_suspend); 2318 init_completion(&ab->wow.wakeup_completed); 2319 init_completion(&ab->restart_completed); 2320 2321 ab->dev = dev; 2322 ab->hif.bus = bus; 2323 2324 return ab; 2325 2326 err_free_wq: 2327 destroy_workqueue(ab->workqueue); 2328 err_sc_free: 2329 kfree(ab); 2330 return NULL; 2331 } 2332 EXPORT_SYMBOL(ath11k_core_alloc); 2333 2334 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2335 MODULE_LICENSE("Dual BSD/GPL"); 2336