xref: /linux/Documentation/devicetree/bindings/net/mediatek,net.yaml (revision d53b8e36925256097a08d7cb749198d85cbf9b2b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7621-eth
23      - mediatek,mt7622-eth
24      - mediatek,mt7629-eth
25      - mediatek,mt7981-eth
26      - mediatek,mt7986-eth
27      - mediatek,mt7988-eth
28      - ralink,rt5350-eth
29
30  reg:
31    maxItems: 1
32
33  clocks: true
34  clock-names: true
35
36  interrupts:
37    minItems: 1
38    maxItems: 4
39
40  power-domains:
41    maxItems: 1
42
43  resets:
44    maxItems: 3
45
46  reset-names:
47    items:
48      - const: fe
49      - const: gmac
50      - const: ppe
51
52  mediatek,ethsys:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description:
55      Phandle to the syscon node that handles the port setup.
56
57  cci-control-port: true
58
59  mediatek,hifsys:
60    $ref: /schemas/types.yaml#/definitions/phandle
61    description:
62      Phandle to the mediatek hifsys controller used to provide various clocks
63      and reset to the system.
64
65  mediatek,infracfg:
66    $ref: /schemas/types.yaml#/definitions/phandle
67    description:
68      Phandle to the syscon node that handles the path from GMAC to
69      PHY variants.
70
71  mediatek,pcie-mirror:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      Phandle to the mediatek pcie-mirror controller.
75
76  mediatek,pctl:
77    $ref: /schemas/types.yaml#/definitions/phandle
78    description:
79      Phandle to the syscon node that handles the ports slew rate and
80      driver current.
81
82  mediatek,sgmiisys:
83    $ref: /schemas/types.yaml#/definitions/phandle-array
84    minItems: 1
85    maxItems: 2
86    items:
87      maxItems: 1
88    description:
89      A list of phandle to the syscon node that handles the SGMII setup which is required for
90      those SoCs equipped with SGMII.
91
92  mediatek,wed:
93    $ref: /schemas/types.yaml#/definitions/phandle-array
94    minItems: 2
95    maxItems: 2
96    items:
97      maxItems: 1
98    description:
99      List of phandles to wireless ethernet dispatch nodes.
100
101  mediatek,wed-pcie:
102    $ref: /schemas/types.yaml#/definitions/phandle
103    description:
104      Phandle to the mediatek wed-pcie controller.
105
106  dma-coherent: true
107
108  mdio-bus:
109    $ref: mdio.yaml#
110    unevaluatedProperties: false
111
112  "#address-cells":
113    const: 1
114
115  "#size-cells":
116    const: 0
117
118allOf:
119  - $ref: ethernet-controller.yaml#
120  - if:
121      properties:
122        compatible:
123          contains:
124            enum:
125              - mediatek,mt2701-eth
126              - mediatek,mt7623-eth
127    then:
128      properties:
129        interrupts:
130          maxItems: 3
131
132        clocks:
133          minItems: 4
134          maxItems: 4
135
136        clock-names:
137          items:
138            - const: ethif
139            - const: esw
140            - const: gp1
141            - const: gp2
142
143        mediatek,infracfg: false
144
145        mediatek,wed: false
146
147        mediatek,wed-pcie: false
148    else:
149      properties:
150        mediatek,pctl: false
151
152  - if:
153      properties:
154        compatible:
155          contains:
156            enum:
157              - mediatek,mt7621-eth
158    then:
159      properties:
160        interrupts:
161          maxItems: 1
162
163        clocks:
164          minItems: 2
165          maxItems: 2
166
167        clock-names:
168          items:
169            - const: ethif
170            - const: fe
171
172        mediatek,infracfg: false
173
174        mediatek,wed: false
175
176        mediatek,wed-pcie: false
177
178  - if:
179      properties:
180        compatible:
181          contains:
182            const: mediatek,mt7622-eth
183    then:
184      properties:
185        interrupts:
186          maxItems: 3
187
188        clocks:
189          minItems: 11
190          maxItems: 11
191
192        clock-names:
193          items:
194            - const: ethif
195            - const: esw
196            - const: gp0
197            - const: gp1
198            - const: gp2
199            - const: sgmii_tx250m
200            - const: sgmii_rx250m
201            - const: sgmii_cdr_ref
202            - const: sgmii_cdr_fb
203            - const: sgmii_ck
204            - const: eth2pll
205
206        mediatek,infracfg: false
207
208        mediatek,sgmiisys:
209          minItems: 1
210          maxItems: 1
211
212        mediatek,wed-pcie: false
213    else:
214      properties:
215        mediatek,pcie-mirror: false
216
217  - if:
218      properties:
219        compatible:
220          contains:
221            const: mediatek,mt7629-eth
222    then:
223      properties:
224        interrupts:
225          maxItems: 3
226
227        clocks:
228          minItems: 17
229          maxItems: 17
230
231        clock-names:
232          items:
233            - const: ethif
234            - const: sgmiitop
235            - const: esw
236            - const: gp0
237            - const: gp1
238            - const: gp2
239            - const: fe
240            - const: sgmii_tx250m
241            - const: sgmii_rx250m
242            - const: sgmii_cdr_ref
243            - const: sgmii_cdr_fb
244            - const: sgmii2_tx250m
245            - const: sgmii2_rx250m
246            - const: sgmii2_cdr_ref
247            - const: sgmii2_cdr_fb
248            - const: sgmii_ck
249            - const: eth2pll
250
251        mediatek,sgmiisys:
252          minItems: 2
253          maxItems: 2
254
255        mediatek,wed: false
256
257        mediatek,wed-pcie: false
258
259  - if:
260      properties:
261        compatible:
262          contains:
263            const: mediatek,mt7981-eth
264    then:
265      properties:
266        interrupts:
267          minItems: 4
268
269        clocks:
270          minItems: 15
271          maxItems: 15
272
273        clock-names:
274          items:
275            - const: fe
276            - const: gp2
277            - const: gp1
278            - const: wocpu0
279            - const: sgmii_ck
280            - const: sgmii_tx250m
281            - const: sgmii_rx250m
282            - const: sgmii_cdr_ref
283            - const: sgmii_cdr_fb
284            - const: sgmii2_tx250m
285            - const: sgmii2_rx250m
286            - const: sgmii2_cdr_ref
287            - const: sgmii2_cdr_fb
288            - const: netsys0
289            - const: netsys1
290
291        mediatek,infracfg: false
292
293        mediatek,sgmiisys:
294          minItems: 2
295          maxItems: 2
296
297  - if:
298      properties:
299        compatible:
300          contains:
301            const: mediatek,mt7986-eth
302    then:
303      properties:
304        interrupts:
305          minItems: 4
306
307        clocks:
308          minItems: 15
309          maxItems: 15
310
311        clock-names:
312          items:
313            - const: fe
314            - const: gp2
315            - const: gp1
316            - const: wocpu1
317            - const: wocpu0
318            - const: sgmii_tx250m
319            - const: sgmii_rx250m
320            - const: sgmii_cdr_ref
321            - const: sgmii_cdr_fb
322            - const: sgmii2_tx250m
323            - const: sgmii2_rx250m
324            - const: sgmii2_cdr_ref
325            - const: sgmii2_cdr_fb
326            - const: netsys0
327            - const: netsys1
328
329        mediatek,infracfg: false
330
331        mediatek,sgmiisys:
332          minItems: 2
333          maxItems: 2
334
335  - if:
336      properties:
337        compatible:
338          contains:
339            const: mediatek,mt7988-eth
340    then:
341      properties:
342        interrupts:
343          minItems: 4
344
345        clocks:
346          minItems: 24
347          maxItems: 24
348
349        clock-names:
350          items:
351            - const: crypto
352            - const: fe
353            - const: gp2
354            - const: gp1
355            - const: gp3
356            - const: ethwarp_wocpu2
357            - const: ethwarp_wocpu1
358            - const: ethwarp_wocpu0
359            - const: esw
360            - const: top_eth_gmii_sel
361            - const: top_eth_refck_50m_sel
362            - const: top_eth_sys_200m_sel
363            - const: top_eth_sys_sel
364            - const: top_eth_xgmii_sel
365            - const: top_eth_mii_sel
366            - const: top_netsys_sel
367            - const: top_netsys_500m_sel
368            - const: top_netsys_pao_2x_sel
369            - const: top_netsys_sync_250m_sel
370            - const: top_netsys_ppefb_250m_sel
371            - const: top_netsys_warp_sel
372            - const: xgp1
373            - const: xgp2
374            - const: xgp3
375
376patternProperties:
377  "^mac@[0-1]$":
378    type: object
379    unevaluatedProperties: false
380    allOf:
381      - $ref: ethernet-controller.yaml#
382    description:
383      Ethernet MAC node
384    properties:
385      compatible:
386        const: mediatek,eth-mac
387
388      reg:
389        maxItems: 1
390
391    required:
392      - reg
393      - compatible
394
395required:
396  - compatible
397  - reg
398  - interrupts
399  - clocks
400  - clock-names
401  - mediatek,ethsys
402
403unevaluatedProperties: false
404
405examples:
406  - |
407    #include <dt-bindings/interrupt-controller/arm-gic.h>
408    #include <dt-bindings/interrupt-controller/irq.h>
409    #include <dt-bindings/clock/mt7622-clk.h>
410    #include <dt-bindings/power/mt7622-power.h>
411
412    soc {
413      #address-cells = <2>;
414      #size-cells = <2>;
415
416      ethernet: ethernet@1b100000 {
417        compatible = "mediatek,mt7622-eth";
418        reg = <0 0x1b100000 0 0x20000>;
419        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
420                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
421                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
422        clocks = <&topckgen CLK_TOP_ETH_SEL>,
423                 <&ethsys CLK_ETH_ESW_EN>,
424                 <&ethsys CLK_ETH_GP0_EN>,
425                 <&ethsys CLK_ETH_GP1_EN>,
426                 <&ethsys CLK_ETH_GP2_EN>,
427                 <&sgmiisys CLK_SGMII_TX250M_EN>,
428                 <&sgmiisys CLK_SGMII_RX250M_EN>,
429                 <&sgmiisys CLK_SGMII_CDR_REF>,
430                 <&sgmiisys CLK_SGMII_CDR_FB>,
431                 <&topckgen CLK_TOP_SGMIIPLL>,
432                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
433        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
434                      "sgmii_tx250m", "sgmii_rx250m",
435                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
436                      "eth2pll";
437        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
438        mediatek,ethsys = <&ethsys>;
439        mediatek,sgmiisys = <&sgmiisys>;
440        cci-control-port = <&cci_control2>;
441        mediatek,pcie-mirror = <&pcie_mirror>;
442        mediatek,hifsys = <&hifsys>;
443        dma-coherent;
444
445        #address-cells = <1>;
446        #size-cells = <0>;
447
448        mdio0: mdio-bus {
449          #address-cells = <1>;
450          #size-cells = <0>;
451
452          phy0: ethernet-phy@0 {
453            reg = <0>;
454          };
455
456          phy1: ethernet-phy@1 {
457            reg = <1>;
458          };
459        };
460
461        gmac0: mac@0 {
462          compatible = "mediatek,eth-mac";
463          phy-mode = "rgmii";
464          phy-handle = <&phy0>;
465          reg = <0>;
466        };
467
468        gmac1: mac@1 {
469          compatible = "mediatek,eth-mac";
470          phy-mode = "rgmii";
471          phy-handle = <&phy1>;
472          reg = <1>;
473        };
474      };
475    };
476
477  - |
478    #include <dt-bindings/interrupt-controller/arm-gic.h>
479    #include <dt-bindings/interrupt-controller/irq.h>
480    #include <dt-bindings/clock/mt7622-clk.h>
481
482    soc {
483      #address-cells = <2>;
484      #size-cells = <2>;
485
486      eth: ethernet@15100000 {
487        #define CLK_ETH_FE_EN               0
488        #define CLK_ETH_WOCPU1_EN           3
489        #define CLK_ETH_WOCPU0_EN           4
490        #define CLK_TOP_NETSYS_SEL          43
491        #define CLK_TOP_NETSYS_500M_SEL     44
492        #define CLK_TOP_NETSYS_2X_SEL       46
493        #define CLK_TOP_SGM_325M_SEL        47
494        #define CLK_APMIXED_NET2PLL         1
495        #define CLK_APMIXED_SGMPLL          3
496
497        compatible = "mediatek,mt7986-eth";
498        reg = <0 0x15100000 0 0x80000>;
499        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
500                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
501                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
502                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
503        clocks = <&ethsys CLK_ETH_FE_EN>,
504                 <&ethsys CLK_ETH_GP2_EN>,
505                 <&ethsys CLK_ETH_GP1_EN>,
506                 <&ethsys CLK_ETH_WOCPU1_EN>,
507                 <&ethsys CLK_ETH_WOCPU0_EN>,
508                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
509                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
510                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
511                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
512                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
513                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
514                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
515                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
516                 <&topckgen CLK_TOP_NETSYS_SEL>,
517                 <&topckgen CLK_TOP_NETSYS_SEL>;
518        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
519                      "sgmii_tx250m", "sgmii_rx250m",
520                      "sgmii_cdr_ref", "sgmii_cdr_fb",
521                      "sgmii2_tx250m", "sgmii2_rx250m",
522                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
523                      "netsys0", "netsys1";
524        mediatek,ethsys = <&ethsys>;
525        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
526        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
527                          <&topckgen CLK_TOP_SGM_325M_SEL>;
528        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
529                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
530
531        #address-cells = <1>;
532        #size-cells = <0>;
533
534        mdio: mdio-bus {
535          #address-cells = <1>;
536          #size-cells = <0>;
537
538          phy5: ethernet-phy@0 {
539            compatible = "ethernet-phy-id67c9.de0a";
540            phy-mode = "2500base-x";
541            reset-gpios = <&pio 6 1>;
542            reset-deassert-us = <20000>;
543            reg = <5>;
544          };
545
546          phy6: ethernet-phy@1 {
547            compatible = "ethernet-phy-id67c9.de0a";
548            phy-mode = "2500base-x";
549            reg = <6>;
550          };
551        };
552
553        mac0: mac@0 {
554          compatible = "mediatek,eth-mac";
555          phy-mode = "2500base-x";
556          phy-handle = <&phy5>;
557          reg = <0>;
558        };
559
560        mac1: mac@1 {
561          compatible = "mediatek,eth-mac";
562          phy-mode = "2500base-x";
563          phy-handle = <&phy6>;
564          reg = <1>;
565        };
566      };
567    };
568