1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 #include "a6xx_gpu.h" 11 #include "a6xx.xml.h" 12 #include "a6xx_gmu.xml.h" 13 14 static const struct adreno_reglist a612_hwcg[] = { 15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, 18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, 33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, 36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, 42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 61 {}, 62 }; 63 64 /* For a615 family (a615, a616, a618 and a619) */ 65 static const struct adreno_reglist a615_hwcg[] = { 66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020}, 103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, 108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, 109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, 110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 129 {}, 130 }; 131 132 static const struct adreno_reglist a630_hwcg[] = { 133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 134 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 135 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 136 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 137 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 138 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 139 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 140 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 141 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 142 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 143 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 144 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 145 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 146 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 147 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 148 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 149 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 150 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 151 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 152 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 153 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 154 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 155 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 156 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 157 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 158 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 159 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 160 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 161 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 162 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 163 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 164 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 165 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 166 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 167 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 168 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 169 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 170 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 171 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 172 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 173 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 174 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 175 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 176 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 177 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 178 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 179 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 180 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 181 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 182 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 183 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 184 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 185 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 186 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 187 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 188 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 189 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 190 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 191 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 192 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 193 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 194 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 195 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 196 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 197 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 198 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 199 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 200 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 201 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 202 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 203 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 204 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 205 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 206 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 207 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 208 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 209 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 210 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 211 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 212 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 213 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 214 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 215 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 216 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 217 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 218 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 219 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 221 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 222 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 223 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 224 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 225 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 226 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 227 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 228 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 229 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 230 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 231 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 232 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 233 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 234 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 235 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 236 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 237 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 238 {}, 239 }; 240 241 static const struct adreno_reglist a640_hwcg[] = { 242 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 243 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 244 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 245 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 246 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 247 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 248 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 249 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 250 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 251 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 252 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 253 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 254 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 255 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 256 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 257 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 258 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 259 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 260 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 261 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 262 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 263 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 265 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 266 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 267 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 268 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 269 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 270 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 271 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 272 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 273 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 274 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 275 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 276 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 277 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 278 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 279 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 280 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 281 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 282 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 283 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 284 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 285 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 286 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 287 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 291 {}, 292 }; 293 294 static const struct adreno_reglist a650_hwcg[] = { 295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 344 {}, 345 }; 346 347 static const struct adreno_reglist a660_hwcg[] = { 348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 397 {}, 398 }; 399 400 static const struct adreno_reglist a690_hwcg[] = { 401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 444 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82}, 445 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 446 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 447 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 448 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 449 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 450 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 451 {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, 452 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, 453 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, 454 {} 455 }; 456 457 /* For a615, a616, a618, a619, a630, a640 and a680 */ 458 static const u32 a630_protect_regs[] = { 459 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 460 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 461 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 462 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 463 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 464 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 465 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 466 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 467 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 468 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 469 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 470 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 471 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 472 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 473 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 474 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 475 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 476 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 477 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 478 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 479 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 480 A6XX_PROTECT_NORDWR(0x09e70, 0x0001), 481 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 482 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 483 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 484 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 485 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 486 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 487 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 488 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 489 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 490 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ 491 }; 492 DECLARE_ADRENO_PROTECT(a630_protect, 32); 493 494 /* These are for a620 and a650 */ 495 static const u32 a650_protect_regs[] = { 496 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 497 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 498 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 499 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 500 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 501 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 502 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 503 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 504 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 505 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 506 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 507 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 508 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 509 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 510 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 511 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 512 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 513 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 514 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 515 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 516 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 517 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 518 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 519 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 520 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 521 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 522 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 523 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 524 A6XX_PROTECT_NORDWR(0x0b608, 0x0007), 525 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 526 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 527 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 528 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 529 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 530 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), 531 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 532 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 533 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 534 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 535 }; 536 DECLARE_ADRENO_PROTECT(a650_protect, 48); 537 538 /* These are for a635 and a660 */ 539 static const u32 a660_protect_regs[] = { 540 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 541 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 542 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 543 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 544 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 545 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 546 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 547 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 548 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 549 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 550 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 551 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 552 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 553 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 554 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 555 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 556 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 557 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 558 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 559 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 560 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 561 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 562 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 563 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 564 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 565 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 566 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), 567 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 568 A6XX_PROTECT_NORDWR(0x0b608, 0x0006), 569 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 570 A6XX_PROTECT_NORDWR(0x0be20, 0x015f), 571 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), 572 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 573 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 574 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 575 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), 576 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 577 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 578 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 579 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 580 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 581 }; 582 DECLARE_ADRENO_PROTECT(a660_protect, 48); 583 584 /* These are for a690 */ 585 static const u32 a690_protect_regs[] = { 586 A6XX_PROTECT_RDONLY(0x00000, 0x004ff), 587 A6XX_PROTECT_RDONLY(0x00501, 0x00001), 588 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4), 589 A6XX_PROTECT_NORDWR(0x0050e, 0x00000), 590 A6XX_PROTECT_NORDWR(0x00510, 0x00000), 591 A6XX_PROTECT_NORDWR(0x00534, 0x00000), 592 A6XX_PROTECT_NORDWR(0x00800, 0x00082), 593 A6XX_PROTECT_NORDWR(0x008a0, 0x00008), 594 A6XX_PROTECT_NORDWR(0x008ab, 0x00024), 595 A6XX_PROTECT_RDONLY(0x008de, 0x000ae), 596 A6XX_PROTECT_NORDWR(0x00900, 0x0004d), 597 A6XX_PROTECT_NORDWR(0x0098d, 0x00272), 598 A6XX_PROTECT_NORDWR(0x00e00, 0x00001), 599 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c), 600 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3), 601 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff), 602 A6XX_PROTECT_NORDWR(0x08630, 0x001cf), 603 A6XX_PROTECT_NORDWR(0x08e00, 0x00000), 604 A6XX_PROTECT_NORDWR(0x08e08, 0x00007), 605 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f), 606 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f), 607 A6XX_PROTECT_NORDWR(0x09624, 0x001db), 608 A6XX_PROTECT_NORDWR(0x09e60, 0x00011), 609 A6XX_PROTECT_NORDWR(0x09e78, 0x00187), 610 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf), 611 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000), 612 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f), 613 A6XX_PROTECT_NORDWR(0x0b604, 0x00000), 614 A6XX_PROTECT_NORDWR(0x0b608, 0x00006), 615 A6XX_PROTECT_NORDWR(0x0be02, 0x00001), 616 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f), 617 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff), 618 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff), 619 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff), 620 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */ 621 }; 622 DECLARE_ADRENO_PROTECT(a690_protect, 48); 623 624 static const struct adreno_info a6xx_gpus[] = { 625 { 626 .chip_ids = ADRENO_CHIP_IDS(0x06010000), 627 .family = ADRENO_6XX_GEN1, 628 .revn = 610, 629 .fw = { 630 [ADRENO_FW_SQE] = "a630_sqe.fw", 631 }, 632 .gmem = (SZ_128K + SZ_4K), 633 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 634 .init = a6xx_gpu_init, 635 .zapfw = "a610_zap.mdt", 636 .a6xx = &(const struct a6xx_info) { 637 .hwcg = a612_hwcg, 638 .protect = &a630_protect, 639 }, 640 /* 641 * There are (at least) three SoCs implementing A610: SM6125 642 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does 643 * not have speedbinning, as only a single SKU exists and we 644 * don't support khaje upstream yet. Hence, this matching 645 * table is only valid for bengal. 646 */ 647 .speedbins = ADRENO_SPEEDBINS( 648 { 0, 0 }, 649 { 206, 1 }, 650 { 200, 2 }, 651 { 157, 3 }, 652 { 127, 4 }, 653 ), 654 }, { 655 .chip_ids = ADRENO_CHIP_IDS(0x06010500), 656 .family = ADRENO_6XX_GEN1, 657 .revn = 615, 658 .fw = { 659 [ADRENO_FW_SQE] = "a630_sqe.fw", 660 [ADRENO_FW_GMU] = "a630_gmu.bin", 661 }, 662 .gmem = SZ_512K, 663 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 664 .init = a6xx_gpu_init, 665 .zapfw = "a615_zap.mdt", 666 .a6xx = &(const struct a6xx_info) { 667 .hwcg = a615_hwcg, 668 .protect = &a630_protect, 669 }, 670 .speedbins = ADRENO_SPEEDBINS( 671 /* 672 * The default speed bin (0) has the same values as 673 * speed bin 90 which goes up to 432 MHz. 674 */ 675 { 0, 0 }, 676 { 90, 0 }, 677 { 105, 1 }, 678 { 146, 2 }, 679 { 163, 3 }, 680 ), 681 }, { 682 .machine = "qcom,sm7150", 683 .chip_ids = ADRENO_CHIP_IDS(0x06010800), 684 .family = ADRENO_6XX_GEN1, 685 .fw = { 686 [ADRENO_FW_SQE] = "a630_sqe.fw", 687 [ADRENO_FW_GMU] = "a630_gmu.bin", 688 }, 689 .gmem = SZ_512K, 690 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 691 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 692 .init = a6xx_gpu_init, 693 .zapfw = "a615_zap.mbn", 694 .a6xx = &(const struct a6xx_info) { 695 .hwcg = a615_hwcg, 696 .protect = &a630_protect, 697 }, 698 .speedbins = ADRENO_SPEEDBINS( 699 { 0, 0 }, 700 { 128, 1 }, 701 { 146, 2 }, 702 { 167, 3 }, 703 { 172, 4 }, 704 ), 705 }, { 706 .chip_ids = ADRENO_CHIP_IDS(0x06010800), 707 .family = ADRENO_6XX_GEN1, 708 .revn = 618, 709 .fw = { 710 [ADRENO_FW_SQE] = "a630_sqe.fw", 711 [ADRENO_FW_GMU] = "a630_gmu.bin", 712 }, 713 .gmem = SZ_512K, 714 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 715 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 716 .init = a6xx_gpu_init, 717 .a6xx = &(const struct a6xx_info) { 718 .protect = &a630_protect, 719 }, 720 .speedbins = ADRENO_SPEEDBINS( 721 { 0, 0 }, 722 { 169, 1 }, 723 { 174, 2 }, 724 ), 725 }, { 726 .machine = "qcom,sm4350", 727 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 728 .family = ADRENO_6XX_GEN1, 729 .revn = 619, 730 .fw = { 731 [ADRENO_FW_SQE] = "a630_sqe.fw", 732 [ADRENO_FW_GMU] = "a619_gmu.bin", 733 }, 734 .gmem = SZ_512K, 735 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 736 .init = a6xx_gpu_init, 737 .zapfw = "a615_zap.mdt", 738 .a6xx = &(const struct a6xx_info) { 739 .hwcg = a615_hwcg, 740 .protect = &a630_protect, 741 }, 742 .speedbins = ADRENO_SPEEDBINS( 743 { 0, 0 }, 744 { 138, 1 }, 745 { 92, 2 }, 746 ), 747 }, { 748 .machine = "qcom,sm6375", 749 .chip_ids = ADRENO_CHIP_IDS(0x06010901), 750 .family = ADRENO_6XX_GEN1, 751 .revn = 619, 752 .fw = { 753 [ADRENO_FW_SQE] = "a630_sqe.fw", 754 [ADRENO_FW_GMU] = "a619_gmu.bin", 755 }, 756 .gmem = SZ_512K, 757 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 758 .init = a6xx_gpu_init, 759 .zapfw = "a615_zap.mdt", 760 .a6xx = &(const struct a6xx_info) { 761 .hwcg = a615_hwcg, 762 .protect = &a630_protect, 763 }, 764 .speedbins = ADRENO_SPEEDBINS( 765 { 0, 0 }, 766 { 190, 1 }, 767 { 177, 2 }, 768 ), 769 }, { 770 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 771 .family = ADRENO_6XX_GEN1, 772 .revn = 619, 773 .fw = { 774 [ADRENO_FW_SQE] = "a630_sqe.fw", 775 [ADRENO_FW_GMU] = "a619_gmu.bin", 776 }, 777 .gmem = SZ_512K, 778 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 779 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 780 .init = a6xx_gpu_init, 781 .zapfw = "a615_zap.mdt", 782 .a6xx = &(const struct a6xx_info) { 783 .hwcg = a615_hwcg, 784 .protect = &a630_protect, 785 }, 786 .speedbins = ADRENO_SPEEDBINS( 787 { 0, 0 }, 788 { 120, 4 }, 789 { 138, 3 }, 790 { 169, 2 }, 791 { 180, 1 }, 792 ), 793 }, { 794 .chip_ids = ADRENO_CHIP_IDS( 795 0x06030001, 796 0x06030002 797 ), 798 .family = ADRENO_6XX_GEN1, 799 .revn = 630, 800 .fw = { 801 [ADRENO_FW_SQE] = "a630_sqe.fw", 802 [ADRENO_FW_GMU] = "a630_gmu.bin", 803 }, 804 .gmem = SZ_1M, 805 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 806 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 807 .init = a6xx_gpu_init, 808 .zapfw = "a630_zap.mdt", 809 .a6xx = &(const struct a6xx_info) { 810 .hwcg = a630_hwcg, 811 .protect = &a630_protect, 812 }, 813 }, { 814 .chip_ids = ADRENO_CHIP_IDS(0x06040001), 815 .family = ADRENO_6XX_GEN2, 816 .revn = 640, 817 .fw = { 818 [ADRENO_FW_SQE] = "a630_sqe.fw", 819 [ADRENO_FW_GMU] = "a640_gmu.bin", 820 }, 821 .gmem = SZ_1M, 822 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 823 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 824 .init = a6xx_gpu_init, 825 .zapfw = "a640_zap.mdt", 826 .a6xx = &(const struct a6xx_info) { 827 .hwcg = a640_hwcg, 828 .protect = &a630_protect, 829 }, 830 .speedbins = ADRENO_SPEEDBINS( 831 { 0, 0 }, 832 { 1, 1 }, 833 ), 834 }, { 835 .chip_ids = ADRENO_CHIP_IDS(0x06050002), 836 .family = ADRENO_6XX_GEN3, 837 .revn = 650, 838 .fw = { 839 [ADRENO_FW_SQE] = "a650_sqe.fw", 840 [ADRENO_FW_GMU] = "a650_gmu.bin", 841 }, 842 .gmem = SZ_1M + SZ_128K, 843 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 844 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 845 ADRENO_QUIRK_HAS_HW_APRIV, 846 .init = a6xx_gpu_init, 847 .zapfw = "a650_zap.mdt", 848 .a6xx = &(const struct a6xx_info) { 849 .hwcg = a650_hwcg, 850 .protect = &a650_protect, 851 }, 852 .address_space_size = SZ_16G, 853 .speedbins = ADRENO_SPEEDBINS( 854 { 0, 0 }, 855 { 1, 1 }, 856 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ 857 { 3, 2 }, 858 ), 859 }, { 860 .chip_ids = ADRENO_CHIP_IDS(0x06060001), 861 .family = ADRENO_6XX_GEN4, 862 .revn = 660, 863 .fw = { 864 [ADRENO_FW_SQE] = "a660_sqe.fw", 865 [ADRENO_FW_GMU] = "a660_gmu.bin", 866 }, 867 .gmem = SZ_1M + SZ_512K, 868 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 869 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 870 ADRENO_QUIRK_HAS_HW_APRIV, 871 .init = a6xx_gpu_init, 872 .zapfw = "a660_zap.mdt", 873 .a6xx = &(const struct a6xx_info) { 874 .hwcg = a660_hwcg, 875 .protect = &a660_protect, 876 }, 877 .address_space_size = SZ_16G, 878 }, { 879 .chip_ids = ADRENO_CHIP_IDS(0x06030500), 880 .family = ADRENO_6XX_GEN4, 881 .fw = { 882 [ADRENO_FW_SQE] = "a660_sqe.fw", 883 [ADRENO_FW_GMU] = "a660_gmu.bin", 884 }, 885 .gmem = SZ_512K, 886 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 887 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 888 ADRENO_QUIRK_HAS_HW_APRIV, 889 .init = a6xx_gpu_init, 890 .zapfw = "a660_zap.mbn", 891 .a6xx = &(const struct a6xx_info) { 892 .hwcg = a660_hwcg, 893 .protect = &a660_protect, 894 }, 895 .address_space_size = SZ_16G, 896 .speedbins = ADRENO_SPEEDBINS( 897 { 0, 0 }, 898 { 117, 0 }, 899 { 129, 4 }, 900 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ 901 { 190, 1 }, 902 ), 903 }, { 904 .chip_ids = ADRENO_CHIP_IDS(0x06080001), 905 .family = ADRENO_6XX_GEN2, 906 .revn = 680, 907 .fw = { 908 [ADRENO_FW_SQE] = "a630_sqe.fw", 909 [ADRENO_FW_GMU] = "a640_gmu.bin", 910 }, 911 .gmem = SZ_2M, 912 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 913 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 914 .init = a6xx_gpu_init, 915 .zapfw = "a640_zap.mdt", 916 .a6xx = &(const struct a6xx_info) { 917 .hwcg = a640_hwcg, 918 .protect = &a630_protect, 919 }, 920 }, { 921 .chip_ids = ADRENO_CHIP_IDS(0x06090000), 922 .family = ADRENO_6XX_GEN4, 923 .fw = { 924 [ADRENO_FW_SQE] = "a660_sqe.fw", 925 [ADRENO_FW_GMU] = "a660_gmu.bin", 926 }, 927 .gmem = SZ_4M, 928 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 929 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 930 ADRENO_QUIRK_HAS_HW_APRIV, 931 .init = a6xx_gpu_init, 932 .zapfw = "a690_zap.mdt", 933 .a6xx = &(const struct a6xx_info) { 934 .hwcg = a690_hwcg, 935 .protect = &a690_protect, 936 }, 937 .address_space_size = SZ_16G, 938 } 939 }; 940 DECLARE_ADRENO_GPULIST(a6xx); 941 942 MODULE_FIRMWARE("qcom/a615_zap.mbn"); 943 MODULE_FIRMWARE("qcom/a619_gmu.bin"); 944 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 945 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 946 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 947 MODULE_FIRMWARE("qcom/a640_gmu.bin"); 948 MODULE_FIRMWARE("qcom/a650_gmu.bin"); 949 MODULE_FIRMWARE("qcom/a650_sqe.fw"); 950 MODULE_FIRMWARE("qcom/a660_gmu.bin"); 951 MODULE_FIRMWARE("qcom/a660_sqe.fw"); 952 953 static const struct adreno_reglist a702_hwcg[] = { 954 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, 955 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, 956 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, 957 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, 958 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, 959 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 960 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 961 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, 962 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 963 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 964 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 965 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 966 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 967 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 968 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 969 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 970 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 971 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, 972 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 973 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, 974 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, 975 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, 976 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 977 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, 978 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 979 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, 980 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, 981 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, 982 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 983 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, 984 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, 985 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 986 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 987 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 988 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 989 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 990 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 991 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 992 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, 993 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, 994 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 995 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 996 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 997 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 998 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 999 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 1000 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, 1001 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, 1002 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, 1003 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, 1004 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, 1005 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, 1006 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, 1007 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, 1008 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, 1009 {} 1010 }; 1011 1012 static const struct adreno_reglist a730_hwcg[] = { 1013 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, 1014 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, 1015 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, 1016 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, 1017 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, 1018 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 1019 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 1020 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, 1021 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 1022 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 1023 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 1024 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 1025 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 1026 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 1027 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 1028 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 1029 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 1030 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, 1031 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, 1032 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 1033 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, 1034 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 1035 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, 1036 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, 1037 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, 1038 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 1039 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, 1040 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 1041 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, 1042 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, 1043 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, 1044 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, 1045 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, 1046 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, 1047 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 1048 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 1049 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 1050 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, 1051 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 1052 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, 1053 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 1054 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 1055 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 1056 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, 1057 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, 1058 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, 1059 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, 1060 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 1061 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 1062 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 1063 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 1064 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 1065 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 1066 {}, 1067 }; 1068 1069 static const struct adreno_reglist a740_hwcg[] = { 1070 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, 1071 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, 1072 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, 1073 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, 1074 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, 1075 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 1076 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 1077 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, 1078 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 1079 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 1080 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 1081 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 1082 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 1083 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 1084 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 1085 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 1086 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 1087 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, 1088 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, 1089 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, 1090 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 1091 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, 1092 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 1093 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, 1094 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, 1095 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, 1096 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 1097 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, 1098 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 1099 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, 1100 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, 1101 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, 1102 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, 1103 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, 1104 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, 1105 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 1106 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 1107 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 1108 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, 1109 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 1110 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, 1111 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 1112 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 1113 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 1114 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, 1115 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, 1116 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, 1117 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, 1118 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 1119 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 1120 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 1121 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 1122 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 1123 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 1124 {}, 1125 }; 1126 1127 static const u32 a730_protect_regs[] = { 1128 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 1129 A6XX_PROTECT_RDONLY(0x0050b, 0x0058), 1130 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 1131 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 1132 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 1133 A6XX_PROTECT_RDONLY(0x005fb, 0x009d), 1134 A6XX_PROTECT_NORDWR(0x00699, 0x01e9), 1135 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 1136 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 1137 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ 1138 A6XX_PROTECT_NORDWR(0x008de, 0x0001), 1139 A6XX_PROTECT_RDONLY(0x008e7, 0x014b), 1140 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 1141 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), 1142 A6XX_PROTECT_NORDWR(0x00a41, 0x01be), 1143 A6XX_PROTECT_NORDWR(0x00df0, 0x0001), 1144 A6XX_PROTECT_NORDWR(0x00e01, 0x0000), 1145 A6XX_PROTECT_NORDWR(0x00e07, 0x0008), 1146 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 1147 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 1148 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 1149 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 1150 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 1151 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 1152 A6XX_PROTECT_NORDWR(0x08e80, 0x0280), 1153 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 1154 A6XX_PROTECT_NORDWR(0x09e40, 0x0000), 1155 A6XX_PROTECT_NORDWR(0x09e64, 0x000d), 1156 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 1157 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 1158 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 1159 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), 1160 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), 1161 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), 1162 A6XX_PROTECT_NORDWR(0x0b604, 0x0003), 1163 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), 1164 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 1165 A6XX_PROTECT_NORDWR(0x18400, 0x0053), 1166 A6XX_PROTECT_RDONLY(0x18454, 0x0004), 1167 A6XX_PROTECT_NORDWR(0x18459, 0x1fff), 1168 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), 1169 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), 1170 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 1171 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 1172 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 1173 A6XX_PROTECT_NORDWR(0x1f878, 0x002a), 1174 /* CP_PROTECT_REG[45, 46] are left untouched! */ 1175 0, 1176 0, 1177 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), 1178 }; 1179 DECLARE_ADRENO_PROTECT(a730_protect, 48); 1180 1181 static const struct adreno_info a7xx_gpus[] = { 1182 { 1183 .chip_ids = ADRENO_CHIP_IDS(0x07000200), 1184 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ 1185 .fw = { 1186 [ADRENO_FW_SQE] = "a702_sqe.fw", 1187 }, 1188 .gmem = SZ_128K, 1189 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1190 .quirks = ADRENO_QUIRK_HAS_HW_APRIV, 1191 .init = a6xx_gpu_init, 1192 .zapfw = "a702_zap.mbn", 1193 .a6xx = &(const struct a6xx_info) { 1194 .hwcg = a702_hwcg, 1195 .protect = &a650_protect, 1196 }, 1197 .speedbins = ADRENO_SPEEDBINS( 1198 { 0, 0 }, 1199 { 236, 1 }, 1200 { 178, 2 }, 1201 { 142, 3 }, 1202 ), 1203 }, { 1204 .chip_ids = ADRENO_CHIP_IDS(0x07030001), 1205 .family = ADRENO_7XX_GEN1, 1206 .fw = { 1207 [ADRENO_FW_SQE] = "a730_sqe.fw", 1208 [ADRENO_FW_GMU] = "gmu_gen70000.bin", 1209 }, 1210 .gmem = SZ_2M, 1211 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1212 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1213 ADRENO_QUIRK_HAS_HW_APRIV, 1214 .init = a6xx_gpu_init, 1215 .zapfw = "a730_zap.mdt", 1216 .a6xx = &(const struct a6xx_info) { 1217 .hwcg = a730_hwcg, 1218 .protect = &a730_protect, 1219 }, 1220 .address_space_size = SZ_16G, 1221 }, { 1222 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ 1223 .family = ADRENO_7XX_GEN2, 1224 .fw = { 1225 [ADRENO_FW_SQE] = "a740_sqe.fw", 1226 [ADRENO_FW_GMU] = "gmu_gen70200.bin", 1227 }, 1228 .gmem = 3 * SZ_1M, 1229 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1230 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1231 ADRENO_QUIRK_HAS_HW_APRIV, 1232 .init = a6xx_gpu_init, 1233 .zapfw = "a740_zap.mdt", 1234 .a6xx = &(const struct a6xx_info) { 1235 .hwcg = a740_hwcg, 1236 .protect = &a730_protect, 1237 .gmu_chipid = 0x7020100, 1238 }, 1239 .address_space_size = SZ_16G, 1240 }, { 1241 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ 1242 .family = ADRENO_7XX_GEN2, 1243 .fw = { 1244 [ADRENO_FW_SQE] = "gen70500_sqe.fw", 1245 [ADRENO_FW_GMU] = "gen70500_gmu.bin", 1246 }, 1247 .gmem = 3 * SZ_1M, 1248 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1249 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1250 ADRENO_QUIRK_HAS_HW_APRIV, 1251 .init = a6xx_gpu_init, 1252 .a6xx = &(const struct a6xx_info) { 1253 .hwcg = a740_hwcg, 1254 .protect = &a730_protect, 1255 .gmu_chipid = 0x7050001, 1256 }, 1257 .address_space_size = SZ_256G, 1258 }, { 1259 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ 1260 .family = ADRENO_7XX_GEN3, 1261 .fw = { 1262 [ADRENO_FW_SQE] = "gen70900_sqe.fw", 1263 [ADRENO_FW_GMU] = "gmu_gen70900.bin", 1264 }, 1265 .gmem = 3 * SZ_1M, 1266 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1267 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1268 ADRENO_QUIRK_HAS_HW_APRIV, 1269 .init = a6xx_gpu_init, 1270 .zapfw = "gen70900_zap.mbn", 1271 .a6xx = &(const struct a6xx_info) { 1272 .protect = &a730_protect, 1273 .gmu_chipid = 0x7090100, 1274 }, 1275 .address_space_size = SZ_16G, 1276 } 1277 }; 1278 DECLARE_ADRENO_GPULIST(a7xx); 1279 1280 static inline __always_unused void __build_asserts(void) 1281 { 1282 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max); 1283 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max); 1284 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); 1285 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); 1286 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); 1287 } 1288