1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* 3 * This header provides constants for pinctrl bindings for TI's K3 SoC 4 * family. 5 * 6 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 #ifndef DTS_ARM64_TI_K3_PINCTRL_H 9 #define DTS_ARM64_TI_K3_PINCTRL_H 10 11 #define PULLUDEN_SHIFT (16) 12 #define PULLTYPESEL_SHIFT (17) 13 #define RXACTIVE_SHIFT (18) 14 #define DEBOUNCE_SHIFT (11) 15 16 #define PULL_DISABLE (1 << PULLUDEN_SHIFT) 17 #define PULL_ENABLE (0 << PULLUDEN_SHIFT) 18 19 #define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) 20 #define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) 21 22 #define INPUT_EN (1 << RXACTIVE_SHIFT) 23 #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) 24 25 /* Only these macros are expected be used directly in device tree files */ 26 #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) 27 #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) 28 #define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) 29 #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 30 #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 31 #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) 32 33 #define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) 34 #define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) 35 #define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) 36 #define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) 37 #define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) 38 #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) 39 #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) 40 41 /* Default mux configuration for gpio-ranges to use with pinctrl */ 42 #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) 43 44 #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 45 #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 46 47 #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 48 #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 49 50 #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 51 #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 52 53 #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 54 #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 55 56 #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 57 #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 58 59 #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 60 #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 61 62 #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 63 #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 64 65 #define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 66 #define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 67 68 #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 69 #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 70 71 #endif 72