1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,qcm2290-smmu-500 39 - qcom,qdu1000-smmu-500 40 - qcom,sa8775p-smmu-500 41 - qcom,sc7180-smmu-500 42 - qcom,sc7280-smmu-500 43 - qcom,sc8180x-smmu-500 44 - qcom,sc8280xp-smmu-500 45 - qcom,sdm670-smmu-500 46 - qcom,sdm845-smmu-500 47 - qcom,sdx55-smmu-500 48 - qcom,sdx65-smmu-500 49 - qcom,sdx75-smmu-500 50 - qcom,sm6115-smmu-500 51 - qcom,sm6125-smmu-500 52 - qcom,sm6350-smmu-500 53 - qcom,sm6375-smmu-500 54 - qcom,sm8150-smmu-500 55 - qcom,sm8250-smmu-500 56 - qcom,sm8350-smmu-500 57 - qcom,sm8450-smmu-500 58 - qcom,sm8550-smmu-500 59 - qcom,sm8650-smmu-500 60 - qcom,x1e80100-smmu-500 61 - const: qcom,smmu-500 62 - const: arm,mmu-500 63 64 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 65 deprecated: true 66 items: 67 # Do not add additional SoC to this list. Instead use two previous lists. 68 - enum: 69 - qcom,qcm2290-smmu-500 70 - qcom,sc7180-smmu-500 71 - qcom,sc7280-smmu-500 72 - qcom,sc8180x-smmu-500 73 - qcom,sc8280xp-smmu-500 74 - qcom,sdm845-smmu-500 75 - qcom,sm6115-smmu-500 76 - qcom,sm6350-smmu-500 77 - qcom,sm6375-smmu-500 78 - qcom,sm8150-smmu-500 79 - qcom,sm8250-smmu-500 80 - qcom,sm8350-smmu-500 81 - qcom,sm8450-smmu-500 82 - const: arm,mmu-500 83 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 84 items: 85 - enum: 86 - qcom,qcm2290-smmu-500 87 - qcom,sa8775p-smmu-500 88 - qcom,sc7280-smmu-500 89 - qcom,sc8180x-smmu-500 90 - qcom,sc8280xp-smmu-500 91 - qcom,sm6115-smmu-500 92 - qcom,sm6125-smmu-500 93 - qcom,sm8150-smmu-500 94 - qcom,sm8250-smmu-500 95 - qcom,sm8350-smmu-500 96 - qcom,sm8450-smmu-500 97 - qcom,sm8550-smmu-500 98 - qcom,sm8650-smmu-500 99 - qcom,x1e80100-smmu-500 100 - const: qcom,adreno-smmu 101 - const: qcom,smmu-500 102 - const: arm,mmu-500 103 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 104 deprecated: true 105 items: 106 # Do not add additional SoC to this list. Instead use previous list. 107 - enum: 108 - qcom,sc7280-smmu-500 109 - qcom,sm8150-smmu-500 110 - qcom,sm8250-smmu-500 111 - const: qcom,adreno-smmu 112 - const: arm,mmu-500 113 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 114 items: 115 - enum: 116 - qcom,msm8996-smmu-v2 117 - qcom,sc7180-smmu-v2 118 - qcom,sdm630-smmu-v2 119 - qcom,sdm845-smmu-v2 120 - qcom,sm6350-smmu-v2 121 - qcom,sm7150-smmu-v2 122 - const: qcom,adreno-smmu 123 - const: qcom,smmu-v2 124 - description: Qcom Adreno GPUs on Google Cheza platform 125 items: 126 - const: qcom,sdm845-smmu-v2 127 - const: qcom,smmu-v2 128 - description: Marvell SoCs implementing "arm,mmu-500" 129 items: 130 - const: marvell,ap806-smmu-500 131 - const: arm,mmu-500 132 - description: NVIDIA SoCs that require memory controller interaction 133 and may program multiple ARM MMU-500s identically with the memory 134 controller interleaving translations between multiple instances 135 for improved performance. 136 items: 137 - enum: 138 - nvidia,tegra186-smmu 139 - nvidia,tegra194-smmu 140 - nvidia,tegra234-smmu 141 - const: nvidia,smmu-500 142 - items: 143 - const: arm,mmu-500 144 - const: arm,smmu-v2 145 - items: 146 - enum: 147 - arm,mmu-400 148 - arm,mmu-401 149 - const: arm,smmu-v1 150 - enum: 151 - arm,smmu-v1 152 - arm,smmu-v2 153 - arm,mmu-400 154 - arm,mmu-401 155 - arm,mmu-500 156 - cavium,smmu-v2 157 158 reg: 159 minItems: 1 160 maxItems: 2 161 162 '#global-interrupts': 163 description: The number of global interrupts exposed by the device. 164 $ref: /schemas/types.yaml#/definitions/uint32 165 minimum: 0 166 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 167 168 '#iommu-cells': 169 enum: [ 1, 2 ] 170 description: | 171 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 172 value of 1, each IOMMU specifier represents a distinct stream ID emitted 173 by that device into the relevant SMMU. 174 175 SMMUs with stream matching support and complex masters may use a value of 176 2, where the second cell of the IOMMU specifier represents an SMR mask to 177 combine with the ID in the first cell. Care must be taken to ensure the 178 set of matched IDs does not result in conflicts. 179 180 interrupts: 181 minItems: 1 182 maxItems: 388 # 260 plus 128 contexts 183 description: | 184 Interrupt list, with the first #global-interrupts entries corresponding to 185 the global interrupts and any following entries corresponding to context 186 interrupts, specified in order of their indexing by the SMMU. 187 188 For SMMUv2 implementations, there must be exactly one interrupt per 189 context bank. In the case of a single, combined interrupt, it must be 190 listed multiple times. 191 192 dma-coherent: 193 description: | 194 Present if page table walks made by the SMMU are cache coherent with the 195 CPU. 196 197 NOTE: this only applies to the SMMU itself, not masters connected 198 upstream of the SMMU. 199 200 calxeda,smmu-secure-config-access: 201 type: boolean 202 description: 203 Enable proper handling of buggy implementations that always use secure 204 access to SMMU configuration registers. In this case non-secure aliases of 205 secure registers have to be used during SMMU configuration. 206 207 stream-match-mask: 208 $ref: /schemas/types.yaml#/definitions/uint32 209 description: | 210 For SMMUs supporting stream matching and using #iommu-cells = <1>, 211 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 212 be programmed into the SMRn.MASK field of every stream match register 213 used). For cases where it is desirable to ignore some portion of every 214 Stream ID (e.g. for certain MMU-500 configurations given globally unique 215 input IDs). This property is not valid for SMMUs using stream indexing, or 216 using stream matching with #iommu-cells = <2>, and may be ignored if 217 present in such cases. 218 219 clock-names: 220 minItems: 1 221 maxItems: 7 222 223 clocks: 224 minItems: 1 225 maxItems: 7 226 227 power-domains: 228 minItems: 1 229 maxItems: 3 230 231 nvidia,memory-controller: 232 description: | 233 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 234 The memory controller needs to be programmed with a mapping of memory 235 client IDs to ARM SMMU stream IDs. 236 237 If this property is absent, the mapping programmed by early firmware 238 will be used and it is not guaranteed that IOMMU translations will be 239 enabled for any given device. 240 $ref: /schemas/types.yaml#/definitions/phandle 241 242required: 243 - compatible 244 - reg 245 - '#global-interrupts' 246 - '#iommu-cells' 247 - interrupts 248 249additionalProperties: false 250 251allOf: 252 - if: 253 properties: 254 compatible: 255 contains: 256 enum: 257 - nvidia,tegra186-smmu 258 - nvidia,tegra194-smmu 259 - nvidia,tegra234-smmu 260 then: 261 properties: 262 reg: 263 minItems: 1 264 maxItems: 2 265 266 # The reference to the memory controller is required to ensure that the 267 # memory client to stream ID mapping can be done synchronously with the 268 # IOMMU attachment. 269 required: 270 - nvidia,memory-controller 271 else: 272 properties: 273 reg: 274 maxItems: 1 275 276 - if: 277 properties: 278 compatible: 279 contains: 280 enum: 281 - qcom,msm8998-smmu-v2 282 - qcom,sdm630-smmu-v2 283 then: 284 anyOf: 285 - properties: 286 clock-names: 287 items: 288 - const: bus 289 clocks: 290 items: 291 - description: bus clock required for downstream bus access and for 292 the smmu ptw 293 - properties: 294 clock-names: 295 items: 296 - const: iface 297 - const: mem 298 - const: mem_iface 299 clocks: 300 items: 301 - description: interface clock required to access smmu's registers 302 through the TCU's programming interface. 303 - description: bus clock required for memory access 304 - description: bus clock required for GPU memory access 305 - properties: 306 clock-names: 307 items: 308 - const: iface-mm 309 - const: iface-smmu 310 - const: bus-smmu 311 clocks: 312 items: 313 - description: interface clock required to access mnoc's registers 314 through the TCU's programming interface. 315 - description: interface clock required to access smmu's registers 316 through the TCU's programming interface. 317 - description: bus clock required for the smmu ptw 318 319 - if: 320 properties: 321 compatible: 322 contains: 323 enum: 324 - qcom,sm6375-smmu-v2 325 then: 326 anyOf: 327 - properties: 328 clock-names: 329 items: 330 - const: bus 331 clocks: 332 items: 333 - description: bus clock required for downstream bus access and for 334 the smmu ptw 335 - properties: 336 clock-names: 337 items: 338 - const: iface 339 - const: mem 340 - const: mem_iface 341 clocks: 342 items: 343 - description: interface clock required to access smmu's registers 344 through the TCU's programming interface. 345 - description: bus clock required for memory access 346 - description: bus clock required for GPU memory access 347 - properties: 348 clock-names: 349 items: 350 - const: iface-mm 351 - const: iface-smmu 352 - const: bus-mm 353 - const: bus-smmu 354 clocks: 355 items: 356 - description: interface clock required to access mnoc's registers 357 through the TCU's programming interface. 358 - description: interface clock required to access smmu's registers 359 through the TCU's programming interface. 360 - description: bus clock required for downstream bus access 361 - description: bus clock required for the smmu ptw 362 363 - if: 364 properties: 365 compatible: 366 contains: 367 enum: 368 - qcom,msm8996-smmu-v2 369 - qcom,sc7180-smmu-v2 370 - qcom,sdm845-smmu-v2 371 then: 372 properties: 373 clock-names: 374 items: 375 - const: bus 376 - const: iface 377 378 clocks: 379 items: 380 - description: bus clock required for downstream bus access and for 381 the smmu ptw 382 - description: interface clock required to access smmu's registers 383 through the TCU's programming interface. 384 385 - if: 386 properties: 387 compatible: 388 contains: 389 enum: 390 - qcom,sa8775p-smmu-500 391 - qcom,sc7280-smmu-500 392 - qcom,sc8280xp-smmu-500 393 then: 394 properties: 395 clock-names: 396 items: 397 - const: gcc_gpu_memnoc_gfx_clk 398 - const: gcc_gpu_snoc_dvm_gfx_clk 399 - const: gpu_cc_ahb_clk 400 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 401 - const: gpu_cc_cx_gmu_clk 402 - const: gpu_cc_hub_cx_int_clk 403 - const: gpu_cc_hub_aon_clk 404 405 clocks: 406 items: 407 - description: GPU memnoc_gfx clock 408 - description: GPU snoc_dvm_gfx clock 409 - description: GPU ahb clock 410 - description: GPU hlos1_vote_GPU smmu clock 411 - description: GPU cx_gmu clock 412 - description: GPU hub_cx_int clock 413 - description: GPU hub_aon clock 414 415 - if: 416 properties: 417 compatible: 418 contains: 419 enum: 420 - qcom,sc8180x-smmu-500 421 - qcom,sm6350-smmu-v2 422 - qcom,sm7150-smmu-v2 423 - qcom,sm8150-smmu-500 424 - qcom,sm8250-smmu-500 425 then: 426 properties: 427 clock-names: 428 items: 429 - const: ahb 430 - const: bus 431 - const: iface 432 433 clocks: 434 items: 435 - description: bus clock required for AHB bus access 436 - description: bus clock required for downstream bus access and for 437 the smmu ptw 438 - description: interface clock required to access smmu's registers 439 through the TCU's programming interface. 440 441 - if: 442 properties: 443 compatible: 444 items: 445 - enum: 446 - qcom,sm8350-smmu-500 447 - const: qcom,adreno-smmu 448 - const: qcom,smmu-500 449 - const: arm,mmu-500 450 then: 451 properties: 452 clock-names: 453 items: 454 - const: bus 455 - const: iface 456 - const: ahb 457 - const: hlos1_vote_gpu_smmu 458 - const: cx_gmu 459 - const: hub_cx_int 460 - const: hub_aon 461 clocks: 462 minItems: 7 463 maxItems: 7 464 465 - if: 466 properties: 467 compatible: 468 items: 469 - enum: 470 - qcom,qcm2290-smmu-500 471 - qcom,sm6115-smmu-500 472 - qcom,sm6125-smmu-500 473 - const: qcom,adreno-smmu 474 - const: qcom,smmu-500 475 - const: arm,mmu-500 476 then: 477 properties: 478 clock-names: 479 items: 480 - const: mem 481 - const: hlos 482 - const: iface 483 484 clocks: 485 items: 486 - description: GPU memory bus clock 487 - description: Voter clock required for HLOS SMMU access 488 - description: Interface clock required for register access 489 490 - if: 491 properties: 492 compatible: 493 items: 494 - const: qcom,sm8450-smmu-500 495 - const: qcom,adreno-smmu 496 - const: qcom,smmu-500 497 - const: arm,mmu-500 498 499 then: 500 properties: 501 clock-names: 502 items: 503 - const: gmu 504 - const: hub 505 - const: hlos 506 - const: bus 507 - const: iface 508 - const: ahb 509 510 clocks: 511 items: 512 - description: GMU clock 513 - description: GPU HUB clock 514 - description: HLOS vote clock 515 - description: GPU memory bus clock 516 - description: GPU SNoC bus clock 517 - description: GPU AHB clock 518 519 - if: 520 properties: 521 compatible: 522 items: 523 - enum: 524 - qcom,sm8550-smmu-500 525 - qcom,sm8650-smmu-500 526 - qcom,x1e80100-smmu-500 527 - const: qcom,adreno-smmu 528 - const: qcom,smmu-500 529 - const: arm,mmu-500 530 then: 531 properties: 532 clock-names: 533 items: 534 - const: hlos 535 - const: bus 536 - const: iface 537 - const: ahb 538 539 clocks: 540 items: 541 - description: HLOS vote clock 542 - description: GPU memory bus clock 543 - description: GPU SNoC bus clock 544 - description: GPU AHB clock 545 546 # Disallow clocks for all other platforms with specific compatibles 547 - if: 548 properties: 549 compatible: 550 contains: 551 enum: 552 - cavium,smmu-v2 553 - marvell,ap806-smmu-500 554 - nvidia,smmu-500 555 - qcom,qdu1000-smmu-500 556 - qcom,sc7180-smmu-500 557 - qcom,sdm670-smmu-500 558 - qcom,sdm845-smmu-500 559 - qcom,sdx55-smmu-500 560 - qcom,sdx65-smmu-500 561 - qcom,sm6350-smmu-500 562 - qcom,sm6375-smmu-500 563 then: 564 properties: 565 clock-names: false 566 clocks: false 567 568 - if: 569 properties: 570 compatible: 571 contains: 572 const: qcom,sm6375-smmu-500 573 then: 574 properties: 575 power-domains: 576 items: 577 - description: SNoC MMU TBU RT GDSC 578 - description: SNoC MMU TBU NRT GDSC 579 - description: SNoC TURING MMU TBU0 GDSC 580 581 required: 582 - power-domains 583 else: 584 properties: 585 power-domains: 586 maxItems: 1 587 588examples: 589 - |+ 590 /* SMMU with stream matching or stream indexing */ 591 smmu1: iommu@ba5e0000 { 592 compatible = "arm,smmu-v1"; 593 reg = <0xba5e0000 0x10000>; 594 #global-interrupts = <2>; 595 interrupts = <0 32 4>, 596 <0 33 4>, 597 <0 34 4>, /* This is the first context interrupt */ 598 <0 35 4>, 599 <0 36 4>, 600 <0 37 4>; 601 #iommu-cells = <1>; 602 }; 603 604 /* device with two stream IDs, 0 and 7 */ 605 master1 { 606 iommus = <&smmu1 0>, 607 <&smmu1 7>; 608 }; 609 610 611 /* SMMU with stream matching */ 612 smmu2: iommu@ba5f0000 { 613 compatible = "arm,smmu-v1"; 614 reg = <0xba5f0000 0x10000>; 615 #global-interrupts = <2>; 616 interrupts = <0 38 4>, 617 <0 39 4>, 618 <0 40 4>, /* This is the first context interrupt */ 619 <0 41 4>, 620 <0 42 4>, 621 <0 43 4>; 622 #iommu-cells = <2>; 623 }; 624 625 /* device with stream IDs 0 and 7 */ 626 master2 { 627 iommus = <&smmu2 0 0>, 628 <&smmu2 7 0>; 629 }; 630 631 /* device with stream IDs 1, 17, 33 and 49 */ 632 master3 { 633 iommus = <&smmu2 1 0x30>; 634 }; 635 636 637 /* ARM MMU-500 with 10-bit stream ID input configuration */ 638 smmu3: iommu@ba600000 { 639 compatible = "arm,mmu-500", "arm,smmu-v2"; 640 reg = <0xba600000 0x10000>; 641 #global-interrupts = <2>; 642 interrupts = <0 44 4>, 643 <0 45 4>, 644 <0 46 4>, /* This is the first context interrupt */ 645 <0 47 4>, 646 <0 48 4>, 647 <0 49 4>; 648 #iommu-cells = <1>; 649 /* always ignore appended 5-bit TBU number */ 650 stream-match-mask = <0x7c00>; 651 }; 652 653 bus { 654 /* bus whose child devices emit one unique 10-bit stream 655 ID each, but may master through multiple SMMU TBUs */ 656 iommu-map = <0 &smmu3 0 0x400>; 657 658 659 }; 660 661 - |+ 662 /* Qcom's arm,smmu-v2 implementation */ 663 #include <dt-bindings/interrupt-controller/arm-gic.h> 664 #include <dt-bindings/interrupt-controller/irq.h> 665 smmu4: iommu@d00000 { 666 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 667 reg = <0xd00000 0x10000>; 668 669 #global-interrupts = <1>; 670 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 673 #iommu-cells = <1>; 674 power-domains = <&mmcc 0>; 675 676 clocks = <&mmcc 123>, 677 <&mmcc 124>; 678 clock-names = "bus", "iface"; 679 }; 680