1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/pm.h> 21 #include <linux/i2c.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/acpi.h> 25 #include <linux/of.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/jack.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <dt-bindings/sound/tlv320aic31xx.h> 35 36 #include "tlv320aic31xx.h" 37 38 static int aic31xx_set_jack(struct snd_soc_component *component, 39 struct snd_soc_jack *jack, void *data); 40 41 static const struct reg_default aic31xx_reg_defaults[] = { 42 { AIC31XX_CLKMUX, 0x00 }, 43 { AIC31XX_PLLPR, 0x11 }, 44 { AIC31XX_PLLJ, 0x04 }, 45 { AIC31XX_PLLDMSB, 0x00 }, 46 { AIC31XX_PLLDLSB, 0x00 }, 47 { AIC31XX_NDAC, 0x01 }, 48 { AIC31XX_MDAC, 0x01 }, 49 { AIC31XX_DOSRMSB, 0x00 }, 50 { AIC31XX_DOSRLSB, 0x80 }, 51 { AIC31XX_NADC, 0x01 }, 52 { AIC31XX_MADC, 0x01 }, 53 { AIC31XX_AOSR, 0x80 }, 54 { AIC31XX_IFACE1, 0x00 }, 55 { AIC31XX_DATA_OFFSET, 0x00 }, 56 { AIC31XX_IFACE2, 0x00 }, 57 { AIC31XX_BCLKN, 0x01 }, 58 { AIC31XX_DACSETUP, 0x14 }, 59 { AIC31XX_DACMUTE, 0x0c }, 60 { AIC31XX_LDACVOL, 0x00 }, 61 { AIC31XX_RDACVOL, 0x00 }, 62 { AIC31XX_ADCSETUP, 0x00 }, 63 { AIC31XX_ADCFGA, 0x80 }, 64 { AIC31XX_ADCVOL, 0x00 }, 65 { AIC31XX_HPDRIVER, 0x04 }, 66 { AIC31XX_SPKAMP, 0x06 }, 67 { AIC31XX_DACMIXERROUTE, 0x00 }, 68 { AIC31XX_LANALOGHPL, 0x7f }, 69 { AIC31XX_RANALOGHPR, 0x7f }, 70 { AIC31XX_LANALOGSPL, 0x7f }, 71 { AIC31XX_RANALOGSPR, 0x7f }, 72 { AIC31XX_HPLGAIN, 0x02 }, 73 { AIC31XX_HPRGAIN, 0x02 }, 74 { AIC31XX_SPLGAIN, 0x00 }, 75 { AIC31XX_SPRGAIN, 0x00 }, 76 { AIC31XX_MICBIAS, 0x00 }, 77 { AIC31XX_MICPGA, 0x80 }, 78 { AIC31XX_MICPGAPI, 0x00 }, 79 { AIC31XX_MICPGAMI, 0x00 }, 80 }; 81 82 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 83 { 84 switch (reg) { 85 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 86 case AIC31XX_RESET: /* always clears after write */ 87 case AIC31XX_OT_FLAG: 88 case AIC31XX_ADCFLAG: 89 case AIC31XX_DACFLAG1: 90 case AIC31XX_DACFLAG2: 91 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 92 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 93 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 94 case AIC31XX_INTRDACFLAG2: 95 case AIC31XX_INTRADCFLAG2: 96 case AIC31XX_HSDETECT: 97 return true; 98 } 99 return false; 100 } 101 102 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 103 { 104 switch (reg) { 105 case AIC31XX_OT_FLAG: 106 case AIC31XX_ADCFLAG: 107 case AIC31XX_DACFLAG1: 108 case AIC31XX_DACFLAG2: 109 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 110 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 111 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 112 case AIC31XX_INTRDACFLAG2: 113 case AIC31XX_INTRADCFLAG2: 114 return false; 115 } 116 return true; 117 } 118 119 static const struct regmap_range_cfg aic31xx_ranges[] = { 120 { 121 .range_min = 0, 122 .range_max = 12 * 128, 123 .selector_reg = AIC31XX_PAGECTL, 124 .selector_mask = 0xff, 125 .selector_shift = 0, 126 .window_start = 0, 127 .window_len = 128, 128 }, 129 }; 130 131 static const struct regmap_config aic31xx_i2c_regmap = { 132 .reg_bits = 8, 133 .val_bits = 8, 134 .writeable_reg = aic31xx_writeable, 135 .volatile_reg = aic31xx_volatile, 136 .reg_defaults = aic31xx_reg_defaults, 137 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 138 .cache_type = REGCACHE_RBTREE, 139 .ranges = aic31xx_ranges, 140 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 141 .max_register = 12 * 128, 142 }; 143 144 static const char * const aic31xx_supply_names[] = { 145 "HPVDD", 146 "SPRVDD", 147 "SPLVDD", 148 "AVDD", 149 "IOVDD", 150 "DVDD", 151 }; 152 153 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 154 155 struct aic31xx_disable_nb { 156 struct notifier_block nb; 157 struct aic31xx_priv *aic31xx; 158 }; 159 160 struct aic31xx_priv { 161 struct snd_soc_component *component; 162 u8 i2c_regs_status; 163 struct device *dev; 164 struct regmap *regmap; 165 enum aic31xx_type codec_type; 166 struct gpio_desc *gpio_reset; 167 int micbias_vg; 168 struct aic31xx_pdata pdata; 169 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 170 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 171 struct snd_soc_jack *jack; 172 u32 sysclk_id; 173 unsigned int sysclk; 174 u8 p_div; 175 int rate_div_line; 176 bool master_dapm_route_applied; 177 int irq; 178 u8 ocmv; /* output common-mode voltage */ 179 }; 180 181 struct aic31xx_rate_divs { 182 u32 mclk_p; 183 u32 rate; 184 u8 pll_r; 185 u8 pll_j; 186 u16 pll_d; 187 u16 dosr; 188 u8 ndac; 189 u8 mdac; 190 u8 aosr; 191 u8 nadc; 192 u8 madc; 193 }; 194 195 /* ADC dividers can be disabled by configuring them to 0 */ 196 static const struct aic31xx_rate_divs aic31xx_divs[] = { 197 /* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */ 198 /* 8k rate */ 199 { 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2}, 200 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2}, 201 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3}, 202 {12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2}, 203 /* 11.025k rate */ 204 { 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3}, 205 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2}, 206 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3}, 207 {12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2}, 208 /* 16k rate */ 209 { 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3}, 210 { 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3}, 211 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2}, 212 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3}, 213 {12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2}, 214 /* 22.05k rate */ 215 { 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3}, 216 { 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3}, 217 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2}, 218 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3}, 219 {12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2}, 220 /* 32k rate */ 221 { 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2}, 222 { 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2}, 223 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2}, 224 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3}, 225 {12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2}, 226 /* 44.1k rate */ 227 { 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2}, 228 { 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2}, 229 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2}, 230 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3}, 231 {12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2}, 232 /* 48k rate */ 233 { 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2}, 234 { 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2}, 235 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2}, 236 {12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4}, 237 {12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2}, 238 /* 88.2k rate */ 239 { 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2}, 240 { 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2}, 241 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2}, 242 {12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3}, 243 {12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2}, 244 /* 96k rate */ 245 { 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2}, 246 { 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2}, 247 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2}, 248 {12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4}, 249 {12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2}, 250 /* 176.4k rate */ 251 { 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2}, 252 {11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2}, 253 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2}, 254 {12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3}, 255 {12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2}, 256 /* 192k rate */ 257 { 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2}, 258 {12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2}, 259 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2}, 260 {12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4}, 261 {12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2}, 262 }; 263 264 static const char * const ldac_in_text[] = { 265 "Off", "Left Data", "Right Data", "Mono" 266 }; 267 268 static const char * const rdac_in_text[] = { 269 "Off", "Right Data", "Left Data", "Mono" 270 }; 271 272 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 273 274 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 275 276 static const char * const mic_select_text[] = { 277 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 278 }; 279 280 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 281 mic_select_text); 282 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 283 mic_select_text); 284 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 285 mic_select_text); 286 287 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 288 mic_select_text); 289 290 static const char * const hp_poweron_time_text[] = { 291 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms", 292 "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" }; 293 294 static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3, 295 hp_poweron_time_text); 296 297 static const char * const hp_rampup_step_text[] = { 298 "0ms", "0.98ms", "1.95ms", "3.9ms" }; 299 300 static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1, 301 hp_rampup_step_text); 302 303 static const char * const vol_soft_step_mode_text[] = { 304 "fast", "slow", "disabled" }; 305 306 static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0, 307 vol_soft_step_mode_text); 308 309 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 310 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 311 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 312 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 313 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 314 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 315 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 316 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 317 318 /* 319 * controls to be exported to the user space 320 */ 321 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 322 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 323 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 324 325 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 326 AIC31XX_HPRGAIN, 2, 1, 0), 327 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 328 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 329 330 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 331 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 332 333 /* HP de-pop control: apply power not immediately but via ramp 334 * function with these psarameters. Note that power up sequence 335 * has to wait for this to complete; this is implemented by 336 * polling HP driver status in aic31xx_dapm_power_event() 337 */ 338 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum), 339 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum), 340 341 SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum), 342 }; 343 344 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 345 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 346 adc_fgain_tlv), 347 348 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 349 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 350 0, -24, 40, 6, 0, adc_cgain_tlv), 351 352 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 353 119, 0, mic_pga_tlv), 354 }; 355 356 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 357 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 358 AIC31XX_SPRGAIN, 2, 1, 0), 359 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 360 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 361 362 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 363 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 364 }; 365 366 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 367 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 368 2, 1, 0), 369 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 370 3, 3, 0, class_D_drv_tlv), 371 372 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 373 0, 0x7F, 1, sp_vol_tlv), 374 }; 375 376 static const struct snd_kcontrol_new ldac_in_control = 377 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 378 379 static const struct snd_kcontrol_new rdac_in_control = 380 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 381 382 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 383 unsigned int mask, unsigned int wbits, int sleep, 384 int count) 385 { 386 unsigned int bits; 387 int counter = count; 388 int ret = regmap_read(aic31xx->regmap, reg, &bits); 389 390 while ((bits & mask) != wbits && counter && !ret) { 391 usleep_range(sleep, sleep * 2); 392 ret = regmap_read(aic31xx->regmap, reg, &bits); 393 counter--; 394 } 395 if ((bits & mask) != wbits) { 396 dev_err(aic31xx->dev, 397 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 398 __func__, reg, bits, wbits, ret, mask, 399 (count - counter) * sleep); 400 ret = -1; 401 } 402 return ret; 403 } 404 405 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 406 407 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 408 struct snd_kcontrol *kcontrol, int event) 409 { 410 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 411 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 412 unsigned int reg = AIC31XX_DACFLAG1; 413 unsigned int mask; 414 unsigned int timeout = 500 * USEC_PER_MSEC; 415 416 switch (WIDGET_BIT(w->reg, w->shift)) { 417 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 418 mask = AIC31XX_LDACPWRSTATUS_MASK; 419 break; 420 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 421 mask = AIC31XX_RDACPWRSTATUS_MASK; 422 break; 423 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 424 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 425 if (event == SND_SOC_DAPM_POST_PMU) 426 timeout = 7 * USEC_PER_SEC; 427 break; 428 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 429 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 430 if (event == SND_SOC_DAPM_POST_PMU) 431 timeout = 7 * USEC_PER_SEC; 432 break; 433 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 434 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 435 break; 436 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 437 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 438 break; 439 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 440 mask = AIC31XX_ADCPWRSTATUS_MASK; 441 reg = AIC31XX_ADCFLAG; 442 break; 443 default: 444 dev_err(component->dev, "Unknown widget '%s' calling %s\n", 445 w->name, __func__); 446 return -EINVAL; 447 } 448 449 switch (event) { 450 case SND_SOC_DAPM_POST_PMU: 451 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 452 5000, timeout / 5000); 453 case SND_SOC_DAPM_POST_PMD: 454 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 455 5000, timeout / 5000); 456 default: 457 dev_dbg(component->dev, 458 "Unhandled dapm widget event %d from %s\n", 459 event, w->name); 460 } 461 return 0; 462 } 463 464 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 465 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 466 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 467 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 468 }; 469 470 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 471 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 472 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 473 }; 474 475 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 476 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 477 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 478 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 479 }; 480 481 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 482 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 483 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 484 }; 485 486 static const struct snd_kcontrol_new p_term_mic1lp = 487 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 488 489 static const struct snd_kcontrol_new p_term_mic1rp = 490 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 491 492 static const struct snd_kcontrol_new p_term_mic1lm = 493 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 494 495 static const struct snd_kcontrol_new m_term_mic1lm = 496 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 497 498 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 499 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 500 501 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 502 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 503 504 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 505 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 506 507 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 508 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 509 510 static int mic_bias_event(struct snd_soc_dapm_widget *w, 511 struct snd_kcontrol *kcontrol, int event) 512 { 513 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 514 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 515 516 switch (event) { 517 case SND_SOC_DAPM_POST_PMU: 518 /* change mic bias voltage to user defined */ 519 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 520 AIC31XX_MICBIAS_MASK, 521 aic31xx->micbias_vg << 522 AIC31XX_MICBIAS_SHIFT); 523 dev_dbg(component->dev, "%s: turned on\n", __func__); 524 break; 525 case SND_SOC_DAPM_PRE_PMD: 526 /* turn mic bias off */ 527 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 528 AIC31XX_MICBIAS_MASK, 0); 529 dev_dbg(component->dev, "%s: turned off\n", __func__); 530 break; 531 } 532 return 0; 533 } 534 535 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 536 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 537 538 SND_SOC_DAPM_MUX("DAC Left Input", 539 SND_SOC_NOPM, 0, 0, &ldac_in_control), 540 SND_SOC_DAPM_MUX("DAC Right Input", 541 SND_SOC_NOPM, 0, 0, &rdac_in_control), 542 /* DACs */ 543 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 544 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 545 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 546 547 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 548 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 549 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 550 551 /* HP */ 552 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 553 &aic31xx_dapm_hpl_switch), 554 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 555 &aic31xx_dapm_hpr_switch), 556 557 /* Output drivers */ 558 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 559 NULL, 0, aic31xx_dapm_power_event, 560 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 561 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 562 NULL, 0, aic31xx_dapm_power_event, 563 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 564 565 /* Mic Bias */ 566 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 567 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 568 569 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */ 570 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0, 571 NULL, 0), 572 573 /* Outputs */ 574 SND_SOC_DAPM_OUTPUT("HPL"), 575 SND_SOC_DAPM_OUTPUT("HPR"), 576 }; 577 578 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 579 /* Inputs */ 580 SND_SOC_DAPM_INPUT("AIN1"), 581 SND_SOC_DAPM_INPUT("AIN2"), 582 583 /* Output Mixers */ 584 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 585 dac31xx_left_output_switches, 586 ARRAY_SIZE(dac31xx_left_output_switches)), 587 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 588 dac31xx_right_output_switches, 589 ARRAY_SIZE(dac31xx_right_output_switches)), 590 }; 591 592 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 593 /* Inputs */ 594 SND_SOC_DAPM_INPUT("MIC1LP"), 595 SND_SOC_DAPM_INPUT("MIC1RP"), 596 SND_SOC_DAPM_INPUT("MIC1LM"), 597 598 /* Input Selection to MIC_PGA */ 599 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 600 &p_term_mic1lp), 601 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 602 &p_term_mic1rp), 603 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 604 &p_term_mic1lm), 605 606 /* ADC */ 607 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 608 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 609 SND_SOC_DAPM_POST_PMD), 610 611 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 612 &m_term_mic1lm), 613 614 /* Enabling & Disabling MIC Gain Ctl */ 615 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 616 7, 1, NULL, 0), 617 618 /* Output Mixers */ 619 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 620 aic31xx_left_output_switches, 621 ARRAY_SIZE(aic31xx_left_output_switches)), 622 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 623 aic31xx_right_output_switches, 624 ARRAY_SIZE(aic31xx_right_output_switches)), 625 626 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 627 }; 628 629 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 630 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 631 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 632 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 633 SND_SOC_DAPM_POST_PMD), 634 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 635 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 636 SND_SOC_DAPM_POST_PMD), 637 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 638 &aic31xx_dapm_spl_switch), 639 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 640 &aic31xx_dapm_spr_switch), 641 SND_SOC_DAPM_OUTPUT("SPL"), 642 SND_SOC_DAPM_OUTPUT("SPR"), 643 }; 644 645 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 646 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 647 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 648 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 649 SND_SOC_DAPM_POST_PMD), 650 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 651 &aic31xx_dapm_spl_switch), 652 SND_SOC_DAPM_OUTPUT("SPK"), 653 }; 654 655 static const struct snd_soc_dapm_route 656 common31xx_audio_map[] = { 657 /* DAC Input Routing */ 658 {"DAC Left Input", "Left Data", "AIF IN"}, 659 {"DAC Left Input", "Right Data", "AIF IN"}, 660 {"DAC Left Input", "Mono", "AIF IN"}, 661 {"DAC Right Input", "Left Data", "AIF IN"}, 662 {"DAC Right Input", "Right Data", "AIF IN"}, 663 {"DAC Right Input", "Mono", "AIF IN"}, 664 {"DAC Left", NULL, "DAC Left Input"}, 665 {"DAC Right", NULL, "DAC Right Input"}, 666 667 /* HPL path */ 668 {"HP Left", "Switch", "Output Left"}, 669 {"HPL Driver", NULL, "HP Left"}, 670 {"HPL", NULL, "HPL Driver"}, 671 672 /* HPR path */ 673 {"HP Right", "Switch", "Output Right"}, 674 {"HPR Driver", NULL, "HP Right"}, 675 {"HPR", NULL, "HPR Driver"}, 676 }; 677 678 static const struct snd_soc_dapm_route 679 dac31xx_audio_map[] = { 680 /* Left Output */ 681 {"Output Left", "From Left DAC", "DAC Left"}, 682 {"Output Left", "From AIN1", "AIN1"}, 683 {"Output Left", "From AIN2", "AIN2"}, 684 685 /* Right Output */ 686 {"Output Right", "From Right DAC", "DAC Right"}, 687 {"Output Right", "From AIN2", "AIN2"}, 688 }; 689 690 static const struct snd_soc_dapm_route 691 aic31xx_audio_map[] = { 692 /* Mic input */ 693 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 694 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 695 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 696 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 697 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 698 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 699 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 700 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 701 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 702 703 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 704 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 705 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 706 707 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 708 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 709 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 710 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 711 712 {"ADC", NULL, "MIC_GAIN_CTL"}, 713 714 {"AIF OUT", NULL, "ADC"}, 715 716 /* Left Output */ 717 {"Output Left", "From Left DAC", "DAC Left"}, 718 {"Output Left", "From MIC1LP", "MIC1LP"}, 719 {"Output Left", "From MIC1RP", "MIC1RP"}, 720 721 /* Right Output */ 722 {"Output Right", "From Right DAC", "DAC Right"}, 723 {"Output Right", "From MIC1RP", "MIC1RP"}, 724 }; 725 726 static const struct snd_soc_dapm_route 727 aic311x_audio_map[] = { 728 /* SP L path */ 729 {"Speaker Left", "Switch", "Output Left"}, 730 {"SPL ClassD", NULL, "Speaker Left"}, 731 {"SPL", NULL, "SPL ClassD"}, 732 733 /* SP R path */ 734 {"Speaker Right", "Switch", "Output Right"}, 735 {"SPR ClassD", NULL, "Speaker Right"}, 736 {"SPR", NULL, "SPR ClassD"}, 737 }; 738 739 static const struct snd_soc_dapm_route 740 aic310x_audio_map[] = { 741 /* SP L path */ 742 {"Speaker", "Switch", "Output Left"}, 743 {"SPK ClassD", NULL, "Speaker"}, 744 {"SPK", NULL, "SPK ClassD"}, 745 }; 746 747 /* 748 * Always connected DAPM routes for codec clock master modes. 749 * If the codec is the master on the I2S bus, we need to power up components 750 * to have valid DAC_CLK. 751 * 752 * In order to have the I2S clocks on the bus either the DACs/ADC need to be 753 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set. 754 * 755 * Otherwise the codec will not generate clocks on the bus. 756 */ 757 static const struct snd_soc_dapm_route 758 common31xx_cm_audio_map[] = { 759 {"HPL", NULL, "AIF IN"}, 760 {"HPR", NULL, "AIF IN"}, 761 762 {"AIF IN", NULL, "Activate I2S clocks"}, 763 }; 764 765 static const struct snd_soc_dapm_route 766 aic31xx_cm_audio_map[] = { 767 {"AIF OUT", NULL, "MIC1LP"}, 768 {"AIF OUT", NULL, "MIC1RP"}, 769 {"AIF OUT", NULL, "MIC1LM"}, 770 771 {"AIF OUT", NULL, "Activate I2S clocks"}, 772 }; 773 774 static int aic31xx_add_controls(struct snd_soc_component *component) 775 { 776 int ret = 0; 777 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 778 779 if (!(aic31xx->codec_type & DAC31XX_BIT)) 780 ret = snd_soc_add_component_controls( 781 component, aic31xx_snd_controls, 782 ARRAY_SIZE(aic31xx_snd_controls)); 783 if (ret) 784 return ret; 785 786 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 787 ret = snd_soc_add_component_controls( 788 component, aic311x_snd_controls, 789 ARRAY_SIZE(aic311x_snd_controls)); 790 else 791 ret = snd_soc_add_component_controls( 792 component, aic310x_snd_controls, 793 ARRAY_SIZE(aic310x_snd_controls)); 794 795 return ret; 796 } 797 798 static int aic31xx_add_widgets(struct snd_soc_component *component) 799 { 800 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 801 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 802 int ret = 0; 803 804 if (aic31xx->codec_type & DAC31XX_BIT) { 805 ret = snd_soc_dapm_new_controls( 806 dapm, dac31xx_dapm_widgets, 807 ARRAY_SIZE(dac31xx_dapm_widgets)); 808 if (ret) 809 return ret; 810 811 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 812 ARRAY_SIZE(dac31xx_audio_map)); 813 if (ret) 814 return ret; 815 } else { 816 ret = snd_soc_dapm_new_controls( 817 dapm, aic31xx_dapm_widgets, 818 ARRAY_SIZE(aic31xx_dapm_widgets)); 819 if (ret) 820 return ret; 821 822 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 823 ARRAY_SIZE(aic31xx_audio_map)); 824 if (ret) 825 return ret; 826 } 827 828 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 829 ret = snd_soc_dapm_new_controls( 830 dapm, aic311x_dapm_widgets, 831 ARRAY_SIZE(aic311x_dapm_widgets)); 832 if (ret) 833 return ret; 834 835 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 836 ARRAY_SIZE(aic311x_audio_map)); 837 if (ret) 838 return ret; 839 } else { 840 ret = snd_soc_dapm_new_controls( 841 dapm, aic310x_dapm_widgets, 842 ARRAY_SIZE(aic310x_dapm_widgets)); 843 if (ret) 844 return ret; 845 846 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 847 ARRAY_SIZE(aic310x_audio_map)); 848 if (ret) 849 return ret; 850 } 851 852 return 0; 853 } 854 855 static int aic31xx_setup_pll(struct snd_soc_component *component, 856 struct snd_pcm_hw_params *params) 857 { 858 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 859 int bclk_score = snd_soc_params_to_frame_size(params); 860 int mclk_p; 861 int bclk_n = 0; 862 int match = -1; 863 int i; 864 865 if (!aic31xx->sysclk || !aic31xx->p_div) { 866 dev_err(component->dev, "Master clock not supplied\n"); 867 return -EINVAL; 868 } 869 mclk_p = aic31xx->sysclk / aic31xx->p_div; 870 871 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 872 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, 873 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 874 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 875 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 876 877 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 878 if (aic31xx_divs[i].rate == params_rate(params) && 879 aic31xx_divs[i].mclk_p == mclk_p) { 880 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 881 snd_soc_params_to_frame_size(params); 882 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 883 snd_soc_params_to_frame_size(params); 884 if (s < bclk_score && bn > 0) { 885 match = i; 886 bclk_n = bn; 887 bclk_score = s; 888 } 889 } 890 } 891 892 if (match == -1) { 893 dev_err(component->dev, 894 "%s: Sample rate (%u) and format not supported\n", 895 __func__, params_rate(params)); 896 /* See bellow for details how fix this. */ 897 return -EINVAL; 898 } 899 if (bclk_score != 0) { 900 dev_warn(component->dev, "Can not produce exact bitclock"); 901 /* This is fine if using dsp format, but if using i2s 902 there may be trouble. To fix the issue edit the 903 aic31xx_divs table for your mclk and sample 904 rate. Details can be found from: 905 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 906 Section: 5.6 CLOCK Generation and PLL 907 */ 908 } 909 i = match; 910 911 /* PLL configuration */ 912 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 913 (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r); 914 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 915 916 snd_soc_component_write(component, AIC31XX_PLLDMSB, 917 aic31xx_divs[i].pll_d >> 8); 918 snd_soc_component_write(component, AIC31XX_PLLDLSB, 919 aic31xx_divs[i].pll_d & 0xff); 920 921 /* DAC dividers configuration */ 922 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK, 923 aic31xx_divs[i].ndac); 924 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK, 925 aic31xx_divs[i].mdac); 926 927 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 928 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 929 930 /* ADC dividers configuration. Write reset value 1 if not used. */ 931 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK, 932 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 933 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK, 934 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 935 936 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr); 937 938 /* Bit clock divider configuration. */ 939 snd_soc_component_update_bits(component, AIC31XX_BCLKN, 940 AIC31XX_PLL_MASK, bclk_n); 941 942 aic31xx->rate_div_line = i; 943 944 dev_dbg(component->dev, 945 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 946 aic31xx_divs[i].pll_j, 947 aic31xx_divs[i].pll_d, 948 aic31xx->p_div, 949 aic31xx_divs[i].dosr, 950 aic31xx_divs[i].ndac, 951 aic31xx_divs[i].mdac, 952 aic31xx_divs[i].aosr, 953 aic31xx_divs[i].nadc, 954 aic31xx_divs[i].madc, 955 bclk_n 956 ); 957 958 return 0; 959 } 960 961 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 962 struct snd_pcm_hw_params *params, 963 struct snd_soc_dai *dai) 964 { 965 struct snd_soc_component *component = dai->component; 966 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 967 u8 data = 0; 968 969 dev_dbg(component->dev, "## %s: width %d rate %d\n", 970 __func__, params_width(params), 971 params_rate(params)); 972 973 switch (params_width(params)) { 974 case 16: 975 break; 976 case 20: 977 data = (AIC31XX_WORD_LEN_20BITS << 978 AIC31XX_IFACE1_DATALEN_SHIFT); 979 break; 980 case 24: 981 data = (AIC31XX_WORD_LEN_24BITS << 982 AIC31XX_IFACE1_DATALEN_SHIFT); 983 break; 984 case 32: 985 data = (AIC31XX_WORD_LEN_32BITS << 986 AIC31XX_IFACE1_DATALEN_SHIFT); 987 break; 988 default: 989 dev_err(component->dev, "%s: Unsupported width %d\n", 990 __func__, params_width(params)); 991 return -EINVAL; 992 } 993 994 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 995 AIC31XX_IFACE1_DATALEN_MASK, 996 data); 997 998 /* 999 * If BCLK is used as PLL input, the sysclk is determined by the hw 1000 * params. So it must be updated here to match the input frequency. 1001 */ 1002 if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) { 1003 aic31xx->sysclk = params_rate(params) * params_width(params) * 1004 params_channels(params); 1005 aic31xx->p_div = 1; 1006 } 1007 1008 return aic31xx_setup_pll(component, params); 1009 } 1010 1011 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute, 1012 int direction) 1013 { 1014 struct snd_soc_component *component = codec_dai->component; 1015 1016 if (mute) { 1017 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 1018 AIC31XX_DACMUTE_MASK, 1019 AIC31XX_DACMUTE_MASK); 1020 } else { 1021 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 1022 AIC31XX_DACMUTE_MASK, 0x0); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int aic31xx_clock_master_routes(struct snd_soc_component *component, 1029 unsigned int fmt) 1030 { 1031 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1032 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1033 int ret; 1034 1035 fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; 1036 if (fmt == SND_SOC_DAIFMT_CBC_CFC && 1037 aic31xx->master_dapm_route_applied) { 1038 /* 1039 * Remove the DAPM route(s) for codec clock master modes, 1040 * if applied 1041 */ 1042 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map, 1043 ARRAY_SIZE(common31xx_cm_audio_map)); 1044 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1045 ret = snd_soc_dapm_del_routes(dapm, 1046 aic31xx_cm_audio_map, 1047 ARRAY_SIZE(aic31xx_cm_audio_map)); 1048 1049 if (ret) 1050 return ret; 1051 1052 aic31xx->master_dapm_route_applied = false; 1053 } else if (fmt != SND_SOC_DAIFMT_CBC_CFC && 1054 !aic31xx->master_dapm_route_applied) { 1055 /* 1056 * Add the needed DAPM route(s) for codec clock master modes, 1057 * if it is not done already 1058 */ 1059 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map, 1060 ARRAY_SIZE(common31xx_cm_audio_map)); 1061 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1062 ret = snd_soc_dapm_add_routes(dapm, 1063 aic31xx_cm_audio_map, 1064 ARRAY_SIZE(aic31xx_cm_audio_map)); 1065 1066 if (ret) 1067 return ret; 1068 1069 aic31xx->master_dapm_route_applied = true; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1076 unsigned int fmt) 1077 { 1078 struct snd_soc_component *component = codec_dai->component; 1079 u8 iface_reg1 = 0; 1080 u8 iface_reg2 = 0; 1081 u8 dsp_a_val = 0; 1082 1083 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 1084 1085 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1086 case SND_SOC_DAIFMT_CBP_CFP: 1087 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 1088 break; 1089 case SND_SOC_DAIFMT_CBC_CFP: 1090 iface_reg1 |= AIC31XX_WCLK_MASTER; 1091 break; 1092 case SND_SOC_DAIFMT_CBP_CFC: 1093 iface_reg1 |= AIC31XX_BCLK_MASTER; 1094 break; 1095 case SND_SOC_DAIFMT_CBC_CFC: 1096 break; 1097 default: 1098 dev_err(component->dev, "Invalid DAI clock provider\n"); 1099 return -EINVAL; 1100 } 1101 1102 /* signal polarity */ 1103 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1104 case SND_SOC_DAIFMT_NB_NF: 1105 break; 1106 case SND_SOC_DAIFMT_IB_NF: 1107 iface_reg2 |= AIC31XX_BCLKINV_MASK; 1108 break; 1109 default: 1110 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 1111 return -EINVAL; 1112 } 1113 1114 /* interface format */ 1115 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1116 case SND_SOC_DAIFMT_I2S: 1117 break; 1118 case SND_SOC_DAIFMT_DSP_A: 1119 dsp_a_val = 0x1; 1120 fallthrough; 1121 case SND_SOC_DAIFMT_DSP_B: 1122 /* 1123 * NOTE: This CODEC samples on the falling edge of BCLK in 1124 * DSP mode, this is inverted compared to what most DAIs 1125 * expect, so we invert for this mode 1126 */ 1127 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 1128 iface_reg1 |= (AIC31XX_DSP_MODE << 1129 AIC31XX_IFACE1_DATATYPE_SHIFT); 1130 break; 1131 case SND_SOC_DAIFMT_RIGHT_J: 1132 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 1133 AIC31XX_IFACE1_DATATYPE_SHIFT); 1134 break; 1135 case SND_SOC_DAIFMT_LEFT_J: 1136 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 1137 AIC31XX_IFACE1_DATATYPE_SHIFT); 1138 break; 1139 default: 1140 dev_err(component->dev, "Invalid DAI interface format\n"); 1141 return -EINVAL; 1142 } 1143 1144 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 1145 AIC31XX_IFACE1_DATATYPE_MASK | 1146 AIC31XX_IFACE1_MASTER_MASK, 1147 iface_reg1); 1148 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET, 1149 AIC31XX_DATA_OFFSET_MASK, 1150 dsp_a_val); 1151 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 1152 AIC31XX_BCLKINV_MASK, 1153 iface_reg2); 1154 1155 return aic31xx_clock_master_routes(component, fmt); 1156 } 1157 1158 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1159 int clk_id, unsigned int freq, int dir) 1160 { 1161 struct snd_soc_component *component = codec_dai->component; 1162 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1163 int i; 1164 1165 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1166 __func__, clk_id, freq, dir); 1167 1168 for (i = 1; i < 8; i++) 1169 if (freq / i <= 20000000) 1170 break; 1171 if (freq/i > 20000000) { 1172 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1173 __func__, freq); 1174 return -EINVAL; 1175 } 1176 aic31xx->p_div = i; 1177 1178 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1179 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1180 break; 1181 if (i == ARRAY_SIZE(aic31xx_divs)) { 1182 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1183 __func__, freq); 1184 return -EINVAL; 1185 } 1186 1187 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1188 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1189 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1190 1191 aic31xx->sysclk_id = clk_id; 1192 aic31xx->sysclk = freq; 1193 1194 return 0; 1195 } 1196 1197 static int aic31xx_regulator_event(struct notifier_block *nb, 1198 unsigned long event, void *data) 1199 { 1200 struct aic31xx_disable_nb *disable_nb = 1201 container_of(nb, struct aic31xx_disable_nb, nb); 1202 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1203 1204 if (event & REGULATOR_EVENT_DISABLE) { 1205 /* 1206 * Put codec to reset and as at least one of the 1207 * supplies was disabled. 1208 */ 1209 if (aic31xx->gpio_reset) 1210 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1); 1211 1212 regcache_mark_dirty(aic31xx->regmap); 1213 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1220 { 1221 int ret = 0; 1222 1223 if (aic31xx->gpio_reset) { 1224 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1); 1225 ndelay(10); /* At least 10ns */ 1226 gpiod_set_value_cansleep(aic31xx->gpio_reset, 0); 1227 } else { 1228 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1229 } 1230 mdelay(1); /* At least 1ms */ 1231 1232 return ret; 1233 } 1234 1235 static void aic31xx_clk_on(struct snd_soc_component *component) 1236 { 1237 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1238 u8 mask = AIC31XX_PM_MASK; 1239 u8 on = AIC31XX_PM_MASK; 1240 1241 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", 1242 aic31xx_divs[aic31xx->rate_div_line].rate); 1243 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); 1244 mdelay(10); 1245 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); 1246 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); 1247 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1248 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); 1249 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1250 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); 1251 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); 1252 } 1253 1254 static void aic31xx_clk_off(struct snd_soc_component *component) 1255 { 1256 u8 mask = AIC31XX_PM_MASK; 1257 u8 off = 0; 1258 1259 dev_dbg(component->dev, "codec clock -> off\n"); 1260 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); 1261 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); 1262 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); 1263 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); 1264 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); 1265 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); 1266 } 1267 1268 static int aic31xx_power_on(struct snd_soc_component *component) 1269 { 1270 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1271 int ret; 1272 1273 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1274 aic31xx->supplies); 1275 if (ret) 1276 return ret; 1277 1278 regcache_cache_only(aic31xx->regmap, false); 1279 1280 /* Reset device registers for a consistent power-on like state */ 1281 ret = aic31xx_reset(aic31xx); 1282 if (ret < 0) 1283 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1284 1285 ret = regcache_sync(aic31xx->regmap); 1286 if (ret) { 1287 dev_err(component->dev, 1288 "Failed to restore cache: %d\n", ret); 1289 regcache_cache_only(aic31xx->regmap, true); 1290 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1291 aic31xx->supplies); 1292 return ret; 1293 } 1294 1295 /* 1296 * The jack detection configuration is in the same register 1297 * that is used to report jack detect status so is volatile 1298 * and not covered by the cache sync, restore it separately. 1299 */ 1300 aic31xx_set_jack(component, aic31xx->jack, NULL); 1301 1302 return 0; 1303 } 1304 1305 static void aic31xx_power_off(struct snd_soc_component *component) 1306 { 1307 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1308 1309 regcache_cache_only(aic31xx->regmap, true); 1310 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1311 aic31xx->supplies); 1312 } 1313 1314 static int aic31xx_set_bias_level(struct snd_soc_component *component, 1315 enum snd_soc_bias_level level) 1316 { 1317 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, 1318 snd_soc_component_get_bias_level(component), level); 1319 1320 switch (level) { 1321 case SND_SOC_BIAS_ON: 1322 break; 1323 case SND_SOC_BIAS_PREPARE: 1324 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1325 aic31xx_clk_on(component); 1326 break; 1327 case SND_SOC_BIAS_STANDBY: 1328 switch (snd_soc_component_get_bias_level(component)) { 1329 case SND_SOC_BIAS_OFF: 1330 aic31xx_power_on(component); 1331 break; 1332 case SND_SOC_BIAS_PREPARE: 1333 aic31xx_clk_off(component); 1334 break; 1335 default: 1336 BUG(); 1337 } 1338 break; 1339 case SND_SOC_BIAS_OFF: 1340 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1341 aic31xx_power_off(component); 1342 break; 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int aic31xx_set_jack(struct snd_soc_component *component, 1349 struct snd_soc_jack *jack, void *data) 1350 { 1351 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1352 1353 aic31xx->jack = jack; 1354 1355 /* Enable/Disable jack detection */ 1356 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT, 1357 jack ? AIC31XX_HSD_ENABLE : 0); 1358 1359 return 0; 1360 } 1361 1362 static int aic31xx_codec_probe(struct snd_soc_component *component) 1363 { 1364 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1365 int i, ret; 1366 1367 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1368 1369 aic31xx->component = component; 1370 1371 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1372 aic31xx->disable_nb[i].nb.notifier_call = 1373 aic31xx_regulator_event; 1374 aic31xx->disable_nb[i].aic31xx = aic31xx; 1375 ret = devm_regulator_register_notifier( 1376 aic31xx->supplies[i].consumer, 1377 &aic31xx->disable_nb[i].nb); 1378 if (ret) { 1379 dev_err(component->dev, 1380 "Failed to request regulator notifier: %d\n", 1381 ret); 1382 return ret; 1383 } 1384 } 1385 1386 regcache_cache_only(aic31xx->regmap, true); 1387 regcache_mark_dirty(aic31xx->regmap); 1388 1389 ret = aic31xx_add_controls(component); 1390 if (ret) 1391 return ret; 1392 1393 ret = aic31xx_add_widgets(component); 1394 if (ret) 1395 return ret; 1396 1397 /* set output common-mode voltage */ 1398 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER, 1399 AIC31XX_HPD_OCMV_MASK, 1400 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT); 1401 1402 return 0; 1403 } 1404 1405 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = { 1406 .probe = aic31xx_codec_probe, 1407 .set_jack = aic31xx_set_jack, 1408 .set_bias_level = aic31xx_set_bias_level, 1409 .controls = common31xx_snd_controls, 1410 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1411 .dapm_widgets = common31xx_dapm_widgets, 1412 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1413 .dapm_routes = common31xx_audio_map, 1414 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1415 .suspend_bias_off = 1, 1416 .idle_bias_on = 1, 1417 .use_pmdown_time = 1, 1418 .endianness = 1, 1419 }; 1420 1421 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1422 .hw_params = aic31xx_hw_params, 1423 .set_sysclk = aic31xx_set_dai_sysclk, 1424 .set_fmt = aic31xx_set_dai_fmt, 1425 .mute_stream = aic31xx_dac_mute, 1426 .no_capture_mute = 1, 1427 }; 1428 1429 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1430 { 1431 .name = "tlv320dac31xx-hifi", 1432 .playback = { 1433 .stream_name = "Playback", 1434 .channels_min = 2, 1435 .channels_max = 2, 1436 .rates = AIC31XX_RATES, 1437 .formats = AIC31XX_FORMATS, 1438 }, 1439 .ops = &aic31xx_dai_ops, 1440 .symmetric_rate = 1, 1441 } 1442 }; 1443 1444 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1445 { 1446 .name = "tlv320aic31xx-hifi", 1447 .playback = { 1448 .stream_name = "Playback", 1449 .channels_min = 2, 1450 .channels_max = 2, 1451 .rates = AIC31XX_RATES, 1452 .formats = AIC31XX_FORMATS, 1453 }, 1454 .capture = { 1455 .stream_name = "Capture", 1456 .channels_min = 2, 1457 .channels_max = 2, 1458 .rates = AIC31XX_RATES, 1459 .formats = AIC31XX_FORMATS, 1460 }, 1461 .ops = &aic31xx_dai_ops, 1462 .symmetric_rate = 1, 1463 } 1464 }; 1465 1466 #if defined(CONFIG_OF) 1467 static const struct of_device_id tlv320aic31xx_of_match[] = { 1468 { .compatible = "ti,tlv320aic310x" }, 1469 { .compatible = "ti,tlv320aic311x" }, 1470 { .compatible = "ti,tlv320aic3100" }, 1471 { .compatible = "ti,tlv320aic3110" }, 1472 { .compatible = "ti,tlv320aic3120" }, 1473 { .compatible = "ti,tlv320aic3111" }, 1474 { .compatible = "ti,tlv320dac3100" }, 1475 { .compatible = "ti,tlv320dac3101" }, 1476 {}, 1477 }; 1478 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1479 #endif /* CONFIG_OF */ 1480 1481 #ifdef CONFIG_ACPI 1482 static const struct acpi_device_id aic31xx_acpi_match[] = { 1483 { "10TI3100", 0 }, 1484 { } 1485 }; 1486 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1487 #endif 1488 1489 static irqreturn_t aic31xx_irq(int irq, void *data) 1490 { 1491 struct aic31xx_priv *aic31xx = data; 1492 struct device *dev = aic31xx->dev; 1493 unsigned int value; 1494 bool handled = false; 1495 int ret; 1496 1497 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); 1498 if (ret) { 1499 dev_err(dev, "Failed to read interrupt mask: %d\n", ret); 1500 goto exit; 1501 } 1502 1503 if (value) 1504 handled = true; 1505 else 1506 goto read_overflow; 1507 1508 if (value & AIC31XX_HPLSCDETECT) 1509 dev_err(dev, "Short circuit on Left output is detected\n"); 1510 if (value & AIC31XX_HPRSCDETECT) 1511 dev_err(dev, "Short circuit on Right output is detected\n"); 1512 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) { 1513 unsigned int val; 1514 int status = 0; 1515 1516 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2, 1517 &val); 1518 if (ret) { 1519 dev_err(dev, "Failed to read interrupt mask: %d\n", 1520 ret); 1521 goto exit; 1522 } 1523 1524 if (val & AIC31XX_BUTTONPRESS) 1525 status |= SND_JACK_BTN_0; 1526 1527 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); 1528 if (ret) { 1529 dev_err(dev, "Failed to read headset type: %d\n", ret); 1530 goto exit; 1531 } 1532 1533 switch ((val & AIC31XX_HSD_TYPE_MASK) >> 1534 AIC31XX_HSD_TYPE_SHIFT) { 1535 case AIC31XX_HSD_HP: 1536 status |= SND_JACK_HEADPHONE; 1537 break; 1538 case AIC31XX_HSD_HS: 1539 status |= SND_JACK_HEADSET; 1540 break; 1541 default: 1542 break; 1543 } 1544 1545 if (aic31xx->jack) 1546 snd_soc_jack_report(aic31xx->jack, status, 1547 AIC31XX_JACK_MASK); 1548 } 1549 if (value & ~(AIC31XX_HPLSCDETECT | 1550 AIC31XX_HPRSCDETECT | 1551 AIC31XX_HSPLUG | 1552 AIC31XX_BUTTONPRESS)) 1553 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); 1554 1555 read_overflow: 1556 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); 1557 if (ret) { 1558 dev_err(dev, "Failed to read overflow flag: %d\n", ret); 1559 goto exit; 1560 } 1561 1562 if (value) 1563 handled = true; 1564 else 1565 goto exit; 1566 1567 if (value & AIC31XX_DAC_OF_LEFT) 1568 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); 1569 if (value & AIC31XX_DAC_OF_RIGHT) 1570 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); 1571 if (value & AIC31XX_DAC_OF_SHIFTER) 1572 dev_warn(dev, "DAC barrel shifter overflow has occurred\n"); 1573 if (value & AIC31XX_ADC_OF) 1574 dev_warn(dev, "ADC overflow has occurred\n"); 1575 if (value & AIC31XX_ADC_OF_SHIFTER) 1576 dev_warn(dev, "ADC barrel shifter overflow has occurred\n"); 1577 if (value & ~(AIC31XX_DAC_OF_LEFT | 1578 AIC31XX_DAC_OF_RIGHT | 1579 AIC31XX_DAC_OF_SHIFTER | 1580 AIC31XX_ADC_OF | 1581 AIC31XX_ADC_OF_SHIFTER)) 1582 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); 1583 1584 exit: 1585 if (handled) 1586 return IRQ_HANDLED; 1587 else 1588 return IRQ_NONE; 1589 } 1590 1591 static void aic31xx_configure_ocmv(struct aic31xx_priv *priv) 1592 { 1593 struct device *dev = priv->dev; 1594 int dvdd, avdd; 1595 u32 value; 1596 1597 if (dev->fwnode && 1598 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) { 1599 /* OCMV setting is forced by DT */ 1600 if (value <= 3) { 1601 priv->ocmv = value; 1602 return; 1603 } 1604 } 1605 1606 avdd = regulator_get_voltage(priv->supplies[3].consumer); 1607 dvdd = regulator_get_voltage(priv->supplies[5].consumer); 1608 1609 if (avdd > 3600000 || dvdd > 1950000) { 1610 dev_warn(dev, 1611 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1612 avdd, dvdd); 1613 } else if (avdd == 3600000 && dvdd == 1950000) { 1614 priv->ocmv = AIC31XX_HPD_OCMV_1_8V; 1615 } else if (avdd >= 3300000 && dvdd >= 1800000) { 1616 priv->ocmv = AIC31XX_HPD_OCMV_1_65V; 1617 } else if (avdd >= 3000000 && dvdd >= 1650000) { 1618 priv->ocmv = AIC31XX_HPD_OCMV_1_5V; 1619 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1620 priv->ocmv = AIC31XX_HPD_OCMV_1_35V; 1621 } else { 1622 dev_warn(dev, 1623 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1624 avdd, dvdd); 1625 } 1626 } 1627 1628 static const struct i2c_device_id aic31xx_i2c_id[] = { 1629 { "tlv320aic310x", AIC3100 }, 1630 { "tlv320aic311x", AIC3110 }, 1631 { "tlv320aic3100", AIC3100 }, 1632 { "tlv320aic3110", AIC3110 }, 1633 { "tlv320aic3120", AIC3120 }, 1634 { "tlv320aic3111", AIC3111 }, 1635 { "tlv320dac3100", DAC3100 }, 1636 { "tlv320dac3101", DAC3101 }, 1637 { } 1638 }; 1639 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1640 1641 static int aic31xx_i2c_probe(struct i2c_client *i2c) 1642 { 1643 struct aic31xx_priv *aic31xx; 1644 unsigned int micbias_value = MICBIAS_2_0V; 1645 const struct i2c_device_id *id = i2c_match_id(aic31xx_i2c_id, i2c); 1646 int i, ret; 1647 1648 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1649 id->name, (int)id->driver_data); 1650 1651 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1652 if (!aic31xx) 1653 return -ENOMEM; 1654 1655 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1656 if (IS_ERR(aic31xx->regmap)) { 1657 ret = PTR_ERR(aic31xx->regmap); 1658 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1659 ret); 1660 return ret; 1661 } 1662 regcache_cache_only(aic31xx->regmap, true); 1663 1664 aic31xx->dev = &i2c->dev; 1665 aic31xx->irq = i2c->irq; 1666 1667 aic31xx->codec_type = id->driver_data; 1668 1669 dev_set_drvdata(aic31xx->dev, aic31xx); 1670 1671 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1672 &micbias_value); 1673 switch (micbias_value) { 1674 case MICBIAS_2_0V: 1675 case MICBIAS_2_5V: 1676 case MICBIAS_AVDDV: 1677 aic31xx->micbias_vg = micbias_value; 1678 break; 1679 default: 1680 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1681 micbias_value); 1682 aic31xx->micbias_vg = MICBIAS_2_0V; 1683 } 1684 1685 if (dev_get_platdata(aic31xx->dev)) { 1686 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1687 aic31xx->codec_type = aic31xx->pdata.codec_type; 1688 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1689 } 1690 1691 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1692 GPIOD_OUT_LOW); 1693 if (IS_ERR(aic31xx->gpio_reset)) 1694 return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset), 1695 "not able to acquire gpio\n"); 1696 1697 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1698 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1699 1700 ret = devm_regulator_bulk_get(aic31xx->dev, 1701 ARRAY_SIZE(aic31xx->supplies), 1702 aic31xx->supplies); 1703 if (ret) 1704 return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n"); 1705 1706 aic31xx_configure_ocmv(aic31xx); 1707 1708 if (aic31xx->irq > 0) { 1709 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, 1710 AIC31XX_GPIO1_FUNC_MASK, 1711 AIC31XX_GPIO1_INT1 << 1712 AIC31XX_GPIO1_FUNC_SHIFT); 1713 1714 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, 1715 AIC31XX_HSPLUGDET | 1716 AIC31XX_BUTTONPRESSDET | 1717 AIC31XX_SC | 1718 AIC31XX_ENGINE); 1719 1720 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, 1721 NULL, aic31xx_irq, 1722 IRQF_ONESHOT, "aic31xx-irq", 1723 aic31xx); 1724 if (ret) { 1725 dev_err(aic31xx->dev, "Unable to request IRQ\n"); 1726 return ret; 1727 } 1728 } 1729 1730 if (aic31xx->codec_type & DAC31XX_BIT) 1731 return devm_snd_soc_register_component(&i2c->dev, 1732 &soc_codec_driver_aic31xx, 1733 dac31xx_dai_driver, 1734 ARRAY_SIZE(dac31xx_dai_driver)); 1735 else 1736 return devm_snd_soc_register_component(&i2c->dev, 1737 &soc_codec_driver_aic31xx, 1738 aic31xx_dai_driver, 1739 ARRAY_SIZE(aic31xx_dai_driver)); 1740 } 1741 1742 static struct i2c_driver aic31xx_i2c_driver = { 1743 .driver = { 1744 .name = "tlv320aic31xx-codec", 1745 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1746 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1747 }, 1748 .probe = aic31xx_i2c_probe, 1749 .id_table = aic31xx_i2c_id, 1750 }; 1751 module_i2c_driver(aic31xx_i2c_driver); 1752 1753 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1754 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1755 MODULE_LICENSE("GPL v2"); 1756