xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml (revision d53b8e36925256097a08d7cb749198d85cbf9b2b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm video clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,sm8450-videocc.h
19    include/dt-bindings/clock/qcom,sm8650-videocc.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,sm8450-videocc
25      - qcom,sm8550-videocc
26      - qcom,sm8650-videocc
27
28  clocks:
29    items:
30      - description: Board XO source
31      - description: Video AHB clock from GCC
32
33  power-domains:
34    maxItems: 1
35    description:
36      MMCX power domain.
37
38  required-opps:
39    maxItems: 1
40    description:
41      A phandle to an OPP node describing required MMCX performance point.
42
43required:
44  - compatible
45  - clocks
46  - power-domains
47  - required-opps
48  - '#power-domain-cells'
49
50allOf:
51  - $ref: qcom,gcc.yaml#
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
58    #include <dt-bindings/clock/qcom,rpmh.h>
59    #include <dt-bindings/power/qcom,rpmhpd.h>
60    videocc: clock-controller@aaf0000 {
61      compatible = "qcom,sm8450-videocc";
62      reg = <0x0aaf0000 0x10000>;
63      clocks = <&rpmhcc RPMH_CXO_CLK>,
64               <&gcc GCC_VIDEO_AHB_CLK>;
65      power-domains = <&rpmhpd RPMHPD_MMCX>;
66      required-opps = <&rpmhpd_opp_low_svs>;
67      #clock-cells = <1>;
68      #reset-cells = <1>;
69      #power-domain-cells = <1>;
70    };
71...
72