1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8226-tsens 33 - qcom,msm8909-tsens 34 - qcom,msm8916-tsens 35 - qcom,msm8939-tsens 36 - qcom,msm8974-tsens 37 - const: qcom,tsens-v0_1 38 39 - description: v1 of TSENS 40 items: 41 - enum: 42 - qcom,msm8956-tsens 43 - qcom,msm8976-tsens 44 - qcom,qcs404-tsens 45 - const: qcom,tsens-v1 46 47 - description: v2 of TSENS 48 items: 49 - enum: 50 - qcom,msm8953-tsens 51 - qcom,msm8996-tsens 52 - qcom,msm8998-tsens 53 - qcom,qcm2290-tsens 54 - qcom,sa8775p-tsens 55 - qcom,sc7180-tsens 56 - qcom,sc7280-tsens 57 - qcom,sc8180x-tsens 58 - qcom,sc8280xp-tsens 59 - qcom,sdm630-tsens 60 - qcom,sdm845-tsens 61 - qcom,sm6115-tsens 62 - qcom,sm6350-tsens 63 - qcom,sm6375-tsens 64 - qcom,sm8150-tsens 65 - qcom,sm8250-tsens 66 - qcom,sm8350-tsens 67 - qcom,sm8450-tsens 68 - qcom,sm8550-tsens 69 - qcom,sm8650-tsens 70 - qcom,x1e80100-tsens 71 - const: qcom,tsens-v2 72 73 - description: v2 of TSENS with combined interrupt 74 enum: 75 - qcom,ipq8074-tsens 76 77 - description: v2 of TSENS with combined interrupt 78 items: 79 - enum: 80 - qcom,ipq9574-tsens 81 - const: qcom,ipq8074-tsens 82 83 reg: 84 items: 85 - description: TM registers 86 - description: SROT registers 87 88 interrupts: 89 minItems: 1 90 maxItems: 2 91 92 interrupt-names: 93 minItems: 1 94 maxItems: 2 95 96 nvmem-cells: 97 oneOf: 98 - minItems: 1 99 maxItems: 2 100 description: 101 Reference to an nvmem node for the calibration data 102 - minItems: 5 103 maxItems: 35 104 description: | 105 Reference to nvmem cells for the calibration mode, two calibration 106 bases and two cells per each sensor 107 # special case for msm8974 / apq8084 108 - maxItems: 51 109 description: | 110 Reference to nvmem cells for the calibration mode, two calibration 111 bases and two cells per each sensor, main and backup copies, plus use_backup cell 112 113 nvmem-cell-names: 114 oneOf: 115 - minItems: 1 116 items: 117 - const: calib 118 - enum: 119 - calib_backup 120 - calib_sel 121 - minItems: 5 122 items: 123 - const: mode 124 - const: base1 125 - const: base2 126 - pattern: '^s[0-9]+_p1$' 127 - pattern: '^s[0-9]+_p2$' 128 - pattern: '^s[0-9]+_p1$' 129 - pattern: '^s[0-9]+_p2$' 130 - pattern: '^s[0-9]+_p1$' 131 - pattern: '^s[0-9]+_p2$' 132 - pattern: '^s[0-9]+_p1$' 133 - pattern: '^s[0-9]+_p2$' 134 - pattern: '^s[0-9]+_p1$' 135 - pattern: '^s[0-9]+_p2$' 136 - pattern: '^s[0-9]+_p1$' 137 - pattern: '^s[0-9]+_p2$' 138 - pattern: '^s[0-9]+_p1$' 139 - pattern: '^s[0-9]+_p2$' 140 - pattern: '^s[0-9]+_p1$' 141 - pattern: '^s[0-9]+_p2$' 142 - pattern: '^s[0-9]+_p1$' 143 - pattern: '^s[0-9]+_p2$' 144 - pattern: '^s[0-9]+_p1$' 145 - pattern: '^s[0-9]+_p2$' 146 - pattern: '^s[0-9]+_p1$' 147 - pattern: '^s[0-9]+_p2$' 148 - pattern: '^s[0-9]+_p1$' 149 - pattern: '^s[0-9]+_p2$' 150 - pattern: '^s[0-9]+_p1$' 151 - pattern: '^s[0-9]+_p2$' 152 - pattern: '^s[0-9]+_p1$' 153 - pattern: '^s[0-9]+_p2$' 154 - pattern: '^s[0-9]+_p1$' 155 - pattern: '^s[0-9]+_p2$' 156 - pattern: '^s[0-9]+_p1$' 157 - pattern: '^s[0-9]+_p2$' 158 # special case for msm8974 / apq8084 159 - items: 160 - const: mode 161 - const: base1 162 - const: base2 163 - const: use_backup 164 - const: mode_backup 165 - const: base1_backup 166 - const: base2_backup 167 - const: s0_p1 168 - const: s0_p2 169 - const: s1_p1 170 - const: s1_p2 171 - const: s2_p1 172 - const: s2_p2 173 - const: s3_p1 174 - const: s3_p2 175 - const: s4_p1 176 - const: s4_p2 177 - const: s5_p1 178 - const: s5_p2 179 - const: s6_p1 180 - const: s6_p2 181 - const: s7_p1 182 - const: s7_p2 183 - const: s8_p1 184 - const: s8_p2 185 - const: s9_p1 186 - const: s9_p2 187 - const: s10_p1 188 - const: s10_p2 189 - const: s0_p1_backup 190 - const: s0_p2_backup 191 - const: s1_p1_backup 192 - const: s1_p2_backup 193 - const: s2_p1_backup 194 - const: s2_p2_backup 195 - const: s3_p1_backup 196 - const: s3_p2_backup 197 - const: s4_p1_backup 198 - const: s4_p2_backup 199 - const: s5_p1_backup 200 - const: s5_p2_backup 201 - const: s6_p1_backup 202 - const: s6_p2_backup 203 - const: s7_p1_backup 204 - const: s7_p2_backup 205 - const: s8_p1_backup 206 - const: s8_p2_backup 207 - const: s9_p1_backup 208 - const: s9_p2_backup 209 - const: s10_p1_backup 210 - const: s10_p2_backup 211 212 "#qcom,sensors": 213 description: 214 Number of sensors enabled on this platform 215 $ref: /schemas/types.yaml#/definitions/uint32 216 minimum: 1 217 maximum: 16 218 219 "#thermal-sensor-cells": 220 const: 1 221 222required: 223 - compatible 224 - interrupts 225 - interrupt-names 226 - "#qcom,sensors" 227 228allOf: 229 - $ref: thermal-sensor.yaml# 230 231 - if: 232 properties: 233 compatible: 234 contains: 235 enum: 236 - qcom,ipq8064-tsens 237 - qcom,msm8960-tsens 238 - qcom,tsens-v0_1 239 - qcom,tsens-v1 240 then: 241 properties: 242 interrupts: 243 items: 244 - description: Combined interrupt if upper or lower threshold crossed 245 interrupt-names: 246 items: 247 - const: uplow 248 249 - if: 250 properties: 251 compatible: 252 contains: 253 const: qcom,tsens-v2 254 then: 255 properties: 256 interrupts: 257 items: 258 - description: Combined interrupt if upper or lower threshold crossed 259 - description: Interrupt if critical threshold crossed 260 interrupt-names: 261 items: 262 - const: uplow 263 - const: critical 264 265 - if: 266 properties: 267 compatible: 268 contains: 269 enum: 270 - qcom,ipq8074-tsens 271 then: 272 properties: 273 interrupts: 274 items: 275 - description: Combined interrupt if upper, lower or critical thresholds crossed 276 interrupt-names: 277 items: 278 - const: combined 279 280 - if: 281 properties: 282 compatible: 283 contains: 284 enum: 285 - qcom,ipq8074-tsens 286 - qcom,tsens-v0_1 287 - qcom,tsens-v1 288 - qcom,tsens-v2 289 290 then: 291 required: 292 - reg 293 294unevaluatedProperties: false 295 296examples: 297 - | 298 #include <dt-bindings/interrupt-controller/arm-gic.h> 299 thermal-sensor { 300 compatible = "qcom,ipq8064-tsens"; 301 302 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 303 nvmem-cell-names = "calib", "calib_backup"; 304 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "uplow"; 306 307 #qcom,sensors = <11>; 308 #thermal-sensor-cells = <1>; 309 }; 310 311 - | 312 #include <dt-bindings/interrupt-controller/arm-gic.h> 313 // Example 1 (new calbiration data: for pre v1 IP): 314 thermal-sensor@4a9000 { 315 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 316 reg = <0x4a9000 0x1000>, /* TM */ 317 <0x4a8000 0x1000>; /* SROT */ 318 319 nvmem-cells = <&tsens_mode>, 320 <&tsens_base1>, <&tsens_base2>, 321 <&tsens_s0_p1>, <&tsens_s0_p2>, 322 <&tsens_s1_p1>, <&tsens_s1_p2>, 323 <&tsens_s2_p1>, <&tsens_s2_p2>, 324 <&tsens_s4_p1>, <&tsens_s4_p2>, 325 <&tsens_s5_p1>, <&tsens_s5_p2>; 326 nvmem-cell-names = "mode", 327 "base1", "base2", 328 "s0_p1", "s0_p2", 329 "s1_p1", "s1_p2", 330 "s2_p1", "s2_p2", 331 "s4_p1", "s4_p2", 332 "s5_p1", "s5_p2"; 333 334 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-names = "uplow"; 336 337 #qcom,sensors = <5>; 338 #thermal-sensor-cells = <1>; 339 }; 340 341 - | 342 #include <dt-bindings/interrupt-controller/arm-gic.h> 343 // Example 1 (legacy: for pre v1 IP): 344 tsens1: thermal-sensor@4a9000 { 345 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 346 reg = <0x4a9000 0x1000>, /* TM */ 347 <0x4a8000 0x1000>; /* SROT */ 348 349 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 350 nvmem-cell-names = "calib", "calib_sel"; 351 352 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-names = "uplow"; 354 355 #qcom,sensors = <5>; 356 #thermal-sensor-cells = <1>; 357 }; 358 359 - | 360 #include <dt-bindings/interrupt-controller/arm-gic.h> 361 // Example 2 (for any platform containing v1 of the TSENS IP): 362 tsens2: thermal-sensor@4a9000 { 363 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 364 reg = <0x004a9000 0x1000>, /* TM */ 365 <0x004a8000 0x1000>; /* SROT */ 366 367 nvmem-cells = <&tsens_caldata>; 368 nvmem-cell-names = "calib"; 369 370 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "uplow"; 372 373 #qcom,sensors = <10>; 374 #thermal-sensor-cells = <1>; 375 }; 376 377 - | 378 #include <dt-bindings/interrupt-controller/arm-gic.h> 379 // Example 3 (for any platform containing v2 of the TSENS IP): 380 tsens3: thermal-sensor@c263000 { 381 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 382 reg = <0xc263000 0x1ff>, 383 <0xc222000 0x1ff>; 384 385 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "uplow", "critical"; 388 389 #qcom,sensors = <13>; 390 #thermal-sensor-cells = <1>; 391 }; 392 393 - | 394 #include <dt-bindings/interrupt-controller/arm-gic.h> 395 // Example 4 (for any IPQ8074 based SoC-s): 396 tsens4: thermal-sensor@4a9000 { 397 compatible = "qcom,ipq8074-tsens"; 398 reg = <0x4a9000 0x1000>, 399 <0x4a8000 0x1000>; 400 401 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "combined"; 403 404 #qcom,sensors = <16>; 405 #thermal-sensor-cells = <1>; 406 }; 407... 408