1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // ALSA SoC IMX MQS driver 4 // 5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6 // Copyright 2019 NXP 7 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/pm.h> 15 #include <linux/slab.h> 16 #include <sound/soc.h> 17 #include <sound/pcm.h> 18 #include <sound/initval.h> 19 20 #define REG_MQS_CTRL 0x00 21 22 #define MQS_EN_MASK (0x1 << 28) 23 #define MQS_EN_SHIFT (28) 24 #define MQS_SW_RST_MASK (0x1 << 24) 25 #define MQS_SW_RST_SHIFT (24) 26 #define MQS_OVERSAMPLE_MASK (0x1 << 20) 27 #define MQS_OVERSAMPLE_SHIFT (20) 28 #define MQS_CLK_DIV_MASK (0xFF << 0) 29 #define MQS_CLK_DIV_SHIFT (0) 30 31 enum reg_type { 32 TYPE_REG_OWN, /* module own register space */ 33 TYPE_REG_GPR, /* register in GPR space */ 34 TYPE_REG_SM, /* System Manager controls the register */ 35 }; 36 37 /** 38 * struct fsl_mqs_soc_data - soc specific data 39 * 40 * @type: control register space type 41 * @ctrl_off: control register offset 42 * @en_mask: enable bit mask 43 * @en_shift: enable bit shift 44 * @rst_mask: reset bit mask 45 * @rst_shift: reset bit shift 46 * @osr_mask: oversample bit mask 47 * @osr_shift: oversample bit shift 48 * @div_mask: clock divider mask 49 * @div_shift: clock divider bit shift 50 */ 51 struct fsl_mqs_soc_data { 52 enum reg_type type; 53 int ctrl_off; 54 int en_mask; 55 int en_shift; 56 int rst_mask; 57 int rst_shift; 58 int osr_mask; 59 int osr_shift; 60 int div_mask; 61 int div_shift; 62 }; 63 64 /* codec private data */ 65 struct fsl_mqs { 66 struct regmap *regmap; 67 struct clk *mclk; 68 struct clk *ipg; 69 const struct fsl_mqs_soc_data *soc; 70 71 unsigned int reg_mqs_ctrl; 72 }; 73 74 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 75 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 76 77 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 78 struct snd_pcm_hw_params *params, 79 struct snd_soc_dai *dai) 80 { 81 struct snd_soc_component *component = dai->component; 82 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 83 unsigned long mclk_rate; 84 int div, res; 85 int lrclk; 86 87 mclk_rate = clk_get_rate(mqs_priv->mclk); 88 lrclk = params_rate(params); 89 90 /* 91 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 92 * if repeat_rate is 8, mqs can achieve better quality. 93 * oversample rate is fix to 32 currently. 94 */ 95 div = mclk_rate / (32 * lrclk * 2 * 8); 96 res = mclk_rate % (32 * lrclk * 2 * 8); 97 98 if (res == 0 && div > 0 && div <= 256) { 99 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 100 mqs_priv->soc->div_mask, 101 (div - 1) << mqs_priv->soc->div_shift); 102 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 103 mqs_priv->soc->osr_mask, 0); 104 } else { 105 dev_err(component->dev, "can't get proper divider\n"); 106 } 107 108 return 0; 109 } 110 111 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 112 { 113 /* Only LEFT_J & SLAVE mode is supported. */ 114 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 115 case SND_SOC_DAIFMT_LEFT_J: 116 break; 117 default: 118 return -EINVAL; 119 } 120 121 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 122 case SND_SOC_DAIFMT_NB_NF: 123 break; 124 default: 125 return -EINVAL; 126 } 127 128 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 129 case SND_SOC_DAIFMT_CBC_CFC: 130 break; 131 default: 132 return -EINVAL; 133 } 134 135 return 0; 136 } 137 138 static int fsl_mqs_startup(struct snd_pcm_substream *substream, 139 struct snd_soc_dai *dai) 140 { 141 struct snd_soc_component *component = dai->component; 142 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 143 144 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 145 mqs_priv->soc->en_mask, 146 1 << mqs_priv->soc->en_shift); 147 return 0; 148 } 149 150 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 151 struct snd_soc_dai *dai) 152 { 153 struct snd_soc_component *component = dai->component; 154 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 155 156 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 157 mqs_priv->soc->en_mask, 0); 158 } 159 160 static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 161 .idle_bias_on = 1, 162 }; 163 164 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 165 .startup = fsl_mqs_startup, 166 .shutdown = fsl_mqs_shutdown, 167 .hw_params = fsl_mqs_hw_params, 168 .set_fmt = fsl_mqs_set_dai_fmt, 169 }; 170 171 static struct snd_soc_dai_driver fsl_mqs_dai = { 172 .name = "fsl-mqs-dai", 173 .playback = { 174 .stream_name = "Playback", 175 .channels_min = 2, 176 .channels_max = 2, 177 .rates = FSL_MQS_RATES, 178 .formats = FSL_MQS_FORMATS, 179 }, 180 .ops = &fsl_mqs_dai_ops, 181 }; 182 183 static const struct regmap_config fsl_mqs_regmap_config = { 184 .reg_bits = 32, 185 .reg_stride = 4, 186 .val_bits = 32, 187 .max_register = REG_MQS_CTRL, 188 .cache_type = REGCACHE_NONE, 189 }; 190 191 static int fsl_mqs_probe(struct platform_device *pdev) 192 { 193 struct device_node *np = pdev->dev.of_node; 194 struct device_node *gpr_np = NULL; 195 struct fsl_mqs *mqs_priv; 196 void __iomem *regs; 197 int ret; 198 199 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 200 if (!mqs_priv) 201 return -ENOMEM; 202 203 /* On i.MX6sx the MQS control register is in GPR domain 204 * But in i.MX8QM/i.MX8QXP the control register is moved 205 * to its own domain. 206 */ 207 mqs_priv->soc = of_device_get_match_data(&pdev->dev); 208 209 if (mqs_priv->soc->type == TYPE_REG_GPR) { 210 gpr_np = of_parse_phandle(np, "gpr", 0); 211 if (!gpr_np) { 212 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 213 return -EINVAL; 214 } 215 216 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 217 of_node_put(gpr_np); 218 if (IS_ERR(mqs_priv->regmap)) { 219 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 220 return PTR_ERR(mqs_priv->regmap); 221 } 222 } else { 223 regs = devm_platform_ioremap_resource(pdev, 0); 224 if (IS_ERR(regs)) 225 return PTR_ERR(regs); 226 227 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 228 "core", 229 regs, 230 &fsl_mqs_regmap_config); 231 if (IS_ERR(mqs_priv->regmap)) { 232 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 233 PTR_ERR(mqs_priv->regmap)); 234 return PTR_ERR(mqs_priv->regmap); 235 } 236 237 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 238 if (IS_ERR(mqs_priv->ipg)) { 239 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 240 PTR_ERR(mqs_priv->ipg)); 241 return PTR_ERR(mqs_priv->ipg); 242 } 243 } 244 245 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 246 if (IS_ERR(mqs_priv->mclk)) { 247 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 248 PTR_ERR(mqs_priv->mclk)); 249 return PTR_ERR(mqs_priv->mclk); 250 } 251 252 dev_set_drvdata(&pdev->dev, mqs_priv); 253 pm_runtime_enable(&pdev->dev); 254 255 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 256 &fsl_mqs_dai, 1); 257 if (ret) 258 return ret; 259 260 return 0; 261 } 262 263 static void fsl_mqs_remove(struct platform_device *pdev) 264 { 265 pm_runtime_disable(&pdev->dev); 266 } 267 268 #ifdef CONFIG_PM 269 static int fsl_mqs_runtime_resume(struct device *dev) 270 { 271 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 272 int ret; 273 274 ret = clk_prepare_enable(mqs_priv->ipg); 275 if (ret) { 276 dev_err(dev, "failed to enable ipg clock\n"); 277 return ret; 278 } 279 280 ret = clk_prepare_enable(mqs_priv->mclk); 281 if (ret) { 282 dev_err(dev, "failed to enable mclk clock\n"); 283 clk_disable_unprepare(mqs_priv->ipg); 284 return ret; 285 } 286 287 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl); 288 return 0; 289 } 290 291 static int fsl_mqs_runtime_suspend(struct device *dev) 292 { 293 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 294 295 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl); 296 297 clk_disable_unprepare(mqs_priv->mclk); 298 clk_disable_unprepare(mqs_priv->ipg); 299 300 return 0; 301 } 302 #endif 303 304 static const struct dev_pm_ops fsl_mqs_pm_ops = { 305 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 306 fsl_mqs_runtime_resume, 307 NULL) 308 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 309 pm_runtime_force_resume) 310 }; 311 312 static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { 313 .type = TYPE_REG_OWN, 314 .ctrl_off = REG_MQS_CTRL, 315 .en_mask = MQS_EN_MASK, 316 .en_shift = MQS_EN_SHIFT, 317 .rst_mask = MQS_SW_RST_MASK, 318 .rst_shift = MQS_SW_RST_SHIFT, 319 .osr_mask = MQS_OVERSAMPLE_MASK, 320 .osr_shift = MQS_OVERSAMPLE_SHIFT, 321 .div_mask = MQS_CLK_DIV_MASK, 322 .div_shift = MQS_CLK_DIV_SHIFT, 323 }; 324 325 static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { 326 .type = TYPE_REG_GPR, 327 .ctrl_off = IOMUXC_GPR2, 328 .en_mask = IMX6SX_GPR2_MQS_EN_MASK, 329 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT, 330 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK, 331 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT, 332 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 333 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT, 334 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK, 335 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT, 336 }; 337 338 static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = { 339 .type = TYPE_REG_GPR, 340 .ctrl_off = 0x20, 341 .en_mask = BIT(1), 342 .en_shift = 1, 343 .rst_mask = BIT(2), 344 .rst_shift = 2, 345 .osr_mask = BIT(3), 346 .osr_shift = 3, 347 .div_mask = GENMASK(15, 8), 348 .div_shift = 8, 349 }; 350 351 static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = { 352 .type = TYPE_REG_SM, 353 .ctrl_off = 0x88, 354 .en_mask = BIT(1), 355 .en_shift = 1, 356 .rst_mask = BIT(2), 357 .rst_shift = 2, 358 .osr_mask = BIT(3), 359 .osr_shift = 3, 360 .div_mask = GENMASK(15, 8), 361 .div_shift = 8, 362 }; 363 364 static const struct fsl_mqs_soc_data fsl_mqs_imx95_netc_data = { 365 .type = TYPE_REG_GPR, 366 .ctrl_off = 0x0, 367 .en_mask = BIT(2), 368 .en_shift = 2, 369 .rst_mask = BIT(3), 370 .rst_shift = 3, 371 .osr_mask = BIT(4), 372 .osr_shift = 4, 373 .div_mask = GENMASK(16, 9), 374 .div_shift = 9, 375 }; 376 377 static const struct of_device_id fsl_mqs_dt_ids[] = { 378 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data }, 379 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data }, 380 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data }, 381 { .compatible = "fsl,imx95-aonmix-mqs", .data = &fsl_mqs_imx95_aon_data }, 382 { .compatible = "fsl,imx95-netcmix-mqs", .data = &fsl_mqs_imx95_netc_data }, 383 {} 384 }; 385 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 386 387 static struct platform_driver fsl_mqs_driver = { 388 .probe = fsl_mqs_probe, 389 .remove_new = fsl_mqs_remove, 390 .driver = { 391 .name = "fsl-mqs", 392 .of_match_table = fsl_mqs_dt_ids, 393 .pm = &fsl_mqs_pm_ops, 394 }, 395 }; 396 397 module_platform_driver(fsl_mqs_driver); 398 399 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 400 MODULE_DESCRIPTION("MQS codec driver"); 401 MODULE_LICENSE("GPL v2"); 402 MODULE_ALIAS("platform:fsl-mqs"); 403