1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 */ 7 8#include "imx93.dtsi" 9 10/{ 11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; 12 compatible = "tq,imx93-tqma9352", "fsl,imx93"; 13 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 linux,cma { 20 compatible = "shared-dma-pool"; 21 reusable; 22 alloc-ranges = <0 0x60000000 0 0x40000000>; 23 size = <0 0x10000000>; 24 linux,cma-default; 25 }; 26 }; 27 28 reg_v1v8: regulator-v1v8 { 29 compatible = "regulator-fixed"; 30 regulator-name = "V_1V8"; 31 regulator-min-microvolt = <1800000>; 32 regulator-max-microvolt = <1800000>; 33 }; 34 35 reg_v3v3: regulator-v3v3 { 36 compatible = "regulator-fixed"; 37 regulator-name = "V_3V3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 }; 41 42 /* SD2 RST# via PMIC SW_EN */ 43 reg_usdhc2_vmmc: regulator-usdhc2 { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 vin-supply = <®_v3v3>; 51 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54}; 55 56&adc1 { 57 vref-supply = <®_v1v8>; 58}; 59 60&flexspi1 { 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_flexspi1>; 63 status = "okay"; 64 65 flash0: flash@0 { 66 compatible = "jedec,spi-nor"; 67 reg = <0>; 68 /* 69 * no DQS, RXCLKSRC internal loop back, max 66 MHz 70 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST 71 * selected value together with root from 72 * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to 73 * respect the maximum value. 74 */ 75 spi-max-frequency = <62000000>; 76 spi-tx-bus-width = <4>; 77 spi-rx-bus-width = <4>; 78 79 partitions { 80 compatible = "fixed-partitions"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 }; 84 }; 85}; 86 87&gpio1 { 88 pmic-irq-hog { 89 gpio-hog; 90 gpios = <3 GPIO_ACTIVE_LOW>; 91 input; 92 line-name = "PMIC_IRQ#"; 93 }; 94}; 95 96&lpi2c1 { 97 clock-frequency = <400000>; 98 pinctrl-names = "default", "sleep"; 99 pinctrl-0 = <&pinctrl_lpi2c1>; 100 pinctrl-1 = <&pinctrl_lpi2c1>; 101 status = "okay"; 102 103 se97_som: temperature-sensor@1b { 104 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 105 reg = <0x1b>; 106 }; 107 108 pcf85063: rtc@51 { 109 compatible = "nxp,pcf85063a"; 110 reg = <0x51>; 111 quartz-load-femtofarads = <7000>; 112 }; 113 114 eeprom0: eeprom@53 { 115 compatible = "nxp,se97b", "atmel,24c02"; 116 reg = <0x53>; 117 pagesize = <16>; 118 read-only; 119 vcc-supply = <®_v3v3>; 120 }; 121 122 eeprom1: eeprom@57 { 123 compatible = "atmel,24c64"; 124 reg = <0x57>; 125 pagesize = <32>; 126 vcc-supply = <®_v3v3>; 127 }; 128 129 /* protectable identification memory (part of M24C64-D @57) */ 130 eeprom@5f { 131 compatible = "atmel,24c64d-wl"; 132 reg = <0x5f>; 133 vcc-supply = <®_v3v3>; 134 }; 135 136 imu@6a { 137 compatible = "st,ism330dhcx"; 138 reg = <0x6a>; 139 vdd-supply = <®_v3v3>; 140 vddio-supply = <®_v3v3>; 141 }; 142}; 143 144&usdhc1 { 145 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 146 pinctrl-0 = <&pinctrl_usdhc1>; 147 pinctrl-1 = <&pinctrl_usdhc1>; 148 pinctrl-2 = <&pinctrl_usdhc1>; 149 bus-width = <8>; 150 non-removable; 151 no-sdio; 152 no-sd; 153 status = "okay"; 154}; 155 156&wdog3 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_wdog>; 159 status = "okay"; 160}; 161 162&iomuxc { 163 pinctrl_flexspi1: flexspi1grp { 164 fsl,pins = < 165 MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe 166 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe 167 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe 168 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe 169 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe 170 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe 171 >; 172 }; 173 174 pinctrl_lpi2c1: lpi2c1grp { 175 fsl,pins = < 176 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 177 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 178 >; 179 }; 180 181 pinctrl_pca9451: pca9451grp { 182 fsl,pins = < 183 MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1306 184 >; 185 }; 186 187 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 188 fsl,pins = < 189 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x1306 190 >; 191 }; 192 193 pinctrl_usdhc1: usdhc1grp { 194 fsl,pins = < 195 /* HYS | PU | PD | FSEL_3 | X5 */ 196 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 197 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17be 198 /* HYS | PU | FSEL_3 | X5 */ 199 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13be 200 /* HYS | PU | FSEL_3 | X4 */ 201 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x139e 202 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x139e 203 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x139e 204 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x139e 205 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x139e 206 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x139e 207 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x139e 208 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x139e 209 >; 210 }; 211 212 pinctrl_wdog: wdoggrp { 213 fsl,pins = < 214 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 215 >; 216 }; 217}; 218