1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/platform_device.h> 10 11 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 12 13 #include "clk-gate.h" 14 #include "clk-mtk.h" 15 16 static const struct mtk_gate_regs wpe_top_cg_regs = { 17 .set_ofs = 0x0, 18 .clr_ofs = 0x0, 19 .sta_ofs = 0x0, 20 }; 21 22 static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = { 23 .set_ofs = 0x58, 24 .clr_ofs = 0x58, 25 .sta_ofs = 0x58, 26 }; 27 28 static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = { 29 .set_ofs = 0x5c, 30 .clr_ofs = 0x5c, 31 .sta_ofs = 0x5c, 32 }; 33 34 #define GATE_WPE_TOP(_id, _name, _parent, _shift) \ 35 GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 36 37 #define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \ 38 GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 39 40 #define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \ 41 GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 42 43 static const struct mtk_gate wpe_top_clks[] = { 44 GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16), 45 GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18), 46 GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20), 47 GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24), 48 }; 49 50 static const struct mtk_gate wpe_vpp0_clks[] = { 51 /* WPE_VPP00 */ 52 GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0), 53 GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1), 54 GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2), 55 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3), 56 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4), 57 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5), 58 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6), 59 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7), 60 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8), 61 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9), 62 GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10), 63 GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11), 64 GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12), 65 GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13), 66 GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14), 67 GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15), 68 GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16), 69 GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17), 70 /* WPE_VPP0_1 */ 71 GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0), 72 GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1), 73 GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2), 74 GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3), 75 GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4), 76 }; 77 78 static const struct mtk_clk_desc wpe_top_desc = { 79 .clks = wpe_top_clks, 80 .num_clks = ARRAY_SIZE(wpe_top_clks), 81 }; 82 83 static const struct mtk_clk_desc wpe_vpp0_desc = { 84 .clks = wpe_vpp0_clks, 85 .num_clks = ARRAY_SIZE(wpe_vpp0_clks), 86 }; 87 88 static const struct of_device_id of_match_clk_mt8188_wpe[] = { 89 { .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc }, 90 { .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc }, 91 { /* sentinel */ } 92 }; 93 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_wpe); 94 95 static struct platform_driver clk_mt8188_wpe_drv = { 96 .probe = mtk_clk_simple_probe, 97 .remove_new = mtk_clk_simple_remove, 98 .driver = { 99 .name = "clk-mt8188-wpe", 100 .of_match_table = of_match_clk_mt8188_wpe, 101 }, 102 }; 103 module_platform_driver(clk_mt8188_wpe_drv); 104 105 MODULE_DESCRIPTION("MediaTek MT8188 Warp Engine clocks driver"); 106 MODULE_LICENSE("GPL"); 107