1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #include "hclge_trace.h" 31 32 #define HCLGE_NAME "hclge" 33 34 #define HCLGE_BUF_SIZE_UNIT 256U 35 #define HCLGE_BUF_MUL_BY 2 36 #define HCLGE_BUF_DIV_BY 2 37 #define NEED_RESERVE_TC_NUM 2 38 #define BUF_MAX_PERCENT 100 39 #define BUF_RESERVE_PERCENT 90 40 41 #define HCLGE_RESET_MAX_FAIL_CNT 5 42 #define HCLGE_RESET_SYNC_TIME 100 43 #define HCLGE_PF_RESET_SYNC_TIME 20 44 #define HCLGE_PF_RESET_SYNC_CNT 1500 45 46 #define HCLGE_LINK_STATUS_MS 10 47 48 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 49 static int hclge_init_vlan_config(struct hclge_dev *hdev); 50 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 51 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 52 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 53 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 54 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 55 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 56 unsigned long *addr); 57 static int hclge_set_default_loopback(struct hclge_dev *hdev); 58 59 static void hclge_sync_mac_table(struct hclge_dev *hdev); 60 static void hclge_restore_hw_table(struct hclge_dev *hdev); 61 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 62 static void hclge_sync_fd_table(struct hclge_dev *hdev); 63 static void hclge_update_fec_stats(struct hclge_dev *hdev); 64 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 65 int wait_cnt); 66 static int hclge_update_port_info(struct hclge_dev *hdev); 67 68 static struct hnae3_ae_algo ae_algo; 69 70 static struct workqueue_struct *hclge_wq; 71 72 static const struct pci_device_id ae_algo_pci_tbl[] = { 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 81 /* required last entry */ 82 {0, } 83 }; 84 85 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 86 87 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 88 "External Loopback test", 89 "App Loopback test", 90 "Serdes serial Loopback test", 91 "Serdes parallel Loopback test", 92 "Phy Loopback test" 93 }; 94 95 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 96 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 98 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 100 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 102 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 104 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 106 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 108 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 110 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 112 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 114 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 116 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 118 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 120 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 122 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 124 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 126 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 128 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 130 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 132 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 134 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 136 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 138 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 140 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 142 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 144 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 146 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 148 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 150 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 152 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 154 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 156 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 158 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 160 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 162 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 164 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 166 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 168 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 170 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 172 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 174 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 176 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 178 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 180 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 182 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 184 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 186 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 188 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 190 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 192 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 194 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 196 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 198 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 200 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 202 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 204 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 206 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 208 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 210 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 212 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 214 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 216 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 218 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 220 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 222 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 224 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 226 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 228 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 230 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 232 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 234 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 236 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 238 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 240 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 242 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 244 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 246 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 248 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 250 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 252 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 254 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 256 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 258 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 260 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 262 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 264 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 266 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 268 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 270 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 272 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 274 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 276 277 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 279 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 281 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 283 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 285 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 287 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 289 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 291 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 293 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 295 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 297 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 299 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 301 }; 302 303 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 304 { 305 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 306 .ethter_type = cpu_to_le16(ETH_P_LLDP), 307 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 308 .i_port_bitmap = 0x1, 309 }, 310 }; 311 312 static const struct key_info meta_data_key_info[] = { 313 { PACKET_TYPE_ID, 6 }, 314 { IP_FRAGEMENT, 1 }, 315 { ROCE_TYPE, 1 }, 316 { NEXT_KEY, 5 }, 317 { VLAN_NUMBER, 2 }, 318 { SRC_VPORT, 12 }, 319 { DST_VPORT, 12 }, 320 { TUNNEL_PACKET, 1 }, 321 }; 322 323 static const struct key_info tuple_key_info[] = { 324 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 325 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 326 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 329 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 330 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 331 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 332 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 333 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 334 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 336 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 337 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 338 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 339 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 340 { INNER_DST_MAC, 48, KEY_OPT_MAC, 341 offsetof(struct hclge_fd_rule, tuples.dst_mac), 342 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 343 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 344 offsetof(struct hclge_fd_rule, tuples.src_mac), 345 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 346 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 347 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 348 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 349 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 350 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 351 offsetof(struct hclge_fd_rule, tuples.ether_proto), 352 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 353 { INNER_L2_RSV, 16, KEY_OPT_LE16, 354 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 355 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 356 { INNER_IP_TOS, 8, KEY_OPT_U8, 357 offsetof(struct hclge_fd_rule, tuples.ip_tos), 358 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 359 { INNER_IP_PROTO, 8, KEY_OPT_U8, 360 offsetof(struct hclge_fd_rule, tuples.ip_proto), 361 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 362 { INNER_SRC_IP, 32, KEY_OPT_IP, 363 offsetof(struct hclge_fd_rule, tuples.src_ip), 364 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 365 { INNER_DST_IP, 32, KEY_OPT_IP, 366 offsetof(struct hclge_fd_rule, tuples.dst_ip), 367 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 368 { INNER_L3_RSV, 16, KEY_OPT_LE16, 369 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 370 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 371 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 372 offsetof(struct hclge_fd_rule, tuples.src_port), 373 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 374 { INNER_DST_PORT, 16, KEY_OPT_LE16, 375 offsetof(struct hclge_fd_rule, tuples.dst_port), 376 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 377 { INNER_L4_RSV, 32, KEY_OPT_LE32, 378 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 379 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 380 }; 381 382 /** 383 * hclge_cmd_send - send command to command queue 384 * @hw: pointer to the hw struct 385 * @desc: prefilled descriptor for describing the command 386 * @num : the number of descriptors to be sent 387 * 388 * This is the main send command for command queue, it 389 * sends the queue, cleans the queue, etc 390 **/ 391 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 392 { 393 return hclge_comm_cmd_send(&hw->hw, desc, num); 394 } 395 396 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 397 int num, bool is_special) 398 { 399 int i; 400 401 trace_hclge_pf_cmd_send(hw, desc, 0, num); 402 403 if (!is_special) { 404 for (i = 1; i < num; i++) 405 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 406 } else { 407 for (i = 1; i < num; i++) 408 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 409 i, num); 410 } 411 } 412 413 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 414 int num, bool is_special) 415 { 416 int i; 417 418 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 419 return; 420 421 trace_hclge_pf_cmd_get(hw, desc, 0, num); 422 423 if (!is_special) { 424 for (i = 1; i < num; i++) 425 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 426 } else { 427 for (i = 1; i < num; i++) 428 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 429 i, num); 430 } 431 } 432 433 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 434 .trace_cmd_send = hclge_trace_cmd_send, 435 .trace_cmd_get = hclge_trace_cmd_get, 436 }; 437 438 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 439 { 440 #define HCLGE_MAC_CMD_NUM 21 441 442 u64 *data = (u64 *)(&hdev->mac_stats); 443 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 444 __le64 *desc_data; 445 u32 data_size; 446 int ret; 447 u32 i; 448 449 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 450 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 451 if (ret) { 452 dev_err(&hdev->pdev->dev, 453 "Get MAC pkt stats fail, status = %d.\n", ret); 454 455 return ret; 456 } 457 458 /* The first desc has a 64-bit header, so data size need to minus 1 */ 459 data_size = sizeof(desc) / (sizeof(u64)) - 1; 460 461 desc_data = (__le64 *)(&desc[0].data[0]); 462 for (i = 0; i < data_size; i++) { 463 /* data memory is continuous becase only the first desc has a 464 * header in this command 465 */ 466 *data += le64_to_cpu(*desc_data); 467 data++; 468 desc_data++; 469 } 470 471 return 0; 472 } 473 474 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 475 { 476 #define HCLGE_REG_NUM_PER_DESC 4 477 478 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 479 u64 *data = (u64 *)(&hdev->mac_stats); 480 struct hclge_desc *desc; 481 __le64 *desc_data; 482 u32 data_size; 483 u32 desc_num; 484 int ret; 485 u32 i; 486 487 /* The first desc has a 64-bit header, so need to consider it */ 488 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 489 490 /* This may be called inside atomic sections, 491 * so GFP_ATOMIC is more suitalbe here 492 */ 493 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 494 if (!desc) 495 return -ENOMEM; 496 497 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 498 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 499 if (ret) { 500 kfree(desc); 501 return ret; 502 } 503 504 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 505 506 desc_data = (__le64 *)(&desc[0].data[0]); 507 for (i = 0; i < data_size; i++) { 508 /* data memory is continuous becase only the first desc has a 509 * header in this command 510 */ 511 *data += le64_to_cpu(*desc_data); 512 data++; 513 desc_data++; 514 } 515 516 kfree(desc); 517 518 return 0; 519 } 520 521 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 522 { 523 struct hclge_desc desc; 524 int ret; 525 526 /* Driver needs total register number of both valid registers and 527 * reserved registers, but the old firmware only returns number 528 * of valid registers in device V2. To be compatible with these 529 * devices, driver uses a fixed value. 530 */ 531 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 532 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 533 return 0; 534 } 535 536 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 537 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 538 if (ret) { 539 dev_err(&hdev->pdev->dev, 540 "failed to query mac statistic reg number, ret = %d\n", 541 ret); 542 return ret; 543 } 544 545 *reg_num = le32_to_cpu(desc.data[0]); 546 if (*reg_num == 0) { 547 dev_err(&hdev->pdev->dev, 548 "mac statistic reg number is invalid!\n"); 549 return -ENODATA; 550 } 551 552 return 0; 553 } 554 555 int hclge_mac_update_stats(struct hclge_dev *hdev) 556 { 557 /* The firmware supports the new statistics acquisition method */ 558 if (hdev->ae_dev->dev_specs.mac_stats_num) 559 return hclge_mac_update_stats_complete(hdev); 560 else 561 return hclge_mac_update_stats_defective(hdev); 562 } 563 564 static int hclge_comm_get_count(struct hclge_dev *hdev, 565 const struct hclge_comm_stats_str strs[], 566 u32 size) 567 { 568 int count = 0; 569 u32 i; 570 571 for (i = 0; i < size; i++) 572 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 573 count++; 574 575 return count; 576 } 577 578 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 579 const struct hclge_comm_stats_str strs[], 580 int size, u64 *data) 581 { 582 u64 *buf = data; 583 u32 i; 584 585 for (i = 0; i < size; i++) { 586 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 587 continue; 588 589 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 590 buf++; 591 } 592 593 return buf; 594 } 595 596 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 597 const struct hclge_comm_stats_str strs[], 598 int size, u8 *data) 599 { 600 char *buff = (char *)data; 601 u32 i; 602 603 if (stringset != ETH_SS_STATS) 604 return buff; 605 606 for (i = 0; i < size; i++) { 607 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 608 continue; 609 610 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 611 buff = buff + ETH_GSTRING_LEN; 612 } 613 614 return (u8 *)buff; 615 } 616 617 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 618 { 619 struct hnae3_handle *handle; 620 int status; 621 622 handle = &hdev->vport[0].nic; 623 if (handle->client) { 624 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 625 if (status) { 626 dev_err(&hdev->pdev->dev, 627 "Update TQPS stats fail, status = %d.\n", 628 status); 629 } 630 } 631 632 hclge_update_fec_stats(hdev); 633 634 status = hclge_mac_update_stats(hdev); 635 if (status) 636 dev_err(&hdev->pdev->dev, 637 "Update MAC stats fail, status = %d.\n", status); 638 } 639 640 static void hclge_update_stats(struct hnae3_handle *handle) 641 { 642 struct hclge_vport *vport = hclge_get_vport(handle); 643 struct hclge_dev *hdev = vport->back; 644 int status; 645 646 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 647 return; 648 649 status = hclge_mac_update_stats(hdev); 650 if (status) 651 dev_err(&hdev->pdev->dev, 652 "Update MAC stats fail, status = %d.\n", 653 status); 654 655 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 656 if (status) 657 dev_err(&hdev->pdev->dev, 658 "Update TQPS stats fail, status = %d.\n", 659 status); 660 661 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 662 } 663 664 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 665 { 666 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 667 HNAE3_SUPPORT_PHY_LOOPBACK | \ 668 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 669 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 670 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 671 672 struct hclge_vport *vport = hclge_get_vport(handle); 673 struct hclge_dev *hdev = vport->back; 674 int count = 0; 675 676 /* Loopback test support rules: 677 * mac: only GE mode support 678 * serdes: all mac mode will support include GE/XGE/LGE/CGE 679 * phy: only support when phy device exist on board 680 */ 681 if (stringset == ETH_SS_TEST) { 682 /* clear loopback bit flags at first */ 683 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 684 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 685 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 686 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 687 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 688 count += 1; 689 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 690 } 691 692 if (hdev->ae_dev->dev_specs.hilink_version != 693 HCLGE_HILINK_H60) { 694 count += 1; 695 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 696 } 697 698 count += 1; 699 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 700 count += 1; 701 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 702 703 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 704 hdev->hw.mac.phydev->drv->set_loopback) || 705 hnae3_dev_phy_imp_supported(hdev)) { 706 count += 1; 707 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 708 } 709 } else if (stringset == ETH_SS_STATS) { 710 count = hclge_comm_get_count(hdev, g_mac_stats_string, 711 ARRAY_SIZE(g_mac_stats_string)) + 712 hclge_comm_tqps_get_sset_count(handle); 713 } 714 715 return count; 716 } 717 718 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 719 u8 *data) 720 { 721 struct hclge_vport *vport = hclge_get_vport(handle); 722 struct hclge_dev *hdev = vport->back; 723 u8 *p = (char *)data; 724 int size; 725 726 if (stringset == ETH_SS_STATS) { 727 size = ARRAY_SIZE(g_mac_stats_string); 728 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 729 size, p); 730 p = hclge_comm_tqps_get_strings(handle, p); 731 } else if (stringset == ETH_SS_TEST) { 732 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 733 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 734 ETH_GSTRING_LEN); 735 p += ETH_GSTRING_LEN; 736 } 737 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 738 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 739 ETH_GSTRING_LEN); 740 p += ETH_GSTRING_LEN; 741 } 742 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 743 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 744 ETH_GSTRING_LEN); 745 p += ETH_GSTRING_LEN; 746 } 747 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 748 memcpy(p, 749 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 750 ETH_GSTRING_LEN); 751 p += ETH_GSTRING_LEN; 752 } 753 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 754 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 755 ETH_GSTRING_LEN); 756 p += ETH_GSTRING_LEN; 757 } 758 } 759 } 760 761 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 762 { 763 struct hclge_vport *vport = hclge_get_vport(handle); 764 struct hclge_dev *hdev = vport->back; 765 u64 *p; 766 767 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 768 ARRAY_SIZE(g_mac_stats_string), data); 769 p = hclge_comm_tqps_get_stats(handle, p); 770 } 771 772 static void hclge_get_mac_stat(struct hnae3_handle *handle, 773 struct hns3_mac_stats *mac_stats) 774 { 775 struct hclge_vport *vport = hclge_get_vport(handle); 776 struct hclge_dev *hdev = vport->back; 777 778 hclge_update_stats(handle); 779 780 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 781 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 782 } 783 784 static int hclge_parse_func_status(struct hclge_dev *hdev, 785 struct hclge_func_status_cmd *status) 786 { 787 #define HCLGE_MAC_ID_MASK 0xF 788 789 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 790 return -EINVAL; 791 792 /* Set the pf to main pf */ 793 if (status->pf_state & HCLGE_PF_STATE_MAIN) 794 hdev->flag |= HCLGE_FLAG_MAIN; 795 else 796 hdev->flag &= ~HCLGE_FLAG_MAIN; 797 798 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 799 return 0; 800 } 801 802 static int hclge_query_function_status(struct hclge_dev *hdev) 803 { 804 #define HCLGE_QUERY_MAX_CNT 5 805 806 struct hclge_func_status_cmd *req; 807 struct hclge_desc desc; 808 int timeout = 0; 809 int ret; 810 811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 812 req = (struct hclge_func_status_cmd *)desc.data; 813 814 do { 815 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 816 if (ret) { 817 dev_err(&hdev->pdev->dev, 818 "query function status failed %d.\n", ret); 819 return ret; 820 } 821 822 /* Check pf reset is done */ 823 if (req->pf_state) 824 break; 825 usleep_range(1000, 2000); 826 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 827 828 return hclge_parse_func_status(hdev, req); 829 } 830 831 static int hclge_query_pf_resource(struct hclge_dev *hdev) 832 { 833 struct hclge_pf_res_cmd *req; 834 struct hclge_desc desc; 835 int ret; 836 837 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 838 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 839 if (ret) { 840 dev_err(&hdev->pdev->dev, 841 "query pf resource failed %d.\n", ret); 842 return ret; 843 } 844 845 req = (struct hclge_pf_res_cmd *)desc.data; 846 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 847 le16_to_cpu(req->ext_tqp_num); 848 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 849 850 if (req->tx_buf_size) 851 hdev->tx_buf_size = 852 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 853 else 854 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 855 856 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 857 858 if (req->dv_buf_size) 859 hdev->dv_buf_size = 860 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 861 else 862 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 863 864 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 865 866 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 867 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 868 dev_err(&hdev->pdev->dev, 869 "only %u msi resources available, not enough for pf(min:2).\n", 870 hdev->num_nic_msi); 871 return -EINVAL; 872 } 873 874 if (hnae3_dev_roce_supported(hdev)) { 875 hdev->num_roce_msi = 876 le16_to_cpu(req->pf_intr_vector_number_roce); 877 878 /* PF should have NIC vectors and Roce vectors, 879 * NIC vectors are queued before Roce vectors. 880 */ 881 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 882 } else { 883 hdev->num_msi = hdev->num_nic_msi; 884 } 885 886 return 0; 887 } 888 889 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 890 { 891 switch (speed_cmd) { 892 case HCLGE_FW_MAC_SPEED_10M: 893 *speed = HCLGE_MAC_SPEED_10M; 894 break; 895 case HCLGE_FW_MAC_SPEED_100M: 896 *speed = HCLGE_MAC_SPEED_100M; 897 break; 898 case HCLGE_FW_MAC_SPEED_1G: 899 *speed = HCLGE_MAC_SPEED_1G; 900 break; 901 case HCLGE_FW_MAC_SPEED_10G: 902 *speed = HCLGE_MAC_SPEED_10G; 903 break; 904 case HCLGE_FW_MAC_SPEED_25G: 905 *speed = HCLGE_MAC_SPEED_25G; 906 break; 907 case HCLGE_FW_MAC_SPEED_40G: 908 *speed = HCLGE_MAC_SPEED_40G; 909 break; 910 case HCLGE_FW_MAC_SPEED_50G: 911 *speed = HCLGE_MAC_SPEED_50G; 912 break; 913 case HCLGE_FW_MAC_SPEED_100G: 914 *speed = HCLGE_MAC_SPEED_100G; 915 break; 916 case HCLGE_FW_MAC_SPEED_200G: 917 *speed = HCLGE_MAC_SPEED_200G; 918 break; 919 default: 920 return -EINVAL; 921 } 922 923 return 0; 924 } 925 926 static const struct hclge_speed_bit_map speed_bit_map[] = { 927 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 928 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 929 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 930 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 931 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 932 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 933 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 934 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 935 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 936 }; 937 938 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 939 { 940 u16 i; 941 942 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 943 if (speed == speed_bit_map[i].speed) { 944 *speed_bit = speed_bit_map[i].speed_bit; 945 return 0; 946 } 947 } 948 949 return -EINVAL; 950 } 951 952 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 953 { 954 struct hclge_vport *vport = hclge_get_vport(handle); 955 struct hclge_dev *hdev = vport->back; 956 u32 speed_ability = hdev->hw.mac.speed_ability; 957 u32 speed_bit = 0; 958 int ret; 959 960 ret = hclge_get_speed_bit(speed, &speed_bit); 961 if (ret) 962 return ret; 963 964 if (speed_bit & speed_ability) 965 return 0; 966 967 return -EINVAL; 968 } 969 970 static void hclge_update_fec_support(struct hclge_mac *mac) 971 { 972 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 973 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 974 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 975 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 976 977 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 978 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 979 mac->supported); 980 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 981 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 982 mac->supported); 983 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 984 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 985 mac->supported); 986 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 987 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 988 mac->supported); 989 } 990 991 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 992 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 993 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 994 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 995 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 996 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 997 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 998 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 999 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1000 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 1001 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 1002 }; 1003 1004 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 1005 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 1006 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 1007 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 1008 {HCLGE_SUPPORT_100G_R4_BIT, 1009 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 1010 {HCLGE_SUPPORT_100G_R2_BIT, 1011 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 1012 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1013 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1014 {HCLGE_SUPPORT_200G_R4_BIT, 1015 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1016 }; 1017 1018 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 1019 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 1020 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 1021 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 1022 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 1023 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 1024 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 1025 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 1026 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1027 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1028 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1029 }; 1030 1031 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 1032 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 1033 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 1034 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 1035 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 1036 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 1037 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 1038 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 1039 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 1040 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1041 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1042 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1043 }; 1044 1045 static void hclge_convert_setting_sr(u16 speed_ability, 1046 unsigned long *link_mode) 1047 { 1048 int i; 1049 1050 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 1051 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 1052 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 1053 link_mode); 1054 } 1055 } 1056 1057 static void hclge_convert_setting_lr(u16 speed_ability, 1058 unsigned long *link_mode) 1059 { 1060 int i; 1061 1062 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 1063 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 1064 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 1065 link_mode); 1066 } 1067 } 1068 1069 static void hclge_convert_setting_cr(u16 speed_ability, 1070 unsigned long *link_mode) 1071 { 1072 int i; 1073 1074 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 1075 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 1076 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 1077 link_mode); 1078 } 1079 } 1080 1081 static void hclge_convert_setting_kr(u16 speed_ability, 1082 unsigned long *link_mode) 1083 { 1084 int i; 1085 1086 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1087 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1088 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1089 link_mode); 1090 } 1091 } 1092 1093 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1094 { 1095 /* If firmware has reported fec_ability, don't need to convert by speed */ 1096 if (mac->fec_ability) 1097 goto out; 1098 1099 switch (mac->speed) { 1100 case HCLGE_MAC_SPEED_10G: 1101 case HCLGE_MAC_SPEED_40G: 1102 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1103 BIT(HNAE3_FEC_NONE); 1104 break; 1105 case HCLGE_MAC_SPEED_25G: 1106 case HCLGE_MAC_SPEED_50G: 1107 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1108 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1109 break; 1110 case HCLGE_MAC_SPEED_100G: 1111 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1112 BIT(HNAE3_FEC_NONE); 1113 break; 1114 case HCLGE_MAC_SPEED_200G: 1115 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1116 BIT(HNAE3_FEC_LLRS); 1117 break; 1118 default: 1119 mac->fec_ability = 0; 1120 break; 1121 } 1122 1123 out: 1124 hclge_update_fec_support(mac); 1125 } 1126 1127 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1128 u16 speed_ability) 1129 { 1130 struct hclge_mac *mac = &hdev->hw.mac; 1131 1132 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1134 mac->supported); 1135 1136 hclge_convert_setting_sr(speed_ability, mac->supported); 1137 hclge_convert_setting_lr(speed_ability, mac->supported); 1138 hclge_convert_setting_cr(speed_ability, mac->supported); 1139 if (hnae3_dev_fec_supported(hdev)) 1140 hclge_convert_setting_fec(mac); 1141 1142 if (hnae3_dev_pause_supported(hdev)) 1143 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1144 1145 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1146 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1147 } 1148 1149 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1150 u16 speed_ability) 1151 { 1152 struct hclge_mac *mac = &hdev->hw.mac; 1153 1154 hclge_convert_setting_kr(speed_ability, mac->supported); 1155 if (hnae3_dev_fec_supported(hdev)) 1156 hclge_convert_setting_fec(mac); 1157 1158 if (hnae3_dev_pause_supported(hdev)) 1159 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1160 1161 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1162 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1163 } 1164 1165 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1166 u16 speed_ability) 1167 { 1168 unsigned long *supported = hdev->hw.mac.supported; 1169 1170 /* default to support all speed for GE port */ 1171 if (!speed_ability) 1172 speed_ability = HCLGE_SUPPORT_GE; 1173 1174 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1175 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1176 supported); 1177 1178 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1179 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1180 supported); 1181 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1182 supported); 1183 } 1184 1185 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1186 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1188 } 1189 1190 if (hnae3_dev_pause_supported(hdev)) { 1191 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1192 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1193 } 1194 1195 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1196 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1197 } 1198 1199 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1200 { 1201 u8 media_type = hdev->hw.mac.media_type; 1202 1203 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1204 hclge_parse_fiber_link_mode(hdev, speed_ability); 1205 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1206 hclge_parse_copper_link_mode(hdev, speed_ability); 1207 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1208 hclge_parse_backplane_link_mode(hdev, speed_ability); 1209 } 1210 1211 static u32 hclge_get_max_speed(u16 speed_ability) 1212 { 1213 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1214 return HCLGE_MAC_SPEED_200G; 1215 1216 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1217 return HCLGE_MAC_SPEED_100G; 1218 1219 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1220 return HCLGE_MAC_SPEED_50G; 1221 1222 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1223 return HCLGE_MAC_SPEED_40G; 1224 1225 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1226 return HCLGE_MAC_SPEED_25G; 1227 1228 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1229 return HCLGE_MAC_SPEED_10G; 1230 1231 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1232 return HCLGE_MAC_SPEED_1G; 1233 1234 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1235 return HCLGE_MAC_SPEED_100M; 1236 1237 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1238 return HCLGE_MAC_SPEED_10M; 1239 1240 return HCLGE_MAC_SPEED_1G; 1241 } 1242 1243 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1244 { 1245 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1246 #define SPEED_ABILITY_EXT_SHIFT 8 1247 1248 struct hclge_cfg_param_cmd *req; 1249 u64 mac_addr_tmp_high; 1250 u16 speed_ability_ext; 1251 u64 mac_addr_tmp; 1252 unsigned int i; 1253 1254 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1255 1256 /* get the configuration */ 1257 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1258 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1259 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1260 HCLGE_CFG_TQP_DESC_N_M, 1261 HCLGE_CFG_TQP_DESC_N_S); 1262 1263 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1264 HCLGE_CFG_PHY_ADDR_M, 1265 HCLGE_CFG_PHY_ADDR_S); 1266 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1267 HCLGE_CFG_MEDIA_TP_M, 1268 HCLGE_CFG_MEDIA_TP_S); 1269 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1270 HCLGE_CFG_RX_BUF_LEN_M, 1271 HCLGE_CFG_RX_BUF_LEN_S); 1272 /* get mac_address */ 1273 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1274 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1275 HCLGE_CFG_MAC_ADDR_H_M, 1276 HCLGE_CFG_MAC_ADDR_H_S); 1277 1278 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1279 1280 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1281 HCLGE_CFG_DEFAULT_SPEED_M, 1282 HCLGE_CFG_DEFAULT_SPEED_S); 1283 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1284 HCLGE_CFG_RSS_SIZE_M, 1285 HCLGE_CFG_RSS_SIZE_S); 1286 1287 for (i = 0; i < ETH_ALEN; i++) 1288 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1289 1290 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1291 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1292 1293 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1294 HCLGE_CFG_SPEED_ABILITY_M, 1295 HCLGE_CFG_SPEED_ABILITY_S); 1296 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1297 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1298 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1299 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1300 1301 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1302 HCLGE_CFG_VLAN_FLTR_CAP_M, 1303 HCLGE_CFG_VLAN_FLTR_CAP_S); 1304 1305 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1306 HCLGE_CFG_UMV_TBL_SPACE_M, 1307 HCLGE_CFG_UMV_TBL_SPACE_S); 1308 1309 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1310 HCLGE_CFG_PF_RSS_SIZE_M, 1311 HCLGE_CFG_PF_RSS_SIZE_S); 1312 1313 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1314 * power of 2, instead of reading out directly. This would 1315 * be more flexible for future changes and expansions. 1316 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1317 * it does not make sense if PF's field is 0. In this case, PF and VF 1318 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1319 */ 1320 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1321 1U << cfg->pf_rss_size_max : 1322 cfg->vf_rss_size_max; 1323 1324 /* The unit of the tx spare buffer size queried from configuration 1325 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1326 * needed here. 1327 */ 1328 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1329 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1330 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1331 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1332 } 1333 1334 /* hclge_get_cfg: query the static parameter from flash 1335 * @hdev: pointer to struct hclge_dev 1336 * @hcfg: the config structure to be getted 1337 */ 1338 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1339 { 1340 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1341 struct hclge_cfg_param_cmd *req; 1342 unsigned int i; 1343 int ret; 1344 1345 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1346 u32 offset = 0; 1347 1348 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1349 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1350 true); 1351 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1352 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1353 /* Len should be united by 4 bytes when send to hardware */ 1354 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1355 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1356 req->offset = cpu_to_le32(offset); 1357 } 1358 1359 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1360 if (ret) { 1361 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1362 return ret; 1363 } 1364 1365 hclge_parse_cfg(hcfg, desc); 1366 1367 return 0; 1368 } 1369 1370 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1371 { 1372 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1373 1374 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1375 1376 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1377 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1378 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1379 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1380 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1381 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1382 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1383 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1384 ae_dev->dev_specs.tnl_num = 0; 1385 } 1386 1387 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1388 struct hclge_desc *desc) 1389 { 1390 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1391 struct hclge_dev_specs_0_cmd *req0; 1392 struct hclge_dev_specs_1_cmd *req1; 1393 1394 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1395 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1396 1397 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1398 ae_dev->dev_specs.rss_ind_tbl_size = 1399 le16_to_cpu(req0->rss_ind_tbl_size); 1400 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1401 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1402 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1403 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1404 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1405 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1406 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1407 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1408 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1409 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1410 } 1411 1412 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1413 { 1414 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1415 1416 if (!dev_specs->max_non_tso_bd_num) 1417 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1418 if (!dev_specs->rss_ind_tbl_size) 1419 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1420 if (!dev_specs->rss_key_size) 1421 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1422 if (!dev_specs->max_tm_rate) 1423 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1424 if (!dev_specs->max_qset_num) 1425 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1426 if (!dev_specs->max_int_gl) 1427 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1428 if (!dev_specs->max_frm_size) 1429 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1430 if (!dev_specs->umv_size) 1431 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1432 } 1433 1434 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1435 { 1436 u32 reg_num = 0; 1437 int ret; 1438 1439 ret = hclge_mac_query_reg_num(hdev, ®_num); 1440 if (ret && ret != -EOPNOTSUPP) 1441 return ret; 1442 1443 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1444 return 0; 1445 } 1446 1447 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1448 { 1449 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1450 int ret; 1451 int i; 1452 1453 ret = hclge_query_mac_stats_num(hdev); 1454 if (ret) 1455 return ret; 1456 1457 /* set default specifications as devices lower than version V3 do not 1458 * support querying specifications from firmware. 1459 */ 1460 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1461 hclge_set_default_dev_specs(hdev); 1462 return 0; 1463 } 1464 1465 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1466 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1467 true); 1468 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1469 } 1470 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1471 1472 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1473 if (ret) 1474 return ret; 1475 1476 hclge_parse_dev_specs(hdev, desc); 1477 hclge_check_dev_specs(hdev); 1478 1479 return 0; 1480 } 1481 1482 static int hclge_get_cap(struct hclge_dev *hdev) 1483 { 1484 int ret; 1485 1486 ret = hclge_query_function_status(hdev); 1487 if (ret) { 1488 dev_err(&hdev->pdev->dev, 1489 "query function status error %d.\n", ret); 1490 return ret; 1491 } 1492 1493 /* get pf resource */ 1494 return hclge_query_pf_resource(hdev); 1495 } 1496 1497 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1498 { 1499 #define HCLGE_MIN_TX_DESC 64 1500 #define HCLGE_MIN_RX_DESC 64 1501 1502 if (!is_kdump_kernel()) 1503 return; 1504 1505 dev_info(&hdev->pdev->dev, 1506 "Running kdump kernel. Using minimal resources\n"); 1507 1508 /* minimal queue pairs equals to the number of vports */ 1509 hdev->num_tqps = hdev->num_req_vfs + 1; 1510 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1511 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1512 } 1513 1514 static void hclge_init_tc_config(struct hclge_dev *hdev) 1515 { 1516 unsigned int i; 1517 1518 if (hdev->tc_max > HNAE3_MAX_TC || 1519 hdev->tc_max < 1) { 1520 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1521 hdev->tc_max); 1522 hdev->tc_max = 1; 1523 } 1524 1525 /* Dev does not support DCB */ 1526 if (!hnae3_dev_dcb_supported(hdev)) { 1527 hdev->tc_max = 1; 1528 hdev->pfc_max = 0; 1529 } else { 1530 hdev->pfc_max = hdev->tc_max; 1531 } 1532 1533 hdev->tm_info.num_tc = 1; 1534 1535 /* Currently not support uncontiuous tc */ 1536 for (i = 0; i < hdev->tm_info.num_tc; i++) 1537 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1538 1539 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1540 } 1541 1542 static int hclge_configure(struct hclge_dev *hdev) 1543 { 1544 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1545 struct hclge_cfg cfg; 1546 int ret; 1547 1548 ret = hclge_get_cfg(hdev, &cfg); 1549 if (ret) 1550 return ret; 1551 1552 hdev->base_tqp_pid = 0; 1553 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1554 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1555 hdev->rx_buf_len = cfg.rx_buf_len; 1556 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1557 hdev->hw.mac.media_type = cfg.media_type; 1558 hdev->hw.mac.phy_addr = cfg.phy_addr; 1559 hdev->num_tx_desc = cfg.tqp_desc_num; 1560 hdev->num_rx_desc = cfg.tqp_desc_num; 1561 hdev->tm_info.num_pg = 1; 1562 hdev->tc_max = cfg.tc_num; 1563 hdev->tm_info.hw_pfc_map = 0; 1564 if (cfg.umv_space) 1565 hdev->wanted_umv_size = cfg.umv_space; 1566 else 1567 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1568 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1569 hdev->gro_en = true; 1570 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1571 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1572 1573 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1574 hdev->fd_en = true; 1575 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1576 } 1577 1578 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1579 if (ret) { 1580 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1581 cfg.default_speed, ret); 1582 return ret; 1583 } 1584 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1585 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1586 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1587 1588 hclge_parse_link_mode(hdev, cfg.speed_ability); 1589 1590 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1591 1592 hclge_init_tc_config(hdev); 1593 hclge_init_kdump_kernel_config(hdev); 1594 1595 return ret; 1596 } 1597 1598 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1599 u16 tso_mss_max) 1600 { 1601 struct hclge_cfg_tso_status_cmd *req; 1602 struct hclge_desc desc; 1603 1604 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1605 1606 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1607 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1608 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1609 1610 return hclge_cmd_send(&hdev->hw, &desc, 1); 1611 } 1612 1613 static int hclge_config_gro(struct hclge_dev *hdev) 1614 { 1615 struct hclge_cfg_gro_status_cmd *req; 1616 struct hclge_desc desc; 1617 int ret; 1618 1619 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1620 return 0; 1621 1622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1623 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1624 1625 req->gro_en = hdev->gro_en ? 1 : 0; 1626 1627 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1628 if (ret) 1629 dev_err(&hdev->pdev->dev, 1630 "GRO hardware config cmd failed, ret = %d\n", ret); 1631 1632 return ret; 1633 } 1634 1635 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1636 { 1637 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1638 struct hclge_comm_tqp *tqp; 1639 int i; 1640 1641 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1642 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1643 if (!hdev->htqp) 1644 return -ENOMEM; 1645 1646 tqp = hdev->htqp; 1647 1648 for (i = 0; i < hdev->num_tqps; i++) { 1649 tqp->dev = &hdev->pdev->dev; 1650 tqp->index = i; 1651 1652 tqp->q.ae_algo = &ae_algo; 1653 tqp->q.buf_size = hdev->rx_buf_len; 1654 tqp->q.tx_desc_num = hdev->num_tx_desc; 1655 tqp->q.rx_desc_num = hdev->num_rx_desc; 1656 1657 /* need an extended offset to configure queues >= 1658 * HCLGE_TQP_MAX_SIZE_DEV_V2 1659 */ 1660 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1661 tqp->q.io_base = hdev->hw.hw.io_base + 1662 HCLGE_TQP_REG_OFFSET + 1663 i * HCLGE_TQP_REG_SIZE; 1664 else 1665 tqp->q.io_base = hdev->hw.hw.io_base + 1666 HCLGE_TQP_REG_OFFSET + 1667 HCLGE_TQP_EXT_REG_OFFSET + 1668 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1669 HCLGE_TQP_REG_SIZE; 1670 1671 /* when device supports tx push and has device memory, 1672 * the queue can execute push mode or doorbell mode on 1673 * device memory. 1674 */ 1675 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1676 tqp->q.mem_base = hdev->hw.hw.mem_base + 1677 HCLGE_TQP_MEM_OFFSET(hdev, i); 1678 1679 tqp++; 1680 } 1681 1682 return 0; 1683 } 1684 1685 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1686 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1687 { 1688 struct hclge_tqp_map_cmd *req; 1689 struct hclge_desc desc; 1690 int ret; 1691 1692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1693 1694 req = (struct hclge_tqp_map_cmd *)desc.data; 1695 req->tqp_id = cpu_to_le16(tqp_pid); 1696 req->tqp_vf = func_id; 1697 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1698 if (!is_pf) 1699 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1700 req->tqp_vid = cpu_to_le16(tqp_vid); 1701 1702 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1703 if (ret) 1704 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1705 1706 return ret; 1707 } 1708 1709 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1710 { 1711 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1712 struct hclge_dev *hdev = vport->back; 1713 int i, alloced; 1714 1715 for (i = 0, alloced = 0; i < hdev->num_tqps && 1716 alloced < num_tqps; i++) { 1717 if (!hdev->htqp[i].alloced) { 1718 hdev->htqp[i].q.handle = &vport->nic; 1719 hdev->htqp[i].q.tqp_index = alloced; 1720 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1721 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1722 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1723 hdev->htqp[i].alloced = true; 1724 alloced++; 1725 } 1726 } 1727 vport->alloc_tqps = alloced; 1728 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1729 vport->alloc_tqps / hdev->tm_info.num_tc); 1730 1731 /* ensure one to one mapping between irq and queue at default */ 1732 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1733 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1734 1735 return 0; 1736 } 1737 1738 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1739 u16 num_tx_desc, u16 num_rx_desc) 1740 1741 { 1742 struct hnae3_handle *nic = &vport->nic; 1743 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1744 struct hclge_dev *hdev = vport->back; 1745 int ret; 1746 1747 kinfo->num_tx_desc = num_tx_desc; 1748 kinfo->num_rx_desc = num_rx_desc; 1749 1750 kinfo->rx_buf_len = hdev->rx_buf_len; 1751 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1752 1753 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1754 sizeof(struct hnae3_queue *), GFP_KERNEL); 1755 if (!kinfo->tqp) 1756 return -ENOMEM; 1757 1758 ret = hclge_assign_tqp(vport, num_tqps); 1759 if (ret) 1760 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1761 1762 return ret; 1763 } 1764 1765 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1766 struct hclge_vport *vport) 1767 { 1768 struct hnae3_handle *nic = &vport->nic; 1769 struct hnae3_knic_private_info *kinfo; 1770 u16 i; 1771 1772 kinfo = &nic->kinfo; 1773 for (i = 0; i < vport->alloc_tqps; i++) { 1774 struct hclge_comm_tqp *q = 1775 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1776 bool is_pf; 1777 int ret; 1778 1779 is_pf = !(vport->vport_id); 1780 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1781 i, is_pf); 1782 if (ret) 1783 return ret; 1784 } 1785 1786 return 0; 1787 } 1788 1789 static int hclge_map_tqp(struct hclge_dev *hdev) 1790 { 1791 struct hclge_vport *vport = hdev->vport; 1792 u16 i, num_vport; 1793 1794 num_vport = hdev->num_req_vfs + 1; 1795 for (i = 0; i < num_vport; i++) { 1796 int ret; 1797 1798 ret = hclge_map_tqp_to_vport(hdev, vport); 1799 if (ret) 1800 return ret; 1801 1802 vport++; 1803 } 1804 1805 return 0; 1806 } 1807 1808 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1809 { 1810 struct hnae3_handle *nic = &vport->nic; 1811 struct hclge_dev *hdev = vport->back; 1812 int ret; 1813 1814 nic->pdev = hdev->pdev; 1815 nic->ae_algo = &ae_algo; 1816 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1817 MAX_NUMNODES); 1818 nic->kinfo.io_base = hdev->hw.hw.io_base; 1819 1820 ret = hclge_knic_setup(vport, num_tqps, 1821 hdev->num_tx_desc, hdev->num_rx_desc); 1822 if (ret) 1823 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1824 1825 return ret; 1826 } 1827 1828 static int hclge_alloc_vport(struct hclge_dev *hdev) 1829 { 1830 struct pci_dev *pdev = hdev->pdev; 1831 struct hclge_vport *vport; 1832 u32 tqp_main_vport; 1833 u32 tqp_per_vport; 1834 int num_vport, i; 1835 int ret; 1836 1837 /* We need to alloc a vport for main NIC of PF */ 1838 num_vport = hdev->num_req_vfs + 1; 1839 1840 if (hdev->num_tqps < num_vport) { 1841 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1842 hdev->num_tqps, num_vport); 1843 return -EINVAL; 1844 } 1845 1846 /* Alloc the same number of TQPs for every vport */ 1847 tqp_per_vport = hdev->num_tqps / num_vport; 1848 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1849 1850 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1851 GFP_KERNEL); 1852 if (!vport) 1853 return -ENOMEM; 1854 1855 hdev->vport = vport; 1856 hdev->num_alloc_vport = num_vport; 1857 1858 if (IS_ENABLED(CONFIG_PCI_IOV)) 1859 hdev->num_alloc_vfs = hdev->num_req_vfs; 1860 1861 for (i = 0; i < num_vport; i++) { 1862 vport->back = hdev; 1863 vport->vport_id = i; 1864 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1865 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1866 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1867 vport->port_base_vlan_cfg.tbl_sta = true; 1868 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1869 vport->req_vlan_fltr_en = true; 1870 INIT_LIST_HEAD(&vport->vlan_list); 1871 INIT_LIST_HEAD(&vport->uc_mac_list); 1872 INIT_LIST_HEAD(&vport->mc_mac_list); 1873 spin_lock_init(&vport->mac_list_lock); 1874 1875 if (i == 0) 1876 ret = hclge_vport_setup(vport, tqp_main_vport); 1877 else 1878 ret = hclge_vport_setup(vport, tqp_per_vport); 1879 if (ret) { 1880 dev_err(&pdev->dev, 1881 "vport setup failed for vport %d, %d\n", 1882 i, ret); 1883 return ret; 1884 } 1885 1886 vport++; 1887 } 1888 1889 return 0; 1890 } 1891 1892 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1893 struct hclge_pkt_buf_alloc *buf_alloc) 1894 { 1895 /* TX buffer size is unit by 128 byte */ 1896 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1897 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1898 struct hclge_tx_buff_alloc_cmd *req; 1899 struct hclge_desc desc; 1900 int ret; 1901 u8 i; 1902 1903 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1904 1905 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1906 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1907 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1908 1909 req->tx_pkt_buff[i] = 1910 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1911 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1912 } 1913 1914 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1915 if (ret) 1916 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1917 ret); 1918 1919 return ret; 1920 } 1921 1922 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1923 struct hclge_pkt_buf_alloc *buf_alloc) 1924 { 1925 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1926 1927 if (ret) 1928 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1929 1930 return ret; 1931 } 1932 1933 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1934 { 1935 unsigned int i; 1936 u32 cnt = 0; 1937 1938 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1939 if (hdev->hw_tc_map & BIT(i)) 1940 cnt++; 1941 return cnt; 1942 } 1943 1944 /* Get the number of pfc enabled TCs, which have private buffer */ 1945 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1946 struct hclge_pkt_buf_alloc *buf_alloc) 1947 { 1948 struct hclge_priv_buf *priv; 1949 unsigned int i; 1950 int cnt = 0; 1951 1952 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1953 priv = &buf_alloc->priv_buf[i]; 1954 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1955 priv->enable) 1956 cnt++; 1957 } 1958 1959 return cnt; 1960 } 1961 1962 /* Get the number of pfc disabled TCs, which have private buffer */ 1963 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1964 struct hclge_pkt_buf_alloc *buf_alloc) 1965 { 1966 struct hclge_priv_buf *priv; 1967 unsigned int i; 1968 int cnt = 0; 1969 1970 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1971 priv = &buf_alloc->priv_buf[i]; 1972 if (hdev->hw_tc_map & BIT(i) && 1973 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1974 priv->enable) 1975 cnt++; 1976 } 1977 1978 return cnt; 1979 } 1980 1981 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1982 { 1983 struct hclge_priv_buf *priv; 1984 u32 rx_priv = 0; 1985 int i; 1986 1987 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1988 priv = &buf_alloc->priv_buf[i]; 1989 if (priv->enable) 1990 rx_priv += priv->buf_size; 1991 } 1992 return rx_priv; 1993 } 1994 1995 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1996 { 1997 u32 i, total_tx_size = 0; 1998 1999 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2000 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2001 2002 return total_tx_size; 2003 } 2004 2005 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2006 struct hclge_pkt_buf_alloc *buf_alloc, 2007 u32 rx_all) 2008 { 2009 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2010 u32 tc_num = hclge_get_tc_num(hdev); 2011 u32 shared_buf, aligned_mps; 2012 u32 rx_priv; 2013 int i; 2014 2015 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2016 2017 if (hnae3_dev_dcb_supported(hdev)) 2018 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2019 hdev->dv_buf_size; 2020 else 2021 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2022 + hdev->dv_buf_size; 2023 2024 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2025 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2026 HCLGE_BUF_SIZE_UNIT); 2027 2028 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2029 if (rx_all < rx_priv + shared_std) 2030 return false; 2031 2032 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2033 buf_alloc->s_buf.buf_size = shared_buf; 2034 if (hnae3_dev_dcb_supported(hdev)) { 2035 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2036 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2037 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2038 HCLGE_BUF_SIZE_UNIT); 2039 } else { 2040 buf_alloc->s_buf.self.high = aligned_mps + 2041 HCLGE_NON_DCB_ADDITIONAL_BUF; 2042 buf_alloc->s_buf.self.low = aligned_mps; 2043 } 2044 2045 if (hnae3_dev_dcb_supported(hdev)) { 2046 hi_thrd = shared_buf - hdev->dv_buf_size; 2047 2048 if (tc_num <= NEED_RESERVE_TC_NUM) 2049 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2050 / BUF_MAX_PERCENT; 2051 2052 if (tc_num) 2053 hi_thrd = hi_thrd / tc_num; 2054 2055 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2056 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2057 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2058 } else { 2059 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2060 lo_thrd = aligned_mps; 2061 } 2062 2063 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2064 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2065 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2066 } 2067 2068 return true; 2069 } 2070 2071 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2072 struct hclge_pkt_buf_alloc *buf_alloc) 2073 { 2074 u32 i, total_size; 2075 2076 total_size = hdev->pkt_buf_size; 2077 2078 /* alloc tx buffer for all enabled tc */ 2079 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2080 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2081 2082 if (hdev->hw_tc_map & BIT(i)) { 2083 if (total_size < hdev->tx_buf_size) 2084 return -ENOMEM; 2085 2086 priv->tx_buf_size = hdev->tx_buf_size; 2087 } else { 2088 priv->tx_buf_size = 0; 2089 } 2090 2091 total_size -= priv->tx_buf_size; 2092 } 2093 2094 return 0; 2095 } 2096 2097 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2098 struct hclge_pkt_buf_alloc *buf_alloc) 2099 { 2100 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2101 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2102 unsigned int i; 2103 2104 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2105 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2106 2107 priv->enable = 0; 2108 priv->wl.low = 0; 2109 priv->wl.high = 0; 2110 priv->buf_size = 0; 2111 2112 if (!(hdev->hw_tc_map & BIT(i))) 2113 continue; 2114 2115 priv->enable = 1; 2116 2117 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2118 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2119 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2120 HCLGE_BUF_SIZE_UNIT); 2121 } else { 2122 priv->wl.low = 0; 2123 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2124 aligned_mps; 2125 } 2126 2127 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2128 } 2129 2130 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2131 } 2132 2133 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2134 struct hclge_pkt_buf_alloc *buf_alloc) 2135 { 2136 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2137 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2138 int i; 2139 2140 /* let the last to be cleared first */ 2141 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2142 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2143 unsigned int mask = BIT((unsigned int)i); 2144 2145 if (hdev->hw_tc_map & mask && 2146 !(hdev->tm_info.hw_pfc_map & mask)) { 2147 /* Clear the no pfc TC private buffer */ 2148 priv->wl.low = 0; 2149 priv->wl.high = 0; 2150 priv->buf_size = 0; 2151 priv->enable = 0; 2152 no_pfc_priv_num--; 2153 } 2154 2155 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2156 no_pfc_priv_num == 0) 2157 break; 2158 } 2159 2160 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2161 } 2162 2163 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2164 struct hclge_pkt_buf_alloc *buf_alloc) 2165 { 2166 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2167 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2168 int i; 2169 2170 /* let the last to be cleared first */ 2171 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2172 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2173 unsigned int mask = BIT((unsigned int)i); 2174 2175 if (hdev->hw_tc_map & mask && 2176 hdev->tm_info.hw_pfc_map & mask) { 2177 /* Reduce the number of pfc TC with private buffer */ 2178 priv->wl.low = 0; 2179 priv->enable = 0; 2180 priv->wl.high = 0; 2181 priv->buf_size = 0; 2182 pfc_priv_num--; 2183 } 2184 2185 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2186 pfc_priv_num == 0) 2187 break; 2188 } 2189 2190 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2191 } 2192 2193 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2194 struct hclge_pkt_buf_alloc *buf_alloc) 2195 { 2196 #define COMPENSATE_BUFFER 0x3C00 2197 #define COMPENSATE_HALF_MPS_NUM 5 2198 #define PRIV_WL_GAP 0x1800 2199 2200 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2201 u32 tc_num = hclge_get_tc_num(hdev); 2202 u32 half_mps = hdev->mps >> 1; 2203 u32 min_rx_priv; 2204 unsigned int i; 2205 2206 if (tc_num) 2207 rx_priv = rx_priv / tc_num; 2208 2209 if (tc_num <= NEED_RESERVE_TC_NUM) 2210 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2211 2212 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2213 COMPENSATE_HALF_MPS_NUM * half_mps; 2214 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2215 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2216 if (rx_priv < min_rx_priv) 2217 return false; 2218 2219 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2220 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2221 2222 priv->enable = 0; 2223 priv->wl.low = 0; 2224 priv->wl.high = 0; 2225 priv->buf_size = 0; 2226 2227 if (!(hdev->hw_tc_map & BIT(i))) 2228 continue; 2229 2230 priv->enable = 1; 2231 priv->buf_size = rx_priv; 2232 priv->wl.high = rx_priv - hdev->dv_buf_size; 2233 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2234 } 2235 2236 buf_alloc->s_buf.buf_size = 0; 2237 2238 return true; 2239 } 2240 2241 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2242 * @hdev: pointer to struct hclge_dev 2243 * @buf_alloc: pointer to buffer calculation data 2244 * @return: 0: calculate successful, negative: fail 2245 */ 2246 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2247 struct hclge_pkt_buf_alloc *buf_alloc) 2248 { 2249 /* When DCB is not supported, rx private buffer is not allocated. */ 2250 if (!hnae3_dev_dcb_supported(hdev)) { 2251 u32 rx_all = hdev->pkt_buf_size; 2252 2253 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2254 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2255 return -ENOMEM; 2256 2257 return 0; 2258 } 2259 2260 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2261 return 0; 2262 2263 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2264 return 0; 2265 2266 /* try to decrease the buffer size */ 2267 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2268 return 0; 2269 2270 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2271 return 0; 2272 2273 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2274 return 0; 2275 2276 return -ENOMEM; 2277 } 2278 2279 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2280 struct hclge_pkt_buf_alloc *buf_alloc) 2281 { 2282 struct hclge_rx_priv_buff_cmd *req; 2283 struct hclge_desc desc; 2284 int ret; 2285 int i; 2286 2287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2288 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2289 2290 /* Alloc private buffer TCs */ 2291 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2292 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2293 2294 req->buf_num[i] = 2295 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2296 req->buf_num[i] |= 2297 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2298 } 2299 2300 req->shared_buf = 2301 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2302 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2303 2304 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2305 if (ret) 2306 dev_err(&hdev->pdev->dev, 2307 "rx private buffer alloc cmd failed %d\n", ret); 2308 2309 return ret; 2310 } 2311 2312 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2313 struct hclge_pkt_buf_alloc *buf_alloc) 2314 { 2315 struct hclge_rx_priv_wl_buf *req; 2316 struct hclge_priv_buf *priv; 2317 struct hclge_desc desc[2]; 2318 int i, j; 2319 int ret; 2320 2321 for (i = 0; i < 2; i++) { 2322 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2323 false); 2324 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2325 2326 /* The first descriptor set the NEXT bit to 1 */ 2327 if (i == 0) 2328 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2329 else 2330 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2331 2332 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2333 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2334 2335 priv = &buf_alloc->priv_buf[idx]; 2336 req->tc_wl[j].high = 2337 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2338 req->tc_wl[j].high |= 2339 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2340 req->tc_wl[j].low = 2341 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2342 req->tc_wl[j].low |= 2343 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2344 } 2345 } 2346 2347 /* Send 2 descriptor at one time */ 2348 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2349 if (ret) 2350 dev_err(&hdev->pdev->dev, 2351 "rx private waterline config cmd failed %d\n", 2352 ret); 2353 return ret; 2354 } 2355 2356 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2357 struct hclge_pkt_buf_alloc *buf_alloc) 2358 { 2359 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2360 struct hclge_rx_com_thrd *req; 2361 struct hclge_desc desc[2]; 2362 struct hclge_tc_thrd *tc; 2363 int i, j; 2364 int ret; 2365 2366 for (i = 0; i < 2; i++) { 2367 hclge_cmd_setup_basic_desc(&desc[i], 2368 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2369 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2370 2371 /* The first descriptor set the NEXT bit to 1 */ 2372 if (i == 0) 2373 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2374 else 2375 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2376 2377 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2378 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2379 2380 req->com_thrd[j].high = 2381 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2382 req->com_thrd[j].high |= 2383 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2384 req->com_thrd[j].low = 2385 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2386 req->com_thrd[j].low |= 2387 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2388 } 2389 } 2390 2391 /* Send 2 descriptors at one time */ 2392 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2393 if (ret) 2394 dev_err(&hdev->pdev->dev, 2395 "common threshold config cmd failed %d\n", ret); 2396 return ret; 2397 } 2398 2399 static int hclge_common_wl_config(struct hclge_dev *hdev, 2400 struct hclge_pkt_buf_alloc *buf_alloc) 2401 { 2402 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2403 struct hclge_rx_com_wl *req; 2404 struct hclge_desc desc; 2405 int ret; 2406 2407 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2408 2409 req = (struct hclge_rx_com_wl *)desc.data; 2410 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2411 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2412 2413 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2414 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2415 2416 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2417 if (ret) 2418 dev_err(&hdev->pdev->dev, 2419 "common waterline config cmd failed %d\n", ret); 2420 2421 return ret; 2422 } 2423 2424 int hclge_buffer_alloc(struct hclge_dev *hdev) 2425 { 2426 struct hclge_pkt_buf_alloc *pkt_buf; 2427 int ret; 2428 2429 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2430 if (!pkt_buf) 2431 return -ENOMEM; 2432 2433 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2434 if (ret) { 2435 dev_err(&hdev->pdev->dev, 2436 "could not calc tx buffer size for all TCs %d\n", ret); 2437 goto out; 2438 } 2439 2440 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2441 if (ret) { 2442 dev_err(&hdev->pdev->dev, 2443 "could not alloc tx buffers %d\n", ret); 2444 goto out; 2445 } 2446 2447 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2448 if (ret) { 2449 dev_err(&hdev->pdev->dev, 2450 "could not calc rx priv buffer size for all TCs %d\n", 2451 ret); 2452 goto out; 2453 } 2454 2455 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2456 if (ret) { 2457 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2458 ret); 2459 goto out; 2460 } 2461 2462 if (hnae3_dev_dcb_supported(hdev)) { 2463 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2464 if (ret) { 2465 dev_err(&hdev->pdev->dev, 2466 "could not configure rx private waterline %d\n", 2467 ret); 2468 goto out; 2469 } 2470 2471 ret = hclge_common_thrd_config(hdev, pkt_buf); 2472 if (ret) { 2473 dev_err(&hdev->pdev->dev, 2474 "could not configure common threshold %d\n", 2475 ret); 2476 goto out; 2477 } 2478 } 2479 2480 ret = hclge_common_wl_config(hdev, pkt_buf); 2481 if (ret) 2482 dev_err(&hdev->pdev->dev, 2483 "could not configure common waterline %d\n", ret); 2484 2485 out: 2486 kfree(pkt_buf); 2487 return ret; 2488 } 2489 2490 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2491 { 2492 struct hnae3_handle *roce = &vport->roce; 2493 struct hnae3_handle *nic = &vport->nic; 2494 struct hclge_dev *hdev = vport->back; 2495 2496 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2497 2498 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2499 return -EINVAL; 2500 2501 roce->rinfo.base_vector = hdev->num_nic_msi; 2502 2503 roce->rinfo.netdev = nic->kinfo.netdev; 2504 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2505 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2506 2507 roce->pdev = nic->pdev; 2508 roce->ae_algo = nic->ae_algo; 2509 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2510 MAX_NUMNODES); 2511 2512 return 0; 2513 } 2514 2515 static int hclge_init_msi(struct hclge_dev *hdev) 2516 { 2517 struct pci_dev *pdev = hdev->pdev; 2518 int vectors; 2519 int i; 2520 2521 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2522 hdev->num_msi, 2523 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2524 if (vectors < 0) { 2525 dev_err(&pdev->dev, 2526 "failed(%d) to allocate MSI/MSI-X vectors\n", 2527 vectors); 2528 return vectors; 2529 } 2530 if (vectors < hdev->num_msi) 2531 dev_warn(&hdev->pdev->dev, 2532 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2533 hdev->num_msi, vectors); 2534 2535 hdev->num_msi = vectors; 2536 hdev->num_msi_left = vectors; 2537 2538 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2539 sizeof(u16), GFP_KERNEL); 2540 if (!hdev->vector_status) { 2541 pci_free_irq_vectors(pdev); 2542 return -ENOMEM; 2543 } 2544 2545 for (i = 0; i < hdev->num_msi; i++) 2546 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2547 2548 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2549 sizeof(int), GFP_KERNEL); 2550 if (!hdev->vector_irq) { 2551 pci_free_irq_vectors(pdev); 2552 return -ENOMEM; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2559 { 2560 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2561 duplex = HCLGE_MAC_FULL; 2562 2563 return duplex; 2564 } 2565 2566 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2567 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2568 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2569 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2570 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2571 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2572 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2573 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2574 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2575 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2576 }; 2577 2578 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2579 { 2580 u16 i; 2581 2582 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2583 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2584 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2585 return 0; 2586 } 2587 } 2588 2589 return -EINVAL; 2590 } 2591 2592 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2593 u8 duplex, u8 lane_num) 2594 { 2595 struct hclge_config_mac_speed_dup_cmd *req; 2596 struct hclge_desc desc; 2597 u32 speed_fw; 2598 int ret; 2599 2600 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2601 2602 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2603 2604 if (duplex) 2605 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2606 2607 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2608 if (ret) { 2609 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2610 return ret; 2611 } 2612 2613 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2614 speed_fw); 2615 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2616 1); 2617 req->lane_num = lane_num; 2618 2619 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2620 if (ret) { 2621 dev_err(&hdev->pdev->dev, 2622 "mac speed/duplex config cmd failed %d.\n", ret); 2623 return ret; 2624 } 2625 2626 return 0; 2627 } 2628 2629 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2630 { 2631 struct hclge_mac *mac = &hdev->hw.mac; 2632 int ret; 2633 2634 duplex = hclge_check_speed_dup(duplex, speed); 2635 if (!mac->support_autoneg && mac->speed == speed && 2636 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2637 return 0; 2638 2639 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2640 if (ret) 2641 return ret; 2642 2643 hdev->hw.mac.speed = speed; 2644 hdev->hw.mac.duplex = duplex; 2645 if (!lane_num) 2646 hdev->hw.mac.lane_num = lane_num; 2647 2648 return 0; 2649 } 2650 2651 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2652 u8 duplex, u8 lane_num) 2653 { 2654 struct hclge_vport *vport = hclge_get_vport(handle); 2655 struct hclge_dev *hdev = vport->back; 2656 int ret; 2657 2658 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2659 2660 if (ret) 2661 return ret; 2662 2663 hdev->hw.mac.req_speed = speed; 2664 hdev->hw.mac.req_duplex = duplex; 2665 2666 return 0; 2667 } 2668 2669 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2670 { 2671 struct hclge_config_auto_neg_cmd *req; 2672 struct hclge_desc desc; 2673 u32 flag = 0; 2674 int ret; 2675 2676 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2677 2678 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2679 if (enable) 2680 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2681 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2682 2683 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2684 if (ret) 2685 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2686 ret); 2687 2688 return ret; 2689 } 2690 2691 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2692 { 2693 struct hclge_vport *vport = hclge_get_vport(handle); 2694 struct hclge_dev *hdev = vport->back; 2695 2696 if (!hdev->hw.mac.support_autoneg) { 2697 if (enable) { 2698 dev_err(&hdev->pdev->dev, 2699 "autoneg is not supported by current port\n"); 2700 return -EOPNOTSUPP; 2701 } else { 2702 return 0; 2703 } 2704 } 2705 2706 return hclge_set_autoneg_en(hdev, enable); 2707 } 2708 2709 static int hclge_get_autoneg(struct hnae3_handle *handle) 2710 { 2711 struct hclge_vport *vport = hclge_get_vport(handle); 2712 struct hclge_dev *hdev = vport->back; 2713 struct phy_device *phydev = hdev->hw.mac.phydev; 2714 2715 if (phydev) 2716 return phydev->autoneg; 2717 2718 return hdev->hw.mac.autoneg; 2719 } 2720 2721 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2722 { 2723 struct hclge_vport *vport = hclge_get_vport(handle); 2724 struct hclge_dev *hdev = vport->back; 2725 int ret; 2726 2727 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2728 2729 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2730 if (ret) 2731 return ret; 2732 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2733 } 2734 2735 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2736 { 2737 struct hclge_vport *vport = hclge_get_vport(handle); 2738 struct hclge_dev *hdev = vport->back; 2739 2740 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2741 return hclge_set_autoneg_en(hdev, !halt); 2742 2743 return 0; 2744 } 2745 2746 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2747 struct hclge_desc *desc, u32 desc_len) 2748 { 2749 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2750 u32 desc_index = 0; 2751 u32 data_index = 0; 2752 u32 i; 2753 2754 for (i = 0; i < lane_size; i++) { 2755 if (data_index >= HCLGE_DESC_DATA_LEN) { 2756 desc_index++; 2757 data_index = 0; 2758 } 2759 2760 if (desc_index >= desc_len) 2761 return; 2762 2763 hdev->fec_stats.per_lanes[i] += 2764 le32_to_cpu(desc[desc_index].data[data_index]); 2765 data_index++; 2766 } 2767 } 2768 2769 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2770 struct hclge_desc *desc, u32 desc_len) 2771 { 2772 struct hclge_query_fec_stats_cmd *req; 2773 2774 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2775 2776 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2777 hdev->fec_stats.rs_corr_blocks += 2778 le32_to_cpu(req->rs_fec_corr_blocks); 2779 hdev->fec_stats.rs_uncorr_blocks += 2780 le32_to_cpu(req->rs_fec_uncorr_blocks); 2781 hdev->fec_stats.rs_error_blocks += 2782 le32_to_cpu(req->rs_fec_error_blocks); 2783 hdev->fec_stats.base_r_corr_blocks += 2784 le32_to_cpu(req->base_r_fec_corr_blocks); 2785 hdev->fec_stats.base_r_uncorr_blocks += 2786 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2787 2788 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2789 } 2790 2791 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2792 { 2793 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2794 int ret; 2795 u32 i; 2796 2797 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2798 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2799 true); 2800 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2801 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2802 } 2803 2804 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2805 if (ret) 2806 return ret; 2807 2808 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2809 2810 return 0; 2811 } 2812 2813 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2814 { 2815 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2816 int ret; 2817 2818 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2819 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2820 return; 2821 2822 ret = hclge_update_fec_stats_hw(hdev); 2823 if (ret) 2824 dev_err(&hdev->pdev->dev, 2825 "failed to update fec stats, ret = %d\n", ret); 2826 2827 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2828 } 2829 2830 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2831 struct ethtool_fec_stats *fec_stats) 2832 { 2833 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2834 fec_stats->uncorrectable_blocks.total = 2835 hdev->fec_stats.rs_uncorr_blocks; 2836 } 2837 2838 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2839 struct ethtool_fec_stats *fec_stats) 2840 { 2841 u32 i; 2842 2843 if (hdev->fec_stats.base_r_lane_num == 0 || 2844 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2845 dev_err(&hdev->pdev->dev, 2846 "fec stats lane number(%llu) is invalid\n", 2847 hdev->fec_stats.base_r_lane_num); 2848 return; 2849 } 2850 2851 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2852 fec_stats->corrected_blocks.lanes[i] = 2853 hdev->fec_stats.base_r_corr_per_lanes[i]; 2854 fec_stats->uncorrectable_blocks.lanes[i] = 2855 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2856 } 2857 } 2858 2859 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2860 struct ethtool_fec_stats *fec_stats) 2861 { 2862 u32 fec_mode = hdev->hw.mac.fec_mode; 2863 2864 switch (fec_mode) { 2865 case BIT(HNAE3_FEC_RS): 2866 case BIT(HNAE3_FEC_LLRS): 2867 hclge_get_fec_stats_total(hdev, fec_stats); 2868 break; 2869 case BIT(HNAE3_FEC_BASER): 2870 hclge_get_fec_stats_lanes(hdev, fec_stats); 2871 break; 2872 default: 2873 dev_err(&hdev->pdev->dev, 2874 "fec stats is not supported by current fec mode(0x%x)\n", 2875 fec_mode); 2876 break; 2877 } 2878 } 2879 2880 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2881 struct ethtool_fec_stats *fec_stats) 2882 { 2883 struct hclge_vport *vport = hclge_get_vport(handle); 2884 struct hclge_dev *hdev = vport->back; 2885 u32 fec_mode = hdev->hw.mac.fec_mode; 2886 2887 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2888 fec_mode == BIT(HNAE3_FEC_AUTO) || 2889 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2890 return; 2891 2892 hclge_update_fec_stats(hdev); 2893 2894 hclge_comm_get_fec_stats(hdev, fec_stats); 2895 } 2896 2897 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2898 { 2899 struct hclge_config_fec_cmd *req; 2900 struct hclge_desc desc; 2901 int ret; 2902 2903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2904 2905 req = (struct hclge_config_fec_cmd *)desc.data; 2906 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2907 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2908 if (fec_mode & BIT(HNAE3_FEC_RS)) 2909 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2910 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2911 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2912 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2913 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2914 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2915 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2916 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2917 2918 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2919 if (ret) 2920 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2921 2922 return ret; 2923 } 2924 2925 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2926 { 2927 struct hclge_vport *vport = hclge_get_vport(handle); 2928 struct hclge_dev *hdev = vport->back; 2929 struct hclge_mac *mac = &hdev->hw.mac; 2930 int ret; 2931 2932 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2933 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2934 return -EINVAL; 2935 } 2936 2937 ret = hclge_set_fec_hw(hdev, fec_mode); 2938 if (ret) 2939 return ret; 2940 2941 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2942 return 0; 2943 } 2944 2945 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2946 u8 *fec_mode) 2947 { 2948 struct hclge_vport *vport = hclge_get_vport(handle); 2949 struct hclge_dev *hdev = vport->back; 2950 struct hclge_mac *mac = &hdev->hw.mac; 2951 2952 if (fec_ability) 2953 *fec_ability = mac->fec_ability; 2954 if (fec_mode) 2955 *fec_mode = mac->fec_mode; 2956 } 2957 2958 static int hclge_mac_init(struct hclge_dev *hdev) 2959 { 2960 struct hclge_mac *mac = &hdev->hw.mac; 2961 int ret; 2962 2963 hdev->support_sfp_query = true; 2964 2965 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2966 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2967 2968 if (hdev->hw.mac.support_autoneg) { 2969 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2970 if (ret) 2971 return ret; 2972 } 2973 2974 if (!hdev->hw.mac.autoneg) { 2975 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2976 hdev->hw.mac.req_duplex, 2977 hdev->hw.mac.lane_num); 2978 if (ret) 2979 return ret; 2980 } 2981 2982 mac->link = 0; 2983 2984 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2985 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2986 if (ret) 2987 return ret; 2988 } 2989 2990 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2991 if (ret) { 2992 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2993 return ret; 2994 } 2995 2996 ret = hclge_set_default_loopback(hdev); 2997 if (ret) 2998 return ret; 2999 3000 ret = hclge_buffer_alloc(hdev); 3001 if (ret) 3002 dev_err(&hdev->pdev->dev, 3003 "allocate buffer fail, ret=%d\n", ret); 3004 3005 return ret; 3006 } 3007 3008 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3009 { 3010 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3011 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3012 hdev->last_mbx_scheduled = jiffies; 3013 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3014 } 3015 } 3016 3017 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3018 { 3019 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3020 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3021 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3022 hdev->last_rst_scheduled = jiffies; 3023 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3024 } 3025 } 3026 3027 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3028 { 3029 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3030 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3031 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3032 } 3033 3034 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3035 { 3036 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3037 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3038 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3039 } 3040 3041 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3042 { 3043 struct hclge_link_status_cmd *req; 3044 struct hclge_desc desc; 3045 int ret; 3046 3047 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3048 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3049 if (ret) { 3050 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3051 ret); 3052 return ret; 3053 } 3054 3055 req = (struct hclge_link_status_cmd *)desc.data; 3056 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3057 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3058 3059 return 0; 3060 } 3061 3062 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3063 { 3064 struct phy_device *phydev = hdev->hw.mac.phydev; 3065 3066 *link_status = HCLGE_LINK_STATUS_DOWN; 3067 3068 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3069 return 0; 3070 3071 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3072 return 0; 3073 3074 return hclge_get_mac_link_status(hdev, link_status); 3075 } 3076 3077 static void hclge_push_link_status(struct hclge_dev *hdev) 3078 { 3079 struct hclge_vport *vport; 3080 int ret; 3081 u16 i; 3082 3083 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3084 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3085 3086 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3087 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3088 continue; 3089 3090 ret = hclge_push_vf_link_status(vport); 3091 if (ret) { 3092 dev_err(&hdev->pdev->dev, 3093 "failed to push link status to vf%u, ret = %d\n", 3094 i, ret); 3095 } 3096 } 3097 } 3098 3099 static void hclge_update_link_status(struct hclge_dev *hdev) 3100 { 3101 struct hnae3_handle *handle = &hdev->vport[0].nic; 3102 struct hnae3_client *client = hdev->nic_client; 3103 int state; 3104 int ret; 3105 3106 if (!client) 3107 return; 3108 3109 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3110 return; 3111 3112 ret = hclge_get_mac_phy_link(hdev, &state); 3113 if (ret) { 3114 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3115 return; 3116 } 3117 3118 if (state != hdev->hw.mac.link) { 3119 hdev->hw.mac.link = state; 3120 if (state == HCLGE_LINK_STATUS_UP) 3121 hclge_update_port_info(hdev); 3122 3123 client->ops->link_status_change(handle, state); 3124 hclge_config_mac_tnl_int(hdev, state); 3125 3126 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3127 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3128 struct hnae3_client *rclient = hdev->roce_client; 3129 3130 if (rclient && rclient->ops->link_status_change) 3131 rclient->ops->link_status_change(rhandle, 3132 state); 3133 } 3134 3135 hclge_push_link_status(hdev); 3136 } 3137 3138 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3139 } 3140 3141 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3142 { 3143 u32 speed_ability; 3144 3145 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3146 return; 3147 3148 switch (mac->module_type) { 3149 case HNAE3_MODULE_TYPE_FIBRE_LR: 3150 hclge_convert_setting_lr(speed_ability, mac->advertising); 3151 break; 3152 case HNAE3_MODULE_TYPE_FIBRE_SR: 3153 case HNAE3_MODULE_TYPE_AOC: 3154 hclge_convert_setting_sr(speed_ability, mac->advertising); 3155 break; 3156 case HNAE3_MODULE_TYPE_CR: 3157 hclge_convert_setting_cr(speed_ability, mac->advertising); 3158 break; 3159 case HNAE3_MODULE_TYPE_KR: 3160 hclge_convert_setting_kr(speed_ability, mac->advertising); 3161 break; 3162 default: 3163 break; 3164 } 3165 } 3166 3167 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3168 { 3169 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3170 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3171 mac->advertising); 3172 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3173 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3174 mac->advertising); 3175 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3176 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3177 mac->advertising); 3178 else 3179 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3180 mac->advertising); 3181 } 3182 3183 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3184 { 3185 struct hclge_mac *mac = &hdev->hw.mac; 3186 bool rx_en, tx_en; 3187 3188 switch (hdev->fc_mode_last_time) { 3189 case HCLGE_FC_RX_PAUSE: 3190 rx_en = true; 3191 tx_en = false; 3192 break; 3193 case HCLGE_FC_TX_PAUSE: 3194 rx_en = false; 3195 tx_en = true; 3196 break; 3197 case HCLGE_FC_FULL: 3198 rx_en = true; 3199 tx_en = true; 3200 break; 3201 default: 3202 rx_en = false; 3203 tx_en = false; 3204 break; 3205 } 3206 3207 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3208 } 3209 3210 static void hclge_update_advertising(struct hclge_dev *hdev) 3211 { 3212 struct hclge_mac *mac = &hdev->hw.mac; 3213 3214 linkmode_zero(mac->advertising); 3215 hclge_update_speed_advertising(mac); 3216 hclge_update_fec_advertising(mac); 3217 hclge_update_pause_advertising(hdev); 3218 } 3219 3220 static void hclge_update_port_capability(struct hclge_dev *hdev, 3221 struct hclge_mac *mac) 3222 { 3223 if (hnae3_dev_fec_supported(hdev)) 3224 hclge_convert_setting_fec(mac); 3225 3226 /* firmware can not identify back plane type, the media type 3227 * read from configuration can help deal it 3228 */ 3229 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3230 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3231 mac->module_type = HNAE3_MODULE_TYPE_KR; 3232 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3233 mac->module_type = HNAE3_MODULE_TYPE_TP; 3234 3235 if (mac->support_autoneg) { 3236 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3237 linkmode_copy(mac->advertising, mac->supported); 3238 } else { 3239 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3240 mac->supported); 3241 hclge_update_advertising(hdev); 3242 } 3243 } 3244 3245 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3246 { 3247 struct hclge_sfp_info_cmd *resp; 3248 struct hclge_desc desc; 3249 int ret; 3250 3251 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3252 resp = (struct hclge_sfp_info_cmd *)desc.data; 3253 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3254 if (ret == -EOPNOTSUPP) { 3255 dev_warn(&hdev->pdev->dev, 3256 "IMP do not support get SFP speed %d\n", ret); 3257 return ret; 3258 } else if (ret) { 3259 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3260 return ret; 3261 } 3262 3263 *speed = le32_to_cpu(resp->speed); 3264 3265 return 0; 3266 } 3267 3268 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3269 { 3270 struct hclge_sfp_info_cmd *resp; 3271 struct hclge_desc desc; 3272 int ret; 3273 3274 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3275 resp = (struct hclge_sfp_info_cmd *)desc.data; 3276 3277 resp->query_type = QUERY_ACTIVE_SPEED; 3278 3279 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3280 if (ret == -EOPNOTSUPP) { 3281 dev_warn(&hdev->pdev->dev, 3282 "IMP does not support get SFP info %d\n", ret); 3283 return ret; 3284 } else if (ret) { 3285 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3286 return ret; 3287 } 3288 3289 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3290 * set to mac->speed. 3291 */ 3292 if (!le32_to_cpu(resp->speed)) 3293 return 0; 3294 3295 mac->speed = le32_to_cpu(resp->speed); 3296 /* if resp->speed_ability is 0, it means it's an old version 3297 * firmware, do not update these params 3298 */ 3299 if (resp->speed_ability) { 3300 mac->module_type = le32_to_cpu(resp->module_type); 3301 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3302 mac->autoneg = resp->autoneg; 3303 mac->support_autoneg = resp->autoneg_ability; 3304 mac->speed_type = QUERY_ACTIVE_SPEED; 3305 mac->lane_num = resp->lane_num; 3306 if (!resp->active_fec) 3307 mac->fec_mode = 0; 3308 else 3309 mac->fec_mode = BIT(resp->active_fec); 3310 mac->fec_ability = resp->fec_ability; 3311 } else { 3312 mac->speed_type = QUERY_SFP_SPEED; 3313 } 3314 3315 return 0; 3316 } 3317 3318 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3319 struct ethtool_link_ksettings *cmd) 3320 { 3321 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3322 struct hclge_vport *vport = hclge_get_vport(handle); 3323 struct hclge_phy_link_ksetting_0_cmd *req0; 3324 struct hclge_phy_link_ksetting_1_cmd *req1; 3325 u32 supported, advertising, lp_advertising; 3326 struct hclge_dev *hdev = vport->back; 3327 int ret; 3328 3329 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3330 true); 3331 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3332 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3333 true); 3334 3335 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3336 if (ret) { 3337 dev_err(&hdev->pdev->dev, 3338 "failed to get phy link ksetting, ret = %d.\n", ret); 3339 return ret; 3340 } 3341 3342 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3343 cmd->base.autoneg = req0->autoneg; 3344 cmd->base.speed = le32_to_cpu(req0->speed); 3345 cmd->base.duplex = req0->duplex; 3346 cmd->base.port = req0->port; 3347 cmd->base.transceiver = req0->transceiver; 3348 cmd->base.phy_address = req0->phy_address; 3349 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3350 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3351 supported = le32_to_cpu(req0->supported); 3352 advertising = le32_to_cpu(req0->advertising); 3353 lp_advertising = le32_to_cpu(req0->lp_advertising); 3354 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3355 supported); 3356 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3357 advertising); 3358 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3359 lp_advertising); 3360 3361 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3362 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3363 cmd->base.master_slave_state = req1->master_slave_state; 3364 3365 return 0; 3366 } 3367 3368 static int 3369 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3370 const struct ethtool_link_ksettings *cmd) 3371 { 3372 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3373 struct hclge_vport *vport = hclge_get_vport(handle); 3374 struct hclge_phy_link_ksetting_0_cmd *req0; 3375 struct hclge_phy_link_ksetting_1_cmd *req1; 3376 struct hclge_dev *hdev = vport->back; 3377 u32 advertising; 3378 int ret; 3379 3380 if (cmd->base.autoneg == AUTONEG_DISABLE && 3381 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3382 (cmd->base.duplex != DUPLEX_HALF && 3383 cmd->base.duplex != DUPLEX_FULL))) 3384 return -EINVAL; 3385 3386 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3387 false); 3388 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3389 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3390 false); 3391 3392 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3393 req0->autoneg = cmd->base.autoneg; 3394 req0->speed = cpu_to_le32(cmd->base.speed); 3395 req0->duplex = cmd->base.duplex; 3396 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3397 cmd->link_modes.advertising); 3398 req0->advertising = cpu_to_le32(advertising); 3399 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3400 3401 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3402 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3403 3404 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3405 if (ret) { 3406 dev_err(&hdev->pdev->dev, 3407 "failed to set phy link ksettings, ret = %d.\n", ret); 3408 return ret; 3409 } 3410 3411 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3412 hdev->hw.mac.req_speed = cmd->base.speed; 3413 hdev->hw.mac.req_duplex = cmd->base.duplex; 3414 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3415 3416 return 0; 3417 } 3418 3419 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3420 { 3421 struct ethtool_link_ksettings cmd; 3422 int ret; 3423 3424 if (!hnae3_dev_phy_imp_supported(hdev)) 3425 return 0; 3426 3427 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3428 if (ret) 3429 return ret; 3430 3431 hdev->hw.mac.autoneg = cmd.base.autoneg; 3432 hdev->hw.mac.speed = cmd.base.speed; 3433 hdev->hw.mac.duplex = cmd.base.duplex; 3434 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3435 3436 return 0; 3437 } 3438 3439 static int hclge_tp_port_init(struct hclge_dev *hdev) 3440 { 3441 struct ethtool_link_ksettings cmd; 3442 3443 if (!hnae3_dev_phy_imp_supported(hdev)) 3444 return 0; 3445 3446 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3447 cmd.base.speed = hdev->hw.mac.req_speed; 3448 cmd.base.duplex = hdev->hw.mac.req_duplex; 3449 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3450 3451 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3452 } 3453 3454 static int hclge_update_port_info(struct hclge_dev *hdev) 3455 { 3456 struct hclge_mac *mac = &hdev->hw.mac; 3457 int speed; 3458 int ret; 3459 3460 /* get the port info from SFP cmd if not copper port */ 3461 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3462 return hclge_update_tp_port_info(hdev); 3463 3464 /* if IMP does not support get SFP/qSFP info, return directly */ 3465 if (!hdev->support_sfp_query) 3466 return 0; 3467 3468 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3469 speed = mac->speed; 3470 ret = hclge_get_sfp_info(hdev, mac); 3471 } else { 3472 speed = HCLGE_MAC_SPEED_UNKNOWN; 3473 ret = hclge_get_sfp_speed(hdev, &speed); 3474 } 3475 3476 if (ret == -EOPNOTSUPP) { 3477 hdev->support_sfp_query = false; 3478 return ret; 3479 } else if (ret) { 3480 return ret; 3481 } 3482 3483 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3484 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3485 hclge_update_port_capability(hdev, mac); 3486 if (mac->speed != speed) 3487 (void)hclge_tm_port_shaper_cfg(hdev); 3488 return 0; 3489 } 3490 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3491 HCLGE_MAC_FULL, mac->lane_num); 3492 } else { 3493 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3494 return 0; /* do nothing if no SFP */ 3495 3496 /* must config full duplex for SFP */ 3497 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3498 } 3499 } 3500 3501 static int hclge_get_status(struct hnae3_handle *handle) 3502 { 3503 struct hclge_vport *vport = hclge_get_vport(handle); 3504 struct hclge_dev *hdev = vport->back; 3505 3506 hclge_update_link_status(hdev); 3507 3508 return hdev->hw.mac.link; 3509 } 3510 3511 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3512 { 3513 if (!pci_num_vf(hdev->pdev)) { 3514 dev_err(&hdev->pdev->dev, 3515 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3516 return NULL; 3517 } 3518 3519 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3520 dev_err(&hdev->pdev->dev, 3521 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3522 vf, pci_num_vf(hdev->pdev)); 3523 return NULL; 3524 } 3525 3526 /* VF start from 1 in vport */ 3527 vf += HCLGE_VF_VPORT_START_NUM; 3528 return &hdev->vport[vf]; 3529 } 3530 3531 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3532 struct ifla_vf_info *ivf) 3533 { 3534 struct hclge_vport *vport = hclge_get_vport(handle); 3535 struct hclge_dev *hdev = vport->back; 3536 3537 vport = hclge_get_vf_vport(hdev, vf); 3538 if (!vport) 3539 return -EINVAL; 3540 3541 ivf->vf = vf; 3542 ivf->linkstate = vport->vf_info.link_state; 3543 ivf->spoofchk = vport->vf_info.spoofchk; 3544 ivf->trusted = vport->vf_info.trusted; 3545 ivf->min_tx_rate = 0; 3546 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3547 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3548 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3549 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3550 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3551 3552 return 0; 3553 } 3554 3555 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3556 int link_state) 3557 { 3558 struct hclge_vport *vport = hclge_get_vport(handle); 3559 struct hclge_dev *hdev = vport->back; 3560 int link_state_old; 3561 int ret; 3562 3563 vport = hclge_get_vf_vport(hdev, vf); 3564 if (!vport) 3565 return -EINVAL; 3566 3567 link_state_old = vport->vf_info.link_state; 3568 vport->vf_info.link_state = link_state; 3569 3570 /* return success directly if the VF is unalive, VF will 3571 * query link state itself when it starts work. 3572 */ 3573 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3574 return 0; 3575 3576 ret = hclge_push_vf_link_status(vport); 3577 if (ret) { 3578 vport->vf_info.link_state = link_state_old; 3579 dev_err(&hdev->pdev->dev, 3580 "failed to push vf%d link status, ret = %d\n", vf, ret); 3581 } 3582 3583 return ret; 3584 } 3585 3586 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3587 { 3588 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3589 3590 /* fetch the events from their corresponding regs */ 3591 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3592 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3593 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3594 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3595 3596 /* Assumption: If by any chance reset and mailbox events are reported 3597 * together then we will only process reset event in this go and will 3598 * defer the processing of the mailbox events. Since, we would have not 3599 * cleared RX CMDQ event this time we would receive again another 3600 * interrupt from H/W just for the mailbox. 3601 * 3602 * check for vector0 reset event sources 3603 */ 3604 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3605 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3606 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3607 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3608 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3609 hdev->rst_stats.imp_rst_cnt++; 3610 return HCLGE_VECTOR0_EVENT_RST; 3611 } 3612 3613 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3614 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3615 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3616 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3617 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3618 hdev->rst_stats.global_rst_cnt++; 3619 return HCLGE_VECTOR0_EVENT_RST; 3620 } 3621 3622 /* check for vector0 msix event and hardware error event source */ 3623 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3624 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3625 return HCLGE_VECTOR0_EVENT_ERR; 3626 3627 /* check for vector0 ptp event source */ 3628 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3629 *clearval = msix_src_reg; 3630 return HCLGE_VECTOR0_EVENT_PTP; 3631 } 3632 3633 /* check for vector0 mailbox(=CMDQ RX) event source */ 3634 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3635 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3636 *clearval = cmdq_src_reg; 3637 return HCLGE_VECTOR0_EVENT_MBX; 3638 } 3639 3640 /* print other vector0 event source */ 3641 dev_info(&hdev->pdev->dev, 3642 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3643 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3644 3645 return HCLGE_VECTOR0_EVENT_OTHER; 3646 } 3647 3648 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3649 u32 regclr) 3650 { 3651 #define HCLGE_IMP_RESET_DELAY 5 3652 3653 switch (event_type) { 3654 case HCLGE_VECTOR0_EVENT_PTP: 3655 case HCLGE_VECTOR0_EVENT_RST: 3656 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3657 mdelay(HCLGE_IMP_RESET_DELAY); 3658 3659 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3660 break; 3661 case HCLGE_VECTOR0_EVENT_MBX: 3662 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3663 break; 3664 default: 3665 break; 3666 } 3667 } 3668 3669 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3670 { 3671 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3672 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3673 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3674 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3675 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3676 } 3677 3678 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3679 { 3680 writel(enable ? 1 : 0, vector->addr); 3681 } 3682 3683 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3684 { 3685 struct hclge_dev *hdev = data; 3686 unsigned long flags; 3687 u32 clearval = 0; 3688 u32 event_cause; 3689 3690 hclge_enable_vector(&hdev->misc_vector, false); 3691 event_cause = hclge_check_event_cause(hdev, &clearval); 3692 3693 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3694 switch (event_cause) { 3695 case HCLGE_VECTOR0_EVENT_ERR: 3696 hclge_errhand_task_schedule(hdev); 3697 break; 3698 case HCLGE_VECTOR0_EVENT_RST: 3699 hclge_reset_task_schedule(hdev); 3700 break; 3701 case HCLGE_VECTOR0_EVENT_PTP: 3702 spin_lock_irqsave(&hdev->ptp->lock, flags); 3703 hclge_ptp_clean_tx_hwts(hdev); 3704 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3705 break; 3706 case HCLGE_VECTOR0_EVENT_MBX: 3707 /* If we are here then, 3708 * 1. Either we are not handling any mbx task and we are not 3709 * scheduled as well 3710 * OR 3711 * 2. We could be handling a mbx task but nothing more is 3712 * scheduled. 3713 * In both cases, we should schedule mbx task as there are more 3714 * mbx messages reported by this interrupt. 3715 */ 3716 hclge_mbx_task_schedule(hdev); 3717 break; 3718 default: 3719 dev_warn(&hdev->pdev->dev, 3720 "received unknown or unhandled event of vector0\n"); 3721 break; 3722 } 3723 3724 hclge_clear_event_cause(hdev, event_cause, clearval); 3725 3726 /* Enable interrupt if it is not caused by reset event or error event */ 3727 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3728 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3729 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3730 hclge_enable_vector(&hdev->misc_vector, true); 3731 3732 return IRQ_HANDLED; 3733 } 3734 3735 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3736 { 3737 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3738 dev_warn(&hdev->pdev->dev, 3739 "vector(vector_id %d) has been freed.\n", vector_id); 3740 return; 3741 } 3742 3743 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3744 hdev->num_msi_left += 1; 3745 hdev->num_msi_used -= 1; 3746 } 3747 3748 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3749 { 3750 struct hclge_misc_vector *vector = &hdev->misc_vector; 3751 3752 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3753 3754 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3755 hdev->vector_status[0] = 0; 3756 3757 hdev->num_msi_left -= 1; 3758 hdev->num_msi_used += 1; 3759 } 3760 3761 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3762 { 3763 int ret; 3764 3765 hclge_get_misc_vector(hdev); 3766 3767 /* this would be explicitly freed in the end */ 3768 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3769 HCLGE_NAME, pci_name(hdev->pdev)); 3770 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3771 0, hdev->misc_vector.name, hdev); 3772 if (ret) { 3773 hclge_free_vector(hdev, 0); 3774 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3775 hdev->misc_vector.vector_irq); 3776 } 3777 3778 return ret; 3779 } 3780 3781 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3782 { 3783 free_irq(hdev->misc_vector.vector_irq, hdev); 3784 hclge_free_vector(hdev, 0); 3785 } 3786 3787 int hclge_notify_client(struct hclge_dev *hdev, 3788 enum hnae3_reset_notify_type type) 3789 { 3790 struct hnae3_handle *handle = &hdev->vport[0].nic; 3791 struct hnae3_client *client = hdev->nic_client; 3792 int ret; 3793 3794 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3795 return 0; 3796 3797 if (!client->ops->reset_notify) 3798 return -EOPNOTSUPP; 3799 3800 ret = client->ops->reset_notify(handle, type); 3801 if (ret) 3802 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3803 type, ret); 3804 3805 return ret; 3806 } 3807 3808 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3809 enum hnae3_reset_notify_type type) 3810 { 3811 struct hnae3_handle *handle = &hdev->vport[0].roce; 3812 struct hnae3_client *client = hdev->roce_client; 3813 int ret; 3814 3815 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3816 return 0; 3817 3818 if (!client->ops->reset_notify) 3819 return -EOPNOTSUPP; 3820 3821 ret = client->ops->reset_notify(handle, type); 3822 if (ret) 3823 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3824 type, ret); 3825 3826 return ret; 3827 } 3828 3829 static int hclge_reset_wait(struct hclge_dev *hdev) 3830 { 3831 #define HCLGE_RESET_WATI_MS 100 3832 #define HCLGE_RESET_WAIT_CNT 350 3833 3834 u32 val, reg, reg_bit; 3835 u32 cnt = 0; 3836 3837 switch (hdev->reset_type) { 3838 case HNAE3_IMP_RESET: 3839 reg = HCLGE_GLOBAL_RESET_REG; 3840 reg_bit = HCLGE_IMP_RESET_BIT; 3841 break; 3842 case HNAE3_GLOBAL_RESET: 3843 reg = HCLGE_GLOBAL_RESET_REG; 3844 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3845 break; 3846 case HNAE3_FUNC_RESET: 3847 reg = HCLGE_FUN_RST_ING; 3848 reg_bit = HCLGE_FUN_RST_ING_B; 3849 break; 3850 default: 3851 dev_err(&hdev->pdev->dev, 3852 "Wait for unsupported reset type: %d\n", 3853 hdev->reset_type); 3854 return -EINVAL; 3855 } 3856 3857 val = hclge_read_dev(&hdev->hw, reg); 3858 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3859 msleep(HCLGE_RESET_WATI_MS); 3860 val = hclge_read_dev(&hdev->hw, reg); 3861 cnt++; 3862 } 3863 3864 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3865 dev_warn(&hdev->pdev->dev, 3866 "Wait for reset timeout: %d\n", hdev->reset_type); 3867 return -EBUSY; 3868 } 3869 3870 return 0; 3871 } 3872 3873 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3874 { 3875 struct hclge_vf_rst_cmd *req; 3876 struct hclge_desc desc; 3877 3878 req = (struct hclge_vf_rst_cmd *)desc.data; 3879 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3880 req->dest_vfid = func_id; 3881 3882 if (reset) 3883 req->vf_rst = 0x1; 3884 3885 return hclge_cmd_send(&hdev->hw, &desc, 1); 3886 } 3887 3888 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3889 { 3890 int i; 3891 3892 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3893 struct hclge_vport *vport = &hdev->vport[i]; 3894 int ret; 3895 3896 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3897 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3898 if (ret) { 3899 dev_err(&hdev->pdev->dev, 3900 "set vf(%u) rst failed %d!\n", 3901 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3902 ret); 3903 return ret; 3904 } 3905 3906 if (!reset || 3907 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3908 continue; 3909 3910 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3911 hdev->reset_type == HNAE3_FUNC_RESET) { 3912 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3913 &vport->need_notify); 3914 continue; 3915 } 3916 3917 /* Inform VF to process the reset. 3918 * hclge_inform_reset_assert_to_vf may fail if VF 3919 * driver is not loaded. 3920 */ 3921 ret = hclge_inform_reset_assert_to_vf(vport); 3922 if (ret) 3923 dev_warn(&hdev->pdev->dev, 3924 "inform reset to vf(%u) failed %d!\n", 3925 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3926 ret); 3927 } 3928 3929 return 0; 3930 } 3931 3932 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3933 { 3934 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3935 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3936 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3937 return; 3938 3939 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3940 HCLGE_MBX_SCHED_TIMEOUT)) 3941 dev_warn(&hdev->pdev->dev, 3942 "mbx service task is scheduled after %ums on cpu%u!\n", 3943 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3944 smp_processor_id()); 3945 3946 hclge_mbx_handler(hdev); 3947 3948 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3949 } 3950 3951 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3952 { 3953 struct hclge_pf_rst_sync_cmd *req; 3954 struct hclge_desc desc; 3955 int cnt = 0; 3956 int ret; 3957 3958 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3959 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3960 3961 do { 3962 /* vf need to down netdev by mbx during PF or FLR reset */ 3963 hclge_mailbox_service_task(hdev); 3964 3965 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3966 /* for compatible with old firmware, wait 3967 * 100 ms for VF to stop IO 3968 */ 3969 if (ret == -EOPNOTSUPP) { 3970 msleep(HCLGE_RESET_SYNC_TIME); 3971 return; 3972 } else if (ret) { 3973 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3974 ret); 3975 return; 3976 } else if (req->all_vf_ready) { 3977 return; 3978 } 3979 msleep(HCLGE_PF_RESET_SYNC_TIME); 3980 hclge_comm_cmd_reuse_desc(&desc, true); 3981 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3982 3983 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3984 } 3985 3986 void hclge_report_hw_error(struct hclge_dev *hdev, 3987 enum hnae3_hw_error_type type) 3988 { 3989 struct hnae3_client *client = hdev->nic_client; 3990 3991 if (!client || !client->ops->process_hw_error || 3992 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3993 return; 3994 3995 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3996 } 3997 3998 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3999 { 4000 u32 reg_val; 4001 4002 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4003 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4004 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4005 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4006 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4007 } 4008 4009 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4010 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4011 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4012 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4013 } 4014 } 4015 4016 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4017 { 4018 struct hclge_desc desc; 4019 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4020 int ret; 4021 4022 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4023 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4024 req->fun_reset_vfid = func_id; 4025 4026 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4027 if (ret) 4028 dev_err(&hdev->pdev->dev, 4029 "send function reset cmd fail, status =%d\n", ret); 4030 4031 return ret; 4032 } 4033 4034 static void hclge_do_reset(struct hclge_dev *hdev) 4035 { 4036 struct hnae3_handle *handle = &hdev->vport[0].nic; 4037 struct pci_dev *pdev = hdev->pdev; 4038 u32 val; 4039 4040 if (hclge_get_hw_reset_stat(handle)) { 4041 dev_info(&pdev->dev, "hardware reset not finish\n"); 4042 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4043 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4044 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4045 return; 4046 } 4047 4048 switch (hdev->reset_type) { 4049 case HNAE3_IMP_RESET: 4050 dev_info(&pdev->dev, "IMP reset requested\n"); 4051 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4052 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4053 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4054 break; 4055 case HNAE3_GLOBAL_RESET: 4056 dev_info(&pdev->dev, "global reset requested\n"); 4057 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4058 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4059 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4060 break; 4061 case HNAE3_FUNC_RESET: 4062 dev_info(&pdev->dev, "PF reset requested\n"); 4063 /* schedule again to check later */ 4064 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4065 hclge_reset_task_schedule(hdev); 4066 break; 4067 default: 4068 dev_warn(&pdev->dev, 4069 "unsupported reset type: %d\n", hdev->reset_type); 4070 break; 4071 } 4072 } 4073 4074 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4075 unsigned long *addr) 4076 { 4077 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4078 struct hclge_dev *hdev = ae_dev->priv; 4079 4080 /* return the highest priority reset level amongst all */ 4081 if (test_bit(HNAE3_IMP_RESET, addr)) { 4082 rst_level = HNAE3_IMP_RESET; 4083 clear_bit(HNAE3_IMP_RESET, addr); 4084 clear_bit(HNAE3_GLOBAL_RESET, addr); 4085 clear_bit(HNAE3_FUNC_RESET, addr); 4086 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4087 rst_level = HNAE3_GLOBAL_RESET; 4088 clear_bit(HNAE3_GLOBAL_RESET, addr); 4089 clear_bit(HNAE3_FUNC_RESET, addr); 4090 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4091 rst_level = HNAE3_FUNC_RESET; 4092 clear_bit(HNAE3_FUNC_RESET, addr); 4093 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4094 rst_level = HNAE3_FLR_RESET; 4095 clear_bit(HNAE3_FLR_RESET, addr); 4096 } 4097 4098 if (hdev->reset_type != HNAE3_NONE_RESET && 4099 rst_level < hdev->reset_type) 4100 return HNAE3_NONE_RESET; 4101 4102 return rst_level; 4103 } 4104 4105 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4106 { 4107 u32 clearval = 0; 4108 4109 switch (hdev->reset_type) { 4110 case HNAE3_IMP_RESET: 4111 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4112 break; 4113 case HNAE3_GLOBAL_RESET: 4114 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4115 break; 4116 default: 4117 break; 4118 } 4119 4120 if (!clearval) 4121 return; 4122 4123 /* For revision 0x20, the reset interrupt source 4124 * can only be cleared after hardware reset done 4125 */ 4126 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4127 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4128 clearval); 4129 4130 hclge_enable_vector(&hdev->misc_vector, true); 4131 } 4132 4133 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4134 { 4135 u32 reg_val; 4136 4137 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4138 if (enable) 4139 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4140 else 4141 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4142 4143 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4144 } 4145 4146 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4147 { 4148 int ret; 4149 4150 ret = hclge_set_all_vf_rst(hdev, true); 4151 if (ret) 4152 return ret; 4153 4154 hclge_func_reset_sync_vf(hdev); 4155 4156 return 0; 4157 } 4158 4159 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4160 { 4161 u32 reg_val; 4162 int ret = 0; 4163 4164 switch (hdev->reset_type) { 4165 case HNAE3_FUNC_RESET: 4166 ret = hclge_func_reset_notify_vf(hdev); 4167 if (ret) 4168 return ret; 4169 4170 ret = hclge_func_reset_cmd(hdev, 0); 4171 if (ret) { 4172 dev_err(&hdev->pdev->dev, 4173 "asserting function reset fail %d!\n", ret); 4174 return ret; 4175 } 4176 4177 /* After performaning pf reset, it is not necessary to do the 4178 * mailbox handling or send any command to firmware, because 4179 * any mailbox handling or command to firmware is only valid 4180 * after hclge_comm_cmd_init is called. 4181 */ 4182 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4183 hdev->rst_stats.pf_rst_cnt++; 4184 break; 4185 case HNAE3_FLR_RESET: 4186 ret = hclge_func_reset_notify_vf(hdev); 4187 if (ret) 4188 return ret; 4189 break; 4190 case HNAE3_IMP_RESET: 4191 hclge_handle_imp_error(hdev); 4192 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4193 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4194 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4195 break; 4196 default: 4197 break; 4198 } 4199 4200 /* inform hardware that preparatory work is done */ 4201 msleep(HCLGE_RESET_SYNC_TIME); 4202 hclge_reset_handshake(hdev, true); 4203 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4204 4205 return ret; 4206 } 4207 4208 static void hclge_show_rst_info(struct hclge_dev *hdev) 4209 { 4210 char *buf; 4211 4212 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4213 if (!buf) 4214 return; 4215 4216 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4217 4218 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4219 4220 kfree(buf); 4221 } 4222 4223 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4224 { 4225 #define MAX_RESET_FAIL_CNT 5 4226 4227 if (hdev->reset_pending) { 4228 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4229 hdev->reset_pending); 4230 return true; 4231 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4232 HCLGE_RESET_INT_M) { 4233 dev_info(&hdev->pdev->dev, 4234 "reset failed because new reset interrupt\n"); 4235 hclge_clear_reset_cause(hdev); 4236 return false; 4237 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4238 hdev->rst_stats.reset_fail_cnt++; 4239 set_bit(hdev->reset_type, &hdev->reset_pending); 4240 dev_info(&hdev->pdev->dev, 4241 "re-schedule reset task(%u)\n", 4242 hdev->rst_stats.reset_fail_cnt); 4243 return true; 4244 } 4245 4246 hclge_clear_reset_cause(hdev); 4247 4248 /* recover the handshake status when reset fail */ 4249 hclge_reset_handshake(hdev, true); 4250 4251 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4252 4253 hclge_show_rst_info(hdev); 4254 4255 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4256 4257 return false; 4258 } 4259 4260 static void hclge_update_reset_level(struct hclge_dev *hdev) 4261 { 4262 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4263 enum hnae3_reset_type reset_level; 4264 4265 /* reset request will not be set during reset, so clear 4266 * pending reset request to avoid unnecessary reset 4267 * caused by the same reason. 4268 */ 4269 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4270 4271 /* if default_reset_request has a higher level reset request, 4272 * it should be handled as soon as possible. since some errors 4273 * need this kind of reset to fix. 4274 */ 4275 reset_level = hclge_get_reset_level(ae_dev, 4276 &hdev->default_reset_request); 4277 if (reset_level != HNAE3_NONE_RESET) 4278 set_bit(reset_level, &hdev->reset_request); 4279 } 4280 4281 static int hclge_set_rst_done(struct hclge_dev *hdev) 4282 { 4283 struct hclge_pf_rst_done_cmd *req; 4284 struct hclge_desc desc; 4285 int ret; 4286 4287 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4288 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4289 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4290 4291 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4292 /* To be compatible with the old firmware, which does not support 4293 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4294 * return success 4295 */ 4296 if (ret == -EOPNOTSUPP) { 4297 dev_warn(&hdev->pdev->dev, 4298 "current firmware does not support command(0x%x)!\n", 4299 HCLGE_OPC_PF_RST_DONE); 4300 return 0; 4301 } else if (ret) { 4302 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4303 ret); 4304 } 4305 4306 return ret; 4307 } 4308 4309 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4310 { 4311 int ret = 0; 4312 4313 switch (hdev->reset_type) { 4314 case HNAE3_FUNC_RESET: 4315 case HNAE3_FLR_RESET: 4316 ret = hclge_set_all_vf_rst(hdev, false); 4317 break; 4318 case HNAE3_GLOBAL_RESET: 4319 case HNAE3_IMP_RESET: 4320 ret = hclge_set_rst_done(hdev); 4321 break; 4322 default: 4323 break; 4324 } 4325 4326 /* clear up the handshake status after re-initialize done */ 4327 hclge_reset_handshake(hdev, false); 4328 4329 return ret; 4330 } 4331 4332 static int hclge_reset_stack(struct hclge_dev *hdev) 4333 { 4334 int ret; 4335 4336 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4337 if (ret) 4338 return ret; 4339 4340 ret = hclge_reset_ae_dev(hdev->ae_dev); 4341 if (ret) 4342 return ret; 4343 4344 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4345 } 4346 4347 static int hclge_reset_prepare(struct hclge_dev *hdev) 4348 { 4349 int ret; 4350 4351 hdev->rst_stats.reset_cnt++; 4352 /* perform reset of the stack & ae device for a client */ 4353 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4354 if (ret) 4355 return ret; 4356 4357 rtnl_lock(); 4358 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4359 rtnl_unlock(); 4360 if (ret) 4361 return ret; 4362 4363 return hclge_reset_prepare_wait(hdev); 4364 } 4365 4366 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4367 { 4368 int ret; 4369 4370 hdev->rst_stats.hw_reset_done_cnt++; 4371 4372 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4373 if (ret) 4374 return ret; 4375 4376 rtnl_lock(); 4377 ret = hclge_reset_stack(hdev); 4378 rtnl_unlock(); 4379 if (ret) 4380 return ret; 4381 4382 hclge_clear_reset_cause(hdev); 4383 4384 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4385 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4386 * times 4387 */ 4388 if (ret && 4389 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4390 return ret; 4391 4392 ret = hclge_reset_prepare_up(hdev); 4393 if (ret) 4394 return ret; 4395 4396 rtnl_lock(); 4397 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4398 rtnl_unlock(); 4399 if (ret) 4400 return ret; 4401 4402 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4403 if (ret) 4404 return ret; 4405 4406 hdev->last_reset_time = jiffies; 4407 hdev->rst_stats.reset_fail_cnt = 0; 4408 hdev->rst_stats.reset_done_cnt++; 4409 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4410 4411 hclge_update_reset_level(hdev); 4412 4413 return 0; 4414 } 4415 4416 static void hclge_reset(struct hclge_dev *hdev) 4417 { 4418 if (hclge_reset_prepare(hdev)) 4419 goto err_reset; 4420 4421 if (hclge_reset_wait(hdev)) 4422 goto err_reset; 4423 4424 if (hclge_reset_rebuild(hdev)) 4425 goto err_reset; 4426 4427 return; 4428 4429 err_reset: 4430 if (hclge_reset_err_handle(hdev)) 4431 hclge_reset_task_schedule(hdev); 4432 } 4433 4434 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4435 { 4436 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4437 struct hclge_dev *hdev = ae_dev->priv; 4438 4439 /* We might end up getting called broadly because of 2 below cases: 4440 * 1. Recoverable error was conveyed through APEI and only way to bring 4441 * normalcy is to reset. 4442 * 2. A new reset request from the stack due to timeout 4443 * 4444 * check if this is a new reset request and we are not here just because 4445 * last reset attempt did not succeed and watchdog hit us again. We will 4446 * know this if last reset request did not occur very recently (watchdog 4447 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4448 * In case of new request we reset the "reset level" to PF reset. 4449 * And if it is a repeat reset request of the most recent one then we 4450 * want to make sure we throttle the reset request. Therefore, we will 4451 * not allow it again before 3*HZ times. 4452 */ 4453 4454 if (time_before(jiffies, (hdev->last_reset_time + 4455 HCLGE_RESET_INTERVAL))) { 4456 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4457 return; 4458 } 4459 4460 if (hdev->default_reset_request) { 4461 hdev->reset_level = 4462 hclge_get_reset_level(ae_dev, 4463 &hdev->default_reset_request); 4464 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4465 hdev->reset_level = HNAE3_FUNC_RESET; 4466 } 4467 4468 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4469 hdev->reset_level); 4470 4471 /* request reset & schedule reset task */ 4472 set_bit(hdev->reset_level, &hdev->reset_request); 4473 hclge_reset_task_schedule(hdev); 4474 4475 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4476 hdev->reset_level++; 4477 } 4478 4479 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4480 enum hnae3_reset_type rst_type) 4481 { 4482 struct hclge_dev *hdev = ae_dev->priv; 4483 4484 set_bit(rst_type, &hdev->default_reset_request); 4485 } 4486 4487 static void hclge_reset_timer(struct timer_list *t) 4488 { 4489 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4490 4491 /* if default_reset_request has no value, it means that this reset 4492 * request has already be handled, so just return here 4493 */ 4494 if (!hdev->default_reset_request) 4495 return; 4496 4497 dev_info(&hdev->pdev->dev, 4498 "triggering reset in reset timer\n"); 4499 hclge_reset_event(hdev->pdev, NULL); 4500 } 4501 4502 static void hclge_reset_subtask(struct hclge_dev *hdev) 4503 { 4504 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4505 4506 /* check if there is any ongoing reset in the hardware. This status can 4507 * be checked from reset_pending. If there is then, we need to wait for 4508 * hardware to complete reset. 4509 * a. If we are able to figure out in reasonable time that hardware 4510 * has fully resetted then, we can proceed with driver, client 4511 * reset. 4512 * b. else, we can come back later to check this status so re-sched 4513 * now. 4514 */ 4515 hdev->last_reset_time = jiffies; 4516 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4517 if (hdev->reset_type != HNAE3_NONE_RESET) 4518 hclge_reset(hdev); 4519 4520 /* check if we got any *new* reset requests to be honored */ 4521 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4522 if (hdev->reset_type != HNAE3_NONE_RESET) 4523 hclge_do_reset(hdev); 4524 4525 hdev->reset_type = HNAE3_NONE_RESET; 4526 } 4527 4528 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4529 { 4530 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4531 enum hnae3_reset_type reset_type; 4532 4533 if (ae_dev->hw_err_reset_req) { 4534 reset_type = hclge_get_reset_level(ae_dev, 4535 &ae_dev->hw_err_reset_req); 4536 hclge_set_def_reset_request(ae_dev, reset_type); 4537 } 4538 4539 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4540 ae_dev->ops->reset_event(hdev->pdev, NULL); 4541 4542 /* enable interrupt after error handling complete */ 4543 hclge_enable_vector(&hdev->misc_vector, true); 4544 } 4545 4546 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4547 { 4548 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4549 4550 ae_dev->hw_err_reset_req = 0; 4551 4552 if (hclge_find_error_source(hdev)) { 4553 hclge_handle_error_info_log(ae_dev); 4554 hclge_handle_mac_tnl(hdev); 4555 hclge_handle_vf_queue_err_ras(hdev); 4556 } 4557 4558 hclge_handle_err_reset_request(hdev); 4559 } 4560 4561 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4562 { 4563 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4564 struct device *dev = &hdev->pdev->dev; 4565 u32 msix_sts_reg; 4566 4567 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4568 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4569 if (hclge_handle_hw_msix_error 4570 (hdev, &hdev->default_reset_request)) 4571 dev_info(dev, "received msix interrupt 0x%x\n", 4572 msix_sts_reg); 4573 } 4574 4575 hclge_handle_hw_ras_error(ae_dev); 4576 4577 hclge_handle_err_reset_request(hdev); 4578 } 4579 4580 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4581 { 4582 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4583 return; 4584 4585 if (hnae3_dev_ras_imp_supported(hdev)) 4586 hclge_handle_err_recovery(hdev); 4587 else 4588 hclge_misc_err_recovery(hdev); 4589 } 4590 4591 static void hclge_reset_service_task(struct hclge_dev *hdev) 4592 { 4593 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4594 return; 4595 4596 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4597 HCLGE_RESET_SCHED_TIMEOUT)) 4598 dev_warn(&hdev->pdev->dev, 4599 "reset service task is scheduled after %ums on cpu%u!\n", 4600 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4601 smp_processor_id()); 4602 4603 down(&hdev->reset_sem); 4604 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4605 4606 hclge_reset_subtask(hdev); 4607 4608 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4609 up(&hdev->reset_sem); 4610 } 4611 4612 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4613 { 4614 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4615 4616 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4617 int i; 4618 4619 /* start from vport 1 for PF is always alive */ 4620 for (i = 1; i < hdev->num_alloc_vport; i++) { 4621 struct hclge_vport *vport = &hdev->vport[i]; 4622 4623 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4624 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4625 continue; 4626 if (time_after(jiffies, vport->last_active_jiffies + 4627 alive_time)) { 4628 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4629 dev_warn(&hdev->pdev->dev, 4630 "VF %u heartbeat timeout\n", 4631 i - HCLGE_VF_VPORT_START_NUM); 4632 } 4633 } 4634 } 4635 4636 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4637 { 4638 unsigned long delta = round_jiffies_relative(HZ); 4639 4640 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4641 return; 4642 4643 /* Always handle the link updating to make sure link state is 4644 * updated when it is triggered by mbx. 4645 */ 4646 hclge_update_link_status(hdev); 4647 hclge_sync_mac_table(hdev); 4648 hclge_sync_promisc_mode(hdev); 4649 hclge_sync_fd_table(hdev); 4650 4651 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4652 delta = jiffies - hdev->last_serv_processed; 4653 4654 if (delta < round_jiffies_relative(HZ)) { 4655 delta = round_jiffies_relative(HZ) - delta; 4656 goto out; 4657 } 4658 } 4659 4660 hdev->serv_processed_cnt++; 4661 hclge_update_vport_alive(hdev); 4662 4663 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4664 hdev->last_serv_processed = jiffies; 4665 goto out; 4666 } 4667 4668 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4669 hclge_update_stats_for_all(hdev); 4670 4671 hclge_update_port_info(hdev); 4672 hclge_sync_vlan_filter(hdev); 4673 4674 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4675 hclge_rfs_filter_expire(hdev); 4676 4677 hdev->last_serv_processed = jiffies; 4678 4679 out: 4680 hclge_task_schedule(hdev, delta); 4681 } 4682 4683 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4684 { 4685 unsigned long flags; 4686 4687 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4688 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4689 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4690 return; 4691 4692 /* to prevent concurrence with the irq handler */ 4693 spin_lock_irqsave(&hdev->ptp->lock, flags); 4694 4695 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4696 * handler may handle it just before spin_lock_irqsave(). 4697 */ 4698 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4699 hclge_ptp_clean_tx_hwts(hdev); 4700 4701 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4702 } 4703 4704 static void hclge_service_task(struct work_struct *work) 4705 { 4706 struct hclge_dev *hdev = 4707 container_of(work, struct hclge_dev, service_task.work); 4708 4709 hclge_errhand_service_task(hdev); 4710 hclge_reset_service_task(hdev); 4711 hclge_ptp_service_task(hdev); 4712 hclge_mailbox_service_task(hdev); 4713 hclge_periodic_service_task(hdev); 4714 4715 /* Handle error recovery, reset and mbx again in case periodical task 4716 * delays the handling by calling hclge_task_schedule() in 4717 * hclge_periodic_service_task(). 4718 */ 4719 hclge_errhand_service_task(hdev); 4720 hclge_reset_service_task(hdev); 4721 hclge_mailbox_service_task(hdev); 4722 } 4723 4724 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4725 { 4726 /* VF handle has no client */ 4727 if (!handle->client) 4728 return container_of(handle, struct hclge_vport, nic); 4729 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4730 return container_of(handle, struct hclge_vport, roce); 4731 else 4732 return container_of(handle, struct hclge_vport, nic); 4733 } 4734 4735 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4736 struct hnae3_vector_info *vector_info) 4737 { 4738 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4739 4740 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4741 4742 /* need an extend offset to config vector >= 64 */ 4743 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4744 vector_info->io_addr = hdev->hw.hw.io_base + 4745 HCLGE_VECTOR_REG_BASE + 4746 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4747 else 4748 vector_info->io_addr = hdev->hw.hw.io_base + 4749 HCLGE_VECTOR_EXT_REG_BASE + 4750 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4751 HCLGE_VECTOR_REG_OFFSET_H + 4752 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4753 HCLGE_VECTOR_REG_OFFSET; 4754 4755 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4756 hdev->vector_irq[idx] = vector_info->vector; 4757 } 4758 4759 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4760 struct hnae3_vector_info *vector_info) 4761 { 4762 struct hclge_vport *vport = hclge_get_vport(handle); 4763 struct hnae3_vector_info *vector = vector_info; 4764 struct hclge_dev *hdev = vport->back; 4765 int alloc = 0; 4766 u16 i = 0; 4767 u16 j; 4768 4769 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4770 vector_num = min(hdev->num_msi_left, vector_num); 4771 4772 for (j = 0; j < vector_num; j++) { 4773 while (++i < hdev->num_nic_msi) { 4774 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4775 hclge_get_vector_info(hdev, i, vector); 4776 vector++; 4777 alloc++; 4778 4779 break; 4780 } 4781 } 4782 } 4783 hdev->num_msi_left -= alloc; 4784 hdev->num_msi_used += alloc; 4785 4786 return alloc; 4787 } 4788 4789 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4790 { 4791 int i; 4792 4793 for (i = 0; i < hdev->num_msi; i++) 4794 if (vector == hdev->vector_irq[i]) 4795 return i; 4796 4797 return -EINVAL; 4798 } 4799 4800 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4801 { 4802 struct hclge_vport *vport = hclge_get_vport(handle); 4803 struct hclge_dev *hdev = vport->back; 4804 int vector_id; 4805 4806 vector_id = hclge_get_vector_index(hdev, vector); 4807 if (vector_id < 0) { 4808 dev_err(&hdev->pdev->dev, 4809 "Get vector index fail. vector = %d\n", vector); 4810 return vector_id; 4811 } 4812 4813 hclge_free_vector(hdev, vector_id); 4814 4815 return 0; 4816 } 4817 4818 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4819 u8 *key, u8 *hfunc) 4820 { 4821 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4822 struct hclge_vport *vport = hclge_get_vport(handle); 4823 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4824 4825 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4826 4827 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4828 ae_dev->dev_specs.rss_ind_tbl_size); 4829 4830 return 0; 4831 } 4832 4833 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4834 const u8 *key, const u8 hfunc) 4835 { 4836 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4837 struct hclge_vport *vport = hclge_get_vport(handle); 4838 struct hclge_dev *hdev = vport->back; 4839 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4840 int ret, i; 4841 4842 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4843 if (ret) { 4844 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4845 return ret; 4846 } 4847 4848 /* Update the shadow RSS table with user specified qids */ 4849 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4850 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4851 4852 /* Update the hardware */ 4853 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4854 rss_cfg->rss_indirection_tbl); 4855 } 4856 4857 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4858 struct ethtool_rxnfc *nfc) 4859 { 4860 struct hclge_vport *vport = hclge_get_vport(handle); 4861 struct hclge_dev *hdev = vport->back; 4862 int ret; 4863 4864 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4865 &hdev->rss_cfg, nfc); 4866 if (ret) { 4867 dev_err(&hdev->pdev->dev, 4868 "failed to set rss tuple, ret = %d.\n", ret); 4869 return ret; 4870 } 4871 4872 return 0; 4873 } 4874 4875 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4876 struct ethtool_rxnfc *nfc) 4877 { 4878 struct hclge_vport *vport = hclge_get_vport(handle); 4879 u8 tuple_sets; 4880 int ret; 4881 4882 nfc->data = 0; 4883 4884 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4885 &tuple_sets); 4886 if (ret || !tuple_sets) 4887 return ret; 4888 4889 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4890 4891 return 0; 4892 } 4893 4894 static int hclge_get_tc_size(struct hnae3_handle *handle) 4895 { 4896 struct hclge_vport *vport = hclge_get_vport(handle); 4897 struct hclge_dev *hdev = vport->back; 4898 4899 return hdev->pf_rss_size_max; 4900 } 4901 4902 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4903 { 4904 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4905 struct hclge_vport *vport = hdev->vport; 4906 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4907 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4908 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4909 struct hnae3_tc_info *tc_info; 4910 u16 roundup_size; 4911 u16 rss_size; 4912 int i; 4913 4914 tc_info = &vport->nic.kinfo.tc_info; 4915 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4916 rss_size = tc_info->tqp_count[i]; 4917 tc_valid[i] = 0; 4918 4919 if (!(hdev->hw_tc_map & BIT(i))) 4920 continue; 4921 4922 /* tc_size set to hardware is the log2 of roundup power of two 4923 * of rss_size, the acutal queue size is limited by indirection 4924 * table. 4925 */ 4926 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4927 rss_size == 0) { 4928 dev_err(&hdev->pdev->dev, 4929 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4930 rss_size); 4931 return -EINVAL; 4932 } 4933 4934 roundup_size = roundup_pow_of_two(rss_size); 4935 roundup_size = ilog2(roundup_size); 4936 4937 tc_valid[i] = 1; 4938 tc_size[i] = roundup_size; 4939 tc_offset[i] = tc_info->tqp_offset[i]; 4940 } 4941 4942 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4943 tc_size); 4944 } 4945 4946 int hclge_rss_init_hw(struct hclge_dev *hdev) 4947 { 4948 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4949 u8 *key = hdev->rss_cfg.rss_hash_key; 4950 u8 hfunc = hdev->rss_cfg.rss_algo; 4951 int ret; 4952 4953 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4954 rss_indir); 4955 if (ret) 4956 return ret; 4957 4958 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4959 if (ret) 4960 return ret; 4961 4962 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4963 if (ret) 4964 return ret; 4965 4966 return hclge_init_rss_tc_mode(hdev); 4967 } 4968 4969 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4970 int vector_id, bool en, 4971 struct hnae3_ring_chain_node *ring_chain) 4972 { 4973 struct hclge_dev *hdev = vport->back; 4974 struct hnae3_ring_chain_node *node; 4975 struct hclge_desc desc; 4976 struct hclge_ctrl_vector_chain_cmd *req = 4977 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4978 enum hclge_comm_cmd_status status; 4979 enum hclge_opcode_type op; 4980 u16 tqp_type_and_id; 4981 int i; 4982 4983 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4984 hclge_cmd_setup_basic_desc(&desc, op, false); 4985 req->int_vector_id_l = hnae3_get_field(vector_id, 4986 HCLGE_VECTOR_ID_L_M, 4987 HCLGE_VECTOR_ID_L_S); 4988 req->int_vector_id_h = hnae3_get_field(vector_id, 4989 HCLGE_VECTOR_ID_H_M, 4990 HCLGE_VECTOR_ID_H_S); 4991 4992 i = 0; 4993 for (node = ring_chain; node; node = node->next) { 4994 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4995 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4996 HCLGE_INT_TYPE_S, 4997 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4998 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4999 HCLGE_TQP_ID_S, node->tqp_index); 5000 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5001 HCLGE_INT_GL_IDX_S, 5002 hnae3_get_field(node->int_gl_idx, 5003 HNAE3_RING_GL_IDX_M, 5004 HNAE3_RING_GL_IDX_S)); 5005 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5006 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5007 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5008 req->vfid = vport->vport_id; 5009 5010 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5011 if (status) { 5012 dev_err(&hdev->pdev->dev, 5013 "Map TQP fail, status is %d.\n", 5014 status); 5015 return -EIO; 5016 } 5017 i = 0; 5018 5019 hclge_cmd_setup_basic_desc(&desc, 5020 op, 5021 false); 5022 req->int_vector_id_l = 5023 hnae3_get_field(vector_id, 5024 HCLGE_VECTOR_ID_L_M, 5025 HCLGE_VECTOR_ID_L_S); 5026 req->int_vector_id_h = 5027 hnae3_get_field(vector_id, 5028 HCLGE_VECTOR_ID_H_M, 5029 HCLGE_VECTOR_ID_H_S); 5030 } 5031 } 5032 5033 if (i > 0) { 5034 req->int_cause_num = i; 5035 req->vfid = vport->vport_id; 5036 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5037 if (status) { 5038 dev_err(&hdev->pdev->dev, 5039 "Map TQP fail, status is %d.\n", status); 5040 return -EIO; 5041 } 5042 } 5043 5044 return 0; 5045 } 5046 5047 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5048 struct hnae3_ring_chain_node *ring_chain) 5049 { 5050 struct hclge_vport *vport = hclge_get_vport(handle); 5051 struct hclge_dev *hdev = vport->back; 5052 int vector_id; 5053 5054 vector_id = hclge_get_vector_index(hdev, vector); 5055 if (vector_id < 0) { 5056 dev_err(&hdev->pdev->dev, 5057 "failed to get vector index. vector=%d\n", vector); 5058 return vector_id; 5059 } 5060 5061 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5062 } 5063 5064 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5065 struct hnae3_ring_chain_node *ring_chain) 5066 { 5067 struct hclge_vport *vport = hclge_get_vport(handle); 5068 struct hclge_dev *hdev = vport->back; 5069 int vector_id, ret; 5070 5071 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5072 return 0; 5073 5074 vector_id = hclge_get_vector_index(hdev, vector); 5075 if (vector_id < 0) { 5076 dev_err(&handle->pdev->dev, 5077 "Get vector index fail. ret =%d\n", vector_id); 5078 return vector_id; 5079 } 5080 5081 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5082 if (ret) 5083 dev_err(&handle->pdev->dev, 5084 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5085 vector_id, ret); 5086 5087 return ret; 5088 } 5089 5090 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5091 bool en_uc, bool en_mc, bool en_bc) 5092 { 5093 struct hclge_vport *vport = &hdev->vport[vf_id]; 5094 struct hnae3_handle *handle = &vport->nic; 5095 struct hclge_promisc_cfg_cmd *req; 5096 struct hclge_desc desc; 5097 bool uc_tx_en = en_uc; 5098 u8 promisc_cfg = 0; 5099 int ret; 5100 5101 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5102 5103 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5104 req->vf_id = vf_id; 5105 5106 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5107 uc_tx_en = false; 5108 5109 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5110 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5111 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5112 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5113 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5114 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5115 req->extend_promisc = promisc_cfg; 5116 5117 /* to be compatible with DEVICE_VERSION_V1/2 */ 5118 promisc_cfg = 0; 5119 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5120 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5121 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5122 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5123 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5124 req->promisc = promisc_cfg; 5125 5126 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5127 if (ret) 5128 dev_err(&hdev->pdev->dev, 5129 "failed to set vport %u promisc mode, ret = %d.\n", 5130 vf_id, ret); 5131 5132 return ret; 5133 } 5134 5135 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5136 bool en_mc_pmc, bool en_bc_pmc) 5137 { 5138 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5139 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5140 } 5141 5142 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5143 bool en_mc_pmc) 5144 { 5145 struct hclge_vport *vport = hclge_get_vport(handle); 5146 struct hclge_dev *hdev = vport->back; 5147 bool en_bc_pmc = true; 5148 5149 /* For device whose version below V2, if broadcast promisc enabled, 5150 * vlan filter is always bypassed. So broadcast promisc should be 5151 * disabled until user enable promisc mode 5152 */ 5153 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5154 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5155 5156 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5157 en_bc_pmc); 5158 } 5159 5160 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5161 { 5162 struct hclge_vport *vport = hclge_get_vport(handle); 5163 5164 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5165 } 5166 5167 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5168 { 5169 if (hlist_empty(&hdev->fd_rule_list)) 5170 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5171 } 5172 5173 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5174 { 5175 if (!test_bit(location, hdev->fd_bmap)) { 5176 set_bit(location, hdev->fd_bmap); 5177 hdev->hclge_fd_rule_num++; 5178 } 5179 } 5180 5181 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5182 { 5183 if (test_bit(location, hdev->fd_bmap)) { 5184 clear_bit(location, hdev->fd_bmap); 5185 hdev->hclge_fd_rule_num--; 5186 } 5187 } 5188 5189 static void hclge_fd_free_node(struct hclge_dev *hdev, 5190 struct hclge_fd_rule *rule) 5191 { 5192 hlist_del(&rule->rule_node); 5193 kfree(rule); 5194 hclge_sync_fd_state(hdev); 5195 } 5196 5197 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5198 struct hclge_fd_rule *old_rule, 5199 struct hclge_fd_rule *new_rule, 5200 enum HCLGE_FD_NODE_STATE state) 5201 { 5202 switch (state) { 5203 case HCLGE_FD_TO_ADD: 5204 case HCLGE_FD_ACTIVE: 5205 /* 1) if the new state is TO_ADD, just replace the old rule 5206 * with the same location, no matter its state, because the 5207 * new rule will be configured to the hardware. 5208 * 2) if the new state is ACTIVE, it means the new rule 5209 * has been configured to the hardware, so just replace 5210 * the old rule node with the same location. 5211 * 3) for it doesn't add a new node to the list, so it's 5212 * unnecessary to update the rule number and fd_bmap. 5213 */ 5214 new_rule->rule_node.next = old_rule->rule_node.next; 5215 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5216 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5217 kfree(new_rule); 5218 break; 5219 case HCLGE_FD_DELETED: 5220 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5221 hclge_fd_free_node(hdev, old_rule); 5222 break; 5223 case HCLGE_FD_TO_DEL: 5224 /* if new request is TO_DEL, and old rule is existent 5225 * 1) the state of old rule is TO_DEL, we need do nothing, 5226 * because we delete rule by location, other rule content 5227 * is unncessary. 5228 * 2) the state of old rule is ACTIVE, we need to change its 5229 * state to TO_DEL, so the rule will be deleted when periodic 5230 * task being scheduled. 5231 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5232 * been added to hardware, so we just delete the rule node from 5233 * fd_rule_list directly. 5234 */ 5235 if (old_rule->state == HCLGE_FD_TO_ADD) { 5236 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5237 hclge_fd_free_node(hdev, old_rule); 5238 return; 5239 } 5240 old_rule->state = HCLGE_FD_TO_DEL; 5241 break; 5242 } 5243 } 5244 5245 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5246 u16 location, 5247 struct hclge_fd_rule **parent) 5248 { 5249 struct hclge_fd_rule *rule; 5250 struct hlist_node *node; 5251 5252 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5253 if (rule->location == location) 5254 return rule; 5255 else if (rule->location > location) 5256 return NULL; 5257 /* record the parent node, use to keep the nodes in fd_rule_list 5258 * in ascend order. 5259 */ 5260 *parent = rule; 5261 } 5262 5263 return NULL; 5264 } 5265 5266 /* insert fd rule node in ascend order according to rule->location */ 5267 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5268 struct hclge_fd_rule *rule, 5269 struct hclge_fd_rule *parent) 5270 { 5271 INIT_HLIST_NODE(&rule->rule_node); 5272 5273 if (parent) 5274 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5275 else 5276 hlist_add_head(&rule->rule_node, hlist); 5277 } 5278 5279 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5280 struct hclge_fd_user_def_cfg *cfg) 5281 { 5282 struct hclge_fd_user_def_cfg_cmd *req; 5283 struct hclge_desc desc; 5284 u16 data = 0; 5285 int ret; 5286 5287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5288 5289 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5290 5291 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5292 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5293 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5294 req->ol2_cfg = cpu_to_le16(data); 5295 5296 data = 0; 5297 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5298 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5299 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5300 req->ol3_cfg = cpu_to_le16(data); 5301 5302 data = 0; 5303 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5304 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5305 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5306 req->ol4_cfg = cpu_to_le16(data); 5307 5308 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5309 if (ret) 5310 dev_err(&hdev->pdev->dev, 5311 "failed to set fd user def data, ret= %d\n", ret); 5312 return ret; 5313 } 5314 5315 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5316 { 5317 int ret; 5318 5319 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5320 return; 5321 5322 if (!locked) 5323 spin_lock_bh(&hdev->fd_rule_lock); 5324 5325 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5326 if (ret) 5327 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5328 5329 if (!locked) 5330 spin_unlock_bh(&hdev->fd_rule_lock); 5331 } 5332 5333 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5334 struct hclge_fd_rule *rule) 5335 { 5336 struct hlist_head *hlist = &hdev->fd_rule_list; 5337 struct hclge_fd_rule *fd_rule, *parent = NULL; 5338 struct hclge_fd_user_def_info *info, *old_info; 5339 struct hclge_fd_user_def_cfg *cfg; 5340 5341 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5342 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5343 return 0; 5344 5345 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5346 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5347 info = &rule->ep.user_def; 5348 5349 if (!cfg->ref_cnt || cfg->offset == info->offset) 5350 return 0; 5351 5352 if (cfg->ref_cnt > 1) 5353 goto error; 5354 5355 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5356 if (fd_rule) { 5357 old_info = &fd_rule->ep.user_def; 5358 if (info->layer == old_info->layer) 5359 return 0; 5360 } 5361 5362 error: 5363 dev_err(&hdev->pdev->dev, 5364 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5365 info->layer + 1); 5366 return -ENOSPC; 5367 } 5368 5369 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5370 struct hclge_fd_rule *rule) 5371 { 5372 struct hclge_fd_user_def_cfg *cfg; 5373 5374 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5375 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5376 return; 5377 5378 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5379 if (!cfg->ref_cnt) { 5380 cfg->offset = rule->ep.user_def.offset; 5381 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5382 } 5383 cfg->ref_cnt++; 5384 } 5385 5386 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5387 struct hclge_fd_rule *rule) 5388 { 5389 struct hclge_fd_user_def_cfg *cfg; 5390 5391 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5392 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5393 return; 5394 5395 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5396 if (!cfg->ref_cnt) 5397 return; 5398 5399 cfg->ref_cnt--; 5400 if (!cfg->ref_cnt) { 5401 cfg->offset = 0; 5402 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5403 } 5404 } 5405 5406 static void hclge_update_fd_list(struct hclge_dev *hdev, 5407 enum HCLGE_FD_NODE_STATE state, u16 location, 5408 struct hclge_fd_rule *new_rule) 5409 { 5410 struct hlist_head *hlist = &hdev->fd_rule_list; 5411 struct hclge_fd_rule *fd_rule, *parent = NULL; 5412 5413 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5414 if (fd_rule) { 5415 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5416 if (state == HCLGE_FD_ACTIVE) 5417 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5418 hclge_sync_fd_user_def_cfg(hdev, true); 5419 5420 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5421 return; 5422 } 5423 5424 /* it's unlikely to fail here, because we have checked the rule 5425 * exist before. 5426 */ 5427 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5428 dev_warn(&hdev->pdev->dev, 5429 "failed to delete fd rule %u, it's inexistent\n", 5430 location); 5431 return; 5432 } 5433 5434 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5435 hclge_sync_fd_user_def_cfg(hdev, true); 5436 5437 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5438 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5439 5440 if (state == HCLGE_FD_TO_ADD) { 5441 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5442 hclge_task_schedule(hdev, 0); 5443 } 5444 } 5445 5446 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5447 { 5448 struct hclge_get_fd_mode_cmd *req; 5449 struct hclge_desc desc; 5450 int ret; 5451 5452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5453 5454 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5455 5456 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5457 if (ret) { 5458 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5459 return ret; 5460 } 5461 5462 *fd_mode = req->mode; 5463 5464 return ret; 5465 } 5466 5467 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5468 u32 *stage1_entry_num, 5469 u32 *stage2_entry_num, 5470 u16 *stage1_counter_num, 5471 u16 *stage2_counter_num) 5472 { 5473 struct hclge_get_fd_allocation_cmd *req; 5474 struct hclge_desc desc; 5475 int ret; 5476 5477 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5478 5479 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5480 5481 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5482 if (ret) { 5483 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5484 ret); 5485 return ret; 5486 } 5487 5488 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5489 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5490 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5491 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5492 5493 return ret; 5494 } 5495 5496 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5497 enum HCLGE_FD_STAGE stage_num) 5498 { 5499 struct hclge_set_fd_key_config_cmd *req; 5500 struct hclge_fd_key_cfg *stage; 5501 struct hclge_desc desc; 5502 int ret; 5503 5504 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5505 5506 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5507 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5508 req->stage = stage_num; 5509 req->key_select = stage->key_sel; 5510 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5511 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5512 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5513 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5514 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5515 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5516 5517 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5518 if (ret) 5519 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5520 5521 return ret; 5522 } 5523 5524 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5525 { 5526 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5527 5528 spin_lock_bh(&hdev->fd_rule_lock); 5529 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5530 spin_unlock_bh(&hdev->fd_rule_lock); 5531 5532 hclge_fd_set_user_def_cmd(hdev, cfg); 5533 } 5534 5535 static int hclge_init_fd_config(struct hclge_dev *hdev) 5536 { 5537 #define LOW_2_WORDS 0x03 5538 struct hclge_fd_key_cfg *key_cfg; 5539 int ret; 5540 5541 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5542 return 0; 5543 5544 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5545 if (ret) 5546 return ret; 5547 5548 switch (hdev->fd_cfg.fd_mode) { 5549 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5550 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5551 break; 5552 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5553 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5554 break; 5555 default: 5556 dev_err(&hdev->pdev->dev, 5557 "Unsupported flow director mode %u\n", 5558 hdev->fd_cfg.fd_mode); 5559 return -EOPNOTSUPP; 5560 } 5561 5562 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5563 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5564 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5565 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5566 key_cfg->outer_sipv6_word_en = 0; 5567 key_cfg->outer_dipv6_word_en = 0; 5568 5569 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5570 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5571 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5572 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5573 5574 /* If use max 400bit key, we can support tuples for ether type */ 5575 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5576 key_cfg->tuple_active |= 5577 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5578 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5579 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5580 } 5581 5582 /* roce_type is used to filter roce frames 5583 * dst_vport is used to specify the rule 5584 */ 5585 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5586 5587 ret = hclge_get_fd_allocation(hdev, 5588 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5589 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5590 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5591 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5592 if (ret) 5593 return ret; 5594 5595 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5596 } 5597 5598 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5599 int loc, u8 *key, bool is_add) 5600 { 5601 struct hclge_fd_tcam_config_1_cmd *req1; 5602 struct hclge_fd_tcam_config_2_cmd *req2; 5603 struct hclge_fd_tcam_config_3_cmd *req3; 5604 struct hclge_desc desc[3]; 5605 int ret; 5606 5607 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5608 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5609 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5610 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5611 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5612 5613 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5614 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5615 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5616 5617 req1->stage = stage; 5618 req1->xy_sel = sel_x ? 1 : 0; 5619 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5620 req1->index = cpu_to_le32(loc); 5621 req1->entry_vld = sel_x ? is_add : 0; 5622 5623 if (key) { 5624 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5625 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5626 sizeof(req2->tcam_data)); 5627 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5628 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5629 } 5630 5631 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5632 if (ret) 5633 dev_err(&hdev->pdev->dev, 5634 "config tcam key fail, ret=%d\n", 5635 ret); 5636 5637 return ret; 5638 } 5639 5640 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5641 struct hclge_fd_ad_data *action) 5642 { 5643 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5644 struct hclge_fd_ad_config_cmd *req; 5645 struct hclge_desc desc; 5646 u64 ad_data = 0; 5647 int ret; 5648 5649 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5650 5651 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5652 req->index = cpu_to_le32(loc); 5653 req->stage = stage; 5654 5655 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5656 action->write_rule_id_to_bd); 5657 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5658 action->rule_id); 5659 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5660 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5661 action->override_tc); 5662 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5663 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5664 } 5665 ad_data <<= 32; 5666 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5667 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5668 action->forward_to_direct_queue); 5669 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5670 action->queue_id); 5671 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5672 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5673 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5674 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5675 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5676 action->counter_id); 5677 5678 req->ad_data = cpu_to_le64(ad_data); 5679 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5680 if (ret) 5681 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5682 5683 return ret; 5684 } 5685 5686 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5687 struct hclge_fd_rule *rule) 5688 { 5689 int offset, moffset, ip_offset; 5690 enum HCLGE_FD_KEY_OPT key_opt; 5691 u16 tmp_x_s, tmp_y_s; 5692 u32 tmp_x_l, tmp_y_l; 5693 u8 *p = (u8 *)rule; 5694 int i; 5695 5696 if (rule->unused_tuple & BIT(tuple_bit)) 5697 return true; 5698 5699 key_opt = tuple_key_info[tuple_bit].key_opt; 5700 offset = tuple_key_info[tuple_bit].offset; 5701 moffset = tuple_key_info[tuple_bit].moffset; 5702 5703 switch (key_opt) { 5704 case KEY_OPT_U8: 5705 calc_x(*key_x, p[offset], p[moffset]); 5706 calc_y(*key_y, p[offset], p[moffset]); 5707 5708 return true; 5709 case KEY_OPT_LE16: 5710 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5711 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5712 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5713 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5714 5715 return true; 5716 case KEY_OPT_LE32: 5717 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5718 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5719 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5720 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5721 5722 return true; 5723 case KEY_OPT_MAC: 5724 for (i = 0; i < ETH_ALEN; i++) { 5725 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5726 p[moffset + i]); 5727 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5728 p[moffset + i]); 5729 } 5730 5731 return true; 5732 case KEY_OPT_IP: 5733 ip_offset = IPV4_INDEX * sizeof(u32); 5734 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5735 *(u32 *)(&p[moffset + ip_offset])); 5736 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5737 *(u32 *)(&p[moffset + ip_offset])); 5738 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5739 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5740 5741 return true; 5742 default: 5743 return false; 5744 } 5745 } 5746 5747 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5748 u8 vf_id, u8 network_port_id) 5749 { 5750 u32 port_number = 0; 5751 5752 if (port_type == HOST_PORT) { 5753 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5754 pf_id); 5755 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5756 vf_id); 5757 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5758 } else { 5759 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5760 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5761 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5762 } 5763 5764 return port_number; 5765 } 5766 5767 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5768 __le32 *key_x, __le32 *key_y, 5769 struct hclge_fd_rule *rule) 5770 { 5771 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5772 u8 cur_pos = 0, tuple_size, shift_bits; 5773 unsigned int i; 5774 5775 for (i = 0; i < MAX_META_DATA; i++) { 5776 tuple_size = meta_data_key_info[i].key_length; 5777 tuple_bit = key_cfg->meta_data_active & BIT(i); 5778 5779 switch (tuple_bit) { 5780 case BIT(ROCE_TYPE): 5781 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5782 cur_pos += tuple_size; 5783 break; 5784 case BIT(DST_VPORT): 5785 port_number = hclge_get_port_number(HOST_PORT, 0, 5786 rule->vf_id, 0); 5787 hnae3_set_field(meta_data, 5788 GENMASK(cur_pos + tuple_size, cur_pos), 5789 cur_pos, port_number); 5790 cur_pos += tuple_size; 5791 break; 5792 default: 5793 break; 5794 } 5795 } 5796 5797 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5798 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5799 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5800 5801 *key_x = cpu_to_le32(tmp_x << shift_bits); 5802 *key_y = cpu_to_le32(tmp_y << shift_bits); 5803 } 5804 5805 /* A complete key is combined with meta data key and tuple key. 5806 * Meta data key is stored at the MSB region, and tuple key is stored at 5807 * the LSB region, unused bits will be filled 0. 5808 */ 5809 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5810 struct hclge_fd_rule *rule) 5811 { 5812 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5813 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5814 u8 *cur_key_x, *cur_key_y; 5815 u8 meta_data_region; 5816 u8 tuple_size; 5817 int ret; 5818 u32 i; 5819 5820 memset(key_x, 0, sizeof(key_x)); 5821 memset(key_y, 0, sizeof(key_y)); 5822 cur_key_x = key_x; 5823 cur_key_y = key_y; 5824 5825 for (i = 0; i < MAX_TUPLE; i++) { 5826 bool tuple_valid; 5827 5828 tuple_size = tuple_key_info[i].key_length / 8; 5829 if (!(key_cfg->tuple_active & BIT(i))) 5830 continue; 5831 5832 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5833 cur_key_y, rule); 5834 if (tuple_valid) { 5835 cur_key_x += tuple_size; 5836 cur_key_y += tuple_size; 5837 } 5838 } 5839 5840 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5841 MAX_META_DATA_LENGTH / 8; 5842 5843 hclge_fd_convert_meta_data(key_cfg, 5844 (__le32 *)(key_x + meta_data_region), 5845 (__le32 *)(key_y + meta_data_region), 5846 rule); 5847 5848 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5849 true); 5850 if (ret) { 5851 dev_err(&hdev->pdev->dev, 5852 "fd key_y config fail, loc=%u, ret=%d\n", 5853 rule->queue_id, ret); 5854 return ret; 5855 } 5856 5857 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5858 true); 5859 if (ret) 5860 dev_err(&hdev->pdev->dev, 5861 "fd key_x config fail, loc=%u, ret=%d\n", 5862 rule->queue_id, ret); 5863 return ret; 5864 } 5865 5866 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5867 struct hclge_fd_rule *rule) 5868 { 5869 struct hclge_vport *vport = hdev->vport; 5870 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5871 struct hclge_fd_ad_data ad_data; 5872 5873 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5874 ad_data.ad_id = rule->location; 5875 5876 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5877 ad_data.drop_packet = true; 5878 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5879 ad_data.override_tc = true; 5880 ad_data.queue_id = 5881 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5882 ad_data.tc_size = 5883 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5884 } else { 5885 ad_data.forward_to_direct_queue = true; 5886 ad_data.queue_id = rule->queue_id; 5887 } 5888 5889 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5890 ad_data.use_counter = true; 5891 ad_data.counter_id = rule->vf_id % 5892 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5893 } else { 5894 ad_data.use_counter = false; 5895 ad_data.counter_id = 0; 5896 } 5897 5898 ad_data.use_next_stage = false; 5899 ad_data.next_input_key = 0; 5900 5901 ad_data.write_rule_id_to_bd = true; 5902 ad_data.rule_id = rule->location; 5903 5904 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5905 } 5906 5907 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5908 u32 *unused_tuple) 5909 { 5910 if (!spec || !unused_tuple) 5911 return -EINVAL; 5912 5913 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5914 5915 if (!spec->ip4src) 5916 *unused_tuple |= BIT(INNER_SRC_IP); 5917 5918 if (!spec->ip4dst) 5919 *unused_tuple |= BIT(INNER_DST_IP); 5920 5921 if (!spec->psrc) 5922 *unused_tuple |= BIT(INNER_SRC_PORT); 5923 5924 if (!spec->pdst) 5925 *unused_tuple |= BIT(INNER_DST_PORT); 5926 5927 if (!spec->tos) 5928 *unused_tuple |= BIT(INNER_IP_TOS); 5929 5930 return 0; 5931 } 5932 5933 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5934 u32 *unused_tuple) 5935 { 5936 if (!spec || !unused_tuple) 5937 return -EINVAL; 5938 5939 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5940 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5941 5942 if (!spec->ip4src) 5943 *unused_tuple |= BIT(INNER_SRC_IP); 5944 5945 if (!spec->ip4dst) 5946 *unused_tuple |= BIT(INNER_DST_IP); 5947 5948 if (!spec->tos) 5949 *unused_tuple |= BIT(INNER_IP_TOS); 5950 5951 if (!spec->proto) 5952 *unused_tuple |= BIT(INNER_IP_PROTO); 5953 5954 if (spec->l4_4_bytes) 5955 return -EOPNOTSUPP; 5956 5957 if (spec->ip_ver != ETH_RX_NFC_IP4) 5958 return -EOPNOTSUPP; 5959 5960 return 0; 5961 } 5962 5963 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5964 u32 *unused_tuple) 5965 { 5966 if (!spec || !unused_tuple) 5967 return -EINVAL; 5968 5969 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5970 5971 /* check whether src/dst ip address used */ 5972 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5973 *unused_tuple |= BIT(INNER_SRC_IP); 5974 5975 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5976 *unused_tuple |= BIT(INNER_DST_IP); 5977 5978 if (!spec->psrc) 5979 *unused_tuple |= BIT(INNER_SRC_PORT); 5980 5981 if (!spec->pdst) 5982 *unused_tuple |= BIT(INNER_DST_PORT); 5983 5984 if (!spec->tclass) 5985 *unused_tuple |= BIT(INNER_IP_TOS); 5986 5987 return 0; 5988 } 5989 5990 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5991 u32 *unused_tuple) 5992 { 5993 if (!spec || !unused_tuple) 5994 return -EINVAL; 5995 5996 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5997 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5998 5999 /* check whether src/dst ip address used */ 6000 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6001 *unused_tuple |= BIT(INNER_SRC_IP); 6002 6003 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6004 *unused_tuple |= BIT(INNER_DST_IP); 6005 6006 if (!spec->l4_proto) 6007 *unused_tuple |= BIT(INNER_IP_PROTO); 6008 6009 if (!spec->tclass) 6010 *unused_tuple |= BIT(INNER_IP_TOS); 6011 6012 if (spec->l4_4_bytes) 6013 return -EOPNOTSUPP; 6014 6015 return 0; 6016 } 6017 6018 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6019 { 6020 if (!spec || !unused_tuple) 6021 return -EINVAL; 6022 6023 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6024 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6025 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6026 6027 if (is_zero_ether_addr(spec->h_source)) 6028 *unused_tuple |= BIT(INNER_SRC_MAC); 6029 6030 if (is_zero_ether_addr(spec->h_dest)) 6031 *unused_tuple |= BIT(INNER_DST_MAC); 6032 6033 if (!spec->h_proto) 6034 *unused_tuple |= BIT(INNER_ETH_TYPE); 6035 6036 return 0; 6037 } 6038 6039 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6040 struct ethtool_rx_flow_spec *fs, 6041 u32 *unused_tuple) 6042 { 6043 if (fs->flow_type & FLOW_EXT) { 6044 if (fs->h_ext.vlan_etype) { 6045 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6046 return -EOPNOTSUPP; 6047 } 6048 6049 if (!fs->h_ext.vlan_tci) 6050 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6051 6052 if (fs->m_ext.vlan_tci && 6053 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6054 dev_err(&hdev->pdev->dev, 6055 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6056 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6057 return -EINVAL; 6058 } 6059 } else { 6060 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6061 } 6062 6063 if (fs->flow_type & FLOW_MAC_EXT) { 6064 if (hdev->fd_cfg.fd_mode != 6065 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6066 dev_err(&hdev->pdev->dev, 6067 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6068 return -EOPNOTSUPP; 6069 } 6070 6071 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6072 *unused_tuple |= BIT(INNER_DST_MAC); 6073 else 6074 *unused_tuple &= ~BIT(INNER_DST_MAC); 6075 } 6076 6077 return 0; 6078 } 6079 6080 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6081 struct hclge_fd_user_def_info *info) 6082 { 6083 switch (flow_type) { 6084 case ETHER_FLOW: 6085 info->layer = HCLGE_FD_USER_DEF_L2; 6086 *unused_tuple &= ~BIT(INNER_L2_RSV); 6087 break; 6088 case IP_USER_FLOW: 6089 case IPV6_USER_FLOW: 6090 info->layer = HCLGE_FD_USER_DEF_L3; 6091 *unused_tuple &= ~BIT(INNER_L3_RSV); 6092 break; 6093 case TCP_V4_FLOW: 6094 case UDP_V4_FLOW: 6095 case TCP_V6_FLOW: 6096 case UDP_V6_FLOW: 6097 info->layer = HCLGE_FD_USER_DEF_L4; 6098 *unused_tuple &= ~BIT(INNER_L4_RSV); 6099 break; 6100 default: 6101 return -EOPNOTSUPP; 6102 } 6103 6104 return 0; 6105 } 6106 6107 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6108 { 6109 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6110 } 6111 6112 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6113 struct ethtool_rx_flow_spec *fs, 6114 u32 *unused_tuple, 6115 struct hclge_fd_user_def_info *info) 6116 { 6117 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6118 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6119 u16 data, offset, data_mask, offset_mask; 6120 int ret; 6121 6122 info->layer = HCLGE_FD_USER_DEF_NONE; 6123 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6124 6125 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6126 return 0; 6127 6128 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6129 * for data, and bit32~47 is used for offset. 6130 */ 6131 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6132 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6133 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6134 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6135 6136 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6137 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6138 return -EOPNOTSUPP; 6139 } 6140 6141 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6142 dev_err(&hdev->pdev->dev, 6143 "user-def offset[%u] should be no more than %u\n", 6144 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6145 return -EINVAL; 6146 } 6147 6148 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6149 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6150 return -EINVAL; 6151 } 6152 6153 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6154 if (ret) { 6155 dev_err(&hdev->pdev->dev, 6156 "unsupported flow type for user-def bytes, ret = %d\n", 6157 ret); 6158 return ret; 6159 } 6160 6161 info->data = data; 6162 info->data_mask = data_mask; 6163 info->offset = offset; 6164 6165 return 0; 6166 } 6167 6168 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6169 struct ethtool_rx_flow_spec *fs, 6170 u32 *unused_tuple, 6171 struct hclge_fd_user_def_info *info) 6172 { 6173 u32 flow_type; 6174 int ret; 6175 6176 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6177 dev_err(&hdev->pdev->dev, 6178 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6179 fs->location, 6180 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6181 return -EINVAL; 6182 } 6183 6184 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6185 if (ret) 6186 return ret; 6187 6188 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6189 switch (flow_type) { 6190 case SCTP_V4_FLOW: 6191 case TCP_V4_FLOW: 6192 case UDP_V4_FLOW: 6193 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6194 unused_tuple); 6195 break; 6196 case IP_USER_FLOW: 6197 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6198 unused_tuple); 6199 break; 6200 case SCTP_V6_FLOW: 6201 case TCP_V6_FLOW: 6202 case UDP_V6_FLOW: 6203 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6204 unused_tuple); 6205 break; 6206 case IPV6_USER_FLOW: 6207 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6208 unused_tuple); 6209 break; 6210 case ETHER_FLOW: 6211 if (hdev->fd_cfg.fd_mode != 6212 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6213 dev_err(&hdev->pdev->dev, 6214 "ETHER_FLOW is not supported in current fd mode!\n"); 6215 return -EOPNOTSUPP; 6216 } 6217 6218 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6219 unused_tuple); 6220 break; 6221 default: 6222 dev_err(&hdev->pdev->dev, 6223 "unsupported protocol type, protocol type = %#x\n", 6224 flow_type); 6225 return -EOPNOTSUPP; 6226 } 6227 6228 if (ret) { 6229 dev_err(&hdev->pdev->dev, 6230 "failed to check flow union tuple, ret = %d\n", 6231 ret); 6232 return ret; 6233 } 6234 6235 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6236 } 6237 6238 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6239 struct hclge_fd_rule *rule, u8 ip_proto) 6240 { 6241 rule->tuples.src_ip[IPV4_INDEX] = 6242 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6243 rule->tuples_mask.src_ip[IPV4_INDEX] = 6244 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6245 6246 rule->tuples.dst_ip[IPV4_INDEX] = 6247 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6248 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6249 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6250 6251 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6252 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6253 6254 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6255 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6256 6257 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6258 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6259 6260 rule->tuples.ether_proto = ETH_P_IP; 6261 rule->tuples_mask.ether_proto = 0xFFFF; 6262 6263 rule->tuples.ip_proto = ip_proto; 6264 rule->tuples_mask.ip_proto = 0xFF; 6265 } 6266 6267 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6268 struct hclge_fd_rule *rule) 6269 { 6270 rule->tuples.src_ip[IPV4_INDEX] = 6271 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6272 rule->tuples_mask.src_ip[IPV4_INDEX] = 6273 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6274 6275 rule->tuples.dst_ip[IPV4_INDEX] = 6276 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6277 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6278 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6279 6280 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6281 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6282 6283 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6284 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6285 6286 rule->tuples.ether_proto = ETH_P_IP; 6287 rule->tuples_mask.ether_proto = 0xFFFF; 6288 } 6289 6290 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6291 struct hclge_fd_rule *rule, u8 ip_proto) 6292 { 6293 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6294 IPV6_SIZE); 6295 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6296 IPV6_SIZE); 6297 6298 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6299 IPV6_SIZE); 6300 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6301 IPV6_SIZE); 6302 6303 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6304 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6305 6306 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6307 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6308 6309 rule->tuples.ether_proto = ETH_P_IPV6; 6310 rule->tuples_mask.ether_proto = 0xFFFF; 6311 6312 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6313 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6314 6315 rule->tuples.ip_proto = ip_proto; 6316 rule->tuples_mask.ip_proto = 0xFF; 6317 } 6318 6319 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6320 struct hclge_fd_rule *rule) 6321 { 6322 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6323 IPV6_SIZE); 6324 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6325 IPV6_SIZE); 6326 6327 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6328 IPV6_SIZE); 6329 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6330 IPV6_SIZE); 6331 6332 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6333 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6334 6335 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6336 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6337 6338 rule->tuples.ether_proto = ETH_P_IPV6; 6339 rule->tuples_mask.ether_proto = 0xFFFF; 6340 } 6341 6342 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6343 struct hclge_fd_rule *rule) 6344 { 6345 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6346 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6347 6348 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6349 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6350 6351 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6352 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6353 } 6354 6355 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6356 struct hclge_fd_rule *rule) 6357 { 6358 switch (info->layer) { 6359 case HCLGE_FD_USER_DEF_L2: 6360 rule->tuples.l2_user_def = info->data; 6361 rule->tuples_mask.l2_user_def = info->data_mask; 6362 break; 6363 case HCLGE_FD_USER_DEF_L3: 6364 rule->tuples.l3_user_def = info->data; 6365 rule->tuples_mask.l3_user_def = info->data_mask; 6366 break; 6367 case HCLGE_FD_USER_DEF_L4: 6368 rule->tuples.l4_user_def = (u32)info->data << 16; 6369 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6370 break; 6371 default: 6372 break; 6373 } 6374 6375 rule->ep.user_def = *info; 6376 } 6377 6378 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6379 struct hclge_fd_rule *rule, 6380 struct hclge_fd_user_def_info *info) 6381 { 6382 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6383 6384 switch (flow_type) { 6385 case SCTP_V4_FLOW: 6386 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6387 break; 6388 case TCP_V4_FLOW: 6389 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6390 break; 6391 case UDP_V4_FLOW: 6392 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6393 break; 6394 case IP_USER_FLOW: 6395 hclge_fd_get_ip4_tuple(fs, rule); 6396 break; 6397 case SCTP_V6_FLOW: 6398 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6399 break; 6400 case TCP_V6_FLOW: 6401 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6402 break; 6403 case UDP_V6_FLOW: 6404 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6405 break; 6406 case IPV6_USER_FLOW: 6407 hclge_fd_get_ip6_tuple(fs, rule); 6408 break; 6409 case ETHER_FLOW: 6410 hclge_fd_get_ether_tuple(fs, rule); 6411 break; 6412 default: 6413 return -EOPNOTSUPP; 6414 } 6415 6416 if (fs->flow_type & FLOW_EXT) { 6417 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6418 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6419 hclge_fd_get_user_def_tuple(info, rule); 6420 } 6421 6422 if (fs->flow_type & FLOW_MAC_EXT) { 6423 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6424 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6425 } 6426 6427 return 0; 6428 } 6429 6430 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6431 struct hclge_fd_rule *rule) 6432 { 6433 int ret; 6434 6435 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6436 if (ret) 6437 return ret; 6438 6439 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6440 } 6441 6442 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6443 struct hclge_fd_rule *rule) 6444 { 6445 int ret; 6446 6447 spin_lock_bh(&hdev->fd_rule_lock); 6448 6449 if (hdev->fd_active_type != rule->rule_type && 6450 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6451 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6452 dev_err(&hdev->pdev->dev, 6453 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6454 rule->rule_type, hdev->fd_active_type); 6455 spin_unlock_bh(&hdev->fd_rule_lock); 6456 return -EINVAL; 6457 } 6458 6459 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6460 if (ret) 6461 goto out; 6462 6463 ret = hclge_clear_arfs_rules(hdev); 6464 if (ret) 6465 goto out; 6466 6467 ret = hclge_fd_config_rule(hdev, rule); 6468 if (ret) 6469 goto out; 6470 6471 rule->state = HCLGE_FD_ACTIVE; 6472 hdev->fd_active_type = rule->rule_type; 6473 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6474 6475 out: 6476 spin_unlock_bh(&hdev->fd_rule_lock); 6477 return ret; 6478 } 6479 6480 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6481 { 6482 struct hclge_vport *vport = hclge_get_vport(handle); 6483 struct hclge_dev *hdev = vport->back; 6484 6485 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6486 } 6487 6488 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6489 u16 *vport_id, u8 *action, u16 *queue_id) 6490 { 6491 struct hclge_vport *vport = hdev->vport; 6492 6493 if (ring_cookie == RX_CLS_FLOW_DISC) { 6494 *action = HCLGE_FD_ACTION_DROP_PACKET; 6495 } else { 6496 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6497 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6498 u16 tqps; 6499 6500 /* To keep consistent with user's configuration, minus 1 when 6501 * printing 'vf', because vf id from ethtool is added 1 for vf. 6502 */ 6503 if (vf > hdev->num_req_vfs) { 6504 dev_err(&hdev->pdev->dev, 6505 "Error: vf id (%u) should be less than %u\n", 6506 vf - 1U, hdev->num_req_vfs); 6507 return -EINVAL; 6508 } 6509 6510 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6511 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6512 6513 if (ring >= tqps) { 6514 dev_err(&hdev->pdev->dev, 6515 "Error: queue id (%u) > max tqp num (%u)\n", 6516 ring, tqps - 1U); 6517 return -EINVAL; 6518 } 6519 6520 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6521 *queue_id = ring; 6522 } 6523 6524 return 0; 6525 } 6526 6527 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6528 struct ethtool_rxnfc *cmd) 6529 { 6530 struct hclge_vport *vport = hclge_get_vport(handle); 6531 struct hclge_dev *hdev = vport->back; 6532 struct hclge_fd_user_def_info info; 6533 u16 dst_vport_id = 0, q_index = 0; 6534 struct ethtool_rx_flow_spec *fs; 6535 struct hclge_fd_rule *rule; 6536 u32 unused = 0; 6537 u8 action; 6538 int ret; 6539 6540 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6541 dev_err(&hdev->pdev->dev, 6542 "flow table director is not supported\n"); 6543 return -EOPNOTSUPP; 6544 } 6545 6546 if (!hdev->fd_en) { 6547 dev_err(&hdev->pdev->dev, 6548 "please enable flow director first\n"); 6549 return -EOPNOTSUPP; 6550 } 6551 6552 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6553 6554 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6555 if (ret) 6556 return ret; 6557 6558 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6559 &action, &q_index); 6560 if (ret) 6561 return ret; 6562 6563 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6564 if (!rule) 6565 return -ENOMEM; 6566 6567 ret = hclge_fd_get_tuple(fs, rule, &info); 6568 if (ret) { 6569 kfree(rule); 6570 return ret; 6571 } 6572 6573 rule->flow_type = fs->flow_type; 6574 rule->location = fs->location; 6575 rule->unused_tuple = unused; 6576 rule->vf_id = dst_vport_id; 6577 rule->queue_id = q_index; 6578 rule->action = action; 6579 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6580 6581 ret = hclge_add_fd_entry_common(hdev, rule); 6582 if (ret) 6583 kfree(rule); 6584 6585 return ret; 6586 } 6587 6588 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6589 struct ethtool_rxnfc *cmd) 6590 { 6591 struct hclge_vport *vport = hclge_get_vport(handle); 6592 struct hclge_dev *hdev = vport->back; 6593 struct ethtool_rx_flow_spec *fs; 6594 int ret; 6595 6596 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6597 return -EOPNOTSUPP; 6598 6599 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6600 6601 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6602 return -EINVAL; 6603 6604 spin_lock_bh(&hdev->fd_rule_lock); 6605 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6606 !test_bit(fs->location, hdev->fd_bmap)) { 6607 dev_err(&hdev->pdev->dev, 6608 "Delete fail, rule %u is inexistent\n", fs->location); 6609 spin_unlock_bh(&hdev->fd_rule_lock); 6610 return -ENOENT; 6611 } 6612 6613 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6614 NULL, false); 6615 if (ret) 6616 goto out; 6617 6618 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6619 6620 out: 6621 spin_unlock_bh(&hdev->fd_rule_lock); 6622 return ret; 6623 } 6624 6625 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6626 bool clear_list) 6627 { 6628 struct hclge_fd_rule *rule; 6629 struct hlist_node *node; 6630 u16 location; 6631 6632 spin_lock_bh(&hdev->fd_rule_lock); 6633 6634 for_each_set_bit(location, hdev->fd_bmap, 6635 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6636 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6637 NULL, false); 6638 6639 if (clear_list) { 6640 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6641 rule_node) { 6642 hlist_del(&rule->rule_node); 6643 kfree(rule); 6644 } 6645 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6646 hdev->hclge_fd_rule_num = 0; 6647 bitmap_zero(hdev->fd_bmap, 6648 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6649 } 6650 6651 spin_unlock_bh(&hdev->fd_rule_lock); 6652 } 6653 6654 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6655 { 6656 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6657 return; 6658 6659 hclge_clear_fd_rules_in_list(hdev, true); 6660 hclge_fd_disable_user_def(hdev); 6661 } 6662 6663 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6664 { 6665 struct hclge_vport *vport = hclge_get_vport(handle); 6666 struct hclge_dev *hdev = vport->back; 6667 struct hclge_fd_rule *rule; 6668 struct hlist_node *node; 6669 6670 /* Return ok here, because reset error handling will check this 6671 * return value. If error is returned here, the reset process will 6672 * fail. 6673 */ 6674 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6675 return 0; 6676 6677 /* if fd is disabled, should not restore it when reset */ 6678 if (!hdev->fd_en) 6679 return 0; 6680 6681 spin_lock_bh(&hdev->fd_rule_lock); 6682 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6683 if (rule->state == HCLGE_FD_ACTIVE) 6684 rule->state = HCLGE_FD_TO_ADD; 6685 } 6686 spin_unlock_bh(&hdev->fd_rule_lock); 6687 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6688 6689 return 0; 6690 } 6691 6692 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6693 struct ethtool_rxnfc *cmd) 6694 { 6695 struct hclge_vport *vport = hclge_get_vport(handle); 6696 struct hclge_dev *hdev = vport->back; 6697 6698 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6699 return -EOPNOTSUPP; 6700 6701 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6702 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6703 6704 return 0; 6705 } 6706 6707 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6708 struct ethtool_tcpip4_spec *spec, 6709 struct ethtool_tcpip4_spec *spec_mask) 6710 { 6711 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6712 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6713 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6714 6715 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6716 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6717 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6718 6719 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6720 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6721 0 : cpu_to_be16(rule->tuples_mask.src_port); 6722 6723 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6724 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6725 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6726 6727 spec->tos = rule->tuples.ip_tos; 6728 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6729 0 : rule->tuples_mask.ip_tos; 6730 } 6731 6732 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6733 struct ethtool_usrip4_spec *spec, 6734 struct ethtool_usrip4_spec *spec_mask) 6735 { 6736 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6737 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6738 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6739 6740 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6741 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6742 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6743 6744 spec->tos = rule->tuples.ip_tos; 6745 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6746 0 : rule->tuples_mask.ip_tos; 6747 6748 spec->proto = rule->tuples.ip_proto; 6749 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6750 0 : rule->tuples_mask.ip_proto; 6751 6752 spec->ip_ver = ETH_RX_NFC_IP4; 6753 } 6754 6755 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6756 struct ethtool_tcpip6_spec *spec, 6757 struct ethtool_tcpip6_spec *spec_mask) 6758 { 6759 cpu_to_be32_array(spec->ip6src, 6760 rule->tuples.src_ip, IPV6_SIZE); 6761 cpu_to_be32_array(spec->ip6dst, 6762 rule->tuples.dst_ip, IPV6_SIZE); 6763 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6764 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6765 else 6766 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6767 IPV6_SIZE); 6768 6769 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6770 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6771 else 6772 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6773 IPV6_SIZE); 6774 6775 spec->tclass = rule->tuples.ip_tos; 6776 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6777 0 : rule->tuples_mask.ip_tos; 6778 6779 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6780 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6781 0 : cpu_to_be16(rule->tuples_mask.src_port); 6782 6783 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6784 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6785 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6786 } 6787 6788 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6789 struct ethtool_usrip6_spec *spec, 6790 struct ethtool_usrip6_spec *spec_mask) 6791 { 6792 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6793 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6794 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6795 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6796 else 6797 cpu_to_be32_array(spec_mask->ip6src, 6798 rule->tuples_mask.src_ip, IPV6_SIZE); 6799 6800 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6801 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6802 else 6803 cpu_to_be32_array(spec_mask->ip6dst, 6804 rule->tuples_mask.dst_ip, IPV6_SIZE); 6805 6806 spec->tclass = rule->tuples.ip_tos; 6807 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6808 0 : rule->tuples_mask.ip_tos; 6809 6810 spec->l4_proto = rule->tuples.ip_proto; 6811 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6812 0 : rule->tuples_mask.ip_proto; 6813 } 6814 6815 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6816 struct ethhdr *spec, 6817 struct ethhdr *spec_mask) 6818 { 6819 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6820 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6821 6822 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6823 eth_zero_addr(spec_mask->h_source); 6824 else 6825 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6826 6827 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6828 eth_zero_addr(spec_mask->h_dest); 6829 else 6830 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6831 6832 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6833 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6834 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6835 } 6836 6837 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6838 struct hclge_fd_rule *rule) 6839 { 6840 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6841 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6842 fs->h_ext.data[0] = 0; 6843 fs->h_ext.data[1] = 0; 6844 fs->m_ext.data[0] = 0; 6845 fs->m_ext.data[1] = 0; 6846 } else { 6847 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6848 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6849 fs->m_ext.data[0] = 6850 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6851 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6852 } 6853 } 6854 6855 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6856 struct hclge_fd_rule *rule) 6857 { 6858 if (fs->flow_type & FLOW_EXT) { 6859 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6860 fs->m_ext.vlan_tci = 6861 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6862 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6863 6864 hclge_fd_get_user_def_info(fs, rule); 6865 } 6866 6867 if (fs->flow_type & FLOW_MAC_EXT) { 6868 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6869 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6870 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6871 else 6872 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6873 rule->tuples_mask.dst_mac); 6874 } 6875 } 6876 6877 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6878 u16 location) 6879 { 6880 struct hclge_fd_rule *rule = NULL; 6881 struct hlist_node *node2; 6882 6883 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6884 if (rule->location == location) 6885 return rule; 6886 else if (rule->location > location) 6887 return NULL; 6888 } 6889 6890 return NULL; 6891 } 6892 6893 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6894 struct hclge_fd_rule *rule) 6895 { 6896 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6897 fs->ring_cookie = RX_CLS_FLOW_DISC; 6898 } else { 6899 u64 vf_id; 6900 6901 fs->ring_cookie = rule->queue_id; 6902 vf_id = rule->vf_id; 6903 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6904 fs->ring_cookie |= vf_id; 6905 } 6906 } 6907 6908 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6909 struct ethtool_rxnfc *cmd) 6910 { 6911 struct hclge_vport *vport = hclge_get_vport(handle); 6912 struct hclge_fd_rule *rule = NULL; 6913 struct hclge_dev *hdev = vport->back; 6914 struct ethtool_rx_flow_spec *fs; 6915 6916 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6917 return -EOPNOTSUPP; 6918 6919 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6920 6921 spin_lock_bh(&hdev->fd_rule_lock); 6922 6923 rule = hclge_get_fd_rule(hdev, fs->location); 6924 if (!rule) { 6925 spin_unlock_bh(&hdev->fd_rule_lock); 6926 return -ENOENT; 6927 } 6928 6929 fs->flow_type = rule->flow_type; 6930 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6931 case SCTP_V4_FLOW: 6932 case TCP_V4_FLOW: 6933 case UDP_V4_FLOW: 6934 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6935 &fs->m_u.tcp_ip4_spec); 6936 break; 6937 case IP_USER_FLOW: 6938 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6939 &fs->m_u.usr_ip4_spec); 6940 break; 6941 case SCTP_V6_FLOW: 6942 case TCP_V6_FLOW: 6943 case UDP_V6_FLOW: 6944 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6945 &fs->m_u.tcp_ip6_spec); 6946 break; 6947 case IPV6_USER_FLOW: 6948 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6949 &fs->m_u.usr_ip6_spec); 6950 break; 6951 /* The flow type of fd rule has been checked before adding in to rule 6952 * list. As other flow types have been handled, it must be ETHER_FLOW 6953 * for the default case 6954 */ 6955 default: 6956 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6957 &fs->m_u.ether_spec); 6958 break; 6959 } 6960 6961 hclge_fd_get_ext_info(fs, rule); 6962 6963 hclge_fd_get_ring_cookie(fs, rule); 6964 6965 spin_unlock_bh(&hdev->fd_rule_lock); 6966 6967 return 0; 6968 } 6969 6970 static int hclge_get_all_rules(struct hnae3_handle *handle, 6971 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6972 { 6973 struct hclge_vport *vport = hclge_get_vport(handle); 6974 struct hclge_dev *hdev = vport->back; 6975 struct hclge_fd_rule *rule; 6976 struct hlist_node *node2; 6977 int cnt = 0; 6978 6979 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6980 return -EOPNOTSUPP; 6981 6982 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6983 6984 spin_lock_bh(&hdev->fd_rule_lock); 6985 hlist_for_each_entry_safe(rule, node2, 6986 &hdev->fd_rule_list, rule_node) { 6987 if (cnt == cmd->rule_cnt) { 6988 spin_unlock_bh(&hdev->fd_rule_lock); 6989 return -EMSGSIZE; 6990 } 6991 6992 if (rule->state == HCLGE_FD_TO_DEL) 6993 continue; 6994 6995 rule_locs[cnt] = rule->location; 6996 cnt++; 6997 } 6998 6999 spin_unlock_bh(&hdev->fd_rule_lock); 7000 7001 cmd->rule_cnt = cnt; 7002 7003 return 0; 7004 } 7005 7006 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7007 struct hclge_fd_rule_tuples *tuples) 7008 { 7009 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7010 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7011 7012 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7013 tuples->ip_proto = fkeys->basic.ip_proto; 7014 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7015 7016 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7017 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7018 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7019 } else { 7020 int i; 7021 7022 for (i = 0; i < IPV6_SIZE; i++) { 7023 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7024 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7025 } 7026 } 7027 } 7028 7029 /* traverse all rules, check whether an existed rule has the same tuples */ 7030 static struct hclge_fd_rule * 7031 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7032 const struct hclge_fd_rule_tuples *tuples) 7033 { 7034 struct hclge_fd_rule *rule = NULL; 7035 struct hlist_node *node; 7036 7037 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7038 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7039 return rule; 7040 } 7041 7042 return NULL; 7043 } 7044 7045 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7046 struct hclge_fd_rule *rule) 7047 { 7048 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7049 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7050 BIT(INNER_SRC_PORT); 7051 rule->action = 0; 7052 rule->vf_id = 0; 7053 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7054 rule->state = HCLGE_FD_TO_ADD; 7055 if (tuples->ether_proto == ETH_P_IP) { 7056 if (tuples->ip_proto == IPPROTO_TCP) 7057 rule->flow_type = TCP_V4_FLOW; 7058 else 7059 rule->flow_type = UDP_V4_FLOW; 7060 } else { 7061 if (tuples->ip_proto == IPPROTO_TCP) 7062 rule->flow_type = TCP_V6_FLOW; 7063 else 7064 rule->flow_type = UDP_V6_FLOW; 7065 } 7066 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7067 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7068 } 7069 7070 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7071 u16 flow_id, struct flow_keys *fkeys) 7072 { 7073 struct hclge_vport *vport = hclge_get_vport(handle); 7074 struct hclge_fd_rule_tuples new_tuples = {}; 7075 struct hclge_dev *hdev = vport->back; 7076 struct hclge_fd_rule *rule; 7077 u16 bit_id; 7078 7079 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7080 return -EOPNOTSUPP; 7081 7082 /* when there is already fd rule existed add by user, 7083 * arfs should not work 7084 */ 7085 spin_lock_bh(&hdev->fd_rule_lock); 7086 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7087 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7088 spin_unlock_bh(&hdev->fd_rule_lock); 7089 return -EOPNOTSUPP; 7090 } 7091 7092 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7093 7094 /* check is there flow director filter existed for this flow, 7095 * if not, create a new filter for it; 7096 * if filter exist with different queue id, modify the filter; 7097 * if filter exist with same queue id, do nothing 7098 */ 7099 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7100 if (!rule) { 7101 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7102 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7103 spin_unlock_bh(&hdev->fd_rule_lock); 7104 return -ENOSPC; 7105 } 7106 7107 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7108 if (!rule) { 7109 spin_unlock_bh(&hdev->fd_rule_lock); 7110 return -ENOMEM; 7111 } 7112 7113 rule->location = bit_id; 7114 rule->arfs.flow_id = flow_id; 7115 rule->queue_id = queue_id; 7116 hclge_fd_build_arfs_rule(&new_tuples, rule); 7117 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7118 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7119 } else if (rule->queue_id != queue_id) { 7120 rule->queue_id = queue_id; 7121 rule->state = HCLGE_FD_TO_ADD; 7122 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7123 hclge_task_schedule(hdev, 0); 7124 } 7125 spin_unlock_bh(&hdev->fd_rule_lock); 7126 return rule->location; 7127 } 7128 7129 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7130 { 7131 #ifdef CONFIG_RFS_ACCEL 7132 struct hnae3_handle *handle = &hdev->vport[0].nic; 7133 struct hclge_fd_rule *rule; 7134 struct hlist_node *node; 7135 7136 spin_lock_bh(&hdev->fd_rule_lock); 7137 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7138 spin_unlock_bh(&hdev->fd_rule_lock); 7139 return; 7140 } 7141 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7142 if (rule->state != HCLGE_FD_ACTIVE) 7143 continue; 7144 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7145 rule->arfs.flow_id, rule->location)) { 7146 rule->state = HCLGE_FD_TO_DEL; 7147 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7148 } 7149 } 7150 spin_unlock_bh(&hdev->fd_rule_lock); 7151 #endif 7152 } 7153 7154 /* make sure being called after lock up with fd_rule_lock */ 7155 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7156 { 7157 #ifdef CONFIG_RFS_ACCEL 7158 struct hclge_fd_rule *rule; 7159 struct hlist_node *node; 7160 int ret; 7161 7162 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7163 return 0; 7164 7165 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7166 switch (rule->state) { 7167 case HCLGE_FD_TO_DEL: 7168 case HCLGE_FD_ACTIVE: 7169 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7170 rule->location, NULL, false); 7171 if (ret) 7172 return ret; 7173 fallthrough; 7174 case HCLGE_FD_TO_ADD: 7175 hclge_fd_dec_rule_cnt(hdev, rule->location); 7176 hlist_del(&rule->rule_node); 7177 kfree(rule); 7178 break; 7179 default: 7180 break; 7181 } 7182 } 7183 hclge_sync_fd_state(hdev); 7184 7185 #endif 7186 return 0; 7187 } 7188 7189 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7190 struct hclge_fd_rule *rule) 7191 { 7192 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7193 struct flow_match_basic match; 7194 u16 ethtype_key, ethtype_mask; 7195 7196 flow_rule_match_basic(flow, &match); 7197 ethtype_key = ntohs(match.key->n_proto); 7198 ethtype_mask = ntohs(match.mask->n_proto); 7199 7200 if (ethtype_key == ETH_P_ALL) { 7201 ethtype_key = 0; 7202 ethtype_mask = 0; 7203 } 7204 rule->tuples.ether_proto = ethtype_key; 7205 rule->tuples_mask.ether_proto = ethtype_mask; 7206 rule->tuples.ip_proto = match.key->ip_proto; 7207 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7208 } else { 7209 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7210 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7211 } 7212 } 7213 7214 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7215 struct hclge_fd_rule *rule) 7216 { 7217 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7218 struct flow_match_eth_addrs match; 7219 7220 flow_rule_match_eth_addrs(flow, &match); 7221 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7222 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7223 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7224 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7225 } else { 7226 rule->unused_tuple |= BIT(INNER_DST_MAC); 7227 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7228 } 7229 } 7230 7231 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7232 struct hclge_fd_rule *rule) 7233 { 7234 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7235 struct flow_match_vlan match; 7236 7237 flow_rule_match_vlan(flow, &match); 7238 rule->tuples.vlan_tag1 = match.key->vlan_id | 7239 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7240 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7241 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7242 } else { 7243 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7244 } 7245 } 7246 7247 static int hclge_get_cls_key_ip(const struct flow_rule *flow, 7248 struct hclge_fd_rule *rule, 7249 struct netlink_ext_ack *extack) 7250 { 7251 u16 addr_type = 0; 7252 7253 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7254 struct flow_match_control match; 7255 7256 flow_rule_match_control(flow, &match); 7257 addr_type = match.key->addr_type; 7258 7259 if (flow_rule_has_control_flags(match.mask->flags, extack)) 7260 return -EOPNOTSUPP; 7261 } 7262 7263 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7264 struct flow_match_ipv4_addrs match; 7265 7266 flow_rule_match_ipv4_addrs(flow, &match); 7267 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7268 rule->tuples_mask.src_ip[IPV4_INDEX] = 7269 be32_to_cpu(match.mask->src); 7270 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7271 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7272 be32_to_cpu(match.mask->dst); 7273 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7274 struct flow_match_ipv6_addrs match; 7275 7276 flow_rule_match_ipv6_addrs(flow, &match); 7277 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7278 IPV6_SIZE); 7279 be32_to_cpu_array(rule->tuples_mask.src_ip, 7280 match.mask->src.s6_addr32, IPV6_SIZE); 7281 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7282 IPV6_SIZE); 7283 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7284 match.mask->dst.s6_addr32, IPV6_SIZE); 7285 } else { 7286 rule->unused_tuple |= BIT(INNER_SRC_IP); 7287 rule->unused_tuple |= BIT(INNER_DST_IP); 7288 } 7289 7290 return 0; 7291 } 7292 7293 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7294 struct hclge_fd_rule *rule) 7295 { 7296 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7297 struct flow_match_ports match; 7298 7299 flow_rule_match_ports(flow, &match); 7300 7301 rule->tuples.src_port = be16_to_cpu(match.key->src); 7302 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7303 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7304 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7305 } else { 7306 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7307 rule->unused_tuple |= BIT(INNER_DST_PORT); 7308 } 7309 } 7310 7311 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7312 struct flow_cls_offload *cls_flower, 7313 struct hclge_fd_rule *rule) 7314 { 7315 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7316 struct netlink_ext_ack *extack = cls_flower->common.extack; 7317 struct flow_dissector *dissector = flow->match.dissector; 7318 int ret; 7319 7320 if (dissector->used_keys & 7321 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7322 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7323 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7324 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7325 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7326 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7327 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7328 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7329 dissector->used_keys); 7330 return -EOPNOTSUPP; 7331 } 7332 7333 hclge_get_cls_key_basic(flow, rule); 7334 hclge_get_cls_key_mac(flow, rule); 7335 hclge_get_cls_key_vlan(flow, rule); 7336 7337 ret = hclge_get_cls_key_ip(flow, rule, extack); 7338 if (ret) 7339 return ret; 7340 7341 hclge_get_cls_key_port(flow, rule); 7342 7343 return 0; 7344 } 7345 7346 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7347 struct flow_cls_offload *cls_flower, int tc) 7348 { 7349 u32 prio = cls_flower->common.prio; 7350 7351 if (tc < 0 || tc > hdev->tc_max) { 7352 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7353 return -EINVAL; 7354 } 7355 7356 if (prio == 0 || 7357 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7358 dev_err(&hdev->pdev->dev, 7359 "prio %u should be in range[1, %u]\n", 7360 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7361 return -EINVAL; 7362 } 7363 7364 if (test_bit(prio - 1, hdev->fd_bmap)) { 7365 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7366 return -EINVAL; 7367 } 7368 return 0; 7369 } 7370 7371 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7372 struct flow_cls_offload *cls_flower, 7373 int tc) 7374 { 7375 struct hclge_vport *vport = hclge_get_vport(handle); 7376 struct hclge_dev *hdev = vport->back; 7377 struct hclge_fd_rule *rule; 7378 int ret; 7379 7380 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7381 dev_err(&hdev->pdev->dev, 7382 "cls flower is not supported\n"); 7383 return -EOPNOTSUPP; 7384 } 7385 7386 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7387 if (ret) { 7388 dev_err(&hdev->pdev->dev, 7389 "failed to check cls flower params, ret = %d\n", ret); 7390 return ret; 7391 } 7392 7393 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7394 if (!rule) 7395 return -ENOMEM; 7396 7397 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7398 if (ret) { 7399 kfree(rule); 7400 return ret; 7401 } 7402 7403 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7404 rule->cls_flower.tc = tc; 7405 rule->location = cls_flower->common.prio - 1; 7406 rule->vf_id = 0; 7407 rule->cls_flower.cookie = cls_flower->cookie; 7408 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7409 7410 ret = hclge_add_fd_entry_common(hdev, rule); 7411 if (ret) 7412 kfree(rule); 7413 7414 return ret; 7415 } 7416 7417 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7418 unsigned long cookie) 7419 { 7420 struct hclge_fd_rule *rule; 7421 struct hlist_node *node; 7422 7423 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7424 if (rule->cls_flower.cookie == cookie) 7425 return rule; 7426 } 7427 7428 return NULL; 7429 } 7430 7431 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7432 struct flow_cls_offload *cls_flower) 7433 { 7434 struct hclge_vport *vport = hclge_get_vport(handle); 7435 struct hclge_dev *hdev = vport->back; 7436 struct hclge_fd_rule *rule; 7437 int ret; 7438 7439 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7440 return -EOPNOTSUPP; 7441 7442 spin_lock_bh(&hdev->fd_rule_lock); 7443 7444 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7445 if (!rule) { 7446 spin_unlock_bh(&hdev->fd_rule_lock); 7447 return -EINVAL; 7448 } 7449 7450 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7451 NULL, false); 7452 if (ret) { 7453 /* if tcam config fail, set rule state to TO_DEL, 7454 * so the rule will be deleted when periodic 7455 * task being scheduled. 7456 */ 7457 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7458 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7459 spin_unlock_bh(&hdev->fd_rule_lock); 7460 return ret; 7461 } 7462 7463 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7464 spin_unlock_bh(&hdev->fd_rule_lock); 7465 7466 return 0; 7467 } 7468 7469 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7470 { 7471 struct hclge_fd_rule *rule; 7472 struct hlist_node *node; 7473 int ret = 0; 7474 7475 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7476 return; 7477 7478 spin_lock_bh(&hdev->fd_rule_lock); 7479 7480 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7481 switch (rule->state) { 7482 case HCLGE_FD_TO_ADD: 7483 ret = hclge_fd_config_rule(hdev, rule); 7484 if (ret) 7485 goto out; 7486 rule->state = HCLGE_FD_ACTIVE; 7487 break; 7488 case HCLGE_FD_TO_DEL: 7489 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7490 rule->location, NULL, false); 7491 if (ret) 7492 goto out; 7493 hclge_fd_dec_rule_cnt(hdev, rule->location); 7494 hclge_fd_free_node(hdev, rule); 7495 break; 7496 default: 7497 break; 7498 } 7499 } 7500 7501 out: 7502 if (ret) 7503 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7504 7505 spin_unlock_bh(&hdev->fd_rule_lock); 7506 } 7507 7508 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7509 { 7510 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7511 return; 7512 7513 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7514 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7515 7516 hclge_clear_fd_rules_in_list(hdev, clear_list); 7517 } 7518 7519 hclge_sync_fd_user_def_cfg(hdev, false); 7520 7521 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7522 } 7523 7524 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7525 { 7526 struct hclge_vport *vport = hclge_get_vport(handle); 7527 struct hclge_dev *hdev = vport->back; 7528 7529 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7530 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7531 } 7532 7533 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7534 { 7535 struct hclge_vport *vport = hclge_get_vport(handle); 7536 struct hclge_dev *hdev = vport->back; 7537 7538 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7539 } 7540 7541 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7542 { 7543 struct hclge_vport *vport = hclge_get_vport(handle); 7544 struct hclge_dev *hdev = vport->back; 7545 7546 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7547 } 7548 7549 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7550 { 7551 struct hclge_vport *vport = hclge_get_vport(handle); 7552 struct hclge_dev *hdev = vport->back; 7553 7554 return hdev->rst_stats.hw_reset_done_cnt; 7555 } 7556 7557 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7558 { 7559 struct hclge_vport *vport = hclge_get_vport(handle); 7560 struct hclge_dev *hdev = vport->back; 7561 7562 hdev->fd_en = enable; 7563 7564 if (!enable) 7565 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7566 else 7567 hclge_restore_fd_entries(handle); 7568 7569 hclge_task_schedule(hdev, 0); 7570 } 7571 7572 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7573 { 7574 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7575 7576 struct hclge_desc desc; 7577 struct hclge_config_mac_mode_cmd *req = 7578 (struct hclge_config_mac_mode_cmd *)desc.data; 7579 u32 loop_en = 0; 7580 int ret; 7581 7582 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7583 7584 if (enable) { 7585 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7586 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7587 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7588 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7589 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7590 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7591 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7592 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7593 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7594 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7595 } 7596 7597 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7598 7599 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7600 if (ret) { 7601 dev_err(&hdev->pdev->dev, 7602 "mac enable fail, ret =%d.\n", ret); 7603 return; 7604 } 7605 7606 if (!enable) 7607 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7608 HCLGE_LINK_STATUS_WAIT_CNT); 7609 } 7610 7611 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7612 u8 switch_param, u8 param_mask) 7613 { 7614 struct hclge_mac_vlan_switch_cmd *req; 7615 struct hclge_desc desc; 7616 u32 func_id; 7617 int ret; 7618 7619 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7620 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7621 7622 /* read current config parameter */ 7623 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7624 true); 7625 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7626 req->func_id = cpu_to_le32(func_id); 7627 7628 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7629 if (ret) { 7630 dev_err(&hdev->pdev->dev, 7631 "read mac vlan switch parameter fail, ret = %d\n", ret); 7632 return ret; 7633 } 7634 7635 /* modify and write new config parameter */ 7636 hclge_comm_cmd_reuse_desc(&desc, false); 7637 req->switch_param = (req->switch_param & param_mask) | switch_param; 7638 req->param_mask = param_mask; 7639 7640 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7641 if (ret) 7642 dev_err(&hdev->pdev->dev, 7643 "set mac vlan switch parameter fail, ret = %d\n", ret); 7644 return ret; 7645 } 7646 7647 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7648 int link_ret) 7649 { 7650 #define HCLGE_PHY_LINK_STATUS_NUM 200 7651 7652 struct phy_device *phydev = hdev->hw.mac.phydev; 7653 int i = 0; 7654 int ret; 7655 7656 do { 7657 ret = phy_read_status(phydev); 7658 if (ret) { 7659 dev_err(&hdev->pdev->dev, 7660 "phy update link status fail, ret = %d\n", ret); 7661 return; 7662 } 7663 7664 if (phydev->link == link_ret) 7665 break; 7666 7667 msleep(HCLGE_LINK_STATUS_MS); 7668 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7669 } 7670 7671 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7672 int wait_cnt) 7673 { 7674 int link_status; 7675 int i = 0; 7676 int ret; 7677 7678 do { 7679 ret = hclge_get_mac_link_status(hdev, &link_status); 7680 if (ret) 7681 return ret; 7682 if (link_status == link_ret) 7683 return 0; 7684 7685 msleep(HCLGE_LINK_STATUS_MS); 7686 } while (++i < wait_cnt); 7687 return -EBUSY; 7688 } 7689 7690 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7691 bool is_phy) 7692 { 7693 #define HCLGE_MAC_LINK_STATUS_NUM 100 7694 7695 int link_ret; 7696 7697 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7698 7699 if (is_phy) 7700 hclge_phy_link_status_wait(hdev, link_ret); 7701 7702 return hclge_mac_link_status_wait(hdev, link_ret, 7703 HCLGE_MAC_LINK_STATUS_NUM); 7704 } 7705 7706 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7707 { 7708 struct hclge_config_mac_mode_cmd *req; 7709 struct hclge_desc desc; 7710 u32 loop_en; 7711 int ret; 7712 7713 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7714 /* 1 Read out the MAC mode config at first */ 7715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7716 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7717 if (ret) { 7718 dev_err(&hdev->pdev->dev, 7719 "mac loopback get fail, ret =%d.\n", ret); 7720 return ret; 7721 } 7722 7723 /* 2 Then setup the loopback flag */ 7724 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7725 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7726 7727 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7728 7729 /* 3 Config mac work mode with loopback flag 7730 * and its original configure parameters 7731 */ 7732 hclge_comm_cmd_reuse_desc(&desc, false); 7733 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7734 if (ret) 7735 dev_err(&hdev->pdev->dev, 7736 "mac loopback set fail, ret =%d.\n", ret); 7737 return ret; 7738 } 7739 7740 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7741 enum hnae3_loop loop_mode) 7742 { 7743 struct hclge_common_lb_cmd *req; 7744 struct hclge_desc desc; 7745 u8 loop_mode_b; 7746 int ret; 7747 7748 req = (struct hclge_common_lb_cmd *)desc.data; 7749 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7750 7751 switch (loop_mode) { 7752 case HNAE3_LOOP_SERIAL_SERDES: 7753 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7754 break; 7755 case HNAE3_LOOP_PARALLEL_SERDES: 7756 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7757 break; 7758 case HNAE3_LOOP_PHY: 7759 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7760 break; 7761 default: 7762 dev_err(&hdev->pdev->dev, 7763 "unsupported loopback mode %d\n", loop_mode); 7764 return -ENOTSUPP; 7765 } 7766 7767 req->mask = loop_mode_b; 7768 if (en) 7769 req->enable = loop_mode_b; 7770 7771 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7772 if (ret) 7773 dev_err(&hdev->pdev->dev, 7774 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7775 loop_mode, ret); 7776 7777 return ret; 7778 } 7779 7780 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7781 { 7782 #define HCLGE_COMMON_LB_RETRY_MS 10 7783 #define HCLGE_COMMON_LB_RETRY_NUM 100 7784 7785 struct hclge_common_lb_cmd *req; 7786 struct hclge_desc desc; 7787 u32 i = 0; 7788 int ret; 7789 7790 req = (struct hclge_common_lb_cmd *)desc.data; 7791 7792 do { 7793 msleep(HCLGE_COMMON_LB_RETRY_MS); 7794 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7795 true); 7796 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7797 if (ret) { 7798 dev_err(&hdev->pdev->dev, 7799 "failed to get loopback done status, ret = %d\n", 7800 ret); 7801 return ret; 7802 } 7803 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7804 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7805 7806 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7807 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7808 return -EBUSY; 7809 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7810 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7811 return -EIO; 7812 } 7813 7814 return 0; 7815 } 7816 7817 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7818 enum hnae3_loop loop_mode) 7819 { 7820 int ret; 7821 7822 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7823 if (ret) 7824 return ret; 7825 7826 return hclge_cfg_common_loopback_wait(hdev); 7827 } 7828 7829 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7830 enum hnae3_loop loop_mode) 7831 { 7832 int ret; 7833 7834 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7835 if (ret) 7836 return ret; 7837 7838 hclge_cfg_mac_mode(hdev, en); 7839 7840 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7841 if (ret) 7842 dev_err(&hdev->pdev->dev, 7843 "serdes loopback config mac mode timeout\n"); 7844 7845 return ret; 7846 } 7847 7848 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7849 struct phy_device *phydev) 7850 { 7851 int ret; 7852 7853 if (!phydev->suspended) { 7854 ret = phy_suspend(phydev); 7855 if (ret) 7856 return ret; 7857 } 7858 7859 ret = phy_resume(phydev); 7860 if (ret) 7861 return ret; 7862 7863 return phy_loopback(phydev, true); 7864 } 7865 7866 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7867 struct phy_device *phydev) 7868 { 7869 int ret; 7870 7871 ret = phy_loopback(phydev, false); 7872 if (ret) 7873 return ret; 7874 7875 return phy_suspend(phydev); 7876 } 7877 7878 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7879 { 7880 struct phy_device *phydev = hdev->hw.mac.phydev; 7881 int ret; 7882 7883 if (!phydev) { 7884 if (hnae3_dev_phy_imp_supported(hdev)) 7885 return hclge_set_common_loopback(hdev, en, 7886 HNAE3_LOOP_PHY); 7887 return -ENOTSUPP; 7888 } 7889 7890 if (en) 7891 ret = hclge_enable_phy_loopback(hdev, phydev); 7892 else 7893 ret = hclge_disable_phy_loopback(hdev, phydev); 7894 if (ret) { 7895 dev_err(&hdev->pdev->dev, 7896 "set phy loopback fail, ret = %d\n", ret); 7897 return ret; 7898 } 7899 7900 hclge_cfg_mac_mode(hdev, en); 7901 7902 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7903 if (ret) 7904 dev_err(&hdev->pdev->dev, 7905 "phy loopback config mac mode timeout\n"); 7906 7907 return ret; 7908 } 7909 7910 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7911 u16 stream_id, bool enable) 7912 { 7913 struct hclge_desc desc; 7914 struct hclge_cfg_com_tqp_queue_cmd *req = 7915 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7916 7917 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7918 req->tqp_id = cpu_to_le16(tqp_id); 7919 req->stream_id = cpu_to_le16(stream_id); 7920 if (enable) 7921 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7922 7923 return hclge_cmd_send(&hdev->hw, &desc, 1); 7924 } 7925 7926 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7927 { 7928 struct hclge_vport *vport = hclge_get_vport(handle); 7929 struct hclge_dev *hdev = vport->back; 7930 int ret; 7931 u16 i; 7932 7933 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7934 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7935 if (ret) 7936 return ret; 7937 } 7938 return 0; 7939 } 7940 7941 static int hclge_set_loopback(struct hnae3_handle *handle, 7942 enum hnae3_loop loop_mode, bool en) 7943 { 7944 struct hclge_vport *vport = hclge_get_vport(handle); 7945 struct hclge_dev *hdev = vport->back; 7946 int ret = 0; 7947 7948 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7949 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7950 * the same, the packets are looped back in the SSU. If SSU loopback 7951 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7952 */ 7953 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7954 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7955 7956 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7957 HCLGE_SWITCH_ALW_LPBK_MASK); 7958 if (ret) 7959 return ret; 7960 } 7961 7962 switch (loop_mode) { 7963 case HNAE3_LOOP_APP: 7964 ret = hclge_set_app_loopback(hdev, en); 7965 break; 7966 case HNAE3_LOOP_SERIAL_SERDES: 7967 case HNAE3_LOOP_PARALLEL_SERDES: 7968 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7969 break; 7970 case HNAE3_LOOP_PHY: 7971 ret = hclge_set_phy_loopback(hdev, en); 7972 break; 7973 case HNAE3_LOOP_EXTERNAL: 7974 break; 7975 default: 7976 ret = -ENOTSUPP; 7977 dev_err(&hdev->pdev->dev, 7978 "loop_mode %d is not supported\n", loop_mode); 7979 break; 7980 } 7981 7982 if (ret) 7983 return ret; 7984 7985 ret = hclge_tqp_enable(handle, en); 7986 if (ret) 7987 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7988 en ? "enable" : "disable", ret); 7989 7990 return ret; 7991 } 7992 7993 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7994 { 7995 int ret; 7996 7997 ret = hclge_set_app_loopback(hdev, false); 7998 if (ret) 7999 return ret; 8000 8001 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 8002 if (ret) 8003 return ret; 8004 8005 return hclge_cfg_common_loopback(hdev, false, 8006 HNAE3_LOOP_PARALLEL_SERDES); 8007 } 8008 8009 static void hclge_flush_link_update(struct hclge_dev *hdev) 8010 { 8011 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 8012 8013 unsigned long last = hdev->serv_processed_cnt; 8014 int i = 0; 8015 8016 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8017 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8018 last == hdev->serv_processed_cnt) 8019 usleep_range(1, 1); 8020 } 8021 8022 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8023 { 8024 struct hclge_vport *vport = hclge_get_vport(handle); 8025 struct hclge_dev *hdev = vport->back; 8026 8027 if (enable) { 8028 hclge_task_schedule(hdev, 0); 8029 } else { 8030 /* Set the DOWN flag here to disable link updating */ 8031 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8032 8033 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 8034 hclge_flush_link_update(hdev); 8035 } 8036 } 8037 8038 static int hclge_ae_start(struct hnae3_handle *handle) 8039 { 8040 struct hclge_vport *vport = hclge_get_vport(handle); 8041 struct hclge_dev *hdev = vport->back; 8042 8043 /* mac enable */ 8044 hclge_cfg_mac_mode(hdev, true); 8045 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8046 hdev->hw.mac.link = 0; 8047 8048 /* reset tqp stats */ 8049 hclge_comm_reset_tqp_stats(handle); 8050 8051 hclge_mac_start_phy(hdev); 8052 8053 return 0; 8054 } 8055 8056 static void hclge_ae_stop(struct hnae3_handle *handle) 8057 { 8058 struct hclge_vport *vport = hclge_get_vport(handle); 8059 struct hclge_dev *hdev = vport->back; 8060 8061 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8062 spin_lock_bh(&hdev->fd_rule_lock); 8063 hclge_clear_arfs_rules(hdev); 8064 spin_unlock_bh(&hdev->fd_rule_lock); 8065 8066 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8067 * so it only need to stop phy here. 8068 */ 8069 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8070 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8071 HCLGE_PFC_DISABLE); 8072 if (hdev->reset_type != HNAE3_FUNC_RESET && 8073 hdev->reset_type != HNAE3_FLR_RESET) { 8074 hclge_mac_stop_phy(hdev); 8075 hclge_update_link_status(hdev); 8076 return; 8077 } 8078 } 8079 8080 hclge_reset_tqp(handle); 8081 8082 hclge_config_mac_tnl_int(hdev, false); 8083 8084 /* Mac disable */ 8085 hclge_cfg_mac_mode(hdev, false); 8086 8087 hclge_mac_stop_phy(hdev); 8088 8089 /* reset tqp stats */ 8090 hclge_comm_reset_tqp_stats(handle); 8091 hclge_update_link_status(hdev); 8092 } 8093 8094 int hclge_vport_start(struct hclge_vport *vport) 8095 { 8096 struct hclge_dev *hdev = vport->back; 8097 8098 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8099 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8100 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8101 vport->last_active_jiffies = jiffies; 8102 vport->need_notify = 0; 8103 8104 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8105 if (vport->vport_id) { 8106 hclge_restore_mac_table_common(vport); 8107 hclge_restore_vport_vlan_table(vport); 8108 } else { 8109 hclge_restore_hw_table(hdev); 8110 } 8111 } 8112 8113 clear_bit(vport->vport_id, hdev->vport_config_block); 8114 8115 return 0; 8116 } 8117 8118 void hclge_vport_stop(struct hclge_vport *vport) 8119 { 8120 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8121 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8122 vport->need_notify = 0; 8123 } 8124 8125 static int hclge_client_start(struct hnae3_handle *handle) 8126 { 8127 struct hclge_vport *vport = hclge_get_vport(handle); 8128 8129 return hclge_vport_start(vport); 8130 } 8131 8132 static void hclge_client_stop(struct hnae3_handle *handle) 8133 { 8134 struct hclge_vport *vport = hclge_get_vport(handle); 8135 8136 hclge_vport_stop(vport); 8137 } 8138 8139 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8140 u16 cmdq_resp, u8 resp_code, 8141 enum hclge_mac_vlan_tbl_opcode op) 8142 { 8143 struct hclge_dev *hdev = vport->back; 8144 8145 if (cmdq_resp) { 8146 dev_err(&hdev->pdev->dev, 8147 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8148 cmdq_resp); 8149 return -EIO; 8150 } 8151 8152 if (op == HCLGE_MAC_VLAN_ADD) { 8153 if (!resp_code || resp_code == 1) 8154 return 0; 8155 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8156 resp_code == HCLGE_ADD_MC_OVERFLOW) 8157 return -ENOSPC; 8158 8159 dev_err(&hdev->pdev->dev, 8160 "add mac addr failed for undefined, code=%u.\n", 8161 resp_code); 8162 return -EIO; 8163 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8164 if (!resp_code) { 8165 return 0; 8166 } else if (resp_code == 1) { 8167 dev_dbg(&hdev->pdev->dev, 8168 "remove mac addr failed for miss.\n"); 8169 return -ENOENT; 8170 } 8171 8172 dev_err(&hdev->pdev->dev, 8173 "remove mac addr failed for undefined, code=%u.\n", 8174 resp_code); 8175 return -EIO; 8176 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8177 if (!resp_code) { 8178 return 0; 8179 } else if (resp_code == 1) { 8180 dev_dbg(&hdev->pdev->dev, 8181 "lookup mac addr failed for miss.\n"); 8182 return -ENOENT; 8183 } 8184 8185 dev_err(&hdev->pdev->dev, 8186 "lookup mac addr failed for undefined, code=%u.\n", 8187 resp_code); 8188 return -EIO; 8189 } 8190 8191 dev_err(&hdev->pdev->dev, 8192 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8193 8194 return -EINVAL; 8195 } 8196 8197 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8198 { 8199 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8200 8201 unsigned int word_num; 8202 unsigned int bit_num; 8203 8204 if (vfid > 255 || vfid < 0) 8205 return -EIO; 8206 8207 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8208 word_num = vfid / 32; 8209 bit_num = vfid % 32; 8210 if (clr) 8211 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8212 else 8213 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8214 } else { 8215 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8216 bit_num = vfid % 32; 8217 if (clr) 8218 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8219 else 8220 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8221 } 8222 8223 return 0; 8224 } 8225 8226 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8227 { 8228 #define HCLGE_DESC_NUMBER 3 8229 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8230 int i, j; 8231 8232 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8233 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8234 if (desc[i].data[j]) 8235 return false; 8236 8237 return true; 8238 } 8239 8240 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8241 const u8 *addr, bool is_mc) 8242 { 8243 const unsigned char *mac_addr = addr; 8244 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8245 (mac_addr[0]) | (mac_addr[1] << 8); 8246 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8247 8248 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8249 if (is_mc) { 8250 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8251 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8252 } 8253 8254 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8255 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8256 } 8257 8258 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8259 struct hclge_mac_vlan_tbl_entry_cmd *req) 8260 { 8261 struct hclge_dev *hdev = vport->back; 8262 struct hclge_desc desc; 8263 u8 resp_code; 8264 u16 retval; 8265 int ret; 8266 8267 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8268 8269 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8270 8271 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8272 if (ret) { 8273 dev_err(&hdev->pdev->dev, 8274 "del mac addr failed for cmd_send, ret =%d.\n", 8275 ret); 8276 return ret; 8277 } 8278 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8279 retval = le16_to_cpu(desc.retval); 8280 8281 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8282 HCLGE_MAC_VLAN_REMOVE); 8283 } 8284 8285 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8286 struct hclge_mac_vlan_tbl_entry_cmd *req, 8287 struct hclge_desc *desc, 8288 bool is_mc) 8289 { 8290 struct hclge_dev *hdev = vport->back; 8291 u8 resp_code; 8292 u16 retval; 8293 int ret; 8294 8295 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8296 if (is_mc) { 8297 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8298 memcpy(desc[0].data, 8299 req, 8300 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8301 hclge_cmd_setup_basic_desc(&desc[1], 8302 HCLGE_OPC_MAC_VLAN_ADD, 8303 true); 8304 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8305 hclge_cmd_setup_basic_desc(&desc[2], 8306 HCLGE_OPC_MAC_VLAN_ADD, 8307 true); 8308 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8309 } else { 8310 memcpy(desc[0].data, 8311 req, 8312 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8313 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8314 } 8315 if (ret) { 8316 dev_err(&hdev->pdev->dev, 8317 "lookup mac addr failed for cmd_send, ret =%d.\n", 8318 ret); 8319 return ret; 8320 } 8321 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8322 retval = le16_to_cpu(desc[0].retval); 8323 8324 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8325 HCLGE_MAC_VLAN_LKUP); 8326 } 8327 8328 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8329 struct hclge_mac_vlan_tbl_entry_cmd *req, 8330 struct hclge_desc *mc_desc) 8331 { 8332 struct hclge_dev *hdev = vport->back; 8333 int cfg_status; 8334 u8 resp_code; 8335 u16 retval; 8336 int ret; 8337 8338 if (!mc_desc) { 8339 struct hclge_desc desc; 8340 8341 hclge_cmd_setup_basic_desc(&desc, 8342 HCLGE_OPC_MAC_VLAN_ADD, 8343 false); 8344 memcpy(desc.data, req, 8345 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8346 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8347 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8348 retval = le16_to_cpu(desc.retval); 8349 8350 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8351 resp_code, 8352 HCLGE_MAC_VLAN_ADD); 8353 } else { 8354 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8355 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8356 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8357 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8358 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8359 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8360 memcpy(mc_desc[0].data, req, 8361 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8362 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8363 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8364 retval = le16_to_cpu(mc_desc[0].retval); 8365 8366 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8367 resp_code, 8368 HCLGE_MAC_VLAN_ADD); 8369 } 8370 8371 if (ret) { 8372 dev_err(&hdev->pdev->dev, 8373 "add mac addr failed for cmd_send, ret =%d.\n", 8374 ret); 8375 return ret; 8376 } 8377 8378 return cfg_status; 8379 } 8380 8381 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8382 u16 *allocated_size) 8383 { 8384 struct hclge_umv_spc_alc_cmd *req; 8385 struct hclge_desc desc; 8386 int ret; 8387 8388 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8389 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8390 8391 req->space_size = cpu_to_le32(space_size); 8392 8393 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8394 if (ret) { 8395 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8396 ret); 8397 return ret; 8398 } 8399 8400 *allocated_size = le32_to_cpu(desc.data[1]); 8401 8402 return 0; 8403 } 8404 8405 static int hclge_init_umv_space(struct hclge_dev *hdev) 8406 { 8407 u16 allocated_size = 0; 8408 int ret; 8409 8410 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8411 if (ret) 8412 return ret; 8413 8414 if (allocated_size < hdev->wanted_umv_size) 8415 dev_warn(&hdev->pdev->dev, 8416 "failed to alloc umv space, want %u, get %u\n", 8417 hdev->wanted_umv_size, allocated_size); 8418 8419 hdev->max_umv_size = allocated_size; 8420 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8421 hdev->share_umv_size = hdev->priv_umv_size + 8422 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8423 8424 if (hdev->ae_dev->dev_specs.mc_mac_size) 8425 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8426 8427 return 0; 8428 } 8429 8430 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8431 { 8432 struct hclge_vport *vport; 8433 int i; 8434 8435 for (i = 0; i < hdev->num_alloc_vport; i++) { 8436 vport = &hdev->vport[i]; 8437 vport->used_umv_num = 0; 8438 } 8439 8440 mutex_lock(&hdev->vport_lock); 8441 hdev->share_umv_size = hdev->priv_umv_size + 8442 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8443 mutex_unlock(&hdev->vport_lock); 8444 8445 hdev->used_mc_mac_num = 0; 8446 } 8447 8448 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8449 { 8450 struct hclge_dev *hdev = vport->back; 8451 bool is_full; 8452 8453 if (need_lock) 8454 mutex_lock(&hdev->vport_lock); 8455 8456 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8457 hdev->share_umv_size == 0); 8458 8459 if (need_lock) 8460 mutex_unlock(&hdev->vport_lock); 8461 8462 return is_full; 8463 } 8464 8465 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8466 { 8467 struct hclge_dev *hdev = vport->back; 8468 8469 if (is_free) { 8470 if (vport->used_umv_num > hdev->priv_umv_size) 8471 hdev->share_umv_size++; 8472 8473 if (vport->used_umv_num > 0) 8474 vport->used_umv_num--; 8475 } else { 8476 if (vport->used_umv_num >= hdev->priv_umv_size && 8477 hdev->share_umv_size > 0) 8478 hdev->share_umv_size--; 8479 vport->used_umv_num++; 8480 } 8481 } 8482 8483 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8484 const u8 *mac_addr) 8485 { 8486 struct hclge_mac_node *mac_node, *tmp; 8487 8488 list_for_each_entry_safe(mac_node, tmp, list, node) 8489 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8490 return mac_node; 8491 8492 return NULL; 8493 } 8494 8495 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8496 enum HCLGE_MAC_NODE_STATE state) 8497 { 8498 switch (state) { 8499 /* from set_rx_mode or tmp_add_list */ 8500 case HCLGE_MAC_TO_ADD: 8501 if (mac_node->state == HCLGE_MAC_TO_DEL) 8502 mac_node->state = HCLGE_MAC_ACTIVE; 8503 break; 8504 /* only from set_rx_mode */ 8505 case HCLGE_MAC_TO_DEL: 8506 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8507 list_del(&mac_node->node); 8508 kfree(mac_node); 8509 } else { 8510 mac_node->state = HCLGE_MAC_TO_DEL; 8511 } 8512 break; 8513 /* only from tmp_add_list, the mac_node->state won't be 8514 * ACTIVE. 8515 */ 8516 case HCLGE_MAC_ACTIVE: 8517 if (mac_node->state == HCLGE_MAC_TO_ADD) 8518 mac_node->state = HCLGE_MAC_ACTIVE; 8519 8520 break; 8521 } 8522 } 8523 8524 int hclge_update_mac_list(struct hclge_vport *vport, 8525 enum HCLGE_MAC_NODE_STATE state, 8526 enum HCLGE_MAC_ADDR_TYPE mac_type, 8527 const unsigned char *addr) 8528 { 8529 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8530 struct hclge_dev *hdev = vport->back; 8531 struct hclge_mac_node *mac_node; 8532 struct list_head *list; 8533 8534 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8535 &vport->uc_mac_list : &vport->mc_mac_list; 8536 8537 spin_lock_bh(&vport->mac_list_lock); 8538 8539 /* if the mac addr is already in the mac list, no need to add a new 8540 * one into it, just check the mac addr state, convert it to a new 8541 * state, or just remove it, or do nothing. 8542 */ 8543 mac_node = hclge_find_mac_node(list, addr); 8544 if (mac_node) { 8545 hclge_update_mac_node(mac_node, state); 8546 spin_unlock_bh(&vport->mac_list_lock); 8547 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8548 return 0; 8549 } 8550 8551 /* if this address is never added, unnecessary to delete */ 8552 if (state == HCLGE_MAC_TO_DEL) { 8553 spin_unlock_bh(&vport->mac_list_lock); 8554 hnae3_format_mac_addr(format_mac_addr, addr); 8555 dev_err(&hdev->pdev->dev, 8556 "failed to delete address %s from mac list\n", 8557 format_mac_addr); 8558 return -ENOENT; 8559 } 8560 8561 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8562 if (!mac_node) { 8563 spin_unlock_bh(&vport->mac_list_lock); 8564 return -ENOMEM; 8565 } 8566 8567 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8568 8569 mac_node->state = state; 8570 ether_addr_copy(mac_node->mac_addr, addr); 8571 list_add_tail(&mac_node->node, list); 8572 8573 spin_unlock_bh(&vport->mac_list_lock); 8574 8575 return 0; 8576 } 8577 8578 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8579 const unsigned char *addr) 8580 { 8581 struct hclge_vport *vport = hclge_get_vport(handle); 8582 8583 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8584 addr); 8585 } 8586 8587 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8588 const unsigned char *addr) 8589 { 8590 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8591 struct hclge_dev *hdev = vport->back; 8592 struct hclge_mac_vlan_tbl_entry_cmd req; 8593 struct hclge_desc desc; 8594 u16 egress_port = 0; 8595 int ret; 8596 8597 /* mac addr check */ 8598 if (is_zero_ether_addr(addr) || 8599 is_broadcast_ether_addr(addr) || 8600 is_multicast_ether_addr(addr)) { 8601 hnae3_format_mac_addr(format_mac_addr, addr); 8602 dev_err(&hdev->pdev->dev, 8603 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8604 format_mac_addr, is_zero_ether_addr(addr), 8605 is_broadcast_ether_addr(addr), 8606 is_multicast_ether_addr(addr)); 8607 return -EINVAL; 8608 } 8609 8610 memset(&req, 0, sizeof(req)); 8611 8612 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8613 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8614 8615 req.egress_port = cpu_to_le16(egress_port); 8616 8617 hclge_prepare_mac_addr(&req, addr, false); 8618 8619 /* Lookup the mac address in the mac_vlan table, and add 8620 * it if the entry is inexistent. Repeated unicast entry 8621 * is not allowed in the mac vlan table. 8622 */ 8623 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8624 if (ret == -ENOENT) { 8625 mutex_lock(&hdev->vport_lock); 8626 if (!hclge_is_umv_space_full(vport, false)) { 8627 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8628 if (!ret) 8629 hclge_update_umv_space(vport, false); 8630 mutex_unlock(&hdev->vport_lock); 8631 return ret; 8632 } 8633 mutex_unlock(&hdev->vport_lock); 8634 8635 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8636 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8637 hdev->priv_umv_size); 8638 8639 return -ENOSPC; 8640 } 8641 8642 /* check if we just hit the duplicate */ 8643 if (!ret) 8644 return -EEXIST; 8645 8646 return ret; 8647 } 8648 8649 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8650 const unsigned char *addr) 8651 { 8652 struct hclge_vport *vport = hclge_get_vport(handle); 8653 8654 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8655 addr); 8656 } 8657 8658 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8659 const unsigned char *addr) 8660 { 8661 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8662 struct hclge_dev *hdev = vport->back; 8663 struct hclge_mac_vlan_tbl_entry_cmd req; 8664 int ret; 8665 8666 /* mac addr check */ 8667 if (is_zero_ether_addr(addr) || 8668 is_broadcast_ether_addr(addr) || 8669 is_multicast_ether_addr(addr)) { 8670 hnae3_format_mac_addr(format_mac_addr, addr); 8671 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8672 format_mac_addr); 8673 return -EINVAL; 8674 } 8675 8676 memset(&req, 0, sizeof(req)); 8677 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8678 hclge_prepare_mac_addr(&req, addr, false); 8679 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8680 if (!ret || ret == -ENOENT) { 8681 mutex_lock(&hdev->vport_lock); 8682 hclge_update_umv_space(vport, true); 8683 mutex_unlock(&hdev->vport_lock); 8684 return 0; 8685 } 8686 8687 return ret; 8688 } 8689 8690 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8691 const unsigned char *addr) 8692 { 8693 struct hclge_vport *vport = hclge_get_vport(handle); 8694 8695 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8696 addr); 8697 } 8698 8699 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8700 const unsigned char *addr) 8701 { 8702 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8703 struct hclge_dev *hdev = vport->back; 8704 struct hclge_mac_vlan_tbl_entry_cmd req; 8705 struct hclge_desc desc[3]; 8706 bool is_new_addr = false; 8707 int status; 8708 8709 /* mac addr check */ 8710 if (!is_multicast_ether_addr(addr)) { 8711 hnae3_format_mac_addr(format_mac_addr, addr); 8712 dev_err(&hdev->pdev->dev, 8713 "Add mc mac err! invalid mac:%s.\n", 8714 format_mac_addr); 8715 return -EINVAL; 8716 } 8717 memset(&req, 0, sizeof(req)); 8718 hclge_prepare_mac_addr(&req, addr, true); 8719 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8720 if (status) { 8721 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8722 hdev->used_mc_mac_num >= 8723 hdev->ae_dev->dev_specs.mc_mac_size) 8724 goto err_no_space; 8725 8726 is_new_addr = true; 8727 8728 /* This mac addr do not exist, add new entry for it */ 8729 memset(desc[0].data, 0, sizeof(desc[0].data)); 8730 memset(desc[1].data, 0, sizeof(desc[0].data)); 8731 memset(desc[2].data, 0, sizeof(desc[0].data)); 8732 } 8733 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8734 if (status) 8735 return status; 8736 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8737 if (status == -ENOSPC) 8738 goto err_no_space; 8739 else if (!status && is_new_addr) 8740 hdev->used_mc_mac_num++; 8741 8742 return status; 8743 8744 err_no_space: 8745 /* if already overflow, not to print each time */ 8746 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8747 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8748 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8749 } 8750 8751 return -ENOSPC; 8752 } 8753 8754 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8755 const unsigned char *addr) 8756 { 8757 struct hclge_vport *vport = hclge_get_vport(handle); 8758 8759 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8760 addr); 8761 } 8762 8763 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8764 const unsigned char *addr) 8765 { 8766 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8767 struct hclge_dev *hdev = vport->back; 8768 struct hclge_mac_vlan_tbl_entry_cmd req; 8769 enum hclge_comm_cmd_status status; 8770 struct hclge_desc desc[3]; 8771 8772 /* mac addr check */ 8773 if (!is_multicast_ether_addr(addr)) { 8774 hnae3_format_mac_addr(format_mac_addr, addr); 8775 dev_dbg(&hdev->pdev->dev, 8776 "Remove mc mac err! invalid mac:%s.\n", 8777 format_mac_addr); 8778 return -EINVAL; 8779 } 8780 8781 memset(&req, 0, sizeof(req)); 8782 hclge_prepare_mac_addr(&req, addr, true); 8783 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8784 if (!status) { 8785 /* This mac addr exist, remove this handle's VFID for it */ 8786 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8787 if (status) 8788 return status; 8789 8790 if (hclge_is_all_function_id_zero(desc)) { 8791 /* All the vfid is zero, so need to delete this entry */ 8792 status = hclge_remove_mac_vlan_tbl(vport, &req); 8793 if (!status) 8794 hdev->used_mc_mac_num--; 8795 } else { 8796 /* Not all the vfid is zero, update the vfid */ 8797 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8798 } 8799 } else if (status == -ENOENT) { 8800 status = 0; 8801 } 8802 8803 return status; 8804 } 8805 8806 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8807 struct list_head *list, 8808 enum HCLGE_MAC_ADDR_TYPE mac_type) 8809 { 8810 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8811 struct hclge_mac_node *mac_node, *tmp; 8812 int ret; 8813 8814 if (mac_type == HCLGE_MAC_ADDR_UC) 8815 sync = hclge_add_uc_addr_common; 8816 else 8817 sync = hclge_add_mc_addr_common; 8818 8819 list_for_each_entry_safe(mac_node, tmp, list, node) { 8820 ret = sync(vport, mac_node->mac_addr); 8821 if (!ret) { 8822 mac_node->state = HCLGE_MAC_ACTIVE; 8823 } else { 8824 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8825 &vport->state); 8826 8827 /* If one unicast mac address is existing in hardware, 8828 * we need to try whether other unicast mac addresses 8829 * are new addresses that can be added. 8830 * Multicast mac address can be reusable, even though 8831 * there is no space to add new multicast mac address, 8832 * we should check whether other mac addresses are 8833 * existing in hardware for reuse. 8834 */ 8835 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8836 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8837 break; 8838 } 8839 } 8840 } 8841 8842 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8843 struct list_head *list, 8844 enum HCLGE_MAC_ADDR_TYPE mac_type) 8845 { 8846 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8847 struct hclge_mac_node *mac_node, *tmp; 8848 int ret; 8849 8850 if (mac_type == HCLGE_MAC_ADDR_UC) 8851 unsync = hclge_rm_uc_addr_common; 8852 else 8853 unsync = hclge_rm_mc_addr_common; 8854 8855 list_for_each_entry_safe(mac_node, tmp, list, node) { 8856 ret = unsync(vport, mac_node->mac_addr); 8857 if (!ret || ret == -ENOENT) { 8858 list_del(&mac_node->node); 8859 kfree(mac_node); 8860 } else { 8861 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8862 &vport->state); 8863 break; 8864 } 8865 } 8866 } 8867 8868 static bool hclge_sync_from_add_list(struct list_head *add_list, 8869 struct list_head *mac_list) 8870 { 8871 struct hclge_mac_node *mac_node, *tmp, *new_node; 8872 bool all_added = true; 8873 8874 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8875 if (mac_node->state == HCLGE_MAC_TO_ADD) 8876 all_added = false; 8877 8878 /* if the mac address from tmp_add_list is not in the 8879 * uc/mc_mac_list, it means have received a TO_DEL request 8880 * during the time window of adding the mac address into mac 8881 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8882 * then it will be removed at next time. else it must be TO_ADD, 8883 * this address hasn't been added into mac table, 8884 * so just remove the mac node. 8885 */ 8886 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8887 if (new_node) { 8888 hclge_update_mac_node(new_node, mac_node->state); 8889 list_del(&mac_node->node); 8890 kfree(mac_node); 8891 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8892 mac_node->state = HCLGE_MAC_TO_DEL; 8893 list_move_tail(&mac_node->node, mac_list); 8894 } else { 8895 list_del(&mac_node->node); 8896 kfree(mac_node); 8897 } 8898 } 8899 8900 return all_added; 8901 } 8902 8903 static void hclge_sync_from_del_list(struct list_head *del_list, 8904 struct list_head *mac_list) 8905 { 8906 struct hclge_mac_node *mac_node, *tmp, *new_node; 8907 8908 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8909 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8910 if (new_node) { 8911 /* If the mac addr exists in the mac list, it means 8912 * received a new TO_ADD request during the time window 8913 * of configuring the mac address. For the mac node 8914 * state is TO_ADD, and the address is already in the 8915 * in the hardware(due to delete fail), so we just need 8916 * to change the mac node state to ACTIVE. 8917 */ 8918 new_node->state = HCLGE_MAC_ACTIVE; 8919 list_del(&mac_node->node); 8920 kfree(mac_node); 8921 } else { 8922 list_move_tail(&mac_node->node, mac_list); 8923 } 8924 } 8925 } 8926 8927 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8928 enum HCLGE_MAC_ADDR_TYPE mac_type, 8929 bool is_all_added) 8930 { 8931 if (mac_type == HCLGE_MAC_ADDR_UC) { 8932 if (is_all_added) 8933 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8934 else if (hclge_is_umv_space_full(vport, true)) 8935 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8936 } else { 8937 if (is_all_added) 8938 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8939 else 8940 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8941 } 8942 } 8943 8944 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8945 enum HCLGE_MAC_ADDR_TYPE mac_type) 8946 { 8947 struct hclge_mac_node *mac_node, *tmp, *new_node; 8948 struct list_head tmp_add_list, tmp_del_list; 8949 struct list_head *list; 8950 bool all_added; 8951 8952 INIT_LIST_HEAD(&tmp_add_list); 8953 INIT_LIST_HEAD(&tmp_del_list); 8954 8955 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8956 * we can add/delete these mac addr outside the spin lock 8957 */ 8958 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8959 &vport->uc_mac_list : &vport->mc_mac_list; 8960 8961 spin_lock_bh(&vport->mac_list_lock); 8962 8963 list_for_each_entry_safe(mac_node, tmp, list, node) { 8964 switch (mac_node->state) { 8965 case HCLGE_MAC_TO_DEL: 8966 list_move_tail(&mac_node->node, &tmp_del_list); 8967 break; 8968 case HCLGE_MAC_TO_ADD: 8969 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8970 if (!new_node) 8971 goto stop_traverse; 8972 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8973 new_node->state = mac_node->state; 8974 list_add_tail(&new_node->node, &tmp_add_list); 8975 break; 8976 default: 8977 break; 8978 } 8979 } 8980 8981 stop_traverse: 8982 spin_unlock_bh(&vport->mac_list_lock); 8983 8984 /* delete first, in order to get max mac table space for adding */ 8985 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8986 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8987 8988 /* if some mac addresses were added/deleted fail, move back to the 8989 * mac_list, and retry at next time. 8990 */ 8991 spin_lock_bh(&vport->mac_list_lock); 8992 8993 hclge_sync_from_del_list(&tmp_del_list, list); 8994 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8995 8996 spin_unlock_bh(&vport->mac_list_lock); 8997 8998 hclge_update_overflow_flags(vport, mac_type, all_added); 8999 } 9000 9001 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 9002 { 9003 struct hclge_dev *hdev = vport->back; 9004 9005 if (test_bit(vport->vport_id, hdev->vport_config_block)) 9006 return false; 9007 9008 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 9009 return true; 9010 9011 return false; 9012 } 9013 9014 static void hclge_sync_mac_table(struct hclge_dev *hdev) 9015 { 9016 int i; 9017 9018 for (i = 0; i < hdev->num_alloc_vport; i++) { 9019 struct hclge_vport *vport = &hdev->vport[i]; 9020 9021 if (!hclge_need_sync_mac_table(vport)) 9022 continue; 9023 9024 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9025 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9026 } 9027 } 9028 9029 static void hclge_build_del_list(struct list_head *list, 9030 bool is_del_list, 9031 struct list_head *tmp_del_list) 9032 { 9033 struct hclge_mac_node *mac_cfg, *tmp; 9034 9035 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9036 switch (mac_cfg->state) { 9037 case HCLGE_MAC_TO_DEL: 9038 case HCLGE_MAC_ACTIVE: 9039 list_move_tail(&mac_cfg->node, tmp_del_list); 9040 break; 9041 case HCLGE_MAC_TO_ADD: 9042 if (is_del_list) { 9043 list_del(&mac_cfg->node); 9044 kfree(mac_cfg); 9045 } 9046 break; 9047 } 9048 } 9049 } 9050 9051 static void hclge_unsync_del_list(struct hclge_vport *vport, 9052 int (*unsync)(struct hclge_vport *vport, 9053 const unsigned char *addr), 9054 bool is_del_list, 9055 struct list_head *tmp_del_list) 9056 { 9057 struct hclge_mac_node *mac_cfg, *tmp; 9058 int ret; 9059 9060 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9061 ret = unsync(vport, mac_cfg->mac_addr); 9062 if (!ret || ret == -ENOENT) { 9063 /* clear all mac addr from hardware, but remain these 9064 * mac addr in the mac list, and restore them after 9065 * vf reset finished. 9066 */ 9067 if (!is_del_list && 9068 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9069 mac_cfg->state = HCLGE_MAC_TO_ADD; 9070 } else { 9071 list_del(&mac_cfg->node); 9072 kfree(mac_cfg); 9073 } 9074 } else if (is_del_list) { 9075 mac_cfg->state = HCLGE_MAC_TO_DEL; 9076 } 9077 } 9078 } 9079 9080 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9081 enum HCLGE_MAC_ADDR_TYPE mac_type) 9082 { 9083 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9084 struct hclge_dev *hdev = vport->back; 9085 struct list_head tmp_del_list, *list; 9086 9087 if (mac_type == HCLGE_MAC_ADDR_UC) { 9088 list = &vport->uc_mac_list; 9089 unsync = hclge_rm_uc_addr_common; 9090 } else { 9091 list = &vport->mc_mac_list; 9092 unsync = hclge_rm_mc_addr_common; 9093 } 9094 9095 INIT_LIST_HEAD(&tmp_del_list); 9096 9097 if (!is_del_list) 9098 set_bit(vport->vport_id, hdev->vport_config_block); 9099 9100 spin_lock_bh(&vport->mac_list_lock); 9101 9102 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9103 9104 spin_unlock_bh(&vport->mac_list_lock); 9105 9106 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9107 9108 spin_lock_bh(&vport->mac_list_lock); 9109 9110 hclge_sync_from_del_list(&tmp_del_list, list); 9111 9112 spin_unlock_bh(&vport->mac_list_lock); 9113 } 9114 9115 /* remove all mac address when uninitailize */ 9116 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9117 enum HCLGE_MAC_ADDR_TYPE mac_type) 9118 { 9119 struct hclge_mac_node *mac_node, *tmp; 9120 struct hclge_dev *hdev = vport->back; 9121 struct list_head tmp_del_list, *list; 9122 9123 INIT_LIST_HEAD(&tmp_del_list); 9124 9125 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9126 &vport->uc_mac_list : &vport->mc_mac_list; 9127 9128 spin_lock_bh(&vport->mac_list_lock); 9129 9130 list_for_each_entry_safe(mac_node, tmp, list, node) { 9131 switch (mac_node->state) { 9132 case HCLGE_MAC_TO_DEL: 9133 case HCLGE_MAC_ACTIVE: 9134 list_move_tail(&mac_node->node, &tmp_del_list); 9135 break; 9136 case HCLGE_MAC_TO_ADD: 9137 list_del(&mac_node->node); 9138 kfree(mac_node); 9139 break; 9140 } 9141 } 9142 9143 spin_unlock_bh(&vport->mac_list_lock); 9144 9145 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9146 9147 if (!list_empty(&tmp_del_list)) 9148 dev_warn(&hdev->pdev->dev, 9149 "uninit %s mac list for vport %u not completely.\n", 9150 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9151 vport->vport_id); 9152 9153 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9154 list_del(&mac_node->node); 9155 kfree(mac_node); 9156 } 9157 } 9158 9159 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9160 { 9161 struct hclge_vport *vport; 9162 int i; 9163 9164 for (i = 0; i < hdev->num_alloc_vport; i++) { 9165 vport = &hdev->vport[i]; 9166 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9167 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9168 } 9169 } 9170 9171 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9172 u16 cmdq_resp, u8 resp_code) 9173 { 9174 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9175 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9176 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9177 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9178 9179 int return_status; 9180 9181 if (cmdq_resp) { 9182 dev_err(&hdev->pdev->dev, 9183 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9184 cmdq_resp); 9185 return -EIO; 9186 } 9187 9188 switch (resp_code) { 9189 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9190 case HCLGE_ETHERTYPE_ALREADY_ADD: 9191 return_status = 0; 9192 break; 9193 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9194 dev_err(&hdev->pdev->dev, 9195 "add mac ethertype failed for manager table overflow.\n"); 9196 return_status = -EIO; 9197 break; 9198 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9199 dev_err(&hdev->pdev->dev, 9200 "add mac ethertype failed for key conflict.\n"); 9201 return_status = -EIO; 9202 break; 9203 default: 9204 dev_err(&hdev->pdev->dev, 9205 "add mac ethertype failed for undefined, code=%u.\n", 9206 resp_code); 9207 return_status = -EIO; 9208 } 9209 9210 return return_status; 9211 } 9212 9213 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9214 u8 *mac_addr) 9215 { 9216 struct hclge_vport *vport = hclge_get_vport(handle); 9217 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9218 struct hclge_dev *hdev = vport->back; 9219 9220 vport = hclge_get_vf_vport(hdev, vf); 9221 if (!vport) 9222 return -EINVAL; 9223 9224 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9225 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9226 dev_info(&hdev->pdev->dev, 9227 "Specified MAC(=%s) is same as before, no change committed!\n", 9228 format_mac_addr); 9229 return 0; 9230 } 9231 9232 ether_addr_copy(vport->vf_info.mac, mac_addr); 9233 9234 /* there is a timewindow for PF to know VF unalive, it may 9235 * cause send mailbox fail, but it doesn't matter, VF will 9236 * query it when reinit. 9237 */ 9238 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9239 dev_info(&hdev->pdev->dev, 9240 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9241 vf, format_mac_addr); 9242 (void)hclge_inform_reset_assert_to_vf(vport); 9243 return 0; 9244 } 9245 9246 dev_info(&hdev->pdev->dev, 9247 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9248 vf, format_mac_addr); 9249 return 0; 9250 } 9251 9252 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9253 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9254 { 9255 struct hclge_desc desc; 9256 u8 resp_code; 9257 u16 retval; 9258 int ret; 9259 9260 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9261 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9262 9263 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9264 if (ret) { 9265 dev_err(&hdev->pdev->dev, 9266 "add mac ethertype failed for cmd_send, ret =%d.\n", 9267 ret); 9268 return ret; 9269 } 9270 9271 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9272 retval = le16_to_cpu(desc.retval); 9273 9274 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9275 } 9276 9277 static int init_mgr_tbl(struct hclge_dev *hdev) 9278 { 9279 int ret; 9280 int i; 9281 9282 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9283 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9284 if (ret) { 9285 dev_err(&hdev->pdev->dev, 9286 "add mac ethertype failed, ret =%d.\n", 9287 ret); 9288 return ret; 9289 } 9290 } 9291 9292 return 0; 9293 } 9294 9295 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9296 { 9297 struct hclge_vport *vport = hclge_get_vport(handle); 9298 struct hclge_dev *hdev = vport->back; 9299 9300 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9301 } 9302 9303 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9304 const u8 *old_addr, const u8 *new_addr) 9305 { 9306 struct list_head *list = &vport->uc_mac_list; 9307 struct hclge_mac_node *old_node, *new_node; 9308 9309 new_node = hclge_find_mac_node(list, new_addr); 9310 if (!new_node) { 9311 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9312 if (!new_node) 9313 return -ENOMEM; 9314 9315 new_node->state = HCLGE_MAC_TO_ADD; 9316 ether_addr_copy(new_node->mac_addr, new_addr); 9317 list_add(&new_node->node, list); 9318 } else { 9319 if (new_node->state == HCLGE_MAC_TO_DEL) 9320 new_node->state = HCLGE_MAC_ACTIVE; 9321 9322 /* make sure the new addr is in the list head, avoid dev 9323 * addr may be not re-added into mac table for the umv space 9324 * limitation after global/imp reset which will clear mac 9325 * table by hardware. 9326 */ 9327 list_move(&new_node->node, list); 9328 } 9329 9330 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9331 old_node = hclge_find_mac_node(list, old_addr); 9332 if (old_node) { 9333 if (old_node->state == HCLGE_MAC_TO_ADD) { 9334 list_del(&old_node->node); 9335 kfree(old_node); 9336 } else { 9337 old_node->state = HCLGE_MAC_TO_DEL; 9338 } 9339 } 9340 } 9341 9342 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9343 9344 return 0; 9345 } 9346 9347 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9348 bool is_first) 9349 { 9350 const unsigned char *new_addr = (const unsigned char *)p; 9351 struct hclge_vport *vport = hclge_get_vport(handle); 9352 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9353 struct hclge_dev *hdev = vport->back; 9354 unsigned char *old_addr = NULL; 9355 int ret; 9356 9357 /* mac addr check */ 9358 if (is_zero_ether_addr(new_addr) || 9359 is_broadcast_ether_addr(new_addr) || 9360 is_multicast_ether_addr(new_addr)) { 9361 hnae3_format_mac_addr(format_mac_addr, new_addr); 9362 dev_err(&hdev->pdev->dev, 9363 "change uc mac err! invalid mac: %s.\n", 9364 format_mac_addr); 9365 return -EINVAL; 9366 } 9367 9368 ret = hclge_pause_addr_cfg(hdev, new_addr); 9369 if (ret) { 9370 dev_err(&hdev->pdev->dev, 9371 "failed to configure mac pause address, ret = %d\n", 9372 ret); 9373 return ret; 9374 } 9375 9376 if (!is_first) 9377 old_addr = hdev->hw.mac.mac_addr; 9378 9379 spin_lock_bh(&vport->mac_list_lock); 9380 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9381 if (ret) { 9382 hnae3_format_mac_addr(format_mac_addr, new_addr); 9383 dev_err(&hdev->pdev->dev, 9384 "failed to change the mac addr:%s, ret = %d\n", 9385 format_mac_addr, ret); 9386 spin_unlock_bh(&vport->mac_list_lock); 9387 9388 if (!is_first) 9389 hclge_pause_addr_cfg(hdev, old_addr); 9390 9391 return ret; 9392 } 9393 /* we must update dev addr with spin lock protect, preventing dev addr 9394 * being removed by set_rx_mode path. 9395 */ 9396 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9397 spin_unlock_bh(&vport->mac_list_lock); 9398 9399 hclge_task_schedule(hdev, 0); 9400 9401 return 0; 9402 } 9403 9404 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9405 { 9406 struct mii_ioctl_data *data = if_mii(ifr); 9407 9408 if (!hnae3_dev_phy_imp_supported(hdev)) 9409 return -EOPNOTSUPP; 9410 9411 switch (cmd) { 9412 case SIOCGMIIPHY: 9413 data->phy_id = hdev->hw.mac.phy_addr; 9414 /* this command reads phy id and register at the same time */ 9415 fallthrough; 9416 case SIOCGMIIREG: 9417 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9418 return 0; 9419 9420 case SIOCSMIIREG: 9421 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9422 default: 9423 return -EOPNOTSUPP; 9424 } 9425 } 9426 9427 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9428 int cmd) 9429 { 9430 struct hclge_vport *vport = hclge_get_vport(handle); 9431 struct hclge_dev *hdev = vport->back; 9432 9433 switch (cmd) { 9434 case SIOCGHWTSTAMP: 9435 return hclge_ptp_get_cfg(hdev, ifr); 9436 case SIOCSHWTSTAMP: 9437 return hclge_ptp_set_cfg(hdev, ifr); 9438 default: 9439 if (!hdev->hw.mac.phydev) 9440 return hclge_mii_ioctl(hdev, ifr, cmd); 9441 } 9442 9443 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9444 } 9445 9446 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9447 bool bypass_en) 9448 { 9449 struct hclge_port_vlan_filter_bypass_cmd *req; 9450 struct hclge_desc desc; 9451 int ret; 9452 9453 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9454 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9455 req->vf_id = vf_id; 9456 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9457 bypass_en ? 1 : 0); 9458 9459 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9460 if (ret) 9461 dev_err(&hdev->pdev->dev, 9462 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9463 vf_id, ret); 9464 9465 return ret; 9466 } 9467 9468 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9469 u8 fe_type, bool filter_en, u8 vf_id) 9470 { 9471 struct hclge_vlan_filter_ctrl_cmd *req; 9472 struct hclge_desc desc; 9473 int ret; 9474 9475 /* read current vlan filter parameter */ 9476 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9477 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9478 req->vlan_type = vlan_type; 9479 req->vf_id = vf_id; 9480 9481 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9482 if (ret) { 9483 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9484 vf_id, ret); 9485 return ret; 9486 } 9487 9488 /* modify and write new config parameter */ 9489 hclge_comm_cmd_reuse_desc(&desc, false); 9490 req->vlan_fe = filter_en ? 9491 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9492 9493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9494 if (ret) 9495 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9496 vf_id, ret); 9497 9498 return ret; 9499 } 9500 9501 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9502 { 9503 struct hclge_dev *hdev = vport->back; 9504 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9505 int ret; 9506 9507 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9508 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9509 HCLGE_FILTER_FE_EGRESS_V1_B, 9510 enable, vport->vport_id); 9511 9512 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9513 HCLGE_FILTER_FE_EGRESS, enable, 9514 vport->vport_id); 9515 if (ret) 9516 return ret; 9517 9518 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9519 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9520 !enable); 9521 } else if (!vport->vport_id) { 9522 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9523 enable = false; 9524 9525 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9526 HCLGE_FILTER_FE_INGRESS, 9527 enable, 0); 9528 } 9529 9530 return ret; 9531 } 9532 9533 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9534 { 9535 struct hnae3_handle *handle = &vport->nic; 9536 struct hclge_vport_vlan_cfg *vlan, *tmp; 9537 struct hclge_dev *hdev = vport->back; 9538 9539 if (vport->vport_id) { 9540 if (vport->port_base_vlan_cfg.state != 9541 HNAE3_PORT_BASE_VLAN_DISABLE) 9542 return true; 9543 9544 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9545 return false; 9546 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9547 return false; 9548 } 9549 9550 if (!vport->req_vlan_fltr_en) 9551 return false; 9552 9553 /* compatible with former device, always enable vlan filter */ 9554 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9555 return true; 9556 9557 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9558 if (vlan->vlan_id != 0) 9559 return true; 9560 9561 return false; 9562 } 9563 9564 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9565 { 9566 struct hclge_dev *hdev = vport->back; 9567 bool need_en; 9568 int ret; 9569 9570 mutex_lock(&hdev->vport_lock); 9571 9572 vport->req_vlan_fltr_en = request_en; 9573 9574 need_en = hclge_need_enable_vport_vlan_filter(vport); 9575 if (need_en == vport->cur_vlan_fltr_en) { 9576 mutex_unlock(&hdev->vport_lock); 9577 return 0; 9578 } 9579 9580 ret = hclge_set_vport_vlan_filter(vport, need_en); 9581 if (ret) { 9582 mutex_unlock(&hdev->vport_lock); 9583 return ret; 9584 } 9585 9586 vport->cur_vlan_fltr_en = need_en; 9587 9588 mutex_unlock(&hdev->vport_lock); 9589 9590 return 0; 9591 } 9592 9593 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9594 { 9595 struct hclge_vport *vport = hclge_get_vport(handle); 9596 9597 return hclge_enable_vport_vlan_filter(vport, enable); 9598 } 9599 9600 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9601 bool is_kill, u16 vlan, 9602 struct hclge_desc *desc) 9603 { 9604 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9605 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9606 u8 vf_byte_val; 9607 u8 vf_byte_off; 9608 int ret; 9609 9610 hclge_cmd_setup_basic_desc(&desc[0], 9611 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9612 hclge_cmd_setup_basic_desc(&desc[1], 9613 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9614 9615 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9616 9617 vf_byte_off = vfid / 8; 9618 vf_byte_val = 1 << (vfid % 8); 9619 9620 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9621 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9622 9623 req0->vlan_id = cpu_to_le16(vlan); 9624 req0->vlan_cfg = is_kill; 9625 9626 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9627 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9628 else 9629 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9630 9631 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9632 if (ret) { 9633 dev_err(&hdev->pdev->dev, 9634 "Send vf vlan command fail, ret =%d.\n", 9635 ret); 9636 return ret; 9637 } 9638 9639 return 0; 9640 } 9641 9642 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9643 bool is_kill, struct hclge_desc *desc) 9644 { 9645 struct hclge_vlan_filter_vf_cfg_cmd *req; 9646 9647 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9648 9649 if (!is_kill) { 9650 #define HCLGE_VF_VLAN_NO_ENTRY 2 9651 if (!req->resp_code || req->resp_code == 1) 9652 return 0; 9653 9654 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9655 set_bit(vfid, hdev->vf_vlan_full); 9656 dev_warn(&hdev->pdev->dev, 9657 "vf vlan table is full, vf vlan filter is disabled\n"); 9658 return 0; 9659 } 9660 9661 dev_err(&hdev->pdev->dev, 9662 "Add vf vlan filter fail, ret =%u.\n", 9663 req->resp_code); 9664 } else { 9665 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9666 if (!req->resp_code) 9667 return 0; 9668 9669 /* vf vlan filter is disabled when vf vlan table is full, 9670 * then new vlan id will not be added into vf vlan table. 9671 * Just return 0 without warning, avoid massive verbose 9672 * print logs when unload. 9673 */ 9674 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9675 return 0; 9676 9677 dev_err(&hdev->pdev->dev, 9678 "Kill vf vlan filter fail, ret =%u.\n", 9679 req->resp_code); 9680 } 9681 9682 return -EIO; 9683 } 9684 9685 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9686 bool is_kill, u16 vlan) 9687 { 9688 struct hclge_vport *vport = &hdev->vport[vfid]; 9689 struct hclge_desc desc[2]; 9690 int ret; 9691 9692 /* if vf vlan table is full, firmware will close vf vlan filter, it 9693 * is unable and unnecessary to add new vlan id to vf vlan filter. 9694 * If spoof check is enable, and vf vlan is full, it shouldn't add 9695 * new vlan, because tx packets with these vlan id will be dropped. 9696 */ 9697 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9698 if (vport->vf_info.spoofchk && vlan) { 9699 dev_err(&hdev->pdev->dev, 9700 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9701 return -EPERM; 9702 } 9703 return 0; 9704 } 9705 9706 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9707 if (ret) 9708 return ret; 9709 9710 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9711 } 9712 9713 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9714 u16 vlan_id, bool is_kill) 9715 { 9716 struct hclge_vlan_filter_pf_cfg_cmd *req; 9717 struct hclge_desc desc; 9718 u8 vlan_offset_byte_val; 9719 u8 vlan_offset_byte; 9720 u8 vlan_offset_160; 9721 int ret; 9722 9723 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9724 9725 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9726 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9727 HCLGE_VLAN_BYTE_SIZE; 9728 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9729 9730 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9731 req->vlan_offset = vlan_offset_160; 9732 req->vlan_cfg = is_kill; 9733 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9734 9735 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9736 if (ret) 9737 dev_err(&hdev->pdev->dev, 9738 "port vlan command, send fail, ret =%d.\n", ret); 9739 return ret; 9740 } 9741 9742 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9743 u16 vlan_id, bool is_kill) 9744 { 9745 /* vlan 0 may be added twice when 8021q module is enabled */ 9746 if (!is_kill && !vlan_id && 9747 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9748 return false; 9749 9750 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9751 dev_warn(&hdev->pdev->dev, 9752 "Add port vlan failed, vport %u is already in vlan %u\n", 9753 vport_id, vlan_id); 9754 return false; 9755 } 9756 9757 if (is_kill && 9758 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9759 dev_warn(&hdev->pdev->dev, 9760 "Delete port vlan failed, vport %u is not in vlan %u\n", 9761 vport_id, vlan_id); 9762 return false; 9763 } 9764 9765 return true; 9766 } 9767 9768 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9769 u16 vport_id, u16 vlan_id, 9770 bool is_kill) 9771 { 9772 u16 vport_idx, vport_num = 0; 9773 int ret; 9774 9775 if (is_kill && !vlan_id) 9776 return 0; 9777 9778 if (vlan_id >= VLAN_N_VID) 9779 return -EINVAL; 9780 9781 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9782 if (ret) { 9783 dev_err(&hdev->pdev->dev, 9784 "Set %u vport vlan filter config fail, ret =%d.\n", 9785 vport_id, ret); 9786 return ret; 9787 } 9788 9789 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9790 return 0; 9791 9792 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9793 vport_num++; 9794 9795 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9796 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9797 is_kill); 9798 9799 return ret; 9800 } 9801 9802 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9803 { 9804 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9805 struct hclge_vport_vtag_tx_cfg_cmd *req; 9806 struct hclge_dev *hdev = vport->back; 9807 struct hclge_desc desc; 9808 u16 bmap_index; 9809 int status; 9810 9811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9812 9813 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9814 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9815 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9816 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9817 vcfg->accept_tag1 ? 1 : 0); 9818 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9819 vcfg->accept_untag1 ? 1 : 0); 9820 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9821 vcfg->accept_tag2 ? 1 : 0); 9822 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9823 vcfg->accept_untag2 ? 1 : 0); 9824 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9825 vcfg->insert_tag1_en ? 1 : 0); 9826 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9827 vcfg->insert_tag2_en ? 1 : 0); 9828 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9829 vcfg->tag_shift_mode_en ? 1 : 0); 9830 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9831 9832 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9833 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9834 HCLGE_VF_NUM_PER_BYTE; 9835 req->vf_bitmap[bmap_index] = 9836 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9837 9838 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9839 if (status) 9840 dev_err(&hdev->pdev->dev, 9841 "Send port txvlan cfg command fail, ret =%d\n", 9842 status); 9843 9844 return status; 9845 } 9846 9847 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9848 { 9849 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9850 struct hclge_vport_vtag_rx_cfg_cmd *req; 9851 struct hclge_dev *hdev = vport->back; 9852 struct hclge_desc desc; 9853 u16 bmap_index; 9854 int status; 9855 9856 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9857 9858 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9860 vcfg->strip_tag1_en ? 1 : 0); 9861 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9862 vcfg->strip_tag2_en ? 1 : 0); 9863 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9864 vcfg->vlan1_vlan_prionly ? 1 : 0); 9865 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9866 vcfg->vlan2_vlan_prionly ? 1 : 0); 9867 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9868 vcfg->strip_tag1_discard_en ? 1 : 0); 9869 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9870 vcfg->strip_tag2_discard_en ? 1 : 0); 9871 9872 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9873 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9874 HCLGE_VF_NUM_PER_BYTE; 9875 req->vf_bitmap[bmap_index] = 9876 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9877 9878 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9879 if (status) 9880 dev_err(&hdev->pdev->dev, 9881 "Send port rxvlan cfg command fail, ret =%d\n", 9882 status); 9883 9884 return status; 9885 } 9886 9887 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9888 u16 port_base_vlan_state, 9889 u16 vlan_tag, u8 qos) 9890 { 9891 int ret; 9892 9893 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9894 vport->txvlan_cfg.accept_tag1 = true; 9895 vport->txvlan_cfg.insert_tag1_en = false; 9896 vport->txvlan_cfg.default_tag1 = 0; 9897 } else { 9898 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9899 9900 vport->txvlan_cfg.accept_tag1 = 9901 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9902 vport->txvlan_cfg.insert_tag1_en = true; 9903 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9904 vlan_tag; 9905 } 9906 9907 vport->txvlan_cfg.accept_untag1 = true; 9908 9909 /* accept_tag2 and accept_untag2 are not supported on 9910 * pdev revision(0x20), new revision support them, 9911 * this two fields can not be configured by user. 9912 */ 9913 vport->txvlan_cfg.accept_tag2 = true; 9914 vport->txvlan_cfg.accept_untag2 = true; 9915 vport->txvlan_cfg.insert_tag2_en = false; 9916 vport->txvlan_cfg.default_tag2 = 0; 9917 vport->txvlan_cfg.tag_shift_mode_en = true; 9918 9919 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9920 vport->rxvlan_cfg.strip_tag1_en = false; 9921 vport->rxvlan_cfg.strip_tag2_en = 9922 vport->rxvlan_cfg.rx_vlan_offload_en; 9923 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9924 } else { 9925 vport->rxvlan_cfg.strip_tag1_en = 9926 vport->rxvlan_cfg.rx_vlan_offload_en; 9927 vport->rxvlan_cfg.strip_tag2_en = true; 9928 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9929 } 9930 9931 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9932 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9933 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9934 9935 ret = hclge_set_vlan_tx_offload_cfg(vport); 9936 if (ret) 9937 return ret; 9938 9939 return hclge_set_vlan_rx_offload_cfg(vport); 9940 } 9941 9942 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9943 { 9944 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9945 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9946 struct hclge_desc desc; 9947 int status; 9948 9949 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9950 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9951 rx_req->ot_fst_vlan_type = 9952 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9953 rx_req->ot_sec_vlan_type = 9954 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9955 rx_req->in_fst_vlan_type = 9956 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9957 rx_req->in_sec_vlan_type = 9958 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9959 9960 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9961 if (status) { 9962 dev_err(&hdev->pdev->dev, 9963 "Send rxvlan protocol type command fail, ret =%d\n", 9964 status); 9965 return status; 9966 } 9967 9968 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9969 9970 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9971 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9972 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9973 9974 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9975 if (status) 9976 dev_err(&hdev->pdev->dev, 9977 "Send txvlan protocol type command fail, ret =%d\n", 9978 status); 9979 9980 return status; 9981 } 9982 9983 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9984 { 9985 struct hclge_vport *vport; 9986 bool enable = true; 9987 int ret; 9988 int i; 9989 9990 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9991 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9992 HCLGE_FILTER_FE_EGRESS_V1_B, 9993 true, 0); 9994 9995 /* for revision 0x21, vf vlan filter is per function */ 9996 for (i = 0; i < hdev->num_alloc_vport; i++) { 9997 vport = &hdev->vport[i]; 9998 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9999 HCLGE_FILTER_FE_EGRESS, true, 10000 vport->vport_id); 10001 if (ret) 10002 return ret; 10003 vport->cur_vlan_fltr_en = true; 10004 } 10005 10006 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 10007 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 10008 enable = false; 10009 10010 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 10011 HCLGE_FILTER_FE_INGRESS, enable, 0); 10012 } 10013 10014 static int hclge_init_vlan_type(struct hclge_dev *hdev) 10015 { 10016 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 10017 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 10018 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 10019 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 10020 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10021 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10022 10023 return hclge_set_vlan_protocol_type(hdev); 10024 } 10025 10026 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10027 { 10028 struct hclge_port_base_vlan_config *cfg; 10029 struct hclge_vport *vport; 10030 int ret; 10031 int i; 10032 10033 for (i = 0; i < hdev->num_alloc_vport; i++) { 10034 vport = &hdev->vport[i]; 10035 cfg = &vport->port_base_vlan_cfg; 10036 10037 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10038 cfg->vlan_info.vlan_tag, 10039 cfg->vlan_info.qos); 10040 if (ret) 10041 return ret; 10042 } 10043 return 0; 10044 } 10045 10046 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10047 { 10048 struct hnae3_handle *handle = &hdev->vport[0].nic; 10049 int ret; 10050 10051 ret = hclge_init_vlan_filter(hdev); 10052 if (ret) 10053 return ret; 10054 10055 ret = hclge_init_vlan_type(hdev); 10056 if (ret) 10057 return ret; 10058 10059 ret = hclge_init_vport_vlan_offload(hdev); 10060 if (ret) 10061 return ret; 10062 10063 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10064 } 10065 10066 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10067 bool writen_to_tbl) 10068 { 10069 struct hclge_vport_vlan_cfg *vlan, *tmp; 10070 struct hclge_dev *hdev = vport->back; 10071 10072 mutex_lock(&hdev->vport_lock); 10073 10074 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10075 if (vlan->vlan_id == vlan_id) { 10076 mutex_unlock(&hdev->vport_lock); 10077 return; 10078 } 10079 } 10080 10081 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10082 if (!vlan) { 10083 mutex_unlock(&hdev->vport_lock); 10084 return; 10085 } 10086 10087 vlan->hd_tbl_status = writen_to_tbl; 10088 vlan->vlan_id = vlan_id; 10089 10090 list_add_tail(&vlan->node, &vport->vlan_list); 10091 mutex_unlock(&hdev->vport_lock); 10092 } 10093 10094 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10095 { 10096 struct hclge_vport_vlan_cfg *vlan, *tmp; 10097 struct hclge_dev *hdev = vport->back; 10098 int ret; 10099 10100 mutex_lock(&hdev->vport_lock); 10101 10102 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10103 if (!vlan->hd_tbl_status) { 10104 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10105 vport->vport_id, 10106 vlan->vlan_id, false); 10107 if (ret) { 10108 dev_err(&hdev->pdev->dev, 10109 "restore vport vlan list failed, ret=%d\n", 10110 ret); 10111 10112 mutex_unlock(&hdev->vport_lock); 10113 return ret; 10114 } 10115 } 10116 vlan->hd_tbl_status = true; 10117 } 10118 10119 mutex_unlock(&hdev->vport_lock); 10120 10121 return 0; 10122 } 10123 10124 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10125 bool is_write_tbl) 10126 { 10127 struct hclge_vport_vlan_cfg *vlan, *tmp; 10128 struct hclge_dev *hdev = vport->back; 10129 10130 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10131 if (vlan->vlan_id == vlan_id) { 10132 if (is_write_tbl && vlan->hd_tbl_status) 10133 hclge_set_vlan_filter_hw(hdev, 10134 htons(ETH_P_8021Q), 10135 vport->vport_id, 10136 vlan_id, 10137 true); 10138 10139 list_del(&vlan->node); 10140 kfree(vlan); 10141 break; 10142 } 10143 } 10144 } 10145 10146 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10147 { 10148 struct hclge_vport_vlan_cfg *vlan, *tmp; 10149 struct hclge_dev *hdev = vport->back; 10150 10151 mutex_lock(&hdev->vport_lock); 10152 10153 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10154 if (vlan->hd_tbl_status) 10155 hclge_set_vlan_filter_hw(hdev, 10156 htons(ETH_P_8021Q), 10157 vport->vport_id, 10158 vlan->vlan_id, 10159 true); 10160 10161 vlan->hd_tbl_status = false; 10162 if (is_del_list) { 10163 list_del(&vlan->node); 10164 kfree(vlan); 10165 } 10166 } 10167 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10168 mutex_unlock(&hdev->vport_lock); 10169 } 10170 10171 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10172 { 10173 struct hclge_vport_vlan_cfg *vlan, *tmp; 10174 struct hclge_vport *vport; 10175 int i; 10176 10177 mutex_lock(&hdev->vport_lock); 10178 10179 for (i = 0; i < hdev->num_alloc_vport; i++) { 10180 vport = &hdev->vport[i]; 10181 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10182 list_del(&vlan->node); 10183 kfree(vlan); 10184 } 10185 } 10186 10187 mutex_unlock(&hdev->vport_lock); 10188 } 10189 10190 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10191 { 10192 struct hclge_vlan_info *vlan_info; 10193 struct hclge_vport *vport; 10194 u16 vlan_proto; 10195 u16 vlan_id; 10196 u16 state; 10197 int vf_id; 10198 int ret; 10199 10200 /* PF should restore all vfs port base vlan */ 10201 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10202 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10203 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10204 &vport->port_base_vlan_cfg.vlan_info : 10205 &vport->port_base_vlan_cfg.old_vlan_info; 10206 10207 vlan_id = vlan_info->vlan_tag; 10208 vlan_proto = vlan_info->vlan_proto; 10209 state = vport->port_base_vlan_cfg.state; 10210 10211 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10212 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10213 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10214 vport->vport_id, 10215 vlan_id, false); 10216 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10217 } 10218 } 10219 } 10220 10221 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10222 { 10223 struct hclge_vport_vlan_cfg *vlan, *tmp; 10224 struct hclge_dev *hdev = vport->back; 10225 int ret; 10226 10227 mutex_lock(&hdev->vport_lock); 10228 10229 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10230 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10231 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10232 vport->vport_id, 10233 vlan->vlan_id, false); 10234 if (ret) 10235 break; 10236 vlan->hd_tbl_status = true; 10237 } 10238 } 10239 10240 mutex_unlock(&hdev->vport_lock); 10241 } 10242 10243 /* For global reset and imp reset, hardware will clear the mac table, 10244 * so we change the mac address state from ACTIVE to TO_ADD, then they 10245 * can be restored in the service task after reset complete. Furtherly, 10246 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10247 * be restored after reset, so just remove these mac nodes from mac_list. 10248 */ 10249 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10250 { 10251 struct hclge_mac_node *mac_node, *tmp; 10252 10253 list_for_each_entry_safe(mac_node, tmp, list, node) { 10254 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10255 mac_node->state = HCLGE_MAC_TO_ADD; 10256 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10257 list_del(&mac_node->node); 10258 kfree(mac_node); 10259 } 10260 } 10261 } 10262 10263 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10264 { 10265 spin_lock_bh(&vport->mac_list_lock); 10266 10267 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10268 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10269 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10270 10271 spin_unlock_bh(&vport->mac_list_lock); 10272 } 10273 10274 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10275 { 10276 struct hclge_vport *vport = &hdev->vport[0]; 10277 struct hnae3_handle *handle = &vport->nic; 10278 10279 hclge_restore_mac_table_common(vport); 10280 hclge_restore_vport_port_base_vlan_config(hdev); 10281 hclge_restore_vport_vlan_table(vport); 10282 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10283 hclge_restore_fd_entries(handle); 10284 } 10285 10286 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10287 { 10288 struct hclge_vport *vport = hclge_get_vport(handle); 10289 10290 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10291 vport->rxvlan_cfg.strip_tag1_en = false; 10292 vport->rxvlan_cfg.strip_tag2_en = enable; 10293 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10294 } else { 10295 vport->rxvlan_cfg.strip_tag1_en = enable; 10296 vport->rxvlan_cfg.strip_tag2_en = true; 10297 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10298 } 10299 10300 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10301 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10302 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10303 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10304 10305 return hclge_set_vlan_rx_offload_cfg(vport); 10306 } 10307 10308 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10309 { 10310 struct hclge_dev *hdev = vport->back; 10311 10312 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10313 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10314 } 10315 10316 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10317 u16 port_base_vlan_state, 10318 struct hclge_vlan_info *new_info, 10319 struct hclge_vlan_info *old_info) 10320 { 10321 struct hclge_dev *hdev = vport->back; 10322 int ret; 10323 10324 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10325 hclge_rm_vport_all_vlan_table(vport, false); 10326 /* force clear VLAN 0 */ 10327 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10328 if (ret) 10329 return ret; 10330 return hclge_set_vlan_filter_hw(hdev, 10331 htons(new_info->vlan_proto), 10332 vport->vport_id, 10333 new_info->vlan_tag, 10334 false); 10335 } 10336 10337 vport->port_base_vlan_cfg.tbl_sta = false; 10338 10339 /* force add VLAN 0 */ 10340 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10341 if (ret) 10342 return ret; 10343 10344 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10345 vport->vport_id, old_info->vlan_tag, 10346 true); 10347 if (ret) 10348 return ret; 10349 10350 return hclge_add_vport_all_vlan_table(vport); 10351 } 10352 10353 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10354 const struct hclge_vlan_info *old_cfg) 10355 { 10356 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10357 return true; 10358 10359 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10360 return true; 10361 10362 return false; 10363 } 10364 10365 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10366 struct hclge_vlan_info *new_info, 10367 struct hclge_vlan_info *old_info) 10368 { 10369 struct hclge_dev *hdev = vport->back; 10370 int ret; 10371 10372 /* add new VLAN tag */ 10373 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10374 vport->vport_id, new_info->vlan_tag, 10375 false); 10376 if (ret) 10377 return ret; 10378 10379 vport->port_base_vlan_cfg.tbl_sta = false; 10380 /* remove old VLAN tag */ 10381 if (old_info->vlan_tag == 0) 10382 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10383 true, 0); 10384 else 10385 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10386 vport->vport_id, 10387 old_info->vlan_tag, true); 10388 if (ret) 10389 dev_err(&hdev->pdev->dev, 10390 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10391 vport->vport_id, old_info->vlan_tag, ret); 10392 10393 return ret; 10394 } 10395 10396 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10397 struct hclge_vlan_info *vlan_info) 10398 { 10399 struct hnae3_handle *nic = &vport->nic; 10400 struct hclge_vlan_info *old_vlan_info; 10401 int ret; 10402 10403 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10404 10405 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10406 vlan_info->qos); 10407 if (ret) 10408 return ret; 10409 10410 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10411 goto out; 10412 10413 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10414 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10415 old_vlan_info); 10416 else 10417 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10418 old_vlan_info); 10419 if (ret) 10420 return ret; 10421 10422 out: 10423 vport->port_base_vlan_cfg.state = state; 10424 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10425 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10426 else 10427 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10428 10429 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10430 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10431 vport->port_base_vlan_cfg.tbl_sta = true; 10432 hclge_set_vport_vlan_fltr_change(vport); 10433 10434 return 0; 10435 } 10436 10437 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10438 enum hnae3_port_base_vlan_state state, 10439 u16 vlan, u8 qos) 10440 { 10441 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10442 if (!vlan && !qos) 10443 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10444 10445 return HNAE3_PORT_BASE_VLAN_ENABLE; 10446 } 10447 10448 if (!vlan && !qos) 10449 return HNAE3_PORT_BASE_VLAN_DISABLE; 10450 10451 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10452 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10453 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10454 10455 return HNAE3_PORT_BASE_VLAN_MODIFY; 10456 } 10457 10458 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10459 u16 vlan, u8 qos, __be16 proto) 10460 { 10461 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10462 struct hclge_vport *vport = hclge_get_vport(handle); 10463 struct hclge_dev *hdev = vport->back; 10464 struct hclge_vlan_info vlan_info; 10465 u16 state; 10466 int ret; 10467 10468 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10469 return -EOPNOTSUPP; 10470 10471 vport = hclge_get_vf_vport(hdev, vfid); 10472 if (!vport) 10473 return -EINVAL; 10474 10475 /* qos is a 3 bits value, so can not be bigger than 7 */ 10476 if (vlan > VLAN_N_VID - 1 || qos > 7) 10477 return -EINVAL; 10478 if (proto != htons(ETH_P_8021Q)) 10479 return -EPROTONOSUPPORT; 10480 10481 state = hclge_get_port_base_vlan_state(vport, 10482 vport->port_base_vlan_cfg.state, 10483 vlan, qos); 10484 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10485 return 0; 10486 10487 vlan_info.vlan_tag = vlan; 10488 vlan_info.qos = qos; 10489 vlan_info.vlan_proto = ntohs(proto); 10490 10491 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10492 if (ret) { 10493 dev_err(&hdev->pdev->dev, 10494 "failed to update port base vlan for vf %d, ret = %d\n", 10495 vfid, ret); 10496 return ret; 10497 } 10498 10499 /* there is a timewindow for PF to know VF unalive, it may 10500 * cause send mailbox fail, but it doesn't matter, VF will 10501 * query it when reinit. 10502 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10503 * VLAN state. 10504 */ 10505 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10506 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10507 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10508 vport->vport_id, 10509 state, 10510 &vlan_info); 10511 else 10512 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10513 &vport->need_notify); 10514 } 10515 return 0; 10516 } 10517 10518 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10519 { 10520 struct hclge_vlan_info *vlan_info; 10521 struct hclge_vport *vport; 10522 int ret; 10523 int vf; 10524 10525 /* clear port base vlan for all vf */ 10526 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10527 vport = &hdev->vport[vf]; 10528 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10529 10530 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10531 vport->vport_id, 10532 vlan_info->vlan_tag, true); 10533 if (ret) 10534 dev_err(&hdev->pdev->dev, 10535 "failed to clear vf vlan for vf%d, ret = %d\n", 10536 vf - HCLGE_VF_VPORT_START_NUM, ret); 10537 } 10538 } 10539 10540 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10541 u16 vlan_id, bool is_kill) 10542 { 10543 struct hclge_vport *vport = hclge_get_vport(handle); 10544 struct hclge_dev *hdev = vport->back; 10545 bool writen_to_tbl = false; 10546 int ret = 0; 10547 10548 /* When device is resetting or reset failed, firmware is unable to 10549 * handle mailbox. Just record the vlan id, and remove it after 10550 * reset finished. 10551 */ 10552 mutex_lock(&hdev->vport_lock); 10553 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10554 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10555 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10556 mutex_unlock(&hdev->vport_lock); 10557 return -EBUSY; 10558 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10559 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10560 } 10561 mutex_unlock(&hdev->vport_lock); 10562 10563 /* when port base vlan enabled, we use port base vlan as the vlan 10564 * filter entry. In this case, we don't update vlan filter table 10565 * when user add new vlan or remove exist vlan, just update the vport 10566 * vlan list. The vlan id in vlan list will be writen in vlan filter 10567 * table until port base vlan disabled 10568 */ 10569 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10570 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10571 vlan_id, is_kill); 10572 writen_to_tbl = true; 10573 } 10574 10575 if (!ret) { 10576 if (!is_kill) { 10577 hclge_add_vport_vlan_table(vport, vlan_id, 10578 writen_to_tbl); 10579 } else if (is_kill && vlan_id != 0) { 10580 mutex_lock(&hdev->vport_lock); 10581 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10582 mutex_unlock(&hdev->vport_lock); 10583 } 10584 } else if (is_kill) { 10585 /* when remove hw vlan filter failed, record the vlan id, 10586 * and try to remove it from hw later, to be consistence 10587 * with stack 10588 */ 10589 mutex_lock(&hdev->vport_lock); 10590 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10591 mutex_unlock(&hdev->vport_lock); 10592 } 10593 10594 hclge_set_vport_vlan_fltr_change(vport); 10595 10596 return ret; 10597 } 10598 10599 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10600 { 10601 struct hclge_vport *vport; 10602 int ret; 10603 u16 i; 10604 10605 for (i = 0; i < hdev->num_alloc_vport; i++) { 10606 vport = &hdev->vport[i]; 10607 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10608 &vport->state)) 10609 continue; 10610 10611 ret = hclge_enable_vport_vlan_filter(vport, 10612 vport->req_vlan_fltr_en); 10613 if (ret) { 10614 dev_err(&hdev->pdev->dev, 10615 "failed to sync vlan filter state for vport%u, ret = %d\n", 10616 vport->vport_id, ret); 10617 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10618 &vport->state); 10619 return; 10620 } 10621 } 10622 } 10623 10624 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10625 { 10626 #define HCLGE_MAX_SYNC_COUNT 60 10627 10628 int i, ret, sync_cnt = 0; 10629 u16 vlan_id; 10630 10631 mutex_lock(&hdev->vport_lock); 10632 /* start from vport 1 for PF is always alive */ 10633 for (i = 0; i < hdev->num_alloc_vport; i++) { 10634 struct hclge_vport *vport = &hdev->vport[i]; 10635 10636 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10637 VLAN_N_VID); 10638 while (vlan_id != VLAN_N_VID) { 10639 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10640 vport->vport_id, vlan_id, 10641 true); 10642 if (ret && ret != -EINVAL) { 10643 mutex_unlock(&hdev->vport_lock); 10644 return; 10645 } 10646 10647 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10648 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10649 hclge_set_vport_vlan_fltr_change(vport); 10650 10651 sync_cnt++; 10652 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10653 mutex_unlock(&hdev->vport_lock); 10654 return; 10655 } 10656 10657 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10658 VLAN_N_VID); 10659 } 10660 } 10661 mutex_unlock(&hdev->vport_lock); 10662 10663 hclge_sync_vlan_fltr_state(hdev); 10664 } 10665 10666 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10667 { 10668 struct hclge_config_max_frm_size_cmd *req; 10669 struct hclge_desc desc; 10670 10671 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10672 10673 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10674 req->max_frm_size = cpu_to_le16(new_mps); 10675 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10676 10677 return hclge_cmd_send(&hdev->hw, &desc, 1); 10678 } 10679 10680 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10681 { 10682 struct hclge_vport *vport = hclge_get_vport(handle); 10683 10684 return hclge_set_vport_mtu(vport, new_mtu); 10685 } 10686 10687 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10688 { 10689 struct hclge_dev *hdev = vport->back; 10690 int i, max_frm_size, ret; 10691 10692 /* HW supprt 2 layer vlan */ 10693 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10694 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10695 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10696 return -EINVAL; 10697 10698 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10699 mutex_lock(&hdev->vport_lock); 10700 /* VF's mps must fit within hdev->mps */ 10701 if (vport->vport_id && max_frm_size > hdev->mps) { 10702 mutex_unlock(&hdev->vport_lock); 10703 return -EINVAL; 10704 } else if (vport->vport_id) { 10705 vport->mps = max_frm_size; 10706 mutex_unlock(&hdev->vport_lock); 10707 return 0; 10708 } 10709 10710 /* PF's mps must be greater then VF's mps */ 10711 for (i = 1; i < hdev->num_alloc_vport; i++) 10712 if (max_frm_size < hdev->vport[i].mps) { 10713 dev_err(&hdev->pdev->dev, 10714 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10715 i, hdev->vport[i].mps); 10716 mutex_unlock(&hdev->vport_lock); 10717 return -EINVAL; 10718 } 10719 10720 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10721 10722 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10723 if (ret) { 10724 dev_err(&hdev->pdev->dev, 10725 "Change mtu fail, ret =%d\n", ret); 10726 goto out; 10727 } 10728 10729 hdev->mps = max_frm_size; 10730 vport->mps = max_frm_size; 10731 10732 ret = hclge_buffer_alloc(hdev); 10733 if (ret) 10734 dev_err(&hdev->pdev->dev, 10735 "Allocate buffer fail, ret =%d\n", ret); 10736 10737 out: 10738 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10739 mutex_unlock(&hdev->vport_lock); 10740 return ret; 10741 } 10742 10743 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10744 bool enable) 10745 { 10746 struct hclge_reset_tqp_queue_cmd *req; 10747 struct hclge_desc desc; 10748 int ret; 10749 10750 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10751 10752 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10753 req->tqp_id = cpu_to_le16(queue_id); 10754 if (enable) 10755 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10756 10757 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10758 if (ret) { 10759 dev_err(&hdev->pdev->dev, 10760 "Send tqp reset cmd error, status =%d\n", ret); 10761 return ret; 10762 } 10763 10764 return 0; 10765 } 10766 10767 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10768 u8 *reset_status) 10769 { 10770 struct hclge_reset_tqp_queue_cmd *req; 10771 struct hclge_desc desc; 10772 int ret; 10773 10774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10775 10776 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10777 req->tqp_id = cpu_to_le16(queue_id); 10778 10779 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10780 if (ret) { 10781 dev_err(&hdev->pdev->dev, 10782 "Get reset status error, status =%d\n", ret); 10783 return ret; 10784 } 10785 10786 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10787 10788 return 0; 10789 } 10790 10791 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10792 { 10793 struct hclge_comm_tqp *tqp; 10794 struct hnae3_queue *queue; 10795 10796 queue = handle->kinfo.tqp[queue_id]; 10797 tqp = container_of(queue, struct hclge_comm_tqp, q); 10798 10799 return tqp->index; 10800 } 10801 10802 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10803 { 10804 struct hclge_vport *vport = hclge_get_vport(handle); 10805 struct hclge_dev *hdev = vport->back; 10806 u16 reset_try_times = 0; 10807 u8 reset_status; 10808 u16 queue_gid; 10809 int ret; 10810 u16 i; 10811 10812 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10813 queue_gid = hclge_covert_handle_qid_global(handle, i); 10814 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10815 if (ret) { 10816 dev_err(&hdev->pdev->dev, 10817 "failed to send reset tqp cmd, ret = %d\n", 10818 ret); 10819 return ret; 10820 } 10821 10822 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10823 ret = hclge_get_reset_status(hdev, queue_gid, 10824 &reset_status); 10825 if (ret) 10826 return ret; 10827 10828 if (reset_status) 10829 break; 10830 10831 /* Wait for tqp hw reset */ 10832 usleep_range(1000, 1200); 10833 } 10834 10835 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10836 dev_err(&hdev->pdev->dev, 10837 "wait for tqp hw reset timeout\n"); 10838 return -ETIME; 10839 } 10840 10841 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10842 if (ret) { 10843 dev_err(&hdev->pdev->dev, 10844 "failed to deassert soft reset, ret = %d\n", 10845 ret); 10846 return ret; 10847 } 10848 reset_try_times = 0; 10849 } 10850 return 0; 10851 } 10852 10853 static int hclge_reset_rcb(struct hnae3_handle *handle) 10854 { 10855 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10856 #define HCLGE_RESET_RCB_SUCCESS 1U 10857 10858 struct hclge_vport *vport = hclge_get_vport(handle); 10859 struct hclge_dev *hdev = vport->back; 10860 struct hclge_reset_cmd *req; 10861 struct hclge_desc desc; 10862 u8 return_status; 10863 u16 queue_gid; 10864 int ret; 10865 10866 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10867 10868 req = (struct hclge_reset_cmd *)desc.data; 10869 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10870 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10871 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10872 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10873 10874 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10875 if (ret) { 10876 dev_err(&hdev->pdev->dev, 10877 "failed to send rcb reset cmd, ret = %d\n", ret); 10878 return ret; 10879 } 10880 10881 return_status = req->fun_reset_rcb_return_status; 10882 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10883 return 0; 10884 10885 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10886 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10887 return_status); 10888 return -EIO; 10889 } 10890 10891 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10892 * again to reset all tqps 10893 */ 10894 return hclge_reset_tqp_cmd(handle); 10895 } 10896 10897 int hclge_reset_tqp(struct hnae3_handle *handle) 10898 { 10899 struct hclge_vport *vport = hclge_get_vport(handle); 10900 struct hclge_dev *hdev = vport->back; 10901 int ret; 10902 10903 /* only need to disable PF's tqp */ 10904 if (!vport->vport_id) { 10905 ret = hclge_tqp_enable(handle, false); 10906 if (ret) { 10907 dev_err(&hdev->pdev->dev, 10908 "failed to disable tqp, ret = %d\n", ret); 10909 return ret; 10910 } 10911 } 10912 10913 return hclge_reset_rcb(handle); 10914 } 10915 10916 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10917 { 10918 struct hclge_vport *vport = hclge_get_vport(handle); 10919 struct hclge_dev *hdev = vport->back; 10920 10921 return hdev->fw_version; 10922 } 10923 10924 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 10925 { 10926 struct hclge_comm_query_scc_cmd *resp; 10927 struct hclge_desc desc; 10928 int ret; 10929 10930 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 10931 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 10932 10933 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10934 if (ret) 10935 return ret; 10936 10937 *scc_version = le32_to_cpu(resp->scc_version); 10938 10939 return 0; 10940 } 10941 10942 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10943 { 10944 struct phy_device *phydev = hdev->hw.mac.phydev; 10945 10946 if (!phydev) 10947 return; 10948 10949 phy_set_asym_pause(phydev, rx_en, tx_en); 10950 } 10951 10952 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10953 { 10954 int ret; 10955 10956 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10957 return 0; 10958 10959 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10960 if (ret) 10961 dev_err(&hdev->pdev->dev, 10962 "configure pauseparam error, ret = %d.\n", ret); 10963 10964 return ret; 10965 } 10966 10967 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10968 { 10969 struct phy_device *phydev = hdev->hw.mac.phydev; 10970 u16 remote_advertising = 0; 10971 u16 local_advertising; 10972 u32 rx_pause, tx_pause; 10973 u8 flowctl; 10974 10975 if (!phydev->link) 10976 return 0; 10977 10978 if (!phydev->autoneg) 10979 return hclge_mac_pause_setup_hw(hdev); 10980 10981 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10982 10983 if (phydev->pause) 10984 remote_advertising = LPA_PAUSE_CAP; 10985 10986 if (phydev->asym_pause) 10987 remote_advertising |= LPA_PAUSE_ASYM; 10988 10989 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10990 remote_advertising); 10991 tx_pause = flowctl & FLOW_CTRL_TX; 10992 rx_pause = flowctl & FLOW_CTRL_RX; 10993 10994 if (phydev->duplex == HCLGE_MAC_HALF) { 10995 tx_pause = 0; 10996 rx_pause = 0; 10997 } 10998 10999 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 11000 } 11001 11002 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 11003 u32 *rx_en, u32 *tx_en) 11004 { 11005 struct hclge_vport *vport = hclge_get_vport(handle); 11006 struct hclge_dev *hdev = vport->back; 11007 u8 media_type = hdev->hw.mac.media_type; 11008 11009 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 11010 hclge_get_autoneg(handle) : 0; 11011 11012 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11013 *rx_en = 0; 11014 *tx_en = 0; 11015 return; 11016 } 11017 11018 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 11019 *rx_en = 1; 11020 *tx_en = 0; 11021 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 11022 *tx_en = 1; 11023 *rx_en = 0; 11024 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 11025 *rx_en = 1; 11026 *tx_en = 1; 11027 } else { 11028 *rx_en = 0; 11029 *tx_en = 0; 11030 } 11031 } 11032 11033 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 11034 u32 rx_en, u32 tx_en) 11035 { 11036 if (rx_en && tx_en) 11037 hdev->fc_mode_last_time = HCLGE_FC_FULL; 11038 else if (rx_en && !tx_en) 11039 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 11040 else if (!rx_en && tx_en) 11041 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 11042 else 11043 hdev->fc_mode_last_time = HCLGE_FC_NONE; 11044 11045 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 11046 } 11047 11048 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 11049 u32 rx_en, u32 tx_en) 11050 { 11051 struct hclge_vport *vport = hclge_get_vport(handle); 11052 struct hclge_dev *hdev = vport->back; 11053 struct phy_device *phydev = hdev->hw.mac.phydev; 11054 u32 fc_autoneg; 11055 11056 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11057 fc_autoneg = hclge_get_autoneg(handle); 11058 if (auto_neg != fc_autoneg) { 11059 dev_info(&hdev->pdev->dev, 11060 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11061 return -EOPNOTSUPP; 11062 } 11063 } 11064 11065 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11066 dev_info(&hdev->pdev->dev, 11067 "Priority flow control enabled. Cannot set link flow control.\n"); 11068 return -EOPNOTSUPP; 11069 } 11070 11071 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11072 11073 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11074 11075 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11076 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11077 11078 if (phydev) 11079 return phy_start_aneg(phydev); 11080 11081 return -EOPNOTSUPP; 11082 } 11083 11084 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11085 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11086 { 11087 struct hclge_vport *vport = hclge_get_vport(handle); 11088 struct hclge_dev *hdev = vport->back; 11089 11090 if (speed) 11091 *speed = hdev->hw.mac.speed; 11092 if (duplex) 11093 *duplex = hdev->hw.mac.duplex; 11094 if (auto_neg) 11095 *auto_neg = hdev->hw.mac.autoneg; 11096 if (lane_num) 11097 *lane_num = hdev->hw.mac.lane_num; 11098 } 11099 11100 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11101 u8 *module_type) 11102 { 11103 struct hclge_vport *vport = hclge_get_vport(handle); 11104 struct hclge_dev *hdev = vport->back; 11105 11106 /* When nic is down, the service task is not running, doesn't update 11107 * the port information per second. Query the port information before 11108 * return the media type, ensure getting the correct media information. 11109 */ 11110 hclge_update_port_info(hdev); 11111 11112 if (media_type) 11113 *media_type = hdev->hw.mac.media_type; 11114 11115 if (module_type) 11116 *module_type = hdev->hw.mac.module_type; 11117 } 11118 11119 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11120 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11121 { 11122 struct hclge_vport *vport = hclge_get_vport(handle); 11123 struct hclge_dev *hdev = vport->back; 11124 struct phy_device *phydev = hdev->hw.mac.phydev; 11125 int mdix_ctrl, mdix, is_resolved; 11126 unsigned int retval; 11127 11128 if (!phydev) { 11129 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11130 *tp_mdix = ETH_TP_MDI_INVALID; 11131 return; 11132 } 11133 11134 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11135 11136 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11137 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11138 HCLGE_PHY_MDIX_CTRL_S); 11139 11140 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11141 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11142 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11143 11144 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11145 11146 switch (mdix_ctrl) { 11147 case 0x0: 11148 *tp_mdix_ctrl = ETH_TP_MDI; 11149 break; 11150 case 0x1: 11151 *tp_mdix_ctrl = ETH_TP_MDI_X; 11152 break; 11153 case 0x3: 11154 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11155 break; 11156 default: 11157 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11158 break; 11159 } 11160 11161 if (!is_resolved) 11162 *tp_mdix = ETH_TP_MDI_INVALID; 11163 else if (mdix) 11164 *tp_mdix = ETH_TP_MDI_X; 11165 else 11166 *tp_mdix = ETH_TP_MDI; 11167 } 11168 11169 static void hclge_info_show(struct hclge_dev *hdev) 11170 { 11171 struct hnae3_handle *handle = &hdev->vport->nic; 11172 struct device *dev = &hdev->pdev->dev; 11173 11174 dev_info(dev, "PF info begin:\n"); 11175 11176 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11177 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11178 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11179 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11180 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11181 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11182 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11183 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11184 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11185 dev_info(dev, "This is %s PF\n", 11186 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11187 dev_info(dev, "DCB %s\n", 11188 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11189 dev_info(dev, "MQPRIO %s\n", 11190 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11191 dev_info(dev, "Default tx spare buffer size: %u\n", 11192 hdev->tx_spare_buf_size); 11193 11194 dev_info(dev, "PF info end.\n"); 11195 } 11196 11197 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11198 struct hclge_vport *vport) 11199 { 11200 struct hnae3_client *client = vport->nic.client; 11201 struct hclge_dev *hdev = ae_dev->priv; 11202 int rst_cnt = hdev->rst_stats.reset_cnt; 11203 int ret; 11204 11205 ret = client->ops->init_instance(&vport->nic); 11206 if (ret) 11207 return ret; 11208 11209 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11210 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11211 rst_cnt != hdev->rst_stats.reset_cnt) { 11212 ret = -EBUSY; 11213 goto init_nic_err; 11214 } 11215 11216 /* Enable nic hw error interrupts */ 11217 ret = hclge_config_nic_hw_error(hdev, true); 11218 if (ret) { 11219 dev_err(&ae_dev->pdev->dev, 11220 "fail(%d) to enable hw error interrupts\n", ret); 11221 goto init_nic_err; 11222 } 11223 11224 hnae3_set_client_init_flag(client, ae_dev, 1); 11225 11226 if (netif_msg_drv(&hdev->vport->nic)) 11227 hclge_info_show(hdev); 11228 11229 return ret; 11230 11231 init_nic_err: 11232 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11233 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11234 msleep(HCLGE_WAIT_RESET_DONE); 11235 11236 client->ops->uninit_instance(&vport->nic, 0); 11237 11238 return ret; 11239 } 11240 11241 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11242 struct hclge_vport *vport) 11243 { 11244 struct hclge_dev *hdev = ae_dev->priv; 11245 struct hnae3_client *client; 11246 int rst_cnt; 11247 int ret; 11248 11249 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11250 !hdev->nic_client) 11251 return 0; 11252 11253 client = hdev->roce_client; 11254 ret = hclge_init_roce_base_info(vport); 11255 if (ret) 11256 return ret; 11257 11258 rst_cnt = hdev->rst_stats.reset_cnt; 11259 ret = client->ops->init_instance(&vport->roce); 11260 if (ret) 11261 return ret; 11262 11263 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11264 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11265 rst_cnt != hdev->rst_stats.reset_cnt) { 11266 ret = -EBUSY; 11267 goto init_roce_err; 11268 } 11269 11270 /* Enable roce ras interrupts */ 11271 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11272 if (ret) { 11273 dev_err(&ae_dev->pdev->dev, 11274 "fail(%d) to enable roce ras interrupts\n", ret); 11275 goto init_roce_err; 11276 } 11277 11278 hnae3_set_client_init_flag(client, ae_dev, 1); 11279 11280 return 0; 11281 11282 init_roce_err: 11283 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11284 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11285 msleep(HCLGE_WAIT_RESET_DONE); 11286 11287 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11288 11289 return ret; 11290 } 11291 11292 static int hclge_init_client_instance(struct hnae3_client *client, 11293 struct hnae3_ae_dev *ae_dev) 11294 { 11295 struct hclge_dev *hdev = ae_dev->priv; 11296 struct hclge_vport *vport = &hdev->vport[0]; 11297 int ret; 11298 11299 switch (client->type) { 11300 case HNAE3_CLIENT_KNIC: 11301 hdev->nic_client = client; 11302 vport->nic.client = client; 11303 ret = hclge_init_nic_client_instance(ae_dev, vport); 11304 if (ret) 11305 goto clear_nic; 11306 11307 ret = hclge_init_roce_client_instance(ae_dev, vport); 11308 if (ret) 11309 goto clear_roce; 11310 11311 break; 11312 case HNAE3_CLIENT_ROCE: 11313 if (hnae3_dev_roce_supported(hdev)) { 11314 hdev->roce_client = client; 11315 vport->roce.client = client; 11316 } 11317 11318 ret = hclge_init_roce_client_instance(ae_dev, vport); 11319 if (ret) 11320 goto clear_roce; 11321 11322 break; 11323 default: 11324 return -EINVAL; 11325 } 11326 11327 return 0; 11328 11329 clear_nic: 11330 hdev->nic_client = NULL; 11331 vport->nic.client = NULL; 11332 return ret; 11333 clear_roce: 11334 hdev->roce_client = NULL; 11335 vport->roce.client = NULL; 11336 return ret; 11337 } 11338 11339 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 11340 { 11341 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11342 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 11343 } 11344 11345 static void hclge_uninit_client_instance(struct hnae3_client *client, 11346 struct hnae3_ae_dev *ae_dev) 11347 { 11348 struct hclge_dev *hdev = ae_dev->priv; 11349 struct hclge_vport *vport = &hdev->vport[0]; 11350 11351 if (hdev->roce_client) { 11352 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11353 while (hclge_uninit_need_wait(hdev)) 11354 msleep(HCLGE_WAIT_RESET_DONE); 11355 11356 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11357 hdev->roce_client = NULL; 11358 vport->roce.client = NULL; 11359 } 11360 if (client->type == HNAE3_CLIENT_ROCE) 11361 return; 11362 if (hdev->nic_client && client->ops->uninit_instance) { 11363 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11364 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11365 msleep(HCLGE_WAIT_RESET_DONE); 11366 11367 client->ops->uninit_instance(&vport->nic, 0); 11368 hdev->nic_client = NULL; 11369 vport->nic.client = NULL; 11370 } 11371 } 11372 11373 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11374 { 11375 struct pci_dev *pdev = hdev->pdev; 11376 struct hclge_hw *hw = &hdev->hw; 11377 11378 /* for device does not have device memory, return directly */ 11379 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11380 return 0; 11381 11382 hw->hw.mem_base = 11383 devm_ioremap_wc(&pdev->dev, 11384 pci_resource_start(pdev, HCLGE_MEM_BAR), 11385 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11386 if (!hw->hw.mem_base) { 11387 dev_err(&pdev->dev, "failed to map device memory\n"); 11388 return -EFAULT; 11389 } 11390 11391 return 0; 11392 } 11393 11394 static int hclge_pci_init(struct hclge_dev *hdev) 11395 { 11396 struct pci_dev *pdev = hdev->pdev; 11397 struct hclge_hw *hw; 11398 int ret; 11399 11400 ret = pci_enable_device(pdev); 11401 if (ret) { 11402 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11403 return ret; 11404 } 11405 11406 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11407 if (ret) { 11408 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11409 if (ret) { 11410 dev_err(&pdev->dev, 11411 "can't set consistent PCI DMA"); 11412 goto err_disable_device; 11413 } 11414 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11415 } 11416 11417 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11418 if (ret) { 11419 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11420 goto err_disable_device; 11421 } 11422 11423 pci_set_master(pdev); 11424 hw = &hdev->hw; 11425 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11426 if (!hw->hw.io_base) { 11427 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11428 ret = -ENOMEM; 11429 goto err_release_regions; 11430 } 11431 11432 ret = hclge_dev_mem_map(hdev); 11433 if (ret) 11434 goto err_unmap_io_base; 11435 11436 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11437 11438 return 0; 11439 11440 err_unmap_io_base: 11441 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11442 err_release_regions: 11443 pci_release_regions(pdev); 11444 err_disable_device: 11445 pci_disable_device(pdev); 11446 11447 return ret; 11448 } 11449 11450 static void hclge_pci_uninit(struct hclge_dev *hdev) 11451 { 11452 struct pci_dev *pdev = hdev->pdev; 11453 11454 if (hdev->hw.hw.mem_base) 11455 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11456 11457 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11458 pci_free_irq_vectors(pdev); 11459 pci_release_regions(pdev); 11460 pci_disable_device(pdev); 11461 } 11462 11463 static void hclge_state_init(struct hclge_dev *hdev) 11464 { 11465 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11466 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11467 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11468 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11469 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11470 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11471 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11472 } 11473 11474 static void hclge_state_uninit(struct hclge_dev *hdev) 11475 { 11476 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11477 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11478 11479 if (hdev->reset_timer.function) 11480 del_timer_sync(&hdev->reset_timer); 11481 if (hdev->service_task.work.func) 11482 cancel_delayed_work_sync(&hdev->service_task); 11483 } 11484 11485 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11486 enum hnae3_reset_type rst_type) 11487 { 11488 #define HCLGE_RESET_RETRY_WAIT_MS 500 11489 #define HCLGE_RESET_RETRY_CNT 5 11490 11491 struct hclge_dev *hdev = ae_dev->priv; 11492 int retry_cnt = 0; 11493 int ret; 11494 11495 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11496 down(&hdev->reset_sem); 11497 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11498 hdev->reset_type = rst_type; 11499 ret = hclge_reset_prepare(hdev); 11500 if (!ret && !hdev->reset_pending) 11501 break; 11502 11503 dev_err(&hdev->pdev->dev, 11504 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11505 ret, hdev->reset_pending, retry_cnt); 11506 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11507 up(&hdev->reset_sem); 11508 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11509 } 11510 11511 /* disable misc vector before reset done */ 11512 hclge_enable_vector(&hdev->misc_vector, false); 11513 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11514 11515 if (hdev->reset_type == HNAE3_FLR_RESET) 11516 hdev->rst_stats.flr_rst_cnt++; 11517 } 11518 11519 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11520 { 11521 struct hclge_dev *hdev = ae_dev->priv; 11522 int ret; 11523 11524 hclge_enable_vector(&hdev->misc_vector, true); 11525 11526 ret = hclge_reset_rebuild(hdev); 11527 if (ret) 11528 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11529 11530 hdev->reset_type = HNAE3_NONE_RESET; 11531 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11532 up(&hdev->reset_sem); 11533 } 11534 11535 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11536 { 11537 u16 i; 11538 11539 for (i = 0; i < hdev->num_alloc_vport; i++) { 11540 struct hclge_vport *vport = &hdev->vport[i]; 11541 int ret; 11542 11543 /* Send cmd to clear vport's FUNC_RST_ING */ 11544 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11545 if (ret) 11546 dev_warn(&hdev->pdev->dev, 11547 "clear vport(%u) rst failed %d!\n", 11548 vport->vport_id, ret); 11549 } 11550 } 11551 11552 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11553 { 11554 struct hclge_desc desc; 11555 int ret; 11556 11557 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11558 11559 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11560 /* This new command is only supported by new firmware, it will 11561 * fail with older firmware. Error value -EOPNOSUPP can only be 11562 * returned by older firmware running this command, to keep code 11563 * backward compatible we will override this value and return 11564 * success. 11565 */ 11566 if (ret && ret != -EOPNOTSUPP) { 11567 dev_err(&hdev->pdev->dev, 11568 "failed to clear hw resource, ret = %d\n", ret); 11569 return ret; 11570 } 11571 return 0; 11572 } 11573 11574 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11575 { 11576 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11577 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11578 } 11579 11580 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11581 { 11582 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11583 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11584 } 11585 11586 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11587 { 11588 struct hclge_vport *vport = hclge_get_vport(handle); 11589 11590 return &vport->back->hw.mac.wol; 11591 } 11592 11593 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11594 u32 *wol_supported) 11595 { 11596 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11597 struct hclge_desc desc; 11598 int ret; 11599 11600 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11601 true); 11602 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11603 11604 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11605 if (ret) { 11606 dev_err(&hdev->pdev->dev, 11607 "failed to query wol supported, ret = %d\n", ret); 11608 return ret; 11609 } 11610 11611 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11612 11613 return 0; 11614 } 11615 11616 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11617 struct hclge_wol_info *wol_info) 11618 { 11619 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11620 struct hclge_desc desc; 11621 int ret; 11622 11623 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11624 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11625 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11626 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11627 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11628 11629 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11630 if (ret) 11631 dev_err(&hdev->pdev->dev, 11632 "failed to set wol config, ret = %d\n", ret); 11633 11634 return ret; 11635 } 11636 11637 static int hclge_update_wol(struct hclge_dev *hdev) 11638 { 11639 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11640 11641 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11642 return 0; 11643 11644 return hclge_set_wol_cfg(hdev, wol_info); 11645 } 11646 11647 static int hclge_init_wol(struct hclge_dev *hdev) 11648 { 11649 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11650 int ret; 11651 11652 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11653 return 0; 11654 11655 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11656 ret = hclge_get_wol_supported_mode(hdev, 11657 &wol_info->wol_support_mode); 11658 if (ret) { 11659 wol_info->wol_support_mode = 0; 11660 return ret; 11661 } 11662 11663 return hclge_update_wol(hdev); 11664 } 11665 11666 static void hclge_get_wol(struct hnae3_handle *handle, 11667 struct ethtool_wolinfo *wol) 11668 { 11669 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11670 11671 wol->supported = wol_info->wol_support_mode; 11672 wol->wolopts = wol_info->wol_current_mode; 11673 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11674 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11675 } 11676 11677 static int hclge_set_wol(struct hnae3_handle *handle, 11678 struct ethtool_wolinfo *wol) 11679 { 11680 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11681 struct hclge_vport *vport = hclge_get_vport(handle); 11682 u32 wol_mode; 11683 int ret; 11684 11685 wol_mode = wol->wolopts; 11686 if (wol_mode & ~wol_info->wol_support_mode) 11687 return -EINVAL; 11688 11689 wol_info->wol_current_mode = wol_mode; 11690 if (wol_mode & WAKE_MAGICSECURE) { 11691 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11692 wol_info->wol_sopass_size = SOPASS_MAX; 11693 } else { 11694 wol_info->wol_sopass_size = 0; 11695 } 11696 11697 ret = hclge_set_wol_cfg(vport->back, wol_info); 11698 if (ret) 11699 wol_info->wol_current_mode = 0; 11700 11701 return ret; 11702 } 11703 11704 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11705 { 11706 struct pci_dev *pdev = ae_dev->pdev; 11707 struct hclge_dev *hdev; 11708 int ret; 11709 11710 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11711 if (!hdev) 11712 return -ENOMEM; 11713 11714 hdev->pdev = pdev; 11715 hdev->ae_dev = ae_dev; 11716 hdev->reset_type = HNAE3_NONE_RESET; 11717 hdev->reset_level = HNAE3_FUNC_RESET; 11718 ae_dev->priv = hdev; 11719 11720 /* HW supprt 2 layer vlan */ 11721 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11722 11723 mutex_init(&hdev->vport_lock); 11724 spin_lock_init(&hdev->fd_rule_lock); 11725 sema_init(&hdev->reset_sem, 1); 11726 11727 ret = hclge_pci_init(hdev); 11728 if (ret) 11729 goto out; 11730 11731 /* Firmware command queue initialize */ 11732 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11733 if (ret) 11734 goto err_pci_uninit; 11735 11736 /* Firmware command initialize */ 11737 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 11738 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11739 true, hdev->reset_pending); 11740 if (ret) 11741 goto err_cmd_uninit; 11742 11743 ret = hclge_clear_hw_resource(hdev); 11744 if (ret) 11745 goto err_cmd_uninit; 11746 11747 ret = hclge_get_cap(hdev); 11748 if (ret) 11749 goto err_cmd_uninit; 11750 11751 ret = hclge_query_dev_specs(hdev); 11752 if (ret) { 11753 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11754 ret); 11755 goto err_cmd_uninit; 11756 } 11757 11758 ret = hclge_configure(hdev); 11759 if (ret) { 11760 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11761 goto err_cmd_uninit; 11762 } 11763 11764 ret = hclge_init_msi(hdev); 11765 if (ret) { 11766 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11767 goto err_cmd_uninit; 11768 } 11769 11770 ret = hclge_misc_irq_init(hdev); 11771 if (ret) 11772 goto err_msi_uninit; 11773 11774 ret = hclge_alloc_tqps(hdev); 11775 if (ret) { 11776 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11777 goto err_msi_irq_uninit; 11778 } 11779 11780 ret = hclge_alloc_vport(hdev); 11781 if (ret) 11782 goto err_msi_irq_uninit; 11783 11784 ret = hclge_map_tqp(hdev); 11785 if (ret) 11786 goto err_msi_irq_uninit; 11787 11788 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11789 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11790 if (hnae3_dev_phy_imp_supported(hdev)) 11791 ret = hclge_update_tp_port_info(hdev); 11792 else 11793 ret = hclge_mac_mdio_config(hdev); 11794 11795 if (ret) 11796 goto err_msi_irq_uninit; 11797 } 11798 11799 ret = hclge_init_umv_space(hdev); 11800 if (ret) 11801 goto err_mdiobus_unreg; 11802 11803 ret = hclge_mac_init(hdev); 11804 if (ret) { 11805 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11806 goto err_mdiobus_unreg; 11807 } 11808 11809 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11810 if (ret) { 11811 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11812 goto err_mdiobus_unreg; 11813 } 11814 11815 ret = hclge_config_gro(hdev); 11816 if (ret) 11817 goto err_mdiobus_unreg; 11818 11819 ret = hclge_init_vlan_config(hdev); 11820 if (ret) { 11821 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11822 goto err_mdiobus_unreg; 11823 } 11824 11825 ret = hclge_tm_schd_init(hdev); 11826 if (ret) { 11827 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11828 goto err_mdiobus_unreg; 11829 } 11830 11831 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11832 &hdev->rss_cfg); 11833 if (ret) { 11834 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11835 goto err_mdiobus_unreg; 11836 } 11837 11838 ret = hclge_rss_init_hw(hdev); 11839 if (ret) { 11840 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11841 goto err_mdiobus_unreg; 11842 } 11843 11844 ret = init_mgr_tbl(hdev); 11845 if (ret) { 11846 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11847 goto err_mdiobus_unreg; 11848 } 11849 11850 ret = hclge_init_fd_config(hdev); 11851 if (ret) { 11852 dev_err(&pdev->dev, 11853 "fd table init fail, ret=%d\n", ret); 11854 goto err_mdiobus_unreg; 11855 } 11856 11857 ret = hclge_ptp_init(hdev); 11858 if (ret) 11859 goto err_mdiobus_unreg; 11860 11861 ret = hclge_update_port_info(hdev); 11862 if (ret) 11863 goto err_ptp_uninit; 11864 11865 INIT_KFIFO(hdev->mac_tnl_log); 11866 11867 hclge_dcb_ops_set(hdev); 11868 11869 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11870 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11871 11872 hclge_clear_all_event_cause(hdev); 11873 hclge_clear_resetting_state(hdev); 11874 11875 /* Log and clear the hw errors those already occurred */ 11876 if (hnae3_dev_ras_imp_supported(hdev)) 11877 hclge_handle_occurred_error(hdev); 11878 else 11879 hclge_handle_all_hns_hw_errors(ae_dev); 11880 11881 /* request delayed reset for the error recovery because an immediate 11882 * global reset on a PF affecting pending initialization of other PFs 11883 */ 11884 if (ae_dev->hw_err_reset_req) { 11885 enum hnae3_reset_type reset_level; 11886 11887 reset_level = hclge_get_reset_level(ae_dev, 11888 &ae_dev->hw_err_reset_req); 11889 hclge_set_def_reset_request(ae_dev, reset_level); 11890 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11891 } 11892 11893 hclge_init_rxd_adv_layout(hdev); 11894 11895 /* Enable MISC vector(vector0) */ 11896 hclge_enable_vector(&hdev->misc_vector, true); 11897 11898 ret = hclge_init_wol(hdev); 11899 if (ret) 11900 dev_warn(&pdev->dev, 11901 "failed to wake on lan init, ret = %d\n", ret); 11902 11903 ret = hclge_devlink_init(hdev); 11904 if (ret) 11905 goto err_ptp_uninit; 11906 11907 hclge_state_init(hdev); 11908 hdev->last_reset_time = jiffies; 11909 11910 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11911 HCLGE_DRIVER_NAME); 11912 11913 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11914 return 0; 11915 11916 err_ptp_uninit: 11917 hclge_ptp_uninit(hdev); 11918 err_mdiobus_unreg: 11919 if (hdev->hw.mac.phydev) 11920 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11921 err_msi_irq_uninit: 11922 hclge_misc_irq_uninit(hdev); 11923 err_msi_uninit: 11924 pci_free_irq_vectors(pdev); 11925 err_cmd_uninit: 11926 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11927 err_pci_uninit: 11928 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11929 pci_release_regions(pdev); 11930 pci_disable_device(pdev); 11931 out: 11932 mutex_destroy(&hdev->vport_lock); 11933 return ret; 11934 } 11935 11936 static void hclge_stats_clear(struct hclge_dev *hdev) 11937 { 11938 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11939 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11940 } 11941 11942 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11943 { 11944 return hclge_config_switch_param(hdev, vf, enable, 11945 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11946 } 11947 11948 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11949 { 11950 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11951 HCLGE_FILTER_FE_NIC_INGRESS_B, 11952 enable, vf); 11953 } 11954 11955 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11956 { 11957 int ret; 11958 11959 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11960 if (ret) { 11961 dev_err(&hdev->pdev->dev, 11962 "Set vf %d mac spoof check %s failed, ret=%d\n", 11963 vf, enable ? "on" : "off", ret); 11964 return ret; 11965 } 11966 11967 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11968 if (ret) 11969 dev_err(&hdev->pdev->dev, 11970 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11971 vf, enable ? "on" : "off", ret); 11972 11973 return ret; 11974 } 11975 11976 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11977 bool enable) 11978 { 11979 struct hclge_vport *vport = hclge_get_vport(handle); 11980 struct hclge_dev *hdev = vport->back; 11981 u32 new_spoofchk = enable ? 1 : 0; 11982 int ret; 11983 11984 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11985 return -EOPNOTSUPP; 11986 11987 vport = hclge_get_vf_vport(hdev, vf); 11988 if (!vport) 11989 return -EINVAL; 11990 11991 if (vport->vf_info.spoofchk == new_spoofchk) 11992 return 0; 11993 11994 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11995 dev_warn(&hdev->pdev->dev, 11996 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11997 vf); 11998 else if (enable && hclge_is_umv_space_full(vport, true)) 11999 dev_warn(&hdev->pdev->dev, 12000 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 12001 vf); 12002 12003 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 12004 if (ret) 12005 return ret; 12006 12007 vport->vf_info.spoofchk = new_spoofchk; 12008 return 0; 12009 } 12010 12011 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 12012 { 12013 struct hclge_vport *vport = hdev->vport; 12014 int ret; 12015 int i; 12016 12017 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12018 return 0; 12019 12020 /* resume the vf spoof check state after reset */ 12021 for (i = 0; i < hdev->num_alloc_vport; i++) { 12022 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 12023 vport->vf_info.spoofchk); 12024 if (ret) 12025 return ret; 12026 12027 vport++; 12028 } 12029 12030 return 0; 12031 } 12032 12033 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 12034 { 12035 struct hclge_vport *vport = hclge_get_vport(handle); 12036 struct hclge_dev *hdev = vport->back; 12037 u32 new_trusted = enable ? 1 : 0; 12038 12039 vport = hclge_get_vf_vport(hdev, vf); 12040 if (!vport) 12041 return -EINVAL; 12042 12043 if (vport->vf_info.trusted == new_trusted) 12044 return 0; 12045 12046 vport->vf_info.trusted = new_trusted; 12047 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12048 hclge_task_schedule(hdev, 0); 12049 12050 return 0; 12051 } 12052 12053 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 12054 { 12055 int ret; 12056 int vf; 12057 12058 /* reset vf rate to default value */ 12059 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 12060 struct hclge_vport *vport = &hdev->vport[vf]; 12061 12062 vport->vf_info.max_tx_rate = 0; 12063 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 12064 if (ret) 12065 dev_err(&hdev->pdev->dev, 12066 "vf%d failed to reset to default, ret=%d\n", 12067 vf - HCLGE_VF_VPORT_START_NUM, ret); 12068 } 12069 } 12070 12071 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12072 int min_tx_rate, int max_tx_rate) 12073 { 12074 if (min_tx_rate != 0 || 12075 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 12076 dev_err(&hdev->pdev->dev, 12077 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12078 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12079 return -EINVAL; 12080 } 12081 12082 return 0; 12083 } 12084 12085 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12086 int min_tx_rate, int max_tx_rate, bool force) 12087 { 12088 struct hclge_vport *vport = hclge_get_vport(handle); 12089 struct hclge_dev *hdev = vport->back; 12090 int ret; 12091 12092 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12093 if (ret) 12094 return ret; 12095 12096 vport = hclge_get_vf_vport(hdev, vf); 12097 if (!vport) 12098 return -EINVAL; 12099 12100 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12101 return 0; 12102 12103 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12104 if (ret) 12105 return ret; 12106 12107 vport->vf_info.max_tx_rate = max_tx_rate; 12108 12109 return 0; 12110 } 12111 12112 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12113 { 12114 struct hnae3_handle *handle = &hdev->vport->nic; 12115 struct hclge_vport *vport; 12116 int ret; 12117 int vf; 12118 12119 /* resume the vf max_tx_rate after reset */ 12120 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12121 vport = hclge_get_vf_vport(hdev, vf); 12122 if (!vport) 12123 return -EINVAL; 12124 12125 /* zero means max rate, after reset, firmware already set it to 12126 * max rate, so just continue. 12127 */ 12128 if (!vport->vf_info.max_tx_rate) 12129 continue; 12130 12131 ret = hclge_set_vf_rate(handle, vf, 0, 12132 vport->vf_info.max_tx_rate, true); 12133 if (ret) { 12134 dev_err(&hdev->pdev->dev, 12135 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12136 vf, vport->vf_info.max_tx_rate, ret); 12137 return ret; 12138 } 12139 } 12140 12141 return 0; 12142 } 12143 12144 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12145 { 12146 struct hclge_vport *vport = hdev->vport; 12147 int i; 12148 12149 for (i = 0; i < hdev->num_alloc_vport; i++) { 12150 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12151 vport++; 12152 } 12153 } 12154 12155 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12156 { 12157 struct hclge_dev *hdev = ae_dev->priv; 12158 struct pci_dev *pdev = ae_dev->pdev; 12159 int ret; 12160 12161 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12162 12163 hclge_stats_clear(hdev); 12164 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12165 * so here should not clean table in memory. 12166 */ 12167 if (hdev->reset_type == HNAE3_IMP_RESET || 12168 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12169 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12170 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12171 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12172 hclge_reset_umv_space(hdev); 12173 } 12174 12175 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12176 true, hdev->reset_pending); 12177 if (ret) { 12178 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12179 return ret; 12180 } 12181 12182 ret = hclge_map_tqp(hdev); 12183 if (ret) { 12184 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12185 return ret; 12186 } 12187 12188 ret = hclge_mac_init(hdev); 12189 if (ret) { 12190 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12191 return ret; 12192 } 12193 12194 ret = hclge_tp_port_init(hdev); 12195 if (ret) { 12196 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12197 ret); 12198 return ret; 12199 } 12200 12201 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12202 if (ret) { 12203 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12204 return ret; 12205 } 12206 12207 ret = hclge_config_gro(hdev); 12208 if (ret) 12209 return ret; 12210 12211 ret = hclge_init_vlan_config(hdev); 12212 if (ret) { 12213 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12214 return ret; 12215 } 12216 12217 hclge_reset_tc_config(hdev); 12218 12219 ret = hclge_tm_init_hw(hdev, true); 12220 if (ret) { 12221 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12222 return ret; 12223 } 12224 12225 ret = hclge_rss_init_hw(hdev); 12226 if (ret) { 12227 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12228 return ret; 12229 } 12230 12231 ret = init_mgr_tbl(hdev); 12232 if (ret) { 12233 dev_err(&pdev->dev, 12234 "failed to reinit manager table, ret = %d\n", ret); 12235 return ret; 12236 } 12237 12238 ret = hclge_init_fd_config(hdev); 12239 if (ret) { 12240 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12241 return ret; 12242 } 12243 12244 ret = hclge_ptp_init(hdev); 12245 if (ret) 12246 return ret; 12247 12248 /* Log and clear the hw errors those already occurred */ 12249 if (hnae3_dev_ras_imp_supported(hdev)) 12250 hclge_handle_occurred_error(hdev); 12251 else 12252 hclge_handle_all_hns_hw_errors(ae_dev); 12253 12254 /* Re-enable the hw error interrupts because 12255 * the interrupts get disabled on global reset. 12256 */ 12257 ret = hclge_config_nic_hw_error(hdev, true); 12258 if (ret) { 12259 dev_err(&pdev->dev, 12260 "fail(%d) to re-enable NIC hw error interrupts\n", 12261 ret); 12262 return ret; 12263 } 12264 12265 if (hdev->roce_client) { 12266 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12267 if (ret) { 12268 dev_err(&pdev->dev, 12269 "fail(%d) to re-enable roce ras interrupts\n", 12270 ret); 12271 return ret; 12272 } 12273 } 12274 12275 hclge_reset_vport_state(hdev); 12276 ret = hclge_reset_vport_spoofchk(hdev); 12277 if (ret) 12278 return ret; 12279 12280 ret = hclge_resume_vf_rate(hdev); 12281 if (ret) 12282 return ret; 12283 12284 hclge_init_rxd_adv_layout(hdev); 12285 12286 ret = hclge_update_wol(hdev); 12287 if (ret) 12288 dev_warn(&pdev->dev, 12289 "failed to update wol config, ret = %d\n", ret); 12290 12291 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12292 HCLGE_DRIVER_NAME); 12293 12294 return 0; 12295 } 12296 12297 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12298 { 12299 struct hclge_dev *hdev = ae_dev->priv; 12300 struct hclge_mac *mac = &hdev->hw.mac; 12301 12302 hclge_reset_vf_rate(hdev); 12303 hclge_clear_vf_vlan(hdev); 12304 hclge_state_uninit(hdev); 12305 hclge_ptp_uninit(hdev); 12306 hclge_uninit_rxd_adv_layout(hdev); 12307 hclge_uninit_mac_table(hdev); 12308 hclge_del_all_fd_entries(hdev); 12309 12310 if (mac->phydev) 12311 mdiobus_unregister(mac->mdio_bus); 12312 12313 /* Disable MISC vector(vector0) */ 12314 hclge_enable_vector(&hdev->misc_vector, false); 12315 synchronize_irq(hdev->misc_vector.vector_irq); 12316 12317 /* Disable all hw interrupts */ 12318 hclge_config_mac_tnl_int(hdev, false); 12319 hclge_config_nic_hw_error(hdev, false); 12320 hclge_config_rocee_ras_interrupt(hdev, false); 12321 12322 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12323 hclge_misc_irq_uninit(hdev); 12324 hclge_devlink_uninit(hdev); 12325 hclge_pci_uninit(hdev); 12326 hclge_uninit_vport_vlan_table(hdev); 12327 mutex_destroy(&hdev->vport_lock); 12328 ae_dev->priv = NULL; 12329 } 12330 12331 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12332 { 12333 struct hclge_vport *vport = hclge_get_vport(handle); 12334 struct hclge_dev *hdev = vport->back; 12335 12336 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12337 } 12338 12339 static void hclge_get_channels(struct hnae3_handle *handle, 12340 struct ethtool_channels *ch) 12341 { 12342 ch->max_combined = hclge_get_max_channels(handle); 12343 ch->other_count = 1; 12344 ch->max_other = 1; 12345 ch->combined_count = handle->kinfo.rss_size; 12346 } 12347 12348 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12349 u16 *alloc_tqps, u16 *max_rss_size) 12350 { 12351 struct hclge_vport *vport = hclge_get_vport(handle); 12352 struct hclge_dev *hdev = vport->back; 12353 12354 *alloc_tqps = vport->alloc_tqps; 12355 *max_rss_size = hdev->pf_rss_size_max; 12356 } 12357 12358 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12359 { 12360 struct hclge_vport *vport = hclge_get_vport(handle); 12361 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12362 struct hclge_dev *hdev = vport->back; 12363 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12364 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12365 u16 roundup_size; 12366 unsigned int i; 12367 12368 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12369 roundup_size = ilog2(roundup_size); 12370 /* Set the RSS TC mode according to the new RSS size */ 12371 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12372 tc_valid[i] = 0; 12373 12374 if (!(hdev->hw_tc_map & BIT(i))) 12375 continue; 12376 12377 tc_valid[i] = 1; 12378 tc_size[i] = roundup_size; 12379 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12380 } 12381 12382 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12383 tc_size); 12384 } 12385 12386 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12387 bool rxfh_configured) 12388 { 12389 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12390 struct hclge_vport *vport = hclge_get_vport(handle); 12391 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12392 struct hclge_dev *hdev = vport->back; 12393 u16 cur_rss_size = kinfo->rss_size; 12394 u16 cur_tqps = kinfo->num_tqps; 12395 u32 *rss_indir; 12396 unsigned int i; 12397 int ret; 12398 12399 kinfo->req_rss_size = new_tqps_num; 12400 12401 ret = hclge_tm_vport_map_update(hdev); 12402 if (ret) { 12403 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12404 return ret; 12405 } 12406 12407 ret = hclge_set_rss_tc_mode_cfg(handle); 12408 if (ret) 12409 return ret; 12410 12411 /* RSS indirection table has been configured by user */ 12412 if (rxfh_configured) 12413 goto out; 12414 12415 /* Reinitializes the rss indirect table according to the new RSS size */ 12416 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12417 GFP_KERNEL); 12418 if (!rss_indir) 12419 return -ENOMEM; 12420 12421 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12422 rss_indir[i] = i % kinfo->rss_size; 12423 12424 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12425 if (ret) 12426 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12427 ret); 12428 12429 kfree(rss_indir); 12430 12431 out: 12432 if (!ret) 12433 dev_info(&hdev->pdev->dev, 12434 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12435 cur_rss_size, kinfo->rss_size, 12436 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12437 12438 return ret; 12439 } 12440 12441 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12442 { 12443 struct hclge_set_led_state_cmd *req; 12444 struct hclge_desc desc; 12445 int ret; 12446 12447 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12448 12449 req = (struct hclge_set_led_state_cmd *)desc.data; 12450 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12451 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12452 12453 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12454 if (ret) 12455 dev_err(&hdev->pdev->dev, 12456 "Send set led state cmd error, ret =%d\n", ret); 12457 12458 return ret; 12459 } 12460 12461 enum hclge_led_status { 12462 HCLGE_LED_OFF, 12463 HCLGE_LED_ON, 12464 HCLGE_LED_NO_CHANGE = 0xFF, 12465 }; 12466 12467 static int hclge_set_led_id(struct hnae3_handle *handle, 12468 enum ethtool_phys_id_state status) 12469 { 12470 struct hclge_vport *vport = hclge_get_vport(handle); 12471 struct hclge_dev *hdev = vport->back; 12472 12473 switch (status) { 12474 case ETHTOOL_ID_ACTIVE: 12475 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12476 case ETHTOOL_ID_INACTIVE: 12477 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12478 default: 12479 return -EINVAL; 12480 } 12481 } 12482 12483 static void hclge_get_link_mode(struct hnae3_handle *handle, 12484 unsigned long *supported, 12485 unsigned long *advertising) 12486 { 12487 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12488 struct hclge_vport *vport = hclge_get_vport(handle); 12489 struct hclge_dev *hdev = vport->back; 12490 unsigned int idx = 0; 12491 12492 for (; idx < size; idx++) { 12493 supported[idx] = hdev->hw.mac.supported[idx]; 12494 advertising[idx] = hdev->hw.mac.advertising[idx]; 12495 } 12496 } 12497 12498 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12499 { 12500 struct hclge_vport *vport = hclge_get_vport(handle); 12501 struct hclge_dev *hdev = vport->back; 12502 bool gro_en_old = hdev->gro_en; 12503 int ret; 12504 12505 hdev->gro_en = enable; 12506 ret = hclge_config_gro(hdev); 12507 if (ret) 12508 hdev->gro_en = gro_en_old; 12509 12510 return ret; 12511 } 12512 12513 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12514 { 12515 struct hnae3_handle *handle = &vport->nic; 12516 struct hclge_dev *hdev = vport->back; 12517 bool uc_en = false; 12518 bool mc_en = false; 12519 u8 tmp_flags; 12520 bool bc_en; 12521 int ret; 12522 12523 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12524 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12525 vport->last_promisc_flags = vport->overflow_promisc_flags; 12526 } 12527 12528 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12529 &vport->state)) 12530 return 0; 12531 12532 /* for PF */ 12533 if (!vport->vport_id) { 12534 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12535 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12536 tmp_flags & HNAE3_MPE); 12537 if (!ret) 12538 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12539 &vport->state); 12540 else 12541 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12542 &vport->state); 12543 return ret; 12544 } 12545 12546 /* for VF */ 12547 if (vport->vf_info.trusted) { 12548 uc_en = vport->vf_info.request_uc_en > 0 || 12549 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12550 mc_en = vport->vf_info.request_mc_en > 0 || 12551 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12552 } 12553 bc_en = vport->vf_info.request_bc_en > 0; 12554 12555 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12556 mc_en, bc_en); 12557 if (ret) { 12558 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12559 return ret; 12560 } 12561 hclge_set_vport_vlan_fltr_change(vport); 12562 12563 return 0; 12564 } 12565 12566 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12567 { 12568 struct hclge_vport *vport; 12569 int ret; 12570 u16 i; 12571 12572 for (i = 0; i < hdev->num_alloc_vport; i++) { 12573 vport = &hdev->vport[i]; 12574 12575 ret = hclge_sync_vport_promisc_mode(vport); 12576 if (ret) 12577 return; 12578 } 12579 } 12580 12581 static bool hclge_module_existed(struct hclge_dev *hdev) 12582 { 12583 struct hclge_desc desc; 12584 u32 existed; 12585 int ret; 12586 12587 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12589 if (ret) { 12590 dev_err(&hdev->pdev->dev, 12591 "failed to get SFP exist state, ret = %d\n", ret); 12592 return false; 12593 } 12594 12595 existed = le32_to_cpu(desc.data[0]); 12596 12597 return existed != 0; 12598 } 12599 12600 /* need 6 bds(total 140 bytes) in one reading 12601 * return the number of bytes actually read, 0 means read failed. 12602 */ 12603 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12604 u32 len, u8 *data) 12605 { 12606 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12607 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12608 u16 read_len; 12609 u16 copy_len; 12610 int ret; 12611 int i; 12612 12613 /* setup all 6 bds to read module eeprom info. */ 12614 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12615 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12616 true); 12617 12618 /* bd0~bd4 need next flag */ 12619 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12620 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12621 } 12622 12623 /* setup bd0, this bd contains offset and read length. */ 12624 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12625 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12626 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12627 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12628 12629 ret = hclge_cmd_send(&hdev->hw, desc, i); 12630 if (ret) { 12631 dev_err(&hdev->pdev->dev, 12632 "failed to get SFP eeprom info, ret = %d\n", ret); 12633 return 0; 12634 } 12635 12636 /* copy sfp info from bd0 to out buffer. */ 12637 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12638 memcpy(data, sfp_info_bd0->data, copy_len); 12639 read_len = copy_len; 12640 12641 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12642 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12643 if (read_len >= len) 12644 return read_len; 12645 12646 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12647 memcpy(data + read_len, desc[i].data, copy_len); 12648 read_len += copy_len; 12649 } 12650 12651 return read_len; 12652 } 12653 12654 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12655 u32 len, u8 *data) 12656 { 12657 struct hclge_vport *vport = hclge_get_vport(handle); 12658 struct hclge_dev *hdev = vport->back; 12659 u32 read_len = 0; 12660 u16 data_len; 12661 12662 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12663 return -EOPNOTSUPP; 12664 12665 if (!hclge_module_existed(hdev)) 12666 return -ENXIO; 12667 12668 while (read_len < len) { 12669 data_len = hclge_get_sfp_eeprom_info(hdev, 12670 offset + read_len, 12671 len - read_len, 12672 data + read_len); 12673 if (!data_len) 12674 return -EIO; 12675 12676 read_len += data_len; 12677 } 12678 12679 return 0; 12680 } 12681 12682 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12683 u32 *status_code) 12684 { 12685 struct hclge_vport *vport = hclge_get_vport(handle); 12686 struct hclge_dev *hdev = vport->back; 12687 struct hclge_desc desc; 12688 int ret; 12689 12690 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12691 return -EOPNOTSUPP; 12692 12693 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12694 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12695 if (ret) { 12696 dev_err(&hdev->pdev->dev, 12697 "failed to query link diagnosis info, ret = %d\n", ret); 12698 return ret; 12699 } 12700 12701 *status_code = le32_to_cpu(desc.data[0]); 12702 return 0; 12703 } 12704 12705 /* After disable sriov, VF still has some config and info need clean, 12706 * which configed by PF. 12707 */ 12708 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12709 { 12710 struct hclge_dev *hdev = vport->back; 12711 struct hclge_vlan_info vlan_info; 12712 int ret; 12713 12714 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12715 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12716 vport->need_notify = 0; 12717 vport->mps = 0; 12718 12719 /* after disable sriov, clean VF rate configured by PF */ 12720 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12721 if (ret) 12722 dev_err(&hdev->pdev->dev, 12723 "failed to clean vf%d rate config, ret = %d\n", 12724 vfid, ret); 12725 12726 vlan_info.vlan_tag = 0; 12727 vlan_info.qos = 0; 12728 vlan_info.vlan_proto = ETH_P_8021Q; 12729 ret = hclge_update_port_base_vlan_cfg(vport, 12730 HNAE3_PORT_BASE_VLAN_DISABLE, 12731 &vlan_info); 12732 if (ret) 12733 dev_err(&hdev->pdev->dev, 12734 "failed to clean vf%d port base vlan, ret = %d\n", 12735 vfid, ret); 12736 12737 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12738 if (ret) 12739 dev_err(&hdev->pdev->dev, 12740 "failed to clean vf%d spoof config, ret = %d\n", 12741 vfid, ret); 12742 12743 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12744 } 12745 12746 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12747 { 12748 struct hclge_dev *hdev = ae_dev->priv; 12749 struct hclge_vport *vport; 12750 int i; 12751 12752 for (i = 0; i < num_vfs; i++) { 12753 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12754 12755 hclge_clear_vport_vf_info(vport, i); 12756 } 12757 } 12758 12759 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12760 u8 *priority) 12761 { 12762 struct hclge_vport *vport = hclge_get_vport(h); 12763 12764 if (dscp >= HNAE3_MAX_DSCP) 12765 return -EINVAL; 12766 12767 if (tc_mode) 12768 *tc_mode = vport->nic.kinfo.tc_map_mode; 12769 if (priority) 12770 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12771 vport->nic.kinfo.dscp_prio[dscp]; 12772 12773 return 0; 12774 } 12775 12776 static const struct hnae3_ae_ops hclge_ops = { 12777 .init_ae_dev = hclge_init_ae_dev, 12778 .uninit_ae_dev = hclge_uninit_ae_dev, 12779 .reset_prepare = hclge_reset_prepare_general, 12780 .reset_done = hclge_reset_done, 12781 .init_client_instance = hclge_init_client_instance, 12782 .uninit_client_instance = hclge_uninit_client_instance, 12783 .map_ring_to_vector = hclge_map_ring_to_vector, 12784 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12785 .get_vector = hclge_get_vector, 12786 .put_vector = hclge_put_vector, 12787 .set_promisc_mode = hclge_set_promisc_mode, 12788 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12789 .set_loopback = hclge_set_loopback, 12790 .start = hclge_ae_start, 12791 .stop = hclge_ae_stop, 12792 .client_start = hclge_client_start, 12793 .client_stop = hclge_client_stop, 12794 .get_status = hclge_get_status, 12795 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12796 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12797 .get_media_type = hclge_get_media_type, 12798 .check_port_speed = hclge_check_port_speed, 12799 .get_fec_stats = hclge_get_fec_stats, 12800 .get_fec = hclge_get_fec, 12801 .set_fec = hclge_set_fec, 12802 .get_rss_key_size = hclge_comm_get_rss_key_size, 12803 .get_rss = hclge_get_rss, 12804 .set_rss = hclge_set_rss, 12805 .set_rss_tuple = hclge_set_rss_tuple, 12806 .get_rss_tuple = hclge_get_rss_tuple, 12807 .get_tc_size = hclge_get_tc_size, 12808 .get_mac_addr = hclge_get_mac_addr, 12809 .set_mac_addr = hclge_set_mac_addr, 12810 .do_ioctl = hclge_do_ioctl, 12811 .add_uc_addr = hclge_add_uc_addr, 12812 .rm_uc_addr = hclge_rm_uc_addr, 12813 .add_mc_addr = hclge_add_mc_addr, 12814 .rm_mc_addr = hclge_rm_mc_addr, 12815 .set_autoneg = hclge_set_autoneg, 12816 .get_autoneg = hclge_get_autoneg, 12817 .restart_autoneg = hclge_restart_autoneg, 12818 .halt_autoneg = hclge_halt_autoneg, 12819 .get_pauseparam = hclge_get_pauseparam, 12820 .set_pauseparam = hclge_set_pauseparam, 12821 .set_mtu = hclge_set_mtu, 12822 .reset_queue = hclge_reset_tqp, 12823 .get_stats = hclge_get_stats, 12824 .get_mac_stats = hclge_get_mac_stat, 12825 .update_stats = hclge_update_stats, 12826 .get_strings = hclge_get_strings, 12827 .get_sset_count = hclge_get_sset_count, 12828 .get_fw_version = hclge_get_fw_version, 12829 .get_mdix_mode = hclge_get_mdix_mode, 12830 .enable_vlan_filter = hclge_enable_vlan_filter, 12831 .set_vlan_filter = hclge_set_vlan_filter, 12832 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12833 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12834 .reset_event = hclge_reset_event, 12835 .get_reset_level = hclge_get_reset_level, 12836 .set_default_reset_request = hclge_set_def_reset_request, 12837 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12838 .set_channels = hclge_set_channels, 12839 .get_channels = hclge_get_channels, 12840 .get_regs_len = hclge_get_regs_len, 12841 .get_regs = hclge_get_regs, 12842 .set_led_id = hclge_set_led_id, 12843 .get_link_mode = hclge_get_link_mode, 12844 .add_fd_entry = hclge_add_fd_entry, 12845 .del_fd_entry = hclge_del_fd_entry, 12846 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12847 .get_fd_rule_info = hclge_get_fd_rule_info, 12848 .get_fd_all_rules = hclge_get_all_rules, 12849 .enable_fd = hclge_enable_fd, 12850 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12851 .dbg_read_cmd = hclge_dbg_read_cmd, 12852 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12853 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12854 .ae_dev_resetting = hclge_ae_dev_resetting, 12855 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12856 .set_gro_en = hclge_gro_en, 12857 .get_global_queue_id = hclge_covert_handle_qid_global, 12858 .set_timer_task = hclge_set_timer_task, 12859 .mac_connect_phy = hclge_mac_connect_phy, 12860 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12861 .get_vf_config = hclge_get_vf_config, 12862 .set_vf_link_state = hclge_set_vf_link_state, 12863 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12864 .set_vf_trust = hclge_set_vf_trust, 12865 .set_vf_rate = hclge_set_vf_rate, 12866 .set_vf_mac = hclge_set_vf_mac, 12867 .get_module_eeprom = hclge_get_module_eeprom, 12868 .get_cmdq_stat = hclge_get_cmdq_stat, 12869 .add_cls_flower = hclge_add_cls_flower, 12870 .del_cls_flower = hclge_del_cls_flower, 12871 .cls_flower_active = hclge_is_cls_flower_active, 12872 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12873 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12874 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12875 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12876 .get_ts_info = hclge_ptp_get_ts_info, 12877 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12878 .clean_vf_config = hclge_clean_vport_config, 12879 .get_dscp_prio = hclge_get_dscp_prio, 12880 .get_wol = hclge_get_wol, 12881 .set_wol = hclge_set_wol, 12882 }; 12883 12884 static struct hnae3_ae_algo ae_algo = { 12885 .ops = &hclge_ops, 12886 .pdev_id_table = ae_algo_pci_tbl, 12887 }; 12888 12889 static int __init hclge_init(void) 12890 { 12891 pr_info("%s is initializing\n", HCLGE_NAME); 12892 12893 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12894 if (!hclge_wq) { 12895 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12896 return -ENOMEM; 12897 } 12898 12899 hnae3_register_ae_algo(&ae_algo); 12900 12901 return 0; 12902 } 12903 12904 static void __exit hclge_exit(void) 12905 { 12906 hnae3_unregister_ae_algo_prepare(&ae_algo); 12907 hnae3_unregister_ae_algo(&ae_algo); 12908 destroy_workqueue(hclge_wq); 12909 } 12910 module_init(hclge_init); 12911 module_exit(hclge_exit); 12912 12913 MODULE_LICENSE("GPL"); 12914 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12915 MODULE_DESCRIPTION("HCLGE Driver"); 12916 MODULE_VERSION(HCLGE_MOD_VERSION); 12917