1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2024 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 8 #include <drm/drm_managed.h> 9 #include <drm/drm_print.h> 10 11 #include "regs/xe_bars.h" 12 #include "regs/xe_gt_regs.h" 13 #include "regs/xe_regs.h" 14 #include "xe_assert.h" 15 #include "xe_device.h" 16 #include "xe_force_wake.h" 17 #include "xe_gt_mcr.h" 18 #include "xe_gt_sriov_vf.h" 19 #include "xe_mmio.h" 20 #include "xe_module.h" 21 #include "xe_sriov.h" 22 #include "xe_vram.h" 23 24 #define BAR_SIZE_SHIFT 20 25 26 static void 27 _resize_bar(struct xe_device *xe, int resno, resource_size_t size) 28 { 29 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 30 int bar_size = pci_rebar_bytes_to_size(size); 31 int ret; 32 33 if (pci_resource_len(pdev, resno)) 34 pci_release_resource(pdev, resno); 35 36 ret = pci_resize_resource(pdev, resno, bar_size); 37 if (ret) { 38 drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n", 39 resno, 1 << bar_size, ERR_PTR(ret)); 40 return; 41 } 42 43 drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); 44 } 45 46 /* 47 * if force_vram_bar_size is set, attempt to set to the requested size 48 * else set to maximum possible size 49 */ 50 static void resize_vram_bar(struct xe_device *xe) 51 { 52 u64 force_vram_bar_size = xe_modparam.force_vram_bar_size; 53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 54 struct pci_bus *root = pdev->bus; 55 resource_size_t current_size; 56 resource_size_t rebar_size; 57 struct resource *root_res; 58 u32 bar_size_mask; 59 u32 pci_cmd; 60 int i; 61 62 /* gather some relevant info */ 63 current_size = pci_resource_len(pdev, LMEM_BAR); 64 bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR); 65 66 if (!bar_size_mask) 67 return; 68 69 /* set to a specific size? */ 70 if (force_vram_bar_size) { 71 u32 bar_size_bit; 72 73 rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M; 74 75 bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)); 76 77 if (!bar_size_bit) { 78 drm_info(&xe->drm, 79 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n", 80 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); 81 return; 82 } 83 84 rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); 85 86 if (rebar_size == current_size) 87 return; 88 } else { 89 rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); 90 91 /* only resize if larger than current */ 92 if (rebar_size <= current_size) 93 return; 94 } 95 96 drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n", 97 (u64)current_size >> 20, (u64)rebar_size >> 20); 98 99 while (root->parent) 100 root = root->parent; 101 102 pci_bus_for_each_resource(root, root_res, i) { 103 if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && 104 (u64)root_res->start > 0x100000000ul) 105 break; 106 } 107 108 if (!root_res) { 109 drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n"); 110 return; 111 } 112 113 pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); 114 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); 115 116 _resize_bar(xe, LMEM_BAR, rebar_size); 117 118 pci_assign_unassigned_bus_resources(pdev->bus); 119 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); 120 } 121 122 static bool resource_is_valid(struct pci_dev *pdev, int bar) 123 { 124 if (!pci_resource_flags(pdev, bar)) 125 return false; 126 127 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 128 return false; 129 130 if (!pci_resource_len(pdev, bar)) 131 return false; 132 133 return true; 134 } 135 136 static int determine_lmem_bar_size(struct xe_device *xe) 137 { 138 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 139 140 if (!resource_is_valid(pdev, LMEM_BAR)) { 141 drm_err(&xe->drm, "pci resource is not valid\n"); 142 return -ENXIO; 143 } 144 145 resize_vram_bar(xe); 146 147 xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR); 148 xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR); 149 if (!xe->mem.vram.io_size) 150 return -EIO; 151 152 /* XXX: Need to change when xe link code is ready */ 153 xe->mem.vram.dpa_base = 0; 154 155 /* set up a map to the total memory area. */ 156 xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size); 157 158 return 0; 159 } 160 161 static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) 162 { 163 struct xe_device *xe = gt_to_xe(gt); 164 u64 offset; 165 u32 reg; 166 167 if (GRAPHICS_VER(xe) >= 20) { 168 u64 ccs_size = tile_size / 512; 169 u64 offset_hi, offset_lo; 170 u32 nodes, num_enabled; 171 172 reg = xe_mmio_read32(gt, MIRROR_FUSE3); 173 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 174 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 175 176 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 177 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 178 179 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 180 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 181 182 offset = offset_hi << 32; /* HW view bits 39:32 */ 183 offset |= offset_lo << 6; /* HW view bits 31:6 */ 184 offset *= num_enabled; /* convert to SW view */ 185 offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */ 186 187 /* We don't expect any holes */ 188 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size), 189 "Hole between CCS and GSM.\n"); 190 } else { 191 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 192 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 193 } 194 195 return offset; 196 } 197 198 /* 199 * tile_vram_size() - Collect vram size and offset information 200 * @tile: tile to get info for 201 * @vram_size: available vram (size - device reserved portions) 202 * @tile_size: actual vram size 203 * @tile_offset: physical start point in the vram address space 204 * 205 * There are 4 places for size information: 206 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 207 * - TILEx size (actual vram size) 208 * - GSMBASE offset (TILEx - "stolen") 209 * - CSSBASE offset (TILEx - CSS space necessary) 210 * 211 * CSSBASE is always a lower/smaller offset then GSMBASE. 212 * 213 * The actual available size of memory is to the CCS or GSM base. 214 * NOTE: multi-tile bases will include the tile offset. 215 * 216 */ 217 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 218 u64 *tile_size, u64 *tile_offset) 219 { 220 struct xe_device *xe = tile_to_xe(tile); 221 struct xe_gt *gt = tile->primary_gt; 222 u64 offset; 223 int err; 224 u32 reg; 225 226 if (IS_SRIOV_VF(xe)) { 227 struct xe_tile *t; 228 int id; 229 230 offset = 0; 231 for_each_tile(t, xe, id) 232 for_each_if(t->id < tile->id) 233 offset += xe_gt_sriov_vf_lmem(t->primary_gt); 234 235 *tile_size = xe_gt_sriov_vf_lmem(gt); 236 *vram_size = *tile_size; 237 *tile_offset = offset; 238 239 return 0; 240 } 241 242 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 243 if (err) 244 return err; 245 246 /* actual size */ 247 if (unlikely(xe->info.platform == XE_DG1)) { 248 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 249 *tile_offset = 0; 250 } else { 251 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id)); 252 *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; 253 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 254 } 255 256 /* minus device usage */ 257 if (xe->info.has_flat_ccs) { 258 offset = get_flat_ccs_offset(gt, *tile_size); 259 } else { 260 offset = xe_mmio_read64_2x32(gt, GSMBASE); 261 } 262 263 /* remove the tile offset so we have just the available size */ 264 *vram_size = offset - *tile_offset; 265 266 return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 267 } 268 269 static void vram_fini(void *arg) 270 { 271 struct xe_device *xe = arg; 272 struct xe_tile *tile; 273 int id; 274 275 if (xe->mem.vram.mapping) 276 iounmap(xe->mem.vram.mapping); 277 278 xe->mem.vram.mapping = NULL; 279 280 for_each_tile(tile, xe, id) 281 tile->mem.vram.mapping = NULL; 282 } 283 284 /** 285 * xe_vram_probe() - Probe VRAM configuration 286 * @xe: the &xe_device 287 * 288 * Collect VRAM size and offset information for all tiles. 289 * 290 * Return: 0 on success, error code on failure 291 */ 292 int xe_vram_probe(struct xe_device *xe) 293 { 294 struct xe_tile *tile; 295 resource_size_t io_size; 296 u64 available_size = 0; 297 u64 total_size = 0; 298 u64 tile_offset; 299 u64 tile_size; 300 u64 vram_size; 301 int err; 302 u8 id; 303 304 if (!IS_DGFX(xe)) 305 return 0; 306 307 /* Get the size of the root tile's vram for later accessibility comparison */ 308 tile = xe_device_get_root_tile(xe); 309 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 310 if (err) 311 return err; 312 313 err = determine_lmem_bar_size(xe); 314 if (err) 315 return err; 316 317 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 318 &xe->mem.vram.io_size); 319 320 io_size = xe->mem.vram.io_size; 321 322 /* tile specific ranges */ 323 for_each_tile(tile, xe, id) { 324 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 325 if (err) 326 return err; 327 328 tile->mem.vram.actual_physical_size = tile_size; 329 tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset; 330 tile->mem.vram.io_size = min_t(u64, vram_size, io_size); 331 332 if (!tile->mem.vram.io_size) { 333 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 334 return -ENODEV; 335 } 336 337 tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset; 338 tile->mem.vram.usable_size = vram_size; 339 tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset; 340 341 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) 342 drm_info(&xe->drm, "Small BAR device\n"); 343 drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id, 344 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size); 345 drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id, 346 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size, 347 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size); 348 349 /* calculate total size using tile size to get the correct HW sizing */ 350 total_size += tile_size; 351 available_size += vram_size; 352 353 if (total_size > xe->mem.vram.io_size) { 354 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 355 &total_size, &xe->mem.vram.io_size); 356 } 357 358 io_size -= min_t(u64, tile_size, io_size); 359 } 360 361 xe->mem.vram.actual_physical_size = total_size; 362 363 drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 364 &xe->mem.vram.actual_physical_size); 365 drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 366 &available_size); 367 368 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 369 } 370