1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR111 0x03a1b610 26 #define PHY_ID_AQR111B0 0x03a1b612 27 #define PHY_ID_AQR112 0x03a1b662 28 #define PHY_ID_AQR412 0x03a1b712 29 #define PHY_ID_AQR113 0x31c31c40 30 #define PHY_ID_AQR113C 0x31c31c12 31 #define PHY_ID_AQR114C 0x31c31c22 32 #define PHY_ID_AQR115C 0x31c31c33 33 #define PHY_ID_AQR813 0x31c31cb2 34 35 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 45 46 #define MDIO_AN_VEND_PROV 0xc400 47 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 48 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 49 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 50 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 51 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 52 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 53 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 54 55 #define MDIO_AN_TX_VEND_STATUS1 0xc800 56 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 57 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 58 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 59 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 60 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 61 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 62 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 63 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 64 65 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 66 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 67 68 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 69 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 70 71 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 72 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 73 74 #define MDIO_AN_RX_LP_STAT1 0xe820 75 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 76 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 77 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 78 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 79 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 80 81 #define MDIO_AN_RX_LP_STAT4 0xe823 82 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 83 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 84 85 #define MDIO_AN_RX_VEND_STAT3 0xe832 86 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 87 88 /* Sleep and timeout for checking if the Processor-Intensive 89 * MDIO operation is finished 90 */ 91 #define AQR107_OP_IN_PROG_SLEEP 1000 92 #define AQR107_OP_IN_PROG_TIMEOUT 100000 93 94 static int aqr107_get_sset_count(struct phy_device *phydev) 95 { 96 return AQR107_SGMII_STAT_SZ; 97 } 98 99 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 100 { 101 int i; 102 103 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 104 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 105 ETH_GSTRING_LEN); 106 } 107 108 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 109 { 110 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 111 int len_l = min(stat->size, 16); 112 int len_h = stat->size - len_l; 113 u64 ret; 114 int val; 115 116 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 117 if (val < 0) 118 return U64_MAX; 119 120 ret = val & GENMASK(len_l - 1, 0); 121 if (len_h) { 122 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 123 if (val < 0) 124 return U64_MAX; 125 126 ret += (val & GENMASK(len_h - 1, 0)) << 16; 127 } 128 129 return ret; 130 } 131 132 static void aqr107_get_stats(struct phy_device *phydev, 133 struct ethtool_stats *stats, u64 *data) 134 { 135 struct aqr107_priv *priv = phydev->priv; 136 u64 val; 137 int i; 138 139 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 140 val = aqr107_get_stat(phydev, i); 141 if (val == U64_MAX) 142 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 143 aqr107_hw_stats[i].name); 144 else 145 priv->sgmii_stats[i] += val; 146 147 data[i] = priv->sgmii_stats[i]; 148 } 149 } 150 151 static int aqr_config_aneg(struct phy_device *phydev) 152 { 153 bool changed = false; 154 u16 reg; 155 int ret; 156 157 if (phydev->autoneg == AUTONEG_DISABLE) 158 return genphy_c45_pma_setup_forced(phydev); 159 160 ret = genphy_c45_an_config_aneg(phydev); 161 if (ret < 0) 162 return ret; 163 if (ret > 0) 164 changed = true; 165 166 /* Clause 45 has no standardized support for 1000BaseT, therefore 167 * use vendor registers for this mode. 168 */ 169 reg = 0; 170 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 171 phydev->advertising)) 172 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 173 174 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 175 phydev->advertising)) 176 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 177 178 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 179 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 180 phydev->advertising)) 181 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 182 183 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 184 phydev->advertising)) 185 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 186 187 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 188 MDIO_AN_VEND_PROV_1000BASET_HALF | 189 MDIO_AN_VEND_PROV_1000BASET_FULL | 190 MDIO_AN_VEND_PROV_2500BASET_FULL | 191 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 192 if (ret < 0) 193 return ret; 194 if (ret > 0) 195 changed = true; 196 197 return genphy_c45_check_and_restart_aneg(phydev, changed); 198 } 199 200 static int aqr_config_intr(struct phy_device *phydev) 201 { 202 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 203 int err; 204 205 if (en) { 206 /* Clear any pending interrupts before enabling them */ 207 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 208 if (err < 0) 209 return err; 210 } 211 212 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 213 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 214 if (err < 0) 215 return err; 216 217 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 218 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 219 if (err < 0) 220 return err; 221 222 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 223 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 224 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 225 if (err < 0) 226 return err; 227 228 if (!en) { 229 /* Clear any pending interrupts after we have disabled them */ 230 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 231 if (err < 0) 232 return err; 233 } 234 235 return 0; 236 } 237 238 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 239 { 240 int irq_status; 241 242 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 243 MDIO_AN_TX_VEND_INT_STATUS2); 244 if (irq_status < 0) { 245 phy_error(phydev); 246 return IRQ_NONE; 247 } 248 249 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 250 return IRQ_NONE; 251 252 phy_trigger_machine(phydev); 253 254 return IRQ_HANDLED; 255 } 256 257 static int aqr_read_status(struct phy_device *phydev) 258 { 259 int val; 260 261 if (phydev->autoneg == AUTONEG_ENABLE) { 262 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 263 if (val < 0) 264 return val; 265 266 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 267 phydev->lp_advertising, 268 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 269 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 270 phydev->lp_advertising, 271 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 272 } 273 274 return genphy_c45_read_status(phydev); 275 } 276 277 static int aqr107_read_rate(struct phy_device *phydev) 278 { 279 u32 config_reg; 280 int val; 281 282 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 283 if (val < 0) 284 return val; 285 286 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 287 phydev->duplex = DUPLEX_FULL; 288 else 289 phydev->duplex = DUPLEX_HALF; 290 291 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 292 case MDIO_AN_TX_VEND_STATUS1_10BASET: 293 phydev->speed = SPEED_10; 294 config_reg = VEND1_GLOBAL_CFG_10M; 295 break; 296 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 297 phydev->speed = SPEED_100; 298 config_reg = VEND1_GLOBAL_CFG_100M; 299 break; 300 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 301 phydev->speed = SPEED_1000; 302 config_reg = VEND1_GLOBAL_CFG_1G; 303 break; 304 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 305 phydev->speed = SPEED_2500; 306 config_reg = VEND1_GLOBAL_CFG_2_5G; 307 break; 308 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 309 phydev->speed = SPEED_5000; 310 config_reg = VEND1_GLOBAL_CFG_5G; 311 break; 312 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 313 phydev->speed = SPEED_10000; 314 config_reg = VEND1_GLOBAL_CFG_10G; 315 break; 316 default: 317 phydev->speed = SPEED_UNKNOWN; 318 return 0; 319 } 320 321 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 322 if (val < 0) 323 return val; 324 325 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 326 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 327 phydev->rate_matching = RATE_MATCH_PAUSE; 328 else 329 phydev->rate_matching = RATE_MATCH_NONE; 330 331 return 0; 332 } 333 334 static int aqr107_read_status(struct phy_device *phydev) 335 { 336 int val, ret; 337 338 ret = aqr_read_status(phydev); 339 if (ret) 340 return ret; 341 342 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 343 return 0; 344 345 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 346 if (val < 0) 347 return val; 348 349 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 350 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 351 phydev->interface = PHY_INTERFACE_MODE_10GKR; 352 break; 353 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 354 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 355 break; 356 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 357 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 358 break; 359 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 360 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 361 break; 362 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 363 phydev->interface = PHY_INTERFACE_MODE_XAUI; 364 break; 365 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 366 phydev->interface = PHY_INTERFACE_MODE_SGMII; 367 break; 368 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 369 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 370 break; 371 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 372 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 373 break; 374 default: 375 phydev->interface = PHY_INTERFACE_MODE_NA; 376 break; 377 } 378 379 /* Read possibly downshifted rate from vendor register */ 380 return aqr107_read_rate(phydev); 381 } 382 383 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 384 { 385 int val, cnt, enable; 386 387 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 388 if (val < 0) 389 return val; 390 391 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 392 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 393 394 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 395 396 return 0; 397 } 398 399 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 400 { 401 int val = 0; 402 403 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 404 return -E2BIG; 405 406 if (cnt != DOWNSHIFT_DEV_DISABLE) { 407 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 408 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 409 } 410 411 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 412 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 413 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 414 } 415 416 static int aqr107_get_tunable(struct phy_device *phydev, 417 struct ethtool_tunable *tuna, void *data) 418 { 419 switch (tuna->id) { 420 case ETHTOOL_PHY_DOWNSHIFT: 421 return aqr107_get_downshift(phydev, data); 422 default: 423 return -EOPNOTSUPP; 424 } 425 } 426 427 static int aqr107_set_tunable(struct phy_device *phydev, 428 struct ethtool_tunable *tuna, const void *data) 429 { 430 switch (tuna->id) { 431 case ETHTOOL_PHY_DOWNSHIFT: 432 return aqr107_set_downshift(phydev, *(const u8 *)data); 433 default: 434 return -EOPNOTSUPP; 435 } 436 } 437 438 /* If we configure settings whilst firmware is still initializing the chip, 439 * then these settings may be overwritten. Therefore make sure chip 440 * initialization has completed. Use presence of the firmware ID as 441 * indicator for initialization having completed. 442 * The chip also provides a "reset completed" bit, but it's cleared after 443 * read. Therefore function would time out if called again. 444 */ 445 int aqr_wait_reset_complete(struct phy_device *phydev) 446 { 447 int val; 448 449 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 450 VEND1_GLOBAL_FW_ID, val, val != 0, 451 20000, 2000000, false); 452 } 453 454 static void aqr107_chip_info(struct phy_device *phydev) 455 { 456 u8 fw_major, fw_minor, build_id, prov_id; 457 int val; 458 459 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 460 if (val < 0) 461 return; 462 463 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 464 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 465 466 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 467 if (val < 0) 468 return; 469 470 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 471 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 472 473 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 474 fw_major, fw_minor, build_id, prov_id); 475 } 476 477 static int aqr107_config_init(struct phy_device *phydev) 478 { 479 struct aqr107_priv *priv = phydev->priv; 480 u32 led_active_low; 481 int ret, index = 0; 482 483 /* Check that the PHY interface type is compatible */ 484 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 485 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 486 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 487 phydev->interface != PHY_INTERFACE_MODE_XGMII && 488 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 489 phydev->interface != PHY_INTERFACE_MODE_10GKR && 490 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 491 phydev->interface != PHY_INTERFACE_MODE_XAUI && 492 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 493 return -ENODEV; 494 495 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 496 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 497 498 ret = aqr_wait_reset_complete(phydev); 499 if (!ret) 500 aqr107_chip_info(phydev); 501 502 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 503 if (ret) 504 return ret; 505 506 /* Restore LED polarity state after reset */ 507 for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { 508 ret = aqr_phy_led_active_low_set(phydev, index, led_active_low); 509 if (ret) 510 return ret; 511 index++; 512 } 513 514 return 0; 515 } 516 517 static int aqcs109_config_init(struct phy_device *phydev) 518 { 519 int ret; 520 521 /* Check that the PHY interface type is compatible */ 522 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 523 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 524 return -ENODEV; 525 526 ret = aqr_wait_reset_complete(phydev); 527 if (!ret) 528 aqr107_chip_info(phydev); 529 530 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 531 * PMA speed ability bits are the same for all members of the family, 532 * AQCS109 however supports speeds up to 2.5G only. 533 */ 534 phy_set_max_speed(phydev, SPEED_2500); 535 536 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 537 } 538 539 static void aqr107_link_change_notify(struct phy_device *phydev) 540 { 541 u8 fw_major, fw_minor; 542 bool downshift, short_reach, afr; 543 int mode, val; 544 545 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 546 return; 547 548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 549 /* call failed or link partner is no Aquantia PHY */ 550 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 551 return; 552 553 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 554 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 555 556 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 557 if (val < 0) 558 return; 559 560 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 561 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 562 563 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 564 if (val < 0) 565 return; 566 567 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 568 569 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 570 fw_major, fw_minor, 571 short_reach ? ", short reach mode" : "", 572 downshift ? ", fast-retrain downshift advertised" : "", 573 afr ? ", fast reframe advertised" : ""); 574 575 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 576 if (val < 0) 577 return; 578 579 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 580 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 581 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 582 } 583 584 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 585 { 586 int val, err; 587 588 /* The datasheet notes to wait at least 1ms after issuing a 589 * processor intensive operation before checking. 590 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 591 * because that just determines the maximum time slept, not the minimum. 592 */ 593 usleep_range(1000, 5000); 594 595 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 596 VEND1_GLOBAL_GEN_STAT2, val, 597 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 598 AQR107_OP_IN_PROG_SLEEP, 599 AQR107_OP_IN_PROG_TIMEOUT, false); 600 if (err) { 601 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 602 return err; 603 } 604 605 return 0; 606 } 607 608 static int aqr107_get_rate_matching(struct phy_device *phydev, 609 phy_interface_t iface) 610 { 611 if (iface == PHY_INTERFACE_MODE_10GBASER || 612 iface == PHY_INTERFACE_MODE_2500BASEX || 613 iface == PHY_INTERFACE_MODE_NA) 614 return RATE_MATCH_PAUSE; 615 return RATE_MATCH_NONE; 616 } 617 618 static int aqr107_suspend(struct phy_device *phydev) 619 { 620 int err; 621 622 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 623 MDIO_CTRL1_LPOWER); 624 if (err) 625 return err; 626 627 return aqr107_wait_processor_intensive_op(phydev); 628 } 629 630 static int aqr107_resume(struct phy_device *phydev) 631 { 632 int err; 633 634 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 635 MDIO_CTRL1_LPOWER); 636 if (err) 637 return err; 638 639 return aqr107_wait_processor_intensive_op(phydev); 640 } 641 642 static const u16 aqr_global_cfg_regs[] = { 643 VEND1_GLOBAL_CFG_10M, 644 VEND1_GLOBAL_CFG_100M, 645 VEND1_GLOBAL_CFG_1G, 646 VEND1_GLOBAL_CFG_2_5G, 647 VEND1_GLOBAL_CFG_5G, 648 VEND1_GLOBAL_CFG_10G 649 }; 650 651 static int aqr107_fill_interface_modes(struct phy_device *phydev) 652 { 653 unsigned long *possible = phydev->possible_interfaces; 654 unsigned int serdes_mode, rate_adapt; 655 phy_interface_t interface; 656 int i, val; 657 658 /* Walk the media-speed configuration registers to determine which 659 * host-side serdes modes may be used by the PHY depending on the 660 * negotiated media speed. 661 */ 662 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 663 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 664 aqr_global_cfg_regs[i]); 665 if (val < 0) 666 return val; 667 668 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 669 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 670 671 switch (serdes_mode) { 672 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 673 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 674 interface = PHY_INTERFACE_MODE_USXGMII; 675 else 676 interface = PHY_INTERFACE_MODE_10GBASER; 677 break; 678 679 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 680 interface = PHY_INTERFACE_MODE_5GBASER; 681 break; 682 683 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 684 interface = PHY_INTERFACE_MODE_2500BASEX; 685 break; 686 687 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 688 interface = PHY_INTERFACE_MODE_SGMII; 689 break; 690 691 default: 692 phydev_warn(phydev, "unrecognised serdes mode %u\n", 693 serdes_mode); 694 interface = PHY_INTERFACE_MODE_NA; 695 break; 696 } 697 698 if (interface != PHY_INTERFACE_MODE_NA) 699 __set_bit(interface, possible); 700 } 701 702 return 0; 703 } 704 705 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 706 { 707 int val, ret; 708 709 /* It's been observed on some models that - when coming out of suspend 710 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 711 * continue on returning zeroes for some time. Let's poll the 100M 712 * register until it returns a real value as both 113c and 115c support 713 * this mode. 714 */ 715 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 716 VEND1_GLOBAL_CFG_100M, val, val != 0, 717 1000, 100000, false); 718 if (ret) 719 return ret; 720 721 return aqr107_fill_interface_modes(phydev); 722 } 723 724 static int aqr113c_config_init(struct phy_device *phydev) 725 { 726 int ret; 727 728 ret = aqr107_config_init(phydev); 729 if (ret < 0) 730 return ret; 731 732 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 733 MDIO_PMD_TXDIS_GLOBAL); 734 if (ret) 735 return ret; 736 737 ret = aqr107_wait_processor_intensive_op(phydev); 738 if (ret) 739 return ret; 740 741 return aqr113c_fill_interface_modes(phydev); 742 } 743 744 static int aqr107_probe(struct phy_device *phydev) 745 { 746 int ret; 747 748 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 749 sizeof(struct aqr107_priv), GFP_KERNEL); 750 if (!phydev->priv) 751 return -ENOMEM; 752 753 ret = aqr_firmware_load(phydev); 754 if (ret) 755 return ret; 756 757 return aqr_hwmon_probe(phydev); 758 } 759 760 static int aqr111_config_init(struct phy_device *phydev) 761 { 762 /* AQR111 reports supporting speed up to 10G, 763 * however only speeds up to 5G are supported. 764 */ 765 phy_set_max_speed(phydev, SPEED_5000); 766 767 return aqr107_config_init(phydev); 768 } 769 770 static struct phy_driver aqr_driver[] = { 771 { 772 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 773 .name = "Aquantia AQ1202", 774 .config_aneg = aqr_config_aneg, 775 .config_intr = aqr_config_intr, 776 .handle_interrupt = aqr_handle_interrupt, 777 .read_status = aqr_read_status, 778 }, 779 { 780 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 781 .name = "Aquantia AQ2104", 782 .config_aneg = aqr_config_aneg, 783 .config_intr = aqr_config_intr, 784 .handle_interrupt = aqr_handle_interrupt, 785 .read_status = aqr_read_status, 786 }, 787 { 788 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 789 .name = "Aquantia AQR105", 790 .config_aneg = aqr_config_aneg, 791 .config_intr = aqr_config_intr, 792 .handle_interrupt = aqr_handle_interrupt, 793 .read_status = aqr_read_status, 794 .suspend = aqr107_suspend, 795 .resume = aqr107_resume, 796 }, 797 { 798 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 799 .name = "Aquantia AQR106", 800 .config_aneg = aqr_config_aneg, 801 .config_intr = aqr_config_intr, 802 .handle_interrupt = aqr_handle_interrupt, 803 .read_status = aqr_read_status, 804 }, 805 { 806 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 807 .name = "Aquantia AQR107", 808 .probe = aqr107_probe, 809 .get_rate_matching = aqr107_get_rate_matching, 810 .config_init = aqr107_config_init, 811 .config_aneg = aqr_config_aneg, 812 .config_intr = aqr_config_intr, 813 .handle_interrupt = aqr_handle_interrupt, 814 .read_status = aqr107_read_status, 815 .get_tunable = aqr107_get_tunable, 816 .set_tunable = aqr107_set_tunable, 817 .suspend = aqr107_suspend, 818 .resume = aqr107_resume, 819 .get_sset_count = aqr107_get_sset_count, 820 .get_strings = aqr107_get_strings, 821 .get_stats = aqr107_get_stats, 822 .link_change_notify = aqr107_link_change_notify, 823 .led_brightness_set = aqr_phy_led_brightness_set, 824 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 825 .led_hw_control_set = aqr_phy_led_hw_control_set, 826 .led_hw_control_get = aqr_phy_led_hw_control_get, 827 .led_polarity_set = aqr_phy_led_polarity_set, 828 }, 829 { 830 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 831 .name = "Aquantia AQCS109", 832 .probe = aqr107_probe, 833 .get_rate_matching = aqr107_get_rate_matching, 834 .config_init = aqcs109_config_init, 835 .config_aneg = aqr_config_aneg, 836 .config_intr = aqr_config_intr, 837 .handle_interrupt = aqr_handle_interrupt, 838 .read_status = aqr107_read_status, 839 .get_tunable = aqr107_get_tunable, 840 .set_tunable = aqr107_set_tunable, 841 .suspend = aqr107_suspend, 842 .resume = aqr107_resume, 843 .get_sset_count = aqr107_get_sset_count, 844 .get_strings = aqr107_get_strings, 845 .get_stats = aqr107_get_stats, 846 .link_change_notify = aqr107_link_change_notify, 847 .led_brightness_set = aqr_phy_led_brightness_set, 848 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 849 .led_hw_control_set = aqr_phy_led_hw_control_set, 850 .led_hw_control_get = aqr_phy_led_hw_control_get, 851 .led_polarity_set = aqr_phy_led_polarity_set, 852 }, 853 { 854 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 855 .name = "Aquantia AQR111", 856 .probe = aqr107_probe, 857 .get_rate_matching = aqr107_get_rate_matching, 858 .config_init = aqr111_config_init, 859 .config_aneg = aqr_config_aneg, 860 .config_intr = aqr_config_intr, 861 .handle_interrupt = aqr_handle_interrupt, 862 .read_status = aqr107_read_status, 863 .get_tunable = aqr107_get_tunable, 864 .set_tunable = aqr107_set_tunable, 865 .suspend = aqr107_suspend, 866 .resume = aqr107_resume, 867 .get_sset_count = aqr107_get_sset_count, 868 .get_strings = aqr107_get_strings, 869 .get_stats = aqr107_get_stats, 870 .link_change_notify = aqr107_link_change_notify, 871 .led_brightness_set = aqr_phy_led_brightness_set, 872 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 873 .led_hw_control_set = aqr_phy_led_hw_control_set, 874 .led_hw_control_get = aqr_phy_led_hw_control_get, 875 .led_polarity_set = aqr_phy_led_polarity_set, 876 }, 877 { 878 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 879 .name = "Aquantia AQR111B0", 880 .probe = aqr107_probe, 881 .get_rate_matching = aqr107_get_rate_matching, 882 .config_init = aqr111_config_init, 883 .config_aneg = aqr_config_aneg, 884 .config_intr = aqr_config_intr, 885 .handle_interrupt = aqr_handle_interrupt, 886 .read_status = aqr107_read_status, 887 .get_tunable = aqr107_get_tunable, 888 .set_tunable = aqr107_set_tunable, 889 .suspend = aqr107_suspend, 890 .resume = aqr107_resume, 891 .get_sset_count = aqr107_get_sset_count, 892 .get_strings = aqr107_get_strings, 893 .get_stats = aqr107_get_stats, 894 .link_change_notify = aqr107_link_change_notify, 895 .led_brightness_set = aqr_phy_led_brightness_set, 896 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 897 .led_hw_control_set = aqr_phy_led_hw_control_set, 898 .led_hw_control_get = aqr_phy_led_hw_control_get, 899 .led_polarity_set = aqr_phy_led_polarity_set, 900 }, 901 { 902 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 903 .name = "Aquantia AQR405", 904 .config_aneg = aqr_config_aneg, 905 .config_intr = aqr_config_intr, 906 .handle_interrupt = aqr_handle_interrupt, 907 .read_status = aqr_read_status, 908 }, 909 { 910 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 911 .name = "Aquantia AQR112", 912 .probe = aqr107_probe, 913 .config_aneg = aqr_config_aneg, 914 .config_intr = aqr_config_intr, 915 .handle_interrupt = aqr_handle_interrupt, 916 .get_tunable = aqr107_get_tunable, 917 .set_tunable = aqr107_set_tunable, 918 .suspend = aqr107_suspend, 919 .resume = aqr107_resume, 920 .read_status = aqr107_read_status, 921 .get_rate_matching = aqr107_get_rate_matching, 922 .get_sset_count = aqr107_get_sset_count, 923 .get_strings = aqr107_get_strings, 924 .get_stats = aqr107_get_stats, 925 .link_change_notify = aqr107_link_change_notify, 926 .led_brightness_set = aqr_phy_led_brightness_set, 927 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 928 .led_hw_control_set = aqr_phy_led_hw_control_set, 929 .led_hw_control_get = aqr_phy_led_hw_control_get, 930 .led_polarity_set = aqr_phy_led_polarity_set, 931 }, 932 { 933 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 934 .name = "Aquantia AQR412", 935 .probe = aqr107_probe, 936 .config_aneg = aqr_config_aneg, 937 .config_intr = aqr_config_intr, 938 .handle_interrupt = aqr_handle_interrupt, 939 .get_tunable = aqr107_get_tunable, 940 .set_tunable = aqr107_set_tunable, 941 .suspend = aqr107_suspend, 942 .resume = aqr107_resume, 943 .read_status = aqr107_read_status, 944 .get_rate_matching = aqr107_get_rate_matching, 945 .get_sset_count = aqr107_get_sset_count, 946 .get_strings = aqr107_get_strings, 947 .get_stats = aqr107_get_stats, 948 .link_change_notify = aqr107_link_change_notify, 949 }, 950 { 951 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 952 .name = "Aquantia AQR113", 953 .probe = aqr107_probe, 954 .get_rate_matching = aqr107_get_rate_matching, 955 .config_init = aqr113c_config_init, 956 .config_aneg = aqr_config_aneg, 957 .config_intr = aqr_config_intr, 958 .handle_interrupt = aqr_handle_interrupt, 959 .read_status = aqr107_read_status, 960 .get_tunable = aqr107_get_tunable, 961 .set_tunable = aqr107_set_tunable, 962 .suspend = aqr107_suspend, 963 .resume = aqr107_resume, 964 .get_sset_count = aqr107_get_sset_count, 965 .get_strings = aqr107_get_strings, 966 .get_stats = aqr107_get_stats, 967 .link_change_notify = aqr107_link_change_notify, 968 .led_brightness_set = aqr_phy_led_brightness_set, 969 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 970 .led_hw_control_set = aqr_phy_led_hw_control_set, 971 .led_hw_control_get = aqr_phy_led_hw_control_get, 972 .led_polarity_set = aqr_phy_led_polarity_set, 973 }, 974 { 975 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 976 .name = "Aquantia AQR113C", 977 .probe = aqr107_probe, 978 .get_rate_matching = aqr107_get_rate_matching, 979 .config_init = aqr113c_config_init, 980 .config_aneg = aqr_config_aneg, 981 .config_intr = aqr_config_intr, 982 .handle_interrupt = aqr_handle_interrupt, 983 .read_status = aqr107_read_status, 984 .get_tunable = aqr107_get_tunable, 985 .set_tunable = aqr107_set_tunable, 986 .suspend = aqr107_suspend, 987 .resume = aqr107_resume, 988 .get_sset_count = aqr107_get_sset_count, 989 .get_strings = aqr107_get_strings, 990 .get_stats = aqr107_get_stats, 991 .link_change_notify = aqr107_link_change_notify, 992 .led_brightness_set = aqr_phy_led_brightness_set, 993 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 994 .led_hw_control_set = aqr_phy_led_hw_control_set, 995 .led_hw_control_get = aqr_phy_led_hw_control_get, 996 .led_polarity_set = aqr_phy_led_polarity_set, 997 }, 998 { 999 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1000 .name = "Aquantia AQR114C", 1001 .probe = aqr107_probe, 1002 .get_rate_matching = aqr107_get_rate_matching, 1003 .config_init = aqr111_config_init, 1004 .config_aneg = aqr_config_aneg, 1005 .config_intr = aqr_config_intr, 1006 .handle_interrupt = aqr_handle_interrupt, 1007 .read_status = aqr107_read_status, 1008 .get_tunable = aqr107_get_tunable, 1009 .set_tunable = aqr107_set_tunable, 1010 .suspend = aqr107_suspend, 1011 .resume = aqr107_resume, 1012 .get_sset_count = aqr107_get_sset_count, 1013 .get_strings = aqr107_get_strings, 1014 .get_stats = aqr107_get_stats, 1015 .link_change_notify = aqr107_link_change_notify, 1016 .led_brightness_set = aqr_phy_led_brightness_set, 1017 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1018 .led_hw_control_set = aqr_phy_led_hw_control_set, 1019 .led_hw_control_get = aqr_phy_led_hw_control_get, 1020 .led_polarity_set = aqr_phy_led_polarity_set, 1021 }, 1022 { 1023 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1024 .name = "Aquantia AQR115C", 1025 .probe = aqr107_probe, 1026 .get_rate_matching = aqr107_get_rate_matching, 1027 .config_init = aqr113c_config_init, 1028 .config_aneg = aqr_config_aneg, 1029 .config_intr = aqr_config_intr, 1030 .handle_interrupt = aqr_handle_interrupt, 1031 .read_status = aqr107_read_status, 1032 .get_tunable = aqr107_get_tunable, 1033 .set_tunable = aqr107_set_tunable, 1034 .suspend = aqr107_suspend, 1035 .resume = aqr107_resume, 1036 .get_sset_count = aqr107_get_sset_count, 1037 .get_strings = aqr107_get_strings, 1038 .get_stats = aqr107_get_stats, 1039 .link_change_notify = aqr107_link_change_notify, 1040 .led_brightness_set = aqr_phy_led_brightness_set, 1041 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1042 .led_hw_control_set = aqr_phy_led_hw_control_set, 1043 .led_hw_control_get = aqr_phy_led_hw_control_get, 1044 .led_polarity_set = aqr_phy_led_polarity_set, 1045 }, 1046 { 1047 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1048 .name = "Aquantia AQR813", 1049 .probe = aqr107_probe, 1050 .get_rate_matching = aqr107_get_rate_matching, 1051 .config_init = aqr107_config_init, 1052 .config_aneg = aqr_config_aneg, 1053 .config_intr = aqr_config_intr, 1054 .handle_interrupt = aqr_handle_interrupt, 1055 .read_status = aqr107_read_status, 1056 .get_tunable = aqr107_get_tunable, 1057 .set_tunable = aqr107_set_tunable, 1058 .suspend = aqr107_suspend, 1059 .resume = aqr107_resume, 1060 .get_sset_count = aqr107_get_sset_count, 1061 .get_strings = aqr107_get_strings, 1062 .get_stats = aqr107_get_stats, 1063 .link_change_notify = aqr107_link_change_notify, 1064 .led_brightness_set = aqr_phy_led_brightness_set, 1065 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1066 .led_hw_control_set = aqr_phy_led_hw_control_set, 1067 .led_hw_control_get = aqr_phy_led_hw_control_get, 1068 .led_polarity_set = aqr_phy_led_polarity_set, 1069 }, 1070 }; 1071 1072 module_phy_driver(aqr_driver); 1073 1074 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1075 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1076 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1077 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1078 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1079 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1080 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1081 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1082 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1083 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1084 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1085 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1086 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1087 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1088 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1089 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1090 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1091 { } 1092 }; 1093 1094 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1095 1096 MODULE_DESCRIPTION("Aquantia PHY driver"); 1097 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1098 MODULE_LICENSE("GPL v2"); 1099