1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_cs.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(void *handle, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 /** 63 * jpeg_v4_0_3_early_init - set function pointers 64 * 65 * @handle: amdgpu_device pointer 66 * 67 * Set ring and irq function pointers 68 */ 69 static int jpeg_v4_0_3_early_init(void *handle) 70 { 71 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 72 73 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 74 75 jpeg_v4_0_3_set_dec_ring_funcs(adev); 76 jpeg_v4_0_3_set_irq_funcs(adev); 77 jpeg_v4_0_3_set_ras_funcs(adev); 78 79 return 0; 80 } 81 82 /** 83 * jpeg_v4_0_3_sw_init - sw init for JPEG block 84 * 85 * @handle: amdgpu_device pointer 86 * 87 * Load firmware and sw initialization 88 */ 89 static int jpeg_v4_0_3_sw_init(void *handle) 90 { 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 struct amdgpu_ring *ring; 93 int i, j, r, jpeg_inst; 94 95 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 96 /* JPEG TRAP */ 97 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 98 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 99 if (r) 100 return r; 101 } 102 103 r = amdgpu_jpeg_sw_init(adev); 104 if (r) 105 return r; 106 107 r = amdgpu_jpeg_resume(adev); 108 if (r) 109 return r; 110 111 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 112 jpeg_inst = GET_INST(JPEG, i); 113 114 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 115 ring = &adev->jpeg.inst[i].ring_dec[j]; 116 ring->use_doorbell = true; 117 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 118 if (!amdgpu_sriov_vf(adev)) { 119 ring->doorbell_index = 120 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 121 1 + j + 9 * jpeg_inst; 122 } else { 123 if (j < 4) 124 ring->doorbell_index = 125 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 126 4 + j + 32 * jpeg_inst; 127 else 128 ring->doorbell_index = 129 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 130 8 + j + 32 * jpeg_inst; 131 } 132 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 133 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 134 AMDGPU_RING_PRIO_DEFAULT, NULL); 135 if (r) 136 return r; 137 138 adev->jpeg.internal.jpeg_pitch[j] = 139 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 140 adev->jpeg.inst[i].external.jpeg_pitch[j] = 141 SOC15_REG_OFFSET1( 142 JPEG, jpeg_inst, 143 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 144 (j ? (0x40 * j - 0xc80) : 0)); 145 } 146 } 147 148 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 149 r = amdgpu_jpeg_ras_sw_init(adev); 150 if (r) { 151 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 152 return r; 153 } 154 } 155 156 return 0; 157 } 158 159 /** 160 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 161 * 162 * @handle: amdgpu_device pointer 163 * 164 * JPEG suspend and free up sw allocation 165 */ 166 static int jpeg_v4_0_3_sw_fini(void *handle) 167 { 168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 169 int r; 170 171 r = amdgpu_jpeg_suspend(adev); 172 if (r) 173 return r; 174 175 r = amdgpu_jpeg_sw_fini(adev); 176 177 return r; 178 } 179 180 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 181 { 182 struct amdgpu_ring *ring; 183 uint64_t ctx_addr; 184 uint32_t param, resp, expected; 185 uint32_t tmp, timeout; 186 187 struct amdgpu_mm_table *table = &adev->virt.mm_table; 188 uint32_t *table_loc; 189 uint32_t table_size; 190 uint32_t size, size_dw, item_offset; 191 uint32_t init_status; 192 int i, j, jpeg_inst; 193 194 struct mmsch_v4_0_cmd_direct_write 195 direct_wt = { {0} }; 196 struct mmsch_v4_0_cmd_end end = { {0} }; 197 struct mmsch_v4_0_3_init_header header; 198 199 direct_wt.cmd_header.command_type = 200 MMSCH_COMMAND__DIRECT_REG_WRITE; 201 end.cmd_header.command_type = 202 MMSCH_COMMAND__END; 203 204 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 205 jpeg_inst = GET_INST(JPEG, i); 206 207 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 208 header.version = MMSCH_VERSION; 209 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 210 211 table_loc = (uint32_t *)table->cpu_addr; 212 table_loc += header.total_size; 213 214 item_offset = header.total_size; 215 216 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 217 ring = &adev->jpeg.inst[i].ring_dec[j]; 218 table_size = 0; 219 220 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 221 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 222 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 223 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 224 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 225 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 226 227 if (j <= 3) { 228 header.mjpegdec0[j].table_offset = item_offset; 229 header.mjpegdec0[j].init_status = 0; 230 header.mjpegdec0[j].table_size = table_size; 231 } else { 232 header.mjpegdec1[j - 4].table_offset = item_offset; 233 header.mjpegdec1[j - 4].init_status = 0; 234 header.mjpegdec1[j - 4].table_size = table_size; 235 } 236 header.total_size += table_size; 237 item_offset += table_size; 238 } 239 240 MMSCH_V4_0_INSERT_END(); 241 242 /* send init table to MMSCH */ 243 size = sizeof(struct mmsch_v4_0_3_init_header); 244 table_loc = (uint32_t *)table->cpu_addr; 245 memcpy((void *)table_loc, &header, size); 246 247 ctx_addr = table->gpu_addr; 248 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 249 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 250 251 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 252 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 253 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 254 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 255 256 size = header.total_size; 257 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 258 259 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 260 261 param = 0x00000001; 262 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 263 tmp = 0; 264 timeout = 1000; 265 resp = 0; 266 expected = MMSCH_VF_MAILBOX_RESP__OK; 267 init_status = 268 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 269 while (resp != expected) { 270 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 271 272 if (resp != 0) 273 break; 274 udelay(10); 275 tmp = tmp + 10; 276 if (tmp >= timeout) { 277 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 278 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 279 "(expected=0x%08x, readback=0x%08x)\n", 280 tmp, expected, resp); 281 return -EBUSY; 282 } 283 } 284 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 285 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 286 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 287 resp, init_status); 288 289 } 290 return 0; 291 } 292 293 /** 294 * jpeg_v4_0_3_hw_init - start and test JPEG block 295 * 296 * @handle: amdgpu_device pointer 297 * 298 */ 299 static int jpeg_v4_0_3_hw_init(void *handle) 300 { 301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 302 struct amdgpu_ring *ring; 303 int i, j, r, jpeg_inst; 304 305 if (amdgpu_sriov_vf(adev)) { 306 r = jpeg_v4_0_3_start_sriov(adev); 307 if (r) 308 return r; 309 310 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 311 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 312 ring = &adev->jpeg.inst[i].ring_dec[j]; 313 ring->wptr = 0; 314 ring->wptr_old = 0; 315 jpeg_v4_0_3_dec_ring_set_wptr(ring); 316 ring->sched.ready = true; 317 } 318 } 319 } else { 320 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 321 jpeg_inst = GET_INST(JPEG, i); 322 323 ring = adev->jpeg.inst[i].ring_dec; 324 325 if (ring->use_doorbell) 326 adev->nbio.funcs->vcn_doorbell_range( 327 adev, ring->use_doorbell, 328 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 329 9 * jpeg_inst, 330 adev->jpeg.inst[i].aid_id); 331 332 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 333 ring = &adev->jpeg.inst[i].ring_dec[j]; 334 if (ring->use_doorbell) 335 WREG32_SOC15_OFFSET( 336 VCN, GET_INST(VCN, i), 337 regVCN_JPEG_DB_CTRL, 338 (ring->pipe ? (ring->pipe - 0x15) : 0), 339 ring->doorbell_index 340 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 341 VCN_JPEG_DB_CTRL__EN_MASK); 342 r = amdgpu_ring_test_helper(ring); 343 if (r) 344 return r; 345 } 346 } 347 } 348 349 return 0; 350 } 351 352 /** 353 * jpeg_v4_0_3_hw_fini - stop the hardware block 354 * 355 * @handle: amdgpu_device pointer 356 * 357 * Stop the JPEG block, mark ring as not ready any more 358 */ 359 static int jpeg_v4_0_3_hw_fini(void *handle) 360 { 361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 362 int ret = 0; 363 364 cancel_delayed_work_sync(&adev->jpeg.idle_work); 365 366 if (!amdgpu_sriov_vf(adev)) { 367 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 368 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 369 } 370 371 return ret; 372 } 373 374 /** 375 * jpeg_v4_0_3_suspend - suspend JPEG block 376 * 377 * @handle: amdgpu_device pointer 378 * 379 * HW fini and suspend JPEG block 380 */ 381 static int jpeg_v4_0_3_suspend(void *handle) 382 { 383 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 384 int r; 385 386 r = jpeg_v4_0_3_hw_fini(adev); 387 if (r) 388 return r; 389 390 r = amdgpu_jpeg_suspend(adev); 391 392 return r; 393 } 394 395 /** 396 * jpeg_v4_0_3_resume - resume JPEG block 397 * 398 * @handle: amdgpu_device pointer 399 * 400 * Resume firmware and hw init JPEG block 401 */ 402 static int jpeg_v4_0_3_resume(void *handle) 403 { 404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 405 int r; 406 407 r = amdgpu_jpeg_resume(adev); 408 if (r) 409 return r; 410 411 r = jpeg_v4_0_3_hw_init(adev); 412 413 return r; 414 } 415 416 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 417 { 418 int i, jpeg_inst; 419 uint32_t data; 420 421 jpeg_inst = GET_INST(JPEG, inst_idx); 422 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 423 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 424 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 425 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 426 } else { 427 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 428 } 429 430 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 431 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 432 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 433 434 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 435 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 436 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 437 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 438 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 439 } 440 441 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 442 { 443 int i, jpeg_inst; 444 uint32_t data; 445 446 jpeg_inst = GET_INST(JPEG, inst_idx); 447 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 448 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 449 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 450 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 451 } else { 452 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 453 } 454 455 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 456 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 457 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 458 459 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 460 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 461 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 462 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 463 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 464 } 465 466 /** 467 * jpeg_v4_0_3_start - start JPEG block 468 * 469 * @adev: amdgpu_device pointer 470 * 471 * Setup and start the JPEG block 472 */ 473 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 474 { 475 struct amdgpu_ring *ring; 476 int i, j, jpeg_inst; 477 478 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 479 jpeg_inst = GET_INST(JPEG, i); 480 481 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 482 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 483 SOC15_WAIT_ON_RREG( 484 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 485 UVD_PGFSM_STATUS__UVDJ_PWR_ON 486 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 487 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 488 489 /* disable anti hang mechanism */ 490 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 491 regUVD_JPEG_POWER_STATUS), 492 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 493 494 /* JPEG disable CGC */ 495 jpeg_v4_0_3_disable_clock_gating(adev, i); 496 497 /* MJPEG global tiling registers */ 498 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 499 adev->gfx.config.gb_addr_config); 500 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 501 adev->gfx.config.gb_addr_config); 502 503 /* enable JMI channel */ 504 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 505 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 506 507 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 508 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 509 510 ring = &adev->jpeg.inst[i].ring_dec[j]; 511 512 /* enable System Interrupt for JRBC */ 513 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 514 regJPEG_SYS_INT_EN), 515 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 516 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 517 518 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 519 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 520 reg_offset, 0); 521 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 522 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 523 reg_offset, 524 (0x00000001L | 0x00000002L)); 525 WREG32_SOC15_OFFSET( 526 JPEG, jpeg_inst, 527 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 528 reg_offset, lower_32_bits(ring->gpu_addr)); 529 WREG32_SOC15_OFFSET( 530 JPEG, jpeg_inst, 531 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 532 reg_offset, upper_32_bits(ring->gpu_addr)); 533 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 534 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 535 reg_offset, 0); 536 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 537 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 538 reg_offset, 0); 539 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 540 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 541 reg_offset, 0x00000002L); 542 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 543 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 544 reg_offset, ring->ring_size / 4); 545 ring->wptr = RREG32_SOC15_OFFSET( 546 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 547 reg_offset); 548 } 549 } 550 551 return 0; 552 } 553 554 /** 555 * jpeg_v4_0_3_stop - stop JPEG block 556 * 557 * @adev: amdgpu_device pointer 558 * 559 * stop the JPEG block 560 */ 561 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 562 { 563 int i, jpeg_inst; 564 565 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 566 jpeg_inst = GET_INST(JPEG, i); 567 /* reset JMI */ 568 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 569 UVD_JMI_CNTL__SOFT_RESET_MASK, 570 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 571 572 jpeg_v4_0_3_enable_clock_gating(adev, i); 573 574 /* enable anti hang mechanism */ 575 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 576 regUVD_JPEG_POWER_STATUS), 577 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 578 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 579 580 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 581 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 582 SOC15_WAIT_ON_RREG( 583 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 584 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 585 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 586 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 587 } 588 589 return 0; 590 } 591 592 /** 593 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 594 * 595 * @ring: amdgpu_ring pointer 596 * 597 * Returns the current hardware read pointer 598 */ 599 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 600 { 601 struct amdgpu_device *adev = ring->adev; 602 603 return RREG32_SOC15_OFFSET( 604 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 605 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 606 } 607 608 /** 609 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 610 * 611 * @ring: amdgpu_ring pointer 612 * 613 * Returns the current hardware write pointer 614 */ 615 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 616 { 617 struct amdgpu_device *adev = ring->adev; 618 619 if (ring->use_doorbell) 620 return adev->wb.wb[ring->wptr_offs]; 621 else 622 return RREG32_SOC15_OFFSET( 623 JPEG, GET_INST(JPEG, ring->me), 624 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 625 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 626 } 627 628 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 629 { 630 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 631 * This is a workaround to avoid any HDP flush through JPEG ring. 632 */ 633 } 634 635 /** 636 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 637 * 638 * @ring: amdgpu_ring pointer 639 * 640 * Commits the write pointer to the hardware 641 */ 642 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 643 { 644 struct amdgpu_device *adev = ring->adev; 645 646 if (ring->use_doorbell) { 647 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 648 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 649 } else { 650 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 651 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 652 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 653 0), 654 lower_32_bits(ring->wptr)); 655 } 656 } 657 658 /** 659 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 660 * 661 * @ring: amdgpu_ring pointer 662 * 663 * Write a start command to the ring. 664 */ 665 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 666 { 667 if (!amdgpu_sriov_vf(ring->adev)) { 668 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 669 0, 0, PACKETJ_TYPE0)); 670 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 671 } 672 673 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 674 0, 0, PACKETJ_TYPE0)); 675 amdgpu_ring_write(ring, 0x80004000); 676 } 677 678 /** 679 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 680 * 681 * @ring: amdgpu_ring pointer 682 * 683 * Write a end command to the ring. 684 */ 685 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 686 { 687 if (!amdgpu_sriov_vf(ring->adev)) { 688 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 689 0, 0, PACKETJ_TYPE0)); 690 amdgpu_ring_write(ring, 0x62a04); 691 } 692 693 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 694 0, 0, PACKETJ_TYPE0)); 695 amdgpu_ring_write(ring, 0x00004000); 696 } 697 698 /** 699 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 700 * 701 * @ring: amdgpu_ring pointer 702 * @addr: address 703 * @seq: sequence number 704 * @flags: fence related flags 705 * 706 * Write a fence and a trap command to the ring. 707 */ 708 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 709 unsigned int flags) 710 { 711 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 712 713 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 714 0, 0, PACKETJ_TYPE0)); 715 amdgpu_ring_write(ring, seq); 716 717 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 718 0, 0, PACKETJ_TYPE0)); 719 amdgpu_ring_write(ring, seq); 720 721 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 722 0, 0, PACKETJ_TYPE0)); 723 amdgpu_ring_write(ring, lower_32_bits(addr)); 724 725 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 726 0, 0, PACKETJ_TYPE0)); 727 amdgpu_ring_write(ring, upper_32_bits(addr)); 728 729 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 730 0, 0, PACKETJ_TYPE0)); 731 amdgpu_ring_write(ring, 0x8); 732 733 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 734 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 735 amdgpu_ring_write(ring, 0); 736 737 if (ring->adev->jpeg.inst[ring->me].aid_id) { 738 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 739 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 740 amdgpu_ring_write(ring, 0x4); 741 } else { 742 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 743 amdgpu_ring_write(ring, 0); 744 } 745 746 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 747 0, 0, PACKETJ_TYPE0)); 748 amdgpu_ring_write(ring, 0x3fbc); 749 750 if (ring->adev->jpeg.inst[ring->me].aid_id) { 751 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 752 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 753 amdgpu_ring_write(ring, 0x0); 754 } else { 755 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 756 amdgpu_ring_write(ring, 0); 757 } 758 759 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 760 0, 0, PACKETJ_TYPE0)); 761 amdgpu_ring_write(ring, 0x1); 762 763 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 764 amdgpu_ring_write(ring, 0); 765 } 766 767 /** 768 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 769 * 770 * @ring: amdgpu_ring pointer 771 * @job: job to retrieve vmid from 772 * @ib: indirect buffer to execute 773 * @flags: unused 774 * 775 * Write ring commands to execute the indirect buffer. 776 */ 777 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 778 struct amdgpu_job *job, 779 struct amdgpu_ib *ib, 780 uint32_t flags) 781 { 782 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 783 784 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 785 0, 0, PACKETJ_TYPE0)); 786 787 if (ring->funcs->parse_cs) 788 amdgpu_ring_write(ring, 0); 789 else 790 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 791 792 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 793 0, 0, PACKETJ_TYPE0)); 794 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 795 796 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 797 0, 0, PACKETJ_TYPE0)); 798 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 799 800 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 801 0, 0, PACKETJ_TYPE0)); 802 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 803 804 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 805 0, 0, PACKETJ_TYPE0)); 806 amdgpu_ring_write(ring, ib->length_dw); 807 808 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 809 0, 0, PACKETJ_TYPE0)); 810 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 811 812 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 813 0, 0, PACKETJ_TYPE0)); 814 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 815 816 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 817 amdgpu_ring_write(ring, 0); 818 819 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 820 0, 0, PACKETJ_TYPE0)); 821 amdgpu_ring_write(ring, 0x01400200); 822 823 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 824 0, 0, PACKETJ_TYPE0)); 825 amdgpu_ring_write(ring, 0x2); 826 827 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 828 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 829 amdgpu_ring_write(ring, 0x2); 830 } 831 832 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 833 uint32_t val, uint32_t mask) 834 { 835 uint32_t reg_offset; 836 837 /* For VF, only local offsets should be used */ 838 if (amdgpu_sriov_vf(ring->adev)) 839 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 840 841 reg_offset = (reg << 2); 842 843 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 844 0, 0, PACKETJ_TYPE0)); 845 amdgpu_ring_write(ring, 0x01400200); 846 847 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 848 0, 0, PACKETJ_TYPE0)); 849 amdgpu_ring_write(ring, val); 850 851 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 852 0, 0, PACKETJ_TYPE0)); 853 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 854 amdgpu_ring_write(ring, 0); 855 amdgpu_ring_write(ring, 856 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 857 } else { 858 amdgpu_ring_write(ring, reg_offset); 859 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 860 0, 0, PACKETJ_TYPE3)); 861 } 862 amdgpu_ring_write(ring, mask); 863 } 864 865 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 866 unsigned int vmid, uint64_t pd_addr) 867 { 868 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 869 uint32_t data0, data1, mask; 870 871 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 872 873 /* wait for register write */ 874 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 875 data1 = lower_32_bits(pd_addr); 876 mask = 0xffffffff; 877 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 878 } 879 880 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 881 { 882 uint32_t reg_offset; 883 884 /* For VF, only local offsets should be used */ 885 if (amdgpu_sriov_vf(ring->adev)) 886 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 887 888 reg_offset = (reg << 2); 889 890 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 891 0, 0, PACKETJ_TYPE0)); 892 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 893 amdgpu_ring_write(ring, 0); 894 amdgpu_ring_write(ring, 895 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 896 } else { 897 amdgpu_ring_write(ring, reg_offset); 898 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 899 0, 0, PACKETJ_TYPE0)); 900 } 901 amdgpu_ring_write(ring, val); 902 } 903 904 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 905 { 906 int i; 907 908 WARN_ON(ring->wptr % 2 || count % 2); 909 910 for (i = 0; i < count / 2; i++) { 911 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 912 amdgpu_ring_write(ring, 0); 913 } 914 } 915 916 static bool jpeg_v4_0_3_is_idle(void *handle) 917 { 918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 919 bool ret = false; 920 int i, j; 921 922 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 923 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 924 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 925 926 ret &= ((RREG32_SOC15_OFFSET( 927 JPEG, GET_INST(JPEG, i), 928 regUVD_JRBC0_UVD_JRBC_STATUS, 929 reg_offset) & 930 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 931 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 932 } 933 } 934 935 return ret; 936 } 937 938 static int jpeg_v4_0_3_wait_for_idle(void *handle) 939 { 940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941 int ret = 0; 942 int i, j; 943 944 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 945 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 946 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 947 948 ret &= SOC15_WAIT_ON_RREG_OFFSET( 949 JPEG, GET_INST(JPEG, i), 950 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 951 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 952 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 953 } 954 } 955 return ret; 956 } 957 958 static int jpeg_v4_0_3_set_clockgating_state(void *handle, 959 enum amd_clockgating_state state) 960 { 961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 962 bool enable = state == AMD_CG_STATE_GATE; 963 int i; 964 965 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 966 if (enable) { 967 if (!jpeg_v4_0_3_is_idle(handle)) 968 return -EBUSY; 969 jpeg_v4_0_3_enable_clock_gating(adev, i); 970 } else { 971 jpeg_v4_0_3_disable_clock_gating(adev, i); 972 } 973 } 974 return 0; 975 } 976 977 static int jpeg_v4_0_3_set_powergating_state(void *handle, 978 enum amd_powergating_state state) 979 { 980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 981 int ret; 982 983 if (amdgpu_sriov_vf(adev)) { 984 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 985 return 0; 986 } 987 988 if (state == adev->jpeg.cur_state) 989 return 0; 990 991 if (state == AMD_PG_STATE_GATE) 992 ret = jpeg_v4_0_3_stop(adev); 993 else 994 ret = jpeg_v4_0_3_start(adev); 995 996 if (!ret) 997 adev->jpeg.cur_state = state; 998 999 return ret; 1000 } 1001 1002 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1003 struct amdgpu_irq_src *source, 1004 unsigned int type, 1005 enum amdgpu_interrupt_state state) 1006 { 1007 return 0; 1008 } 1009 1010 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1011 struct amdgpu_irq_src *source, 1012 struct amdgpu_iv_entry *entry) 1013 { 1014 uint32_t i, inst; 1015 1016 i = node_id_to_phys_map[entry->node_id]; 1017 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1018 1019 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1020 if (adev->jpeg.inst[inst].aid_id == i) 1021 break; 1022 1023 if (inst >= adev->jpeg.num_jpeg_inst) { 1024 dev_WARN_ONCE(adev->dev, 1, 1025 "Interrupt received for unknown JPEG instance %d", 1026 entry->node_id); 1027 return 0; 1028 } 1029 1030 switch (entry->src_id) { 1031 case VCN_4_0__SRCID__JPEG_DECODE: 1032 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1033 break; 1034 case VCN_4_0__SRCID__JPEG1_DECODE: 1035 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1036 break; 1037 case VCN_4_0__SRCID__JPEG2_DECODE: 1038 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1039 break; 1040 case VCN_4_0__SRCID__JPEG3_DECODE: 1041 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1042 break; 1043 case VCN_4_0__SRCID__JPEG4_DECODE: 1044 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1045 break; 1046 case VCN_4_0__SRCID__JPEG5_DECODE: 1047 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1048 break; 1049 case VCN_4_0__SRCID__JPEG6_DECODE: 1050 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1051 break; 1052 case VCN_4_0__SRCID__JPEG7_DECODE: 1053 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1054 break; 1055 default: 1056 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1057 entry->src_id, entry->src_data[0]); 1058 break; 1059 } 1060 1061 return 0; 1062 } 1063 1064 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1065 .name = "jpeg_v4_0_3", 1066 .early_init = jpeg_v4_0_3_early_init, 1067 .late_init = NULL, 1068 .sw_init = jpeg_v4_0_3_sw_init, 1069 .sw_fini = jpeg_v4_0_3_sw_fini, 1070 .hw_init = jpeg_v4_0_3_hw_init, 1071 .hw_fini = jpeg_v4_0_3_hw_fini, 1072 .suspend = jpeg_v4_0_3_suspend, 1073 .resume = jpeg_v4_0_3_resume, 1074 .is_idle = jpeg_v4_0_3_is_idle, 1075 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1076 .check_soft_reset = NULL, 1077 .pre_soft_reset = NULL, 1078 .soft_reset = NULL, 1079 .post_soft_reset = NULL, 1080 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1081 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1082 .dump_ip_state = NULL, 1083 .print_ip_state = NULL, 1084 }; 1085 1086 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1087 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1088 .align_mask = 0xf, 1089 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1090 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1091 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1092 .parse_cs = jpeg_v4_0_3_dec_ring_parse_cs, 1093 .emit_frame_size = 1094 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1095 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1096 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1097 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1098 8 + 16, 1099 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1100 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1101 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1102 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1103 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1104 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1105 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1106 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1107 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1108 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1109 .pad_ib = amdgpu_ring_generic_pad_ib, 1110 .begin_use = amdgpu_jpeg_ring_begin_use, 1111 .end_use = amdgpu_jpeg_ring_end_use, 1112 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1113 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1114 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1115 }; 1116 1117 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1118 { 1119 int i, j, jpeg_inst; 1120 1121 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1122 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1123 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1124 adev->jpeg.inst[i].ring_dec[j].me = i; 1125 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1126 } 1127 jpeg_inst = GET_INST(JPEG, i); 1128 adev->jpeg.inst[i].aid_id = 1129 jpeg_inst / adev->jpeg.num_inst_per_aid; 1130 } 1131 } 1132 1133 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1134 .set = jpeg_v4_0_3_set_interrupt_state, 1135 .process = jpeg_v4_0_3_process_interrupt, 1136 }; 1137 1138 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1139 { 1140 int i; 1141 1142 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1143 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1144 } 1145 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1146 } 1147 1148 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1149 .type = AMD_IP_BLOCK_TYPE_JPEG, 1150 .major = 4, 1151 .minor = 0, 1152 .rev = 3, 1153 .funcs = &jpeg_v4_0_3_ip_funcs, 1154 }; 1155 1156 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1157 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1158 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1159 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1160 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1161 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1162 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1163 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1164 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1165 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1166 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1167 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1168 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1169 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1170 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1171 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1172 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1173 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1174 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1175 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1176 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1177 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1178 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1179 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1180 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1181 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1182 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1183 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1184 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1185 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1186 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1187 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1188 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1189 }; 1190 1191 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1192 uint32_t jpeg_inst, 1193 void *ras_err_status) 1194 { 1195 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1196 1197 /* jpeg v4_0_3 only support uncorrectable errors */ 1198 amdgpu_ras_inst_query_ras_error_count(adev, 1199 jpeg_v4_0_3_ue_reg_list, 1200 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1201 NULL, 0, GET_INST(VCN, jpeg_inst), 1202 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1203 &err_data->ue_count); 1204 } 1205 1206 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1207 void *ras_err_status) 1208 { 1209 uint32_t i; 1210 1211 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1212 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1213 return; 1214 } 1215 1216 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1217 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1218 } 1219 1220 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1221 uint32_t jpeg_inst) 1222 { 1223 amdgpu_ras_inst_reset_ras_error_count(adev, 1224 jpeg_v4_0_3_ue_reg_list, 1225 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1226 GET_INST(VCN, jpeg_inst)); 1227 } 1228 1229 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1230 { 1231 uint32_t i; 1232 1233 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1234 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1235 return; 1236 } 1237 1238 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1239 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1240 } 1241 1242 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1243 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1244 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1245 }; 1246 1247 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1248 .ras_block = { 1249 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1250 }, 1251 }; 1252 1253 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1254 { 1255 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1256 } 1257 1258 /** 1259 * jpeg_v4_0_3_dec_ring_parse_cs - command submission parser 1260 * 1261 * @parser: Command submission parser context 1262 * @job: the job to parse 1263 * @ib: the IB to parse 1264 * 1265 * Parse the command stream, return -EINVAL for invalid packet, 1266 * 0 otherwise 1267 */ 1268 int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, 1269 struct amdgpu_job *job, 1270 struct amdgpu_ib *ib) 1271 { 1272 uint32_t i, reg, res, cond, type; 1273 struct amdgpu_device *adev = parser->adev; 1274 1275 for (i = 0; i < ib->length_dw ; i += 2) { 1276 reg = CP_PACKETJ_GET_REG(ib->ptr[i]); 1277 res = CP_PACKETJ_GET_RES(ib->ptr[i]); 1278 cond = CP_PACKETJ_GET_COND(ib->ptr[i]); 1279 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); 1280 1281 if (res) /* only support 0 at the moment */ 1282 return -EINVAL; 1283 1284 switch (type) { 1285 case PACKETJ_TYPE0: 1286 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) { 1287 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 1288 return -EINVAL; 1289 } 1290 break; 1291 case PACKETJ_TYPE3: 1292 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) { 1293 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 1294 return -EINVAL; 1295 } 1296 break; 1297 case PACKETJ_TYPE6: 1298 if (ib->ptr[i] == CP_PACKETJ_NOP) 1299 continue; 1300 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 1301 return -EINVAL; 1302 default: 1303 dev_err(adev->dev, "Unknown packet type %d !\n", type); 1304 return -EINVAL; 1305 } 1306 } 1307 1308 return 0; 1309 } 1310