1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver 4 * 5 * Copyright (c) 2005, Advanced Micro Devices, Inc. 6 * 7 * Developed with help from the 2.4.30 MMC AU1XXX controller including 8 * the following copyright notices: 9 * Copyright (c) 2003-2004 Embedded Edge, LLC. 10 * Portions Copyright (C) 2002 Embedix, Inc 11 * Copyright 2002 Hewlett-Packard Company 12 13 * 2.6 version of this driver inspired by: 14 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, 15 * All Rights Reserved. 16 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, 17 * All Rights Reserved. 18 * 19 20 */ 21 22 /* Why don't we use the SD controllers' carddetect feature? 23 * 24 * From the AU1100 MMC application guide: 25 * If the Au1100-based design is intended to support both MultiMediaCards 26 * and 1- or 4-data bit SecureDigital cards, then the solution is to 27 * connect a weak (560KOhm) pull-up resistor to connector pin 1. 28 * In doing so, a MMC card never enters SPI-mode communications, 29 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective 30 * (the low to high transition will not occur). 31 */ 32 33 #include <linux/clk.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/platform_device.h> 37 #include <linux/mm.h> 38 #include <linux/interrupt.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/scatterlist.h> 41 #include <linux/highmem.h> 42 #include <linux/leds.h> 43 #include <linux/mmc/host.h> 44 #include <linux/slab.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/io.h> 48 #include <asm/mach-au1x00/au1000.h> 49 #include <asm/mach-au1x00/au1xxx_dbdma.h> 50 #include <asm/mach-au1x00/au1100_mmc.h> 51 52 #define DRIVER_NAME "au1xxx-mmc" 53 54 /* Set this to enable special debugging macros */ 55 /* #define DEBUG */ 56 57 #ifdef DEBUG 58 #define DBG(fmt, idx, args...) \ 59 pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args) 60 #else 61 #define DBG(fmt, idx, args...) do {} while (0) 62 #endif 63 64 /* Hardware definitions */ 65 #define AU1XMMC_DESCRIPTOR_COUNT 1 66 67 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ 68 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff 69 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff 70 71 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 72 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 73 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) 74 75 /* This gives us a hard value for the stop command that we can write directly 76 * to the command register. 77 */ 78 #define STOP_CMD \ 79 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) 80 81 /* This is the set of interrupts that we configure by default. */ 82 #define AU1XMMC_INTERRUPTS \ 83 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ 84 SD_CONFIG_CR | SD_CONFIG_I) 85 86 /* The poll event (looking for insert/remove events runs twice a second. */ 87 #define AU1XMMC_DETECT_TIMEOUT (HZ/2) 88 89 struct au1xmmc_host { 90 struct mmc_host *mmc; 91 struct mmc_request *mrq; 92 93 u32 flags; 94 void __iomem *iobase; 95 u32 clock; 96 u32 bus_width; 97 u32 power_mode; 98 99 int status; 100 101 struct { 102 int len; 103 int dir; 104 } dma; 105 106 struct { 107 int index; 108 int offset; 109 int len; 110 } pio; 111 112 u32 tx_chan; 113 u32 rx_chan; 114 115 int irq; 116 117 struct work_struct finish_bh_work; 118 struct work_struct data_bh_work; 119 struct au1xmmc_platform_data *platdata; 120 struct platform_device *pdev; 121 struct resource *ioarea; 122 struct clk *clk; 123 }; 124 125 /* Status flags used by the host structure */ 126 #define HOST_F_XMIT 0x0001 127 #define HOST_F_RECV 0x0002 128 #define HOST_F_DMA 0x0010 129 #define HOST_F_DBDMA 0x0020 130 #define HOST_F_ACTIVE 0x0100 131 #define HOST_F_STOP 0x1000 132 133 #define HOST_S_IDLE 0x0001 134 #define HOST_S_CMD 0x0002 135 #define HOST_S_DATA 0x0003 136 #define HOST_S_STOP 0x0004 137 138 /* Easy access macros */ 139 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) 140 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) 141 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) 142 #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) 143 #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) 144 #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) 145 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) 146 #define HOST_CMD(h) ((h)->iobase + SD_CMD) 147 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) 148 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) 149 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) 150 151 #define DMA_CHANNEL(h) \ 152 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 153 154 static inline int has_dbdma(void) 155 { 156 switch (alchemy_get_cputype()) { 157 case ALCHEMY_CPU_AU1200: 158 case ALCHEMY_CPU_AU1300: 159 return 1; 160 default: 161 return 0; 162 } 163 } 164 165 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 166 { 167 u32 val = __raw_readl(HOST_CONFIG(host)); 168 val |= mask; 169 __raw_writel(val, HOST_CONFIG(host)); 170 wmb(); /* drain writebuffer */ 171 } 172 173 static inline void FLUSH_FIFO(struct au1xmmc_host *host) 174 { 175 u32 val = __raw_readl(HOST_CONFIG2(host)); 176 177 __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 178 wmb(); /* drain writebuffer */ 179 mdelay(1); 180 181 /* SEND_STOP will turn off clock control - this re-enables it */ 182 val &= ~SD_CONFIG2_DF; 183 184 __raw_writel(val, HOST_CONFIG2(host)); 185 wmb(); /* drain writebuffer */ 186 } 187 188 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 189 { 190 u32 val = __raw_readl(HOST_CONFIG(host)); 191 val &= ~mask; 192 __raw_writel(val, HOST_CONFIG(host)); 193 wmb(); /* drain writebuffer */ 194 } 195 196 static inline void SEND_STOP(struct au1xmmc_host *host) 197 { 198 u32 config2; 199 200 WARN_ON(host->status != HOST_S_DATA); 201 host->status = HOST_S_STOP; 202 203 config2 = __raw_readl(HOST_CONFIG2(host)); 204 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 205 wmb(); /* drain writebuffer */ 206 207 /* Send the stop command */ 208 __raw_writel(STOP_CMD, HOST_CMD(host)); 209 wmb(); /* drain writebuffer */ 210 } 211 212 static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 213 { 214 if (host->platdata && host->platdata->set_power) 215 host->platdata->set_power(host->mmc, state); 216 } 217 218 static int au1xmmc_card_inserted(struct mmc_host *mmc) 219 { 220 struct au1xmmc_host *host = mmc_priv(mmc); 221 222 if (host->platdata && host->platdata->card_inserted) 223 return !!host->platdata->card_inserted(host->mmc); 224 225 return -ENOSYS; 226 } 227 228 static int au1xmmc_card_readonly(struct mmc_host *mmc) 229 { 230 struct au1xmmc_host *host = mmc_priv(mmc); 231 232 if (host->platdata && host->platdata->card_readonly) 233 return !!host->platdata->card_readonly(mmc); 234 235 return -ENOSYS; 236 } 237 238 static void au1xmmc_finish_request(struct au1xmmc_host *host) 239 { 240 struct mmc_request *mrq = host->mrq; 241 242 host->mrq = NULL; 243 host->flags &= HOST_F_ACTIVE | HOST_F_DMA; 244 245 host->dma.len = 0; 246 host->dma.dir = 0; 247 248 host->pio.index = 0; 249 host->pio.offset = 0; 250 host->pio.len = 0; 251 252 host->status = HOST_S_IDLE; 253 254 mmc_request_done(host->mmc, mrq); 255 } 256 257 static void au1xmmc_finish_bh_work(struct work_struct *t) 258 { 259 struct au1xmmc_host *host = from_work(host, t, finish_bh_work); 260 au1xmmc_finish_request(host); 261 } 262 263 static int au1xmmc_send_command(struct au1xmmc_host *host, 264 struct mmc_command *cmd, struct mmc_data *data) 265 { 266 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); 267 268 switch (mmc_resp_type(cmd)) { 269 case MMC_RSP_NONE: 270 break; 271 case MMC_RSP_R1: 272 mmccmd |= SD_CMD_RT_1; 273 break; 274 case MMC_RSP_R1B: 275 mmccmd |= SD_CMD_RT_1B; 276 break; 277 case MMC_RSP_R2: 278 mmccmd |= SD_CMD_RT_2; 279 break; 280 case MMC_RSP_R3: 281 mmccmd |= SD_CMD_RT_3; 282 break; 283 default: 284 pr_info("au1xmmc: unhandled response type %02x\n", 285 mmc_resp_type(cmd)); 286 return -EINVAL; 287 } 288 289 if (data) { 290 if (data->flags & MMC_DATA_READ) { 291 if (data->blocks > 1) 292 mmccmd |= SD_CMD_CT_4; 293 else 294 mmccmd |= SD_CMD_CT_2; 295 } else if (data->flags & MMC_DATA_WRITE) { 296 if (data->blocks > 1) 297 mmccmd |= SD_CMD_CT_3; 298 else 299 mmccmd |= SD_CMD_CT_1; 300 } 301 } 302 303 __raw_writel(cmd->arg, HOST_CMDARG(host)); 304 wmb(); /* drain writebuffer */ 305 306 __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 307 wmb(); /* drain writebuffer */ 308 309 /* Wait for the command to go on the line */ 310 while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO) 311 /* nop */; 312 313 return 0; 314 } 315 316 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 317 { 318 struct mmc_request *mrq = host->mrq; 319 struct mmc_data *data; 320 u32 crc; 321 322 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); 323 324 if (host->mrq == NULL) 325 return; 326 327 data = mrq->cmd->data; 328 329 if (status == 0) 330 status = __raw_readl(HOST_STATUS(host)); 331 332 /* The transaction is really over when the SD_STATUS_DB bit is clear */ 333 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 334 status = __raw_readl(HOST_STATUS(host)); 335 336 data->error = 0; 337 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 338 339 /* Process any errors */ 340 crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); 341 if (host->flags & HOST_F_XMIT) 342 crc |= ((status & 0x07) == 0x02) ? 0 : 1; 343 344 if (crc) 345 data->error = -EILSEQ; 346 347 /* Clear the CRC bits */ 348 __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 349 350 data->bytes_xfered = 0; 351 352 if (!data->error) { 353 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 354 u32 chan = DMA_CHANNEL(host); 355 356 chan_tab_t *c = *((chan_tab_t **)chan); 357 au1x_dma_chan_t *cp = c->chan_ptr; 358 data->bytes_xfered = cp->ddma_bytecnt; 359 } else 360 data->bytes_xfered = 361 (data->blocks * data->blksz) - host->pio.len; 362 } 363 364 au1xmmc_finish_request(host); 365 } 366 367 static void au1xmmc_data_bh_work(struct work_struct *t) 368 { 369 struct au1xmmc_host *host = from_work(host, t, data_bh_work); 370 371 u32 status = __raw_readl(HOST_STATUS(host)); 372 au1xmmc_data_complete(host, status); 373 } 374 375 #define AU1XMMC_MAX_TRANSFER 8 376 377 static void au1xmmc_send_pio(struct au1xmmc_host *host) 378 { 379 struct mmc_data *data; 380 int sg_len, max, count; 381 unsigned char *sg_ptr, val; 382 u32 status; 383 struct scatterlist *sg; 384 385 data = host->mrq->data; 386 387 if (!(host->flags & HOST_F_XMIT)) 388 return; 389 390 /* This is the pointer to the data buffer */ 391 sg = &data->sg[host->pio.index]; 392 sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset; 393 394 /* This is the space left inside the buffer */ 395 sg_len = data->sg[host->pio.index].length - host->pio.offset; 396 397 /* Check if we need less than the size of the sg_buffer */ 398 max = (sg_len > host->pio.len) ? host->pio.len : sg_len; 399 if (max > AU1XMMC_MAX_TRANSFER) 400 max = AU1XMMC_MAX_TRANSFER; 401 402 for (count = 0; count < max; count++) { 403 status = __raw_readl(HOST_STATUS(host)); 404 405 if (!(status & SD_STATUS_TH)) 406 break; 407 408 val = sg_ptr[count]; 409 410 __raw_writel((unsigned long)val, HOST_TXPORT(host)); 411 wmb(); /* drain writebuffer */ 412 } 413 kunmap_local(sg_ptr); 414 415 host->pio.len -= count; 416 host->pio.offset += count; 417 418 if (count == sg_len) { 419 host->pio.index++; 420 host->pio.offset = 0; 421 } 422 423 if (host->pio.len == 0) { 424 IRQ_OFF(host, SD_CONFIG_TH); 425 426 if (host->flags & HOST_F_STOP) 427 SEND_STOP(host); 428 429 queue_work(system_bh_wq, &host->data_bh_work); 430 } 431 } 432 433 static void au1xmmc_receive_pio(struct au1xmmc_host *host) 434 { 435 struct mmc_data *data; 436 int max, count, sg_len = 0; 437 unsigned char *sg_ptr = NULL; 438 u32 status, val; 439 struct scatterlist *sg; 440 441 data = host->mrq->data; 442 443 if (!(host->flags & HOST_F_RECV)) 444 return; 445 446 max = host->pio.len; 447 448 if (host->pio.index < host->dma.len) { 449 sg = &data->sg[host->pio.index]; 450 sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset; 451 452 /* This is the space left inside the buffer */ 453 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; 454 455 /* Check if we need less than the size of the sg_buffer */ 456 if (sg_len < max) 457 max = sg_len; 458 } 459 460 if (max > AU1XMMC_MAX_TRANSFER) 461 max = AU1XMMC_MAX_TRANSFER; 462 463 for (count = 0; count < max; count++) { 464 status = __raw_readl(HOST_STATUS(host)); 465 466 if (!(status & SD_STATUS_NE)) 467 break; 468 469 if (status & SD_STATUS_RC) { 470 DBG("RX CRC Error [%d + %d].\n", host->pdev->id, 471 host->pio.len, count); 472 break; 473 } 474 475 if (status & SD_STATUS_RO) { 476 DBG("RX Overrun [%d + %d]\n", host->pdev->id, 477 host->pio.len, count); 478 break; 479 } 480 else if (status & SD_STATUS_RU) { 481 DBG("RX Underrun [%d + %d]\n", host->pdev->id, 482 host->pio.len, count); 483 break; 484 } 485 486 val = __raw_readl(HOST_RXPORT(host)); 487 488 if (sg_ptr) 489 sg_ptr[count] = (unsigned char)(val & 0xFF); 490 } 491 if (sg_ptr) 492 kunmap_local(sg_ptr); 493 494 host->pio.len -= count; 495 host->pio.offset += count; 496 497 if (sg_len && count == sg_len) { 498 host->pio.index++; 499 host->pio.offset = 0; 500 } 501 502 if (host->pio.len == 0) { 503 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 504 IRQ_OFF(host, SD_CONFIG_NE); 505 506 if (host->flags & HOST_F_STOP) 507 SEND_STOP(host); 508 509 queue_work(system_bh_wq, &host->data_bh_work); 510 } 511 } 512 513 /* This is called when a command has been completed - grab the response 514 * and check for errors. Then start the data transfer if it is indicated. 515 */ 516 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 517 { 518 struct mmc_request *mrq = host->mrq; 519 struct mmc_command *cmd; 520 u32 r[4]; 521 int i, trans; 522 523 if (!host->mrq) 524 return; 525 526 cmd = mrq->cmd; 527 cmd->error = 0; 528 529 if (cmd->flags & MMC_RSP_PRESENT) { 530 if (cmd->flags & MMC_RSP_136) { 531 r[0] = __raw_readl(host->iobase + SD_RESP3); 532 r[1] = __raw_readl(host->iobase + SD_RESP2); 533 r[2] = __raw_readl(host->iobase + SD_RESP1); 534 r[3] = __raw_readl(host->iobase + SD_RESP0); 535 536 /* The CRC is omitted from the response, so really 537 * we only got 120 bytes, but the engine expects 538 * 128 bits, so we have to shift things up. 539 */ 540 for (i = 0; i < 4; i++) { 541 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; 542 if (i != 3) 543 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; 544 } 545 } else { 546 /* Techincally, we should be getting all 48 bits of 547 * the response (SD_RESP1 + SD_RESP2), but because 548 * our response omits the CRC, our data ends up 549 * being shifted 8 bits to the right. In this case, 550 * that means that the OSR data starts at bit 31, 551 * so we can just read RESP0 and return that. 552 */ 553 cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0); 554 } 555 } 556 557 /* Figure out errors */ 558 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) 559 cmd->error = -EILSEQ; 560 561 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); 562 563 if (!trans || cmd->error) { 564 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); 565 queue_work(system_bh_wq, &host->finish_bh_work); 566 return; 567 } 568 569 host->status = HOST_S_DATA; 570 571 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) { 572 u32 channel = DMA_CHANNEL(host); 573 574 /* Start the DBDMA as soon as the buffer gets something in it */ 575 576 if (host->flags & HOST_F_RECV) { 577 u32 mask = SD_STATUS_DB | SD_STATUS_NE; 578 579 while((status & mask) != mask) 580 status = __raw_readl(HOST_STATUS(host)); 581 } 582 583 au1xxx_dbdma_start(channel); 584 } 585 } 586 587 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 588 { 589 unsigned int pbus = clk_get_rate(host->clk); 590 unsigned int divisor = ((pbus / rate) / 2) - 1; 591 u32 config; 592 593 config = __raw_readl(HOST_CONFIG(host)); 594 595 config &= ~(SD_CONFIG_DIV); 596 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 597 598 __raw_writel(config, HOST_CONFIG(host)); 599 wmb(); /* drain writebuffer */ 600 } 601 602 static int au1xmmc_prepare_data(struct au1xmmc_host *host, 603 struct mmc_data *data) 604 { 605 int datalen = data->blocks * data->blksz; 606 607 if (data->flags & MMC_DATA_READ) 608 host->flags |= HOST_F_RECV; 609 else 610 host->flags |= HOST_F_XMIT; 611 612 if (host->mrq->stop) 613 host->flags |= HOST_F_STOP; 614 615 host->dma.dir = DMA_BIDIRECTIONAL; 616 617 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, 618 data->sg_len, host->dma.dir); 619 620 if (host->dma.len == 0) 621 return -ETIMEDOUT; 622 623 __raw_writel(data->blksz - 1, HOST_BLKSIZE(host)); 624 625 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 626 int i; 627 u32 channel = DMA_CHANNEL(host); 628 629 au1xxx_dbdma_stop(channel); 630 631 for (i = 0; i < host->dma.len; i++) { 632 u32 ret = 0, flags = DDMA_FLAGS_NOIE; 633 struct scatterlist *sg = &data->sg[i]; 634 int sg_len = sg->length; 635 636 int len = (datalen > sg_len) ? sg_len : datalen; 637 638 if (i == host->dma.len - 1) 639 flags = DDMA_FLAGS_IE; 640 641 if (host->flags & HOST_F_XMIT) { 642 ret = au1xxx_dbdma_put_source(channel, 643 sg_phys(sg), len, flags); 644 } else { 645 ret = au1xxx_dbdma_put_dest(channel, 646 sg_phys(sg), len, flags); 647 } 648 649 if (!ret) 650 goto dataerr; 651 652 datalen -= len; 653 } 654 } else { 655 host->pio.index = 0; 656 host->pio.offset = 0; 657 host->pio.len = datalen; 658 659 if (host->flags & HOST_F_XMIT) 660 IRQ_ON(host, SD_CONFIG_TH); 661 else 662 IRQ_ON(host, SD_CONFIG_NE); 663 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 664 } 665 666 return 0; 667 668 dataerr: 669 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 670 host->dma.dir); 671 return -ETIMEDOUT; 672 } 673 674 /* This actually starts a command or data transaction */ 675 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 676 { 677 struct au1xmmc_host *host = mmc_priv(mmc); 678 int ret = 0; 679 680 WARN_ON(irqs_disabled()); 681 WARN_ON(host->status != HOST_S_IDLE); 682 683 host->mrq = mrq; 684 host->status = HOST_S_CMD; 685 686 /* fail request immediately if no card is present */ 687 if (0 == au1xmmc_card_inserted(mmc)) { 688 mrq->cmd->error = -ENOMEDIUM; 689 au1xmmc_finish_request(host); 690 return; 691 } 692 693 if (mrq->data) { 694 FLUSH_FIFO(host); 695 ret = au1xmmc_prepare_data(host, mrq->data); 696 } 697 698 if (!ret) 699 ret = au1xmmc_send_command(host, mrq->cmd, mrq->data); 700 701 if (ret) { 702 mrq->cmd->error = ret; 703 au1xmmc_finish_request(host); 704 } 705 } 706 707 static void au1xmmc_reset_controller(struct au1xmmc_host *host) 708 { 709 /* Apply the clock */ 710 __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 711 wmb(); /* drain writebuffer */ 712 mdelay(1); 713 714 __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 715 wmb(); /* drain writebuffer */ 716 mdelay(5); 717 718 __raw_writel(~0, HOST_STATUS(host)); 719 wmb(); /* drain writebuffer */ 720 721 __raw_writel(0, HOST_BLKSIZE(host)); 722 __raw_writel(0x001fffff, HOST_TIMEOUT(host)); 723 wmb(); /* drain writebuffer */ 724 725 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 726 wmb(); /* drain writebuffer */ 727 728 __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 729 wmb(); /* drain writebuffer */ 730 mdelay(1); 731 732 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 733 wmb(); /* drain writebuffer */ 734 735 /* Configure interrupts */ 736 __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 737 wmb(); /* drain writebuffer */ 738 } 739 740 741 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 742 { 743 struct au1xmmc_host *host = mmc_priv(mmc); 744 u32 config2; 745 746 if (ios->power_mode == MMC_POWER_OFF) 747 au1xmmc_set_power(host, 0); 748 else if (ios->power_mode == MMC_POWER_ON) { 749 au1xmmc_set_power(host, 1); 750 } 751 752 if (ios->clock && ios->clock != host->clock) { 753 au1xmmc_set_clock(host, ios->clock); 754 host->clock = ios->clock; 755 } 756 757 config2 = __raw_readl(HOST_CONFIG2(host)); 758 switch (ios->bus_width) { 759 case MMC_BUS_WIDTH_8: 760 config2 |= SD_CONFIG2_BB; 761 break; 762 case MMC_BUS_WIDTH_4: 763 config2 &= ~SD_CONFIG2_BB; 764 config2 |= SD_CONFIG2_WB; 765 break; 766 case MMC_BUS_WIDTH_1: 767 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); 768 break; 769 } 770 __raw_writel(config2, HOST_CONFIG2(host)); 771 wmb(); /* drain writebuffer */ 772 } 773 774 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 775 #define STATUS_DATA_IN (SD_STATUS_NE) 776 #define STATUS_DATA_OUT (SD_STATUS_TH) 777 778 static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 779 { 780 struct au1xmmc_host *host = dev_id; 781 u32 status; 782 783 status = __raw_readl(HOST_STATUS(host)); 784 785 if (!(status & SD_STATUS_I)) 786 return IRQ_NONE; /* not ours */ 787 788 if (status & SD_STATUS_SI) /* SDIO */ 789 mmc_signal_sdio_irq(host->mmc); 790 791 if (host->mrq && (status & STATUS_TIMEOUT)) { 792 if (status & SD_STATUS_RAT) 793 host->mrq->cmd->error = -ETIMEDOUT; 794 else if (status & SD_STATUS_DT) 795 host->mrq->data->error = -ETIMEDOUT; 796 797 /* In PIO mode, interrupts might still be enabled */ 798 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); 799 800 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ 801 queue_work(system_bh_wq, &host->finish_bh_work); 802 } 803 #if 0 804 else if (status & SD_STATUS_DD) { 805 /* Sometimes we get a DD before a NE in PIO mode */ 806 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) 807 au1xmmc_receive_pio(host); 808 else { 809 au1xmmc_data_complete(host, status); 810 /* queue_work(system_bh_wq, &host->data_bh_work); */ 811 } 812 } 813 #endif 814 else if (status & SD_STATUS_CR) { 815 if (host->status == HOST_S_CMD) 816 au1xmmc_cmd_complete(host, status); 817 818 } else if (!(host->flags & HOST_F_DMA)) { 819 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) 820 au1xmmc_send_pio(host); 821 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) 822 au1xmmc_receive_pio(host); 823 824 } else if (status & 0x203F3C70) { 825 DBG("Unhandled status %8.8x\n", host->pdev->id, 826 status); 827 } 828 829 __raw_writel(status, HOST_STATUS(host)); 830 wmb(); /* drain writebuffer */ 831 832 return IRQ_HANDLED; 833 } 834 835 /* 8bit memory DMA device */ 836 static dbdev_tab_t au1xmmc_mem_dbdev = { 837 .dev_id = DSCR_CMD0_ALWAYS, 838 .dev_flags = DEV_FLAGS_ANYUSE, 839 .dev_tsize = 0, 840 .dev_devwidth = 8, 841 .dev_physaddr = 0x00000000, 842 .dev_intlevel = 0, 843 .dev_intpolarity = 0, 844 }; 845 static int memid; 846 847 static void au1xmmc_dbdma_callback(int irq, void *dev_id) 848 { 849 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; 850 851 /* Avoid spurious interrupts */ 852 if (!host->mrq) 853 return; 854 855 if (host->flags & HOST_F_STOP) 856 SEND_STOP(host); 857 858 queue_work(system_bh_wq, &host->data_bh_work); 859 } 860 861 static int au1xmmc_dbdma_init(struct au1xmmc_host *host) 862 { 863 struct resource *res; 864 int txid, rxid; 865 866 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); 867 if (!res) 868 return -ENODEV; 869 txid = res->start; 870 871 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); 872 if (!res) 873 return -ENODEV; 874 rxid = res->start; 875 876 if (!memid) 877 return -ENODEV; 878 879 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, 880 au1xmmc_dbdma_callback, (void *)host); 881 if (!host->tx_chan) { 882 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); 883 return -ENODEV; 884 } 885 886 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, 887 au1xmmc_dbdma_callback, (void *)host); 888 if (!host->rx_chan) { 889 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); 890 au1xxx_dbdma_chan_free(host->tx_chan); 891 return -ENODEV; 892 } 893 894 au1xxx_dbdma_set_devwidth(host->tx_chan, 8); 895 au1xxx_dbdma_set_devwidth(host->rx_chan, 8); 896 897 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); 898 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 899 900 /* DBDMA is good to go */ 901 host->flags |= HOST_F_DMA | HOST_F_DBDMA; 902 903 return 0; 904 } 905 906 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) 907 { 908 if (host->flags & HOST_F_DMA) { 909 host->flags &= ~HOST_F_DMA; 910 au1xxx_dbdma_chan_free(host->tx_chan); 911 au1xxx_dbdma_chan_free(host->rx_chan); 912 } 913 } 914 915 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 916 { 917 struct au1xmmc_host *host = mmc_priv(mmc); 918 919 if (en) 920 IRQ_ON(host, SD_CONFIG_SI); 921 else 922 IRQ_OFF(host, SD_CONFIG_SI); 923 } 924 925 static const struct mmc_host_ops au1xmmc_ops = { 926 .request = au1xmmc_request, 927 .set_ios = au1xmmc_set_ios, 928 .get_ro = au1xmmc_card_readonly, 929 .get_cd = au1xmmc_card_inserted, 930 .enable_sdio_irq = au1xmmc_enable_sdio_irq, 931 }; 932 933 static int au1xmmc_probe(struct platform_device *pdev) 934 { 935 struct mmc_host *mmc; 936 struct au1xmmc_host *host; 937 struct resource *r; 938 int ret, iflag; 939 940 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 941 if (!mmc) { 942 dev_err(&pdev->dev, "no memory for mmc_host\n"); 943 ret = -ENOMEM; 944 goto out0; 945 } 946 947 host = mmc_priv(mmc); 948 host->mmc = mmc; 949 host->platdata = pdev->dev.platform_data; 950 host->pdev = pdev; 951 952 ret = -ENODEV; 953 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 954 if (!r) { 955 dev_err(&pdev->dev, "no mmio defined\n"); 956 goto out1; 957 } 958 959 host->ioarea = request_mem_region(r->start, resource_size(r), 960 pdev->name); 961 if (!host->ioarea) { 962 dev_err(&pdev->dev, "mmio already in use\n"); 963 goto out1; 964 } 965 966 host->iobase = ioremap(r->start, 0x3c); 967 if (!host->iobase) { 968 dev_err(&pdev->dev, "cannot remap mmio\n"); 969 goto out2; 970 } 971 972 host->irq = platform_get_irq(pdev, 0); 973 if (host->irq < 0) { 974 ret = host->irq; 975 goto out3; 976 } 977 978 mmc->ops = &au1xmmc_ops; 979 980 mmc->f_min = 450000; 981 mmc->f_max = 24000000; 982 983 mmc->max_blk_size = 2048; 984 mmc->max_blk_count = 512; 985 986 mmc->ocr_avail = AU1XMMC_OCR; 987 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 988 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 989 990 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ 991 992 switch (alchemy_get_cputype()) { 993 case ALCHEMY_CPU_AU1100: 994 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; 995 break; 996 case ALCHEMY_CPU_AU1200: 997 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 998 break; 999 case ALCHEMY_CPU_AU1300: 1000 iflag = 0; /* nothing is shared */ 1001 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1002 mmc->f_max = 52000000; 1003 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) 1004 mmc->caps |= MMC_CAP_8_BIT_DATA; 1005 break; 1006 } 1007 1008 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); 1009 if (ret) { 1010 dev_err(&pdev->dev, "cannot grab IRQ\n"); 1011 goto out3; 1012 } 1013 1014 host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK); 1015 if (IS_ERR(host->clk)) { 1016 dev_err(&pdev->dev, "cannot find clock\n"); 1017 ret = PTR_ERR(host->clk); 1018 goto out_irq; 1019 } 1020 1021 ret = clk_prepare_enable(host->clk); 1022 if (ret) { 1023 dev_err(&pdev->dev, "cannot enable clock\n"); 1024 goto out_clk; 1025 } 1026 1027 host->status = HOST_S_IDLE; 1028 1029 /* board-specific carddetect setup, if any */ 1030 if (host->platdata && host->platdata->cd_setup) { 1031 ret = host->platdata->cd_setup(mmc, 1); 1032 if (ret) { 1033 dev_warn(&pdev->dev, "board CD setup failed\n"); 1034 mmc->caps |= MMC_CAP_NEEDS_POLL; 1035 } 1036 } else 1037 mmc->caps |= MMC_CAP_NEEDS_POLL; 1038 1039 /* platform may not be able to use all advertised caps */ 1040 if (host->platdata) 1041 mmc->caps &= ~(host->platdata->mask_host_caps); 1042 1043 INIT_WORK(&host->data_bh_work, au1xmmc_data_bh_work); 1044 1045 INIT_WORK(&host->finish_bh_work, au1xmmc_finish_bh_work); 1046 1047 if (has_dbdma()) { 1048 ret = au1xmmc_dbdma_init(host); 1049 if (ret) 1050 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n"); 1051 } 1052 1053 #ifdef CONFIG_LEDS_CLASS 1054 if (host->platdata && host->platdata->led) { 1055 struct led_classdev *led = host->platdata->led; 1056 led->name = mmc_hostname(mmc); 1057 led->brightness = LED_OFF; 1058 led->default_trigger = mmc_hostname(mmc); 1059 ret = led_classdev_register(mmc_dev(mmc), led); 1060 if (ret) 1061 goto out5; 1062 } 1063 #endif 1064 1065 au1xmmc_reset_controller(host); 1066 1067 ret = mmc_add_host(mmc); 1068 if (ret) { 1069 dev_err(&pdev->dev, "cannot add mmc host\n"); 1070 goto out6; 1071 } 1072 1073 platform_set_drvdata(pdev, host); 1074 1075 pr_info(DRIVER_NAME ": MMC Controller %d set up at %p" 1076 " (mode=%s)\n", pdev->id, host->iobase, 1077 host->flags & HOST_F_DMA ? "dma" : "pio"); 1078 1079 return 0; /* all ok */ 1080 1081 out6: 1082 #ifdef CONFIG_LEDS_CLASS 1083 if (host->platdata && host->platdata->led) 1084 led_classdev_unregister(host->platdata->led); 1085 out5: 1086 #endif 1087 __raw_writel(0, HOST_ENABLE(host)); 1088 __raw_writel(0, HOST_CONFIG(host)); 1089 __raw_writel(0, HOST_CONFIG2(host)); 1090 wmb(); /* drain writebuffer */ 1091 1092 if (host->flags & HOST_F_DBDMA) 1093 au1xmmc_dbdma_shutdown(host); 1094 1095 cancel_work_sync(&host->data_bh_work); 1096 cancel_work_sync(&host->finish_bh_work); 1097 1098 if (host->platdata && host->platdata->cd_setup && 1099 !(mmc->caps & MMC_CAP_NEEDS_POLL)) 1100 host->platdata->cd_setup(mmc, 0); 1101 1102 clk_disable_unprepare(host->clk); 1103 out_clk: 1104 clk_put(host->clk); 1105 out_irq: 1106 free_irq(host->irq, host); 1107 out3: 1108 iounmap((void *)host->iobase); 1109 out2: 1110 release_resource(host->ioarea); 1111 kfree(host->ioarea); 1112 out1: 1113 mmc_free_host(mmc); 1114 out0: 1115 return ret; 1116 } 1117 1118 static void au1xmmc_remove(struct platform_device *pdev) 1119 { 1120 struct au1xmmc_host *host = platform_get_drvdata(pdev); 1121 1122 if (host) { 1123 mmc_remove_host(host->mmc); 1124 1125 #ifdef CONFIG_LEDS_CLASS 1126 if (host->platdata && host->platdata->led) 1127 led_classdev_unregister(host->platdata->led); 1128 #endif 1129 1130 if (host->platdata && host->platdata->cd_setup && 1131 !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1132 host->platdata->cd_setup(host->mmc, 0); 1133 1134 __raw_writel(0, HOST_ENABLE(host)); 1135 __raw_writel(0, HOST_CONFIG(host)); 1136 __raw_writel(0, HOST_CONFIG2(host)); 1137 wmb(); /* drain writebuffer */ 1138 1139 cancel_work_sync(&host->data_bh_work); 1140 cancel_work_sync(&host->finish_bh_work); 1141 1142 if (host->flags & HOST_F_DBDMA) 1143 au1xmmc_dbdma_shutdown(host); 1144 1145 au1xmmc_set_power(host, 0); 1146 1147 clk_disable_unprepare(host->clk); 1148 clk_put(host->clk); 1149 1150 free_irq(host->irq, host); 1151 iounmap((void *)host->iobase); 1152 release_resource(host->ioarea); 1153 kfree(host->ioarea); 1154 1155 mmc_free_host(host->mmc); 1156 } 1157 } 1158 1159 #ifdef CONFIG_PM 1160 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 1161 { 1162 struct au1xmmc_host *host = platform_get_drvdata(pdev); 1163 1164 __raw_writel(0, HOST_CONFIG2(host)); 1165 __raw_writel(0, HOST_CONFIG(host)); 1166 __raw_writel(0xffffffff, HOST_STATUS(host)); 1167 __raw_writel(0, HOST_ENABLE(host)); 1168 wmb(); /* drain writebuffer */ 1169 1170 return 0; 1171 } 1172 1173 static int au1xmmc_resume(struct platform_device *pdev) 1174 { 1175 struct au1xmmc_host *host = platform_get_drvdata(pdev); 1176 1177 au1xmmc_reset_controller(host); 1178 1179 return 0; 1180 } 1181 #else 1182 #define au1xmmc_suspend NULL 1183 #define au1xmmc_resume NULL 1184 #endif 1185 1186 static struct platform_driver au1xmmc_driver = { 1187 .probe = au1xmmc_probe, 1188 .remove_new = au1xmmc_remove, 1189 .suspend = au1xmmc_suspend, 1190 .resume = au1xmmc_resume, 1191 .driver = { 1192 .name = DRIVER_NAME, 1193 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1194 }, 1195 }; 1196 1197 static int __init au1xmmc_init(void) 1198 { 1199 if (has_dbdma()) { 1200 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1201 * of 8 bits. And since devices are shared, we need to create 1202 * our own to avoid freaking out other devices. 1203 */ 1204 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1205 if (!memid) 1206 pr_err("au1xmmc: cannot add memory dbdma\n"); 1207 } 1208 return platform_driver_register(&au1xmmc_driver); 1209 } 1210 1211 static void __exit au1xmmc_exit(void) 1212 { 1213 if (has_dbdma() && memid) 1214 au1xxx_ddma_del_device(memid); 1215 1216 platform_driver_unregister(&au1xmmc_driver); 1217 } 1218 1219 module_init(au1xmmc_init); 1220 module_exit(au1xmmc_exit); 1221 1222 MODULE_AUTHOR("Advanced Micro Devices, Inc"); 1223 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); 1224 MODULE_LICENSE("GPL"); 1225 MODULE_ALIAS("platform:au1xxx-mmc"); 1226